Resistive memory element having conductive islands embedded in a switching layer

Abstract

The present invention relates to a resistive memory element having a conductive island embedded in a switching layer, and discloses a structure of the resistive memory element and a method of forming the structure of the resistive memory element. The resistive memory element includes a first switching layer, a second switching layer, a conductive spacer wall, a first electrode, and a second electrode. The first switching layer includes a portion between the first electrode and the conductive spacer wall, the second switching layer includes a portion between the second electrode and the conductive spacer wall, and the conductive spacer wall is located between the portion of the first switching layer and the portion of the second switching layer.

Description

Technical Field

[0001] The present invention relates to integrated circuit and semiconductor device manufacturing, and more particularly to the structure of a resistive memory element and a method for forming the structure of a resistive memory element. Background Art

[0002] Resistive random access memory (ReRAM or RRAM) devices provide an embedded non-volatile memory technology. Because its resistive memory elements are non-volatile, the RRAM device retains stored data bits when the memory elements are not powered. The non-volatility of RRAM devices is in contrast to volatile memory technologies such as static random access memory (SRAM) devices (where stored contents are ultimately lost when power is removed) and dynamic random access memory (DRAM) devices (where stored contents are lost if not periodically refreshed).

[0003] Data is stored in a resistive memory element by changing the resistance on a switching layer to provide different information storage states (high resistance state and low resistance state) representing the stored data bit. To change the switching layer, a bias voltage may be applied that is sufficient to create one or more filaments as a conductive path across the thickness of the switching layer to write a low resistance state. The filaments may also be destroyed by applying a bias voltage to write a high resistance state.

[0004] Improved resistive memory element structures and methods of forming resistive memory element structures are needed. Summary of the invention

[0005] According to one embodiment of the present invention, a structure includes a resistive memory element, which has a first switch layer, a second switch layer, a conductive spacer, a first electrode, and a second electrode. The first switch layer includes a portion located between the first electrode and the conductive spacer, the second switch layer includes a portion located between the second electrode and the conductive spacer, and the conductive spacer is located between the portion of the first switch layer and the portion of the second switch layer.

[0006] According to another embodiment of the present invention, a method for forming a structure of a resistive memory element is provided. The method includes forming a first electrode, forming a first switch layer, forming a conductive spacer on the first switch layer, forming a second switch layer on the first switch layer and the conductive spacer, and forming a second electrode on the second switch layer. The first switch layer includes a portion located between the first electrode and the conductive spacer, the second switch layer includes a portion located between the second electrode and the conductive spacer, and the conductive spacer is located between the portion of the first switch layer and the portion of the second switch layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention made above and the detailed description of the embodiments made below, are used to explain the embodiments of the present invention. In the accompanying drawings, like reference numerals represent similar features in different views.

[0008] Figure 1-5 Schematic cross-sectional views showing the structure of a resistive memory element at successive manufacturing stages of a processing method according to an embodiment of the present invention.

[0009] Figure 6-9 A schematic cross-sectional view showing the structure of a resistive memory element according to an alternative embodiment of the present invention. DETAILED DESCRIPTION

[0010] Please refer to Figure 1 According to an embodiment of the present invention, a structure 10 of a resistive memory element is disposed in a metallization level of an interconnect structure 12. The interconnect structure 12 may be fabricated by middle-of-line and back-end-of-line processing on a substrate 14. The structure 10 may be located above a metal feature 16 in one of the metallization levels (e.g., the M2 metallization level) of the interconnect structure. The interconnect structure 12 includes an interlayer dielectric layer 18 that may be composed of a dielectric material such as silicon dioxide, and the metal feature 16 may be composed of a metal such as copper or aluminum.

[0011] The structure 10 includes a bottom electrode 20 disposed in a stacked arrangement over a metal feature 16 and an insulator layer 22 disposed over the bottom electrode 20. In one embodiment, the insulator layer 22 may be in direct contact with a top surface 25 of the bottom electrode 20. The bottom electrode 20 includes a side surface 24, a side surface 26 opposite the side surface 24, and a top surface 25 adjacent to the insulator layer 22. The side surfaces 24, 26 define corners of the bottom electrode 20 located at the top surface 25. In one embodiment, the insulator layer 22 may extend across the top surface 25 of the bottom electrode 20 from the side surface 24 to the side surface 26. In one embodiment, the insulator layer 22 may completely cover the top surface 25 of the bottom electrode 20. The insulator layer 22 has opposing side surfaces 21, 23 that may be aligned with the side surfaces 24, 26 of the bottom electrode 20.

[0012] To form the bottom electrode 20 and the insulator layer 22, the constituent material layers thereof may be deposited on the interlayer dielectric layer 18 and the metal features 16, and then the deposited layers may be patterned using photolithography and etching processes. The etching process for patterning the bottom electrode 20 and the insulator layer 22 may be a reactive ion etching process. The bottom electrode 20 may be composed of a metal such as platinum, ruthenium, titanium nitride, or tantalum nitride deposited by, for example, physical vapor deposition. The insulator layer 22 may be a dielectric layer composed of a dielectric material such as silicon dioxide or silicon nitride.

[0013] A switching layer 28 is formed over the interlayer dielectric layer 18 and the stacked bottom electrode 20 and insulator layer 22. In one embodiment, the switching layer 28 may be composed of a metal oxide such as magnesium oxide, tantalum oxide, hafnium oxide, titanium oxide, aluminum oxide, or silicon dioxide, and may be conformally deposited to a nominally uniform thickness. The switching layer 28 includes portions that are in direct contact with the side surfaces 24, 26 of the bottom electrode 20, respectively. In one embodiment, the switching layer 28 may be in direct contact with the side surfaces 24, 26 of the bottom electrode 20, and in direct contact with the side surfaces 21, 23 and the top surface of the insulator layer 22.

[0014] Please refer to Figure 2 , wherein similar reference numerals denote Figure 1 2, and in the next manufacturing stage of the processing method, conductive spacers 30, 32 are formed on portions of the switch layer 28. The conductive spacers 30, 32 are respectively located adjacent to the opposite side surfaces 21, 23 of the insulator layer 22. The conductive spacers 30, 32 are also respectively adjacent to the opposite side surfaces 24, 26 ( Figure 1 The portions of the switching layer 28 separate the conductive spacers 30 , 32 from the opposite side surfaces 24 , 26 of the bottom electrode 20 and the opposite side surfaces 21 , 23 of the insulator layer 22 , respectively.

[0015] In one embodiment, the conductive spacers 30, 32 may be composed of a metal such as tantalum, copper or titanium and may be formed by depositing a conformal layer on the switching layer 28 and etching the conformal layer using an anisotropic etching process such as a reactive ion etching process. The bottom electrode 20 and the insulator layer 22 together provide a pillar used during the formation of the conductive spacers 30, 32. The pillar provides a non-planar topography for the deposition of the conformal layer and thereby defines a location adjacent to the side surfaces 21, 23 and the side surfaces 24, 26 to form the conductive spacers 30, 32 when the deposited conformal layer is etched using the anisotropic etching process. The conductive spacers 30, 32 may also be further etched using a cut mask to form discontinuous sections associated with the structure 10 and adjacent structures (not shown) similar or identical to the structure 10.

[0016] Please refer to Figure 3 , wherein similar reference numerals denote Figure 1 , and in the next manufacturing stage of the process method, a switching layer 34 is formed over the switching layer 28 and the conductive spacers 30, 32. In one embodiment, the switching layer 34 can be composed of the same metal oxide as the switching layer 28. In one embodiment, the switching layer 34 can be composed of a metal oxide such as magnesium oxide, tantalum oxide, hafnium oxide, titanium oxide, aluminum oxide, or silicon dioxide, and can be conformally deposited to a nominally uniform thickness.

[0017] Conductive spacers 30 are disposed between portions of the switch layer 28 and portions of the switch layer 34, and these portions of the switch layers 28, 34 and the conductive spacers 30 are adjacent to the side surface 24 of the bottom electrode 20 and the side surface 21 of the insulator layer 22. Conductive spacers 32 are disposed between portions of the switch layer 28 and portions of the switch layer 34 adjacent to the side surface 26 of the bottom electrode 20, and these portions of the switch layers 28, 34 and the conductive spacers 32 are adjacent to the side surface 26 of the bottom electrode 20 and the side surface 23 of the insulator layer 22. The conductive spacers 30, 32 are surrounded by the switch layers 28, 34 to provide conductive features or islands embedded in the switch layers 28, 34. The switch layers 28, 34 may be considered as one merged layer, which includes the conductive spacers 30, 32 as embedded conductive features.

[0018] Please refer to Figure 4 , wherein similar reference numerals denote Figure 3, and in the next manufacturing stage of the process method, a top electrode 36 and a top electrode 38 of the structure 10 are formed above the switch layer 34. In one embodiment, the top electrodes 36, 38 may be composed of a metal such as tantalum, hafnium, copper, silver, cobalt, or tungsten deposited by, for example, physical vapor deposition. The top electrodes 36, 38 may be formed by depositing a metal layer and patterning the metal layer using photolithography and etching processes. In one embodiment, the top electrodes 36, 38 are composed of a different metal than the conductive spacers 30, 32.

[0019] The top electrode 36 is located on the switching layer 34 adjacent to and close to the side surface 24 of the bottom electrode 20, the side surface 21 of the insulator layer 22, and the conductive spacer 30. In one embodiment, the top electrode 36 can be in direct physical and electrical contact with the switching layer 34. The conductive spacer 30 is located between the top electrode 36 and the side surface 24 of the bottom electrode 20 and between the top electrode 36 and the side surface 21 of the insulator layer 22. A portion of the switching layer 34 is located between the top electrode 36 and the conductive spacer 30.

[0020] The top electrode 38 is located on the switching layer 34 adjacent to and proximate to the side surface 26 of the bottom electrode 20, the side surface 23 of the insulator layer 22, and the conductive spacer 32. In one embodiment, the top electrode 38 can be in direct physical and electrical contact with the switching layer 34. The conductive spacer 32 is located between the top electrode 38 and the side surface 24 of the bottom electrode 20. A portion of the switching layer 34 is located between the top electrode 36 and the conductive spacer 32. Therefore, the top electrodes 36, 38 contact different portions of the switching layer 34.

[0021] Please refer to Figure 5 , wherein similar reference numerals denote Figure 4 , and in the next manufacturing stage of the processing method, an interlayer dielectric layer 40 of the interconnect structure 12 is formed above the structure 10. The interlayer dielectric layer 40 can be composed of a dielectric material similar to the interlayer dielectric layer 18, such as silicon dioxide. The interlayer dielectric layer 40 can be formed by depositing a layer of dielectric material and planarizing it using chemical mechanical polishing. Bit lines 42, 44 are formed in the interlayer dielectric layer 40 and are coupled to the top electrodes 36, 38 respectively through conductive vias. The bit lines 42, 44 and the conductive vias can be formed by patterning the interlayer dielectric layer 40, depositing one or more metals, and planarizing it using chemical mechanical polishing. The interlayer dielectric layer 40 defines the metallization levels of the interconnect structure 12 arranged above the structure 10.

[0022] During use, by applying an appropriate bias voltage, filaments are formed in the switching layers 28, 34 near the conductive spacers 30, 32. The conductive spacers 30, 32 act as conductive islands to effectively shorten the filament formation path between the bottom electrode 20 and the top electrodes 36, 38 when programming the structure 10 to switch between low resistance and high resistance states. The conductive spacers 30, 32 are adjacent to the upper corners of the bottom electrode 20 that intersect the top surface 25. The filaments are confined to the side surfaces 23, 24 of the bottom electrode 20, and preferably, are located near the upper corners of the bottom electrode 20 where the electric field is highest during operation. The insulator layer 22 located on the top surface 25 of the bottom electrode 20 prevents the filament path from forming between the top surface 25 and the top electrodes 36, 38.

[0023] Please refer to Figure 6 , wherein similar reference numerals denote Figure 5 , and in the next manufacturing stage of the process method, an insulator layer 22 may be formed with segments 22a, 22b at laterally spaced locations over the individual bottom electrodes 20 that are patterned and then embedded in the dielectric layer 46. The segments 22a of the insulator layer 22 are disposed over one of the bottom electrodes 20, and the segments 22b of the insulator layer 22 are disposed over the other of the bottom electrodes 20. The switching layers 28, 34, the conductive spacers 30, 32, and the top electrodes 36, 38 are formed as previously described to define the structure 10 over one of the bottom electrodes 20, and to define an additional structure 10a of another resistive memory element that is nominally equivalent to another one of the bottom electrodes 20 over the other of the bottom electrodes 20.

[0024] The switching layer 28 includes a portion located on the top surface 25 of each bottom electrode 20, a portion located on the segment 22a of the insulator layer 22, and a portion located on the segment 22b of the insulator layer 22. A conductive spacer 30 is located above the top surface 25 of one of the bottom electrodes 20, and a conductive spacer 32 is located above the top surface 25 of another of the bottom electrodes 20. The conductive spacer 30 is located between the top surface 25 of the bottom electrode 20 and the top electrode 36, a portion of the switching layer 28 is located between the bottom electrode 20 and the conductive spacer 30, and a portion of the switching layer 34 is located between the top electrode 36 and the conductive spacer 30. The conductive spacer 32 is located between the top surface 25 of the bottom electrode 20 and the top electrode 38, a portion of the switching layer 28 is located between the bottom electrode 20 and the conductive spacer 32, and a portion of the switching layer 34 is located between the top electrode 38 and the conductive spacer 32.

[0025] The segments 22a, 22b of the insulator layer 22 provide pillars used during the formation of the conductive spacers 30, 32. The pillars provide a non-planar topography and thereby define the formation locations of the conductive spacers 30, 32 adjacent to the side surfaces 21, 23 of the insulator layer 22 when a conformal layer is deposited and etched using an anisotropic etch process to form the conductive spacers 30, 32.

[0026] Please refer to Figure 7 , wherein similar reference numerals denote Figure 6 , and according to an alternative embodiment, before forming the top electrodes 36, 38, a dielectric layer 50 may be formed in the space between the segments 22a, 22b of the insulator layer 22. The dielectric layer 50 may be composed of a dielectric material such as silicon dioxide. The dielectric layer 50 may be formed by depositing a dielectric material layer and planarizing it using chemical mechanical polishing. The dielectric layer 50 is formed after forming the switch layers 28, 34 and the conductive spacers 30, 32 and before forming the top electrodes 36, 38. Each top electrode 36, 38 includes a portion located on the switch layer 34 and a portion located on the dielectric layer 50, and the top electrodes 36, 38 have respective bottom surfaces 37, 39 that are substantially planar.

[0027] Please refer to Figure 8 , wherein similar reference numerals denote Figure 6 , and according to an alternative embodiment, a switch layer 52 may be formed in the space between the segments 22a, 22b of the insulator layer 22 before forming the switch layer 34 and the top electrodes 36, 38. The switch layer 52 is formed after forming the conductive spacers 30, 32. The switch layer 52 may be composed of a metal oxide such as magnesium oxide, tantalum oxide, hafnium oxide, titanium oxide, aluminum oxide, or silicon dioxide, and may be conformally deposited to a nominally uniform thickness. The switch layer 52 may be polished using chemical mechanical polishing after deposition, and the segments 22a, 22b of the insulator layer 22 may serve as polishing stops. The switch layer 52 and the segments 22a, 22b of the insulator layer 22 may be coplanar or substantially coplanar at their respective top surfaces. The switch layer 34 may be polished using chemical mechanical polishing after deposition to provide a planar or substantially planar top surface. Top electrodes 36, 38 are disposed entirely on the top surface of the switching layer 34 at locations overlapping the locations of the conductive spacers 30, 32, and respective bottom surfaces 37, 39 of the top electrodes 36, 38 entirely on the switching layer 34 are substantially planar.

[0028] Please refer to Fig. 9 , wherein similar reference numerals denote Figure 6, and according to an alternative embodiment, the insulator layer 22 may include an additional segment 22c located between the segments 22a and 22b of the insulator layer 22. The segment 22a is separated from the segment 22c by a gap 54, and the segment 22b is separated from the segment 22c by a gap 56. The gaps 54, 56 expose portions of the bottom electrode 20. The switching layer 28 is conformally deposited so that the gaps 54, 56 are partially filled with the material of the switching layer 28. Subsequently, the conductive spacers 30, 32 are formed in the gaps 54, 56 by deposition and planarization.

[0029] Next, the switch layer 34 is formed by deposition and planarization, and top electrodes 36, 38 are formed on the switch layer 34. The top electrode 36 is located on the switch layer 34 above the conductive spacer 30, and the top electrode 38 is located on the switch layer 34 above the conductive spacer 32. The respective bottom surfaces 37, 39 of the top electrodes 36, 38 completely located on the switch layer 34 are substantially planar. The conductive spacer 30 is located between the bottom surface 37 of the top electrode 36 and the portion of the bottom electrode 20 located in the gap 54 between the segments 22a, 22c of the insulator layer 22. The conductive spacer 32 is located between the bottom surface 39 of the top electrode 38 and the portion of the bottom electrode 20 located in the gap 56 between the segments 22b, 22c of the insulator layer 22.

[0030] The above method is used for the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare chip, or in a packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smart phone with a central processing unit.

[0031] Terms modified by approximate language such as "about," "approximately," and "substantially" cited herein are not limited to the exact value specified. The approximate language may correspond to the precision of the instrument used to measure the value, and may represent + / -10% of the value unless otherwise dependent on the precision of the instrument.

[0032] Terms such as "vertical", "horizontal", etc. are cited herein as examples to establish a reference frame and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0033] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intervening features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intervening features. A feature may be "not directly connected" or "not directly coupled" to another feature if there are at least one intervening feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intervening features may be present. A feature may be directly "on" or "in direct contact with" another feature if there are no intervening features. A feature may not be "directly" "on" or "not directly in contact with" another feature if there are at least one intervening feature.

[0034] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: A resistive memory element, comprising a first switching layer, a second switching layer, a first conductive spacer, a first electrode, and a second electrode. The first conductive spacer is surrounded by the first switching layer and the second switching layer. The first switching layer includes a first portion between the first electrode and the first conductive spacer. The second switching layer includes a first portion between the second electrode and the first conductive spacer. And the first conductive spacer is located between the first portion of the first switching layer and the first portion of the second switching layer.

2. The semiconductor structure according to claim 1, further comprising: An insulator layer located on the first electrode. The insulator layer includes a first side surface, wherein the first conductive spacer is located adjacent to the first side surface of the insulator layer.

3. The semiconductor structure according to claim 2, wherein, the insulator layer is composed of a dielectric material.

4. The semiconductor structure according to claim 2, wherein, the first electrode includes a top surface, and the insulator layer completely covers the top surface of the first electrode.

5. The semiconductor structure according to claim 2, wherein, the first electrode includes a side surface, and the first conductive spacer, the first portion of the first switching layer, and the first portion of the second switching layer are located adjacent to the side surface of the first electrode.

6. The semiconductor structure according to claim 5, wherein, the first portion of the first switching layer is in direct contact with the side surface of the first electrode.

7. The semiconductor structure according to claim 2, wherein, the first electrode includes a top surface, and the insulator layer partially covers the top surface of the first electrode.

8. The semiconductor structure according to claim 2, wherein, the first electrode includes a top surface, and the first conductive spacer, the first portion of the first switching layer, and the first portion of the second switching layer are located above a portion of the top surface of the first electrode.

9. The semiconductor structure according to claim 8, further comprising: A dielectric layer adjacent to the first portion of the second switching layer, wherein the second electrode includes a first portion located above the first portion of the second switching layer and a second portion located above the dielectric layer.

10. The semiconductor structure according to claim 9, wherein, the second electrode includes a bottom surface located on the first portion of the second switching layer and on the dielectric layer, and the bottom surface of the second electrode is substantially planar.

11. The semiconductor structure according to claim 8, wherein, the resistive memory element further includes a third switching layer located adjacent to the first conductive spacer, and the third switching layer is located between the first switching layer and the second switching layer.

12. The semiconductor structure according to claim 11, wherein, the second electrode includes a bottom surface completely located on the second switching layer, and the bottom surface of the second electrode is substantially planar.

13. The semiconductor structure according to claim 8, wherein, The insulator layer includes a first section and a second section separated by a gap above the portion of the top surface of the first electrode, and the first portion of the first switching layer and the first conductive gap wall are located in the gap.

14. The semiconductor structure according to claim 1, wherein, the resistive memory element includes a third electrode and a second conductive gap wall, the first switching layer includes a second portion located between the first electrode and the second conductive gap wall, the second switching layer includes a second portion located between the third electrode and the second conductive gap wall, and the second conductive gap wall is located between the second portion of the first switching layer and the second portion of the second switching layer.

15. The semiconductor structure according to claim 1, wherein, the first electrode includes a side surface, and the first conductive gap wall, the first portion of the first switching layer, and the first portion of the second switching layer are located adjacent to the side surface of the first electrode.

16. The semiconductor structure according to claim 1, wherein, the first electrode includes a top surface, and the first conductive gap wall, the first portion of the first switching layer, and the first portion of the second switching layer are located above a portion of the top surface of the first electrode.

17. A method of forming a semiconductor structure of a resistive memory element, the method comprises: forming a first electrode; forming a first switching layer; forming a conductive gap wall on the first switching layer; forming a second switching layer on the first switching layer and the conductive gap wall; and forming a second electrode on the second switching layer, wherein the first switching layer includes a portion located between the first electrode and the conductive gap wall, the second switching layer includes a portion located between the second electrode and the conductive gap wall, and the conductive gap wall is located between the first electrode and the second electrode.

18. The method according to claim 17, further comprises: forming an insulator layer on the first electrode, wherein the insulator layer includes a side surface, and the conductive gap wall is formed adjacent to the side surface of the insulator layer.

19. The method according to claim 17, wherein, the first electrode includes a side surface, and the conductive gap wall, the portion of the first switching layer, and the portion of the second switching layer are located adjacent to the side surface of the first electrode.

20. The method according to claim 17, wherein, the first electrode includes a top surface, and the conductive gap wall, the portion of the first switching layer, and the portion of the second switching layer are located above a portion of the top surface of the first electrode.

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