Semiconductor device and method for operating the same

Abstract

The present application discloses a semiconductor device and a method for operating the same. The semiconductor device includes: a transmitting circuit, comprising: a first transistor and a second transistor coupled in series between a first voltage terminal and a second voltage terminal; and a first common node coupled between the first transistor and the second transistor and coupled to a through-line, the transmitting circuit outputting a signal transmitted from an internal circuit to the first common node according to an output control signal; a receiving circuit, comprising: a third transistor and a fourth transistor coupled in series between the first voltage terminal and the second voltage terminal; and a second common node coupled between the third transistor and the fourth transistor and coupled to the internal circuit, the receiving circuit transmitting the signal transmitted via the through-line to the internal circuit according to a first input control signal; and a degradation acceleration circuit for applying stress to the first transistor and the third transistor according to a test signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0110996, filed on September 1, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor design technology, and particularly to a semiconductor device including unused circuits. Background Art

[0004] Recently, multi-chip packaging has been proposed as a technology for packaging semiconductor devices. Multi-chip packaging technology combines multiple semiconductor chips into a package. Depending on how many semiconductor chips are included in a package, there are different types of packages, namely, single die package (SDP), dual die package (DDP) and quad die package (QDP). For the purpose of cost saving, a product family that can support various specifications with a single development model can be developed by implementing various configurations in a single semiconductor chip. For example, a semiconductor chip can be developed for a multi-chip package, and a fuse selection method can be used to determine which of SDP, DDP and QDP is applied to the semiconductor chip.

[0005] However, since various configurations are implemented in one semiconductor chip, net die and current loss may occur. For example, when the SDP type, DDP type, and QDP type are developed as a single semiconductor chip, a transmitting circuit / receiving circuit for through-silicon vias (TSV, also referred to as (one or more) through electrodes) is implemented in the semiconductor chip, but the transmitting circuit / receiving circuit is not necessary for the SDP type and DDP type. Therefore, the transmitting circuit / receiving circuit for the through electrodes implemented in the SDP type and DDP type semiconductor chips always remains in an idle state, and the cutoff current (i.e., the leakage current of the transistor) in the SDP type and DDP type semiconductor chips may be increased. As a result, the power consumption of the product may increase. Specifically, since the transmitting circuit / receiving circuit for the through electrodes uses a bulky driver in the form of an array in the transmitting circuit and the receiving circuit, the cutoff current may be further increased. Summary of the Invention

[0006] According to an embodiment, a semiconductor device capable of reducing an off-current of a circuit operating in an idle state where the circuit is not used according to a configuration and a test operation method thereof are provided.

[0007] According to one embodiment, a semiconductor device includes: a transmitting circuit, which includes: a first transistor and a second transistor coupled in series between a first voltage terminal and a second voltage terminal; and a first common node coupled between the first transistor and the second transistor and coupled to a through-line, the transmitting circuit outputs a signal transmitted from an internal circuit to the first common node according to an output control signal; a receiving circuit, which includes: a third transistor and a fourth transistor coupled in series between the first voltage terminal and the second voltage terminal; and a second common node coupled between the third transistor and the fourth transistor and coupled to the internal circuit, the receiving circuit transmits the signal transmitted via the through-line to the internal circuit according to a first input control signal; and a degradation acceleration circuit, which is used to apply stress to the first transistor and the third transistor according to a test signal.

[0008] According to one embodiment, a semiconductor device includes: a first pull-up transistor and a first pull-down transistor, which are coupled to a through-line through a first common node and receive a drive control signal transmitted from a first global line or a second global line according to an output control signal to drive the first common node; a second pull-up transistor and a second pull-down transistor, which are coupled to the first global line through a second common node and receive a signal transmitted through the through-line according to a first input control signal to drive the second common node; a third pull-up transistor and a third pull-down transistor, which are coupled to the second global line through a third common node and receive a signal transmitted through the through-line according to a second input control signal to drive the third common node; and a degradation acceleration circuit, which is used to apply stress to the first pull-up transistor to the third pull-up transistor according to a test signal.

[0009] According to one embodiment, a method for operating a semiconductor device includes: driving a first common node coupled to a first pull-up transistor and a first pull-down transistor and also coupled to a through-line, receiving a signal transmitted via the through-line, and driving a second common node coupled to a second pull-up transistor and a second pull-down transistor and also coupled to a first global line, and receiving a signal transmitted via the through-line and driving a third common node coupled to a third pull-up transistor and a third pull-down transistor and also coupled to the second global line; performing a degradation acceleration operation during a test operation to control the application of stress to the first pull-up transistor to the third pull-up transistor; and driving the first common node to the third common node at a ground voltage level during normal operation.

[0010] According to one embodiment, a semiconductor device includes: a transmitting circuit including a first transistor and a second transistor coupled in series between a first voltage terminal and a second voltage terminal and having a first common node coupled to a predetermined line, and outputting a signal transmitted from an internal circuit to the first common node according to an output control signal; and a degradation acceleration circuit for controlling application of stress to only one of the first transistor and the second transistor according to a test signal.

[0011] According to one embodiment, a semiconductor device includes: a first driving circuit, which includes: a first transistor and a second transistor coupled in series between a first voltage terminal and a second voltage terminal, and a first common node coupled between the first transistor and the second transistor and coupled to a predetermined line, the first driving circuit transmits data transmitted from a first pad group to a predetermined line according to a first driving control signal; a second driving circuit, which includes: a third transistor and a fourth transistor coupled in series between the first voltage terminal and the second voltage terminal, and a second common node coupled between the third transistor and the fourth transistor and coupled to a predetermined line, the second driving circuit transmits data transmitted from a second pad group to a predetermined line according to a second driving control signal; and a degradation acceleration circuit, which is used to apply stress to the third transistor according to a test signal.

[0012] According to one embodiment, a semiconductor device includes: an internal circuit; a first global line and a second global line; a pass-through line; a transmitting circuit including a first pull-up transistor and a first pull-down transistor coupled in series between a power supply voltage terminal and a ground voltage terminal, and a first common node coupled between the first pull-up transistor and the first pull-down transistor, the transmitting circuit being coupled to the internal circuit via the first global line and coupled to the pass-through line via the first common node, the transmitting circuit outputting a signal received from the internal circuit to the first common node according to a first control signal; a receiving circuit including a second pull-up transistor and a second pull-down transistor coupled in series between the power supply voltage terminal and the ground voltage terminal, and a first common node coupled between the first pull-up transistor and the first pull-down transistor. At a second common node between the second pull-up transistor and the second pull-down transistor, the receiving circuit is coupled to the through-line and to the internal circuit through the second global line, and the receiving circuit transmits the signal received via the through-line to the internal circuit through the second global line according to the second control signal; and a degradation acceleration circuit is configured to: control the first control signal and the second control signal according to the enablement of the test signal, so that the first pull-up transistor and the second pull-up transistor are turned on and stress is applied to the first pull-up transistor and the second pull-up transistor, and control the first control signal and the second control signal according to the disablement of the test signal, so that the first common node and the second common node are at a ground voltage level.

[0013] According to an embodiment, when various configurations are implemented in one semiconductor chip, a semiconductor device can reduce cutoff current caused by unused circuit(s) by accelerating degradation of certain types of transistors in the unused circuit(s). BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a view showing the configuration of a semiconductor device.

[0015] Figure 2A and Figure 2B Is the description when Figure 1 A view of a semiconductor device during a write operation and a read operation when the semiconductor device is a slave chip and a master chip respectively.

[0016] Figure 3 It shows that Figure 1 A view of the operation of a semiconductor device when implemented as an SDP type chip;

[0017] Figure 4 is a circuit diagram illustrating the BTI phenomenon in an inverter chain;

[0018] Figure 5 is a view showing a configuration of a semiconductor device according to an embodiment;

[0019] Figure 6 It shows Figure 5 A view of accelerated operation of degradation of semiconductor devices;

[0020] Figure 7 It shows Figure 5 A view of normal operation of a semiconductor device;

[0021] Figure 8 is a view illustrating a method for operating a semiconductor device according to an embodiment; and

[0022] Figure 9 is a view showing the configuration of a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings to allow those skilled in the art to easily practice the technical spirit of the present disclosure. When describing embodiments of the present disclosure, well-known information may be omitted from the description. When assigning reference numerals to elements in the accompanying drawings, the same or substantially the same reference numerals may be used to refer to the same or substantially the same elements throughout the specification and the drawings. Throughout the specification, references to "one embodiment" and the like are not necessarily only one embodiment, and different references to any such phrases are not necessarily for (one or more) the same embodiment. When used herein, the term "embodiment" does not necessarily refer to all embodiments.

[0024] Figure 1 1 is a diagram showing the configuration of the semiconductor device 10 .

[0025] refer to Figure 1 , the semiconductor device 10 may include at least one through-electrode TSV, and a transmitting circuit 20 and a receiving circuit 30 corresponding to the through-electrode TSV. For example, Figure 1 The semiconductor device 10 is shown to include one through-electrode, but in practice, the semiconductor device 10 may include a plurality of through-electrodes and transmitting circuits and receiving circuits corresponding to the through-electrodes, respectively.

[0026] The transmitting circuit 20 may include a driving control circuit 22 and a driving circuit 24. The driving control circuit 22 may selectively receive a first transmission signal S1 from the first global line GIO_S or a second transmission signal S2 from the second global line GIO_M according to the master / slave selection signals TSV_S and TSV_M, and transmit the received signal as a driving control signal DRV_C to the control node NO_C0. When the semiconductor device 10 is implemented as a quad die package (QDP) type chip or a 3-dimensional stacked (3DS) semiconductor chip, the master / slave selection signals TSV_S and TSV_M are signals for distinguishing between a master chip and a slave chip. That is, the master / slave selection signal may be divided into a master selection signal TSV_M and a slave selection signal TSV_S, wherein the master selection signal TSV_M is enabled when the semiconductor device 10 operates as a master chip, and the slave selection signal TSV_S is enabled when the semiconductor device 10 operates as a slave chip.

[0027] When the output control signal TX_EN is enabled at a logic high level, the driver circuit 24 can drive the through-line GIO_TSV connected to one end of the through-electrode TSV according to the drive control signal DRV_C. When the output control signal TX_EN is disabled at a logic low level, the driver circuit 24 can maintain the through-line GIO_TSV in a floating state. The output control signal TX_EN is enabled to activate the transmitting circuit 20.

[0028] More specifically, the drive control circuit 22 may include a first buffer 22A and a second buffer 22B. Each of the first buffer 22A and the second buffer 22B may be implemented as an inverter. The outputs of the first buffer 22A and the second buffer 22B may be commonly connected to a control node NO_C0. When the slave select signal TSV_S is enabled at a logic high level, the first buffer 22A may invert and buffer the first transmission signal S1 from the first global line GIO_S and output the resulting signal to the control node NO_C0. When the slave select signal TSV_S is disabled at a logic low level, the first buffer 22A may block the input of the first transmission signal S1. When the master select signal TSV_M is enabled at a logic high level, the second buffer 22B may invert and buffer the second transmission signal S2 from the second global line GIO_M and output the resulting signal to the control node NO_C0. When the master select signal TSV_M is disabled at a logic low level, the second buffer 22B may block the input of the second transmission signal S2.

[0029] The driver circuit 24 may include a first NAND gate ND11, a first NOR gate NR11, a pull-up transistor P11, and a pull-down transistor N11. The first NAND gate ND11 may perform a logical NAND operation on the output control signal TX_EN and the drive control signal DRV_C, and output a pull-up drive signal PTX. The first NOR gate NR11 may perform a logical NOR operation on the inverted signal TX_ENB of the output control signal TX_EN and the drive control signal DRV_C, and output a pull-down drive signal NTX. The pull-up transistor P11 may drive the through-line GIO_TSV at a power supply voltage (VDD) level according to the pull-up drive signal PTX. The pull-down transistor N11 may drive the through-line GIO_TSV at a ground voltage (VSS) level according to the pull-down drive signal NTX. In some embodiments, the pull-up transistor P11 may be configured as a PMOS transistor, and the pull-down transistor N11 may be configured as an NMOS transistor. With the above configuration, when the output control signal TX_EN is enabled at a logic high level and the drive control signal DRV_C is at a logic high level, the driver circuit 24 can drive the through-line GIO_TSV at the power supply voltage VDD. When the output control signal TX_EN is enabled at a logic high level and the drive control signal DRV_C is at a logic low level, the driver circuit 24 can drive the through-line GIO_TSV at a ground voltage (VSS) level.

[0030] The transmission circuit 20 may further include a first latch circuit 26 and a second latch circuit 28. Each of the first latch circuit 26 and the second latch circuit 28 may include two inverters connected in series. The first latch circuit 26 may latch the signal of the control node NO_C0 (i.e., the drive control signal DRV_C) to maintain a logic level. The second latch circuit 28 may latch the signal of the through line GIO_TSV to maintain a logic level.

[0031] The receiving circuit 30 may include a first receiver 32 and a second receiver 34. The first receiver 32 may drive the first global line GIO_S using the signal of the through-line GIO_TSV according to the first input control signal WTEN_S. When the first input control signal WTEN_S is enabled at a logic high level, the first receiver 32 may drive the first global line GIO_S according to the signal of the through-line GIO_TSV. When the first input control signal WTEN_S is disabled at a logic low level, the first receiver 32 may keep the first global line GIO_S in a floating state. The second receiver 34 may drive the second global line GIO_M using the signal of the through-line GIO_TSV according to the second input control signal RDEN_M. When the second input control signal RDEN_M is enabled at a logic high level, the second receiver 34 may drive the second global line GIO_M according to the signal of the through-line GIO_TSV. When the second input control signal RDEN_M is disabled at a logic low level, the second receiver 34 may keep the second global line GIO_M in a floating state. Each of the first receiver 32 and the second receiver 34 is substantially the same in configuration as the driving circuit 24 .

[0032] The receiving circuit 30 may further include a third latch circuit 36 and a fourth latch circuit 38. Each of the third latch circuit 36 and the fourth latch circuit 38 may include two inverters connected in series. The third latch circuit 36 may latch the signal of the first global line GIO_S to maintain a logic level. The fourth latch circuit 38 may latch the signal of the second global line GIO_M to maintain a logic level.

[0033] The first receiver 32 of the receiving circuit 30 and the first buffer 22A of the transmitting circuit 20 may be connected to the internal circuit 40 through the first global line GIO_S. When the semiconductor device 10 is a memory device, the internal circuit 40 may include a memory bank of the memory device. Figure 2A, when the semiconductor device 10 is a slave chip, the first input control signal WTEN_S and the slave select signal TSV_S can be enabled. During a write (WT) operation, the first receiver 32 of the receiving circuit 30 can receive a signal transmitted through the through-electrode TSV and send the received signal to the internal circuit 40 through the first global line GIO_S. The internal circuit 40 can write the transmitted signal to the memory bank. During a read (RD) operation, when the data / signal read from the internal circuit 40 is transmitted to the first buffer 22A of the transmitting circuit 20 through the first global line GIO_S, the first buffer 22A can invert and buffer the first transmission signal S1 and output the resulting signal as a drive control signal DRV_C. When the output control signal TX_EN is enabled to a logic high level, the drive circuit 24 can transmit the signal to the through-electrode TSV by driving the through-line GIO_TSV according to the drive control signal DRV_C. The signal transmitted via the through-electrode TSV can be transmitted to the master chip and can be output to an external device such as a controller (not shown) or a tester device (not shown).

[0034] The second receiver 34 of the receiving circuit 30 and the second buffer 22B of the transmitting circuit 20 may be connected to the input / output (I / O) circuit 50 through the second global line GIO_M. Figure 2B As shown, when the semiconductor device 10 is the master chip, the second input control signal RDEN_M and the master selection signal TSV_M can be enabled. During the write (WT) operation, the signal / data is input to the I / O circuit 50 from the external device. When the second transmission signal S2 is sent from the I / O circuit 50 to the second buffer 22B of the transmitting circuit 20, the second buffer 22B can invert and buffer the second transmission signal S2 and output the resulting signal as the drive control signal DRV_C. When the output control signal TX_EN is enabled to a logic high level, the driver circuit 24 can drive the through-line GIO_TSV according to the drive control signal DRV_C to send the signal to the through-electrode TSV. The signal transmitted via the through-electrode TSV can be transmitted to the slave chip, thereby allowing the write (WT) operation to be performed. On the other hand, during the read operation, the second receiver 34 of the receiving circuit 30 can receive the signal transmitted through the through-electrode TSV and transmit the received signal to the I / O circuit 50 through the second global line GIO_M. The I / O circuit 50 may output received signals / data to external devices.

[0035] As described above, when the semiconductor device functions as a slave chip and a master chip, the transmitting circuit and the receiving circuit may operate in opposite manners during the read operation and the write operation.

[0036] When the semiconductor device 10 is implemented as an SDP and DDP type chip, the through-electrodes TSV are not actually formed, but the transmitting circuit 20 and the receiving circuit 30 for the through-electrodes are formed. In this case, the transmitting circuit 20 and the receiving circuit 30 that are not used can be controlled to remain in an idle state.

[0037] Figure 3 It shows that Figure 1 FIG1 is a diagram illustrating the operation of the semiconductor device 10 when it is implemented as an SDP chip, although the operation is the same or substantially the same when the semiconductor device 10 is implemented as a DDP chip. According to an embodiment, even when the semiconductor device 10 is implemented as a QDP chip and through-hole electrodes TSV are formed, although the through-hole electrodes TSV are not used, when packaged together, the semiconductor device 10 can operate as described below.

[0038] refer to Figure 3 When the semiconductor device 10 is implemented as an SDP type chip, no through-hole electrodes TSV are formed. The output control signal TX_EN, the second input control signal RDEN_M, and the first input control signal WTEN_S are disabled as logic low levels.

[0039] In response to the output control signal TX_EN at a logic low level, the pull-up drive signal PTX is fixed at a logic high level, and the pull-down drive signal NTX is fixed at a logic low level. Therefore, both the pull-up transistor P11 and the pull-down transistor N11 of the driver circuit 24 are turned off, so that the transmitting circuit 20 remains in an idle state.

[0040] In response to the first input control signal WTEN_S at a logic low level, the pull-up drive signal PRX1 is fixed to a logic high level, while the pull-down drive signal NRX1 is fixed to a logic low level. Similarly, in response to the second input control signal RDEN_M at a logic low level, the pull-up drive signal PRX2 is fixed to a logic high level, while the pull-down drive signal NRX2 is fixed to a logic low level. Similarly, the pull-up transistors and pull-down transistors in the first receiver 32 and the second receiver 34 are both turned off, so that the receiving circuit 30 remains in an idle state.

[0041] exist Figure 3In the present invention, the first global line (GIO_S), the second global line (GIO_M), and the through-line (GIO_TSV) can all latch and maintain one of a logic high level and a logic low level arbitrarily determined according to process-voltage-temperature (PVT) conditions, rather than being set to a specific value. Therefore, in the idle state, the leakage path of the pull-up transistor or the pull-down transistor of circuits 24, 32, and 34 is formed by the value latched on the first global line GIO_S, the second global line GIO_M, and the through-line GIO_TSV. For example, when the through-line GIO_TSV maintains a logic low level, a leakage path can be formed between the pull-up transistor P11 and the through-line GIO_TSV, and when the through-line GIO_TSV maintains a logic high level, a leakage path can be formed between the pull-down transistor N11 and the through-line GIO_TSV. As described above, due to the idle transmitting circuit / receiving circuit, in an SDP type or DDP type semiconductor chip, the cut-off current (i.e., the leakage current of the transistor) increases.

[0042] Described below is a method for reducing off-current caused by unused circuit(s) or circuits present only for testing when implementing various configurations in a semiconductor chip.

[0043] Before describing the embodiments of the present disclosure, bias temperature instability (BTI) is described.

[0044] Figure 4 is a diagram illustrating a BTI phenomenon in an inverter chain.

[0045] refer to Figure 4 , the PMOS transistor and the NMOS transistor may be degraded mainly due to stress in an idle state or standby state. In the idle state, since the input signal (INPUT) of the inverter chain reaches the ground voltage (VSS) level, a logic low level signal is applied to the gates of the PMOS transistor and the NMOS transistor arranged in the first stage of the inverter chain, and a logic high level signal is applied to the gates of the PMOS transistor and the NMOS transistor in the second stage of the inverter chain.

[0046] When a high electric field is applied to the gate of a PMOS transistor for a long time, the negative bias voltage used in semiconductor devices becomes unstable due to changes in temperature. This is called negative bias temperature instability (NBTI). When NBTI occurs, the threshold voltage Vth of the PMOS transistor increases, and the performance of the semiconductor memory device may deteriorate. Conversely, the increase in the threshold voltage Vth of the NMOS transistor is called positive bias temperature instability (PBTI), and when PBTI occurs, the threshold voltage Vth of the NMOS transistor increases.

[0047] That is, in the idle state, the PMOS transistor set in the first stage remains turned on, resulting in NBTI. The NMOS transistor in the second stage also remains turned on, resulting in PBTI. In normal operation, assuming that pulses of "L" → "H" → "L" are sequentially applied as the input signal (INPUT) of the inverter chain, the NMOS transistor in the first stage is turned on at the rising edge of the input signal (INPUT), and the PMOS transistor in the second stage is turned on, so that BTI does not occur. However, at the falling edge of the return input signal (INPUT) of "H" → "L", the transistor that has been degraded due to NBTI and PBTI will operate, making the reaction slow. Therefore, although the rising edge timing is constant, the falling edge timing is gradually extended, making it difficult to perform the desired operation.

[0048] Described below is a method of using such BTI to accelerate degradation of one type of transistor among PMOS transistors and NMOS transistors arranged in (one or more) test circuits or (one or more) unused circuits, thereby reducing the off-state current generated by such circuits.

[0049] Figure 5 is a view showing the configuration of a semiconductor device 100 according to an embodiment.

[0050] refer to Figure 5 , the semiconductor device 100 may include a transmitting circuit 120 and a receiving circuit 130 corresponding to the through-hole electrode TSV and a degradation acceleration circuit 170. For example, although Figure 5 The example in which the semiconductor device 100 includes the transmitting circuit 120 and the receiving circuit 130 corresponding to one through-electrode is shown. However, in practice, the semiconductor device 100 may include transmitting circuits and receiving circuits corresponding to multiple through-electrodes. In some embodiments, the semiconductor device 100 may be an SDP-type or DDP-type chip. In other words, the semiconductor device 100 may be an SDP-type or DDP-type chip including the transmitting circuit 120 and the receiving circuit 130 for the through-electrode to be unused.

[0051] The transmission circuit 120 may include a first transistor P21 and a second transistor N21 connected in series between a power supply voltage terminal VDD and a ground voltage terminal VSS and having a first common node C1 connected to a through-line GIO_TSV. The transmission circuit 120 may output a signal transmitted from the internal circuit 140 to the first common node C1 in response to an output control signal TX_END. When the semiconductor device 100 is an SDP-type or DDP-type chip, since a through-electrode TSV is not formed, the through-line GIO_TSV may be an unused line.

[0052] The receiving circuit 130 may include a third transistor P22 and a fourth transistor N22 connected in series between a power supply voltage VDD terminal and a ground voltage VSS terminal and having a second common node C2 connected to the internal circuit 140. The receiving circuit 130 may receive a signal transmitted via the through-line GIO_TSV according to a first input control signal WTEN_SD and transmit the received signal to the internal circuit 140 via the second common node C2. The receiving circuit 130 may include a fifth transistor P23 and a sixth transistor N23 connected in series between the power supply voltage VDD terminal and the ground voltage VSS terminal and having a third common node C3 connected to the input / output (I / O) circuit 150. The receiving circuit 130 may receive a signal transmitted via the through-line GIO_TSV according to a second input control signal RDEN_MD and transmit the received signal to the I / O circuit 150 through the third common node C3.

[0053] In some embodiments, the first transistor P21, the third transistor P22, and the fifth transistor P23 may be pull-up transistors and may be implemented as PMOS transistors. The second transistor N21, the fourth transistor N22, and the sixth transistor N23 may be pull-down transistors and may be implemented as NMOS transistors. Hereinafter, the first transistor P21 and the second transistor N21 may be referred to as the first pull-up transistor and the first pull-down transistor, respectively, the third transistor P22 and the fourth transistor N22 may be referred to as the second pull-up transistor and the second pull-down transistor, respectively, and the fifth transistor P23 and the sixth transistor N23 may be referred to as the third pull-up transistor and the third pull-down transistor, respectively.

[0054] The degradation acceleration circuit 170 can apply stress to the first to third pull-up transistors P21 to P23 based on a test signal TBTI. The test signal TBTI can be enabled during a test operation for a degradation acceleration operation. That is, the degradation acceleration circuit 170 can apply stress to the PMOS transistors during the degradation acceleration operation. According to an embodiment, the degradation acceleration circuit 170 can apply stress to the first to third pull-down transistors N21 to N23 based on the test signal TBTI. That is, the degradation acceleration circuit 170 can apply stress to the NMOS transistors during the degradation acceleration operation.

[0055] Specifically, the transmitting circuit 120 may include a driver control circuit 122 and a driver circuit 124. The driver control circuit 122 may include a first buffer 122A and a second buffer 122B. The driver circuit 124 may include a first NAND gate ND21, a first NOR gate NR21, a first pull-up transistor P21, and a first pull-down transistor N21. The transmitting circuit 120 may also include a first latch circuit 126 and a second latch circuit 128. Figure 5 The drive control circuit 122 and the drive circuit 124 are configured similarly to Figure 1 The drive control circuit 22 and the drive circuit 24 are substantially the same.

[0056] The receiving circuit 130 may include a first receiver 132 and a second receiver 134. The first receiver 132 may include a second pull-up transistor P22 and a second pull-down transistor N22 (the second pull-up transistor P22 and the second pull-down transistor N22 have a second common node C2 connected to the internal circuit 140 via the first global line GIO_S), and transmits a signal transmitted via the through-line GIO_TSV to the first global line GIO_S in response to a first input control signal WTEN_SD. The second receiver 134 may include a third pull-up transistor P23 and a third pull-down transistor N23 (the third pull-up transistor P23 and the third pull-down transistor N23 have a third common node C3 connected to the I / O circuit 150 via the second global line GIO_M), and transmits the signal transmitted via the through-line GIO_TSV to the second global line GIO_M in response to a second input control signal RDEN_MD. The first receiver 132 may include a second NAND gate ND22, a second NOR gate NR22, a second pull-up transistor P22, and a second pull-down transistor N22. The second receiver 134 may include a third NAND gate ND23, a third NOR gate NR23, a third pull-up transistor P23, and a third pull-down transistor N23. The receiving circuit 130 may further include a third latch circuit 136 and a fourth latch circuit 138. Figure 5 The first receiver 132, the second receiver 134, the third latch circuit 136 and the fourth latch circuit 138 are similar in configuration to Figure 1 Those are basically the same.

[0057] The degradation acceleration circuit 170 may include first to third conduction control circuits 171 to 173 and first to third bias application circuits 174 to 176 .

[0058] The first conduction control circuit 171 can control the first pull-up transistor P21 to be turned on according to the test signal TBTI. The first conduction control circuit 171 can perform a logical OR operation on the test signal TBTI and the preliminary output control signal TX_EN, and output the resulting signal as the output control signal TX_END. When the test signal TBTI is enabled as a logic high level, the first conduction control circuit 171 can output the output control signal TX_END at a logic high level. When the output control signal TX_EN is enabled as a logic high level, the driver circuit 124 can drive the through-line GIO_TSV according to the drive control signal DRV_C. Specifically, when the output control signal TX_END is enabled as a logic high level and the drive control signal DRV_C is at a logic high level, the driver circuit 124 can drive the through-line GIO_TSV with the power supply voltage VDD.

[0059] The second conduction control circuit 172 can control the second pull-up transistor P22 to be turned on according to the test signal TBTI. The second conduction control circuit 172 can perform a logical OR operation on the test signal TBTI and the first preliminary input control signal WTEN_S and output the resulting signal as the first input control signal WTEN_SD. When the test signal TBTI is enabled to a logic high level, the second conduction control circuit 172 can output the first input control signal WTEN_SD at a logic high level. When the first input control signal WTEN_SD is enabled to a logic high level, the first receiver 132 can send the signal transmitted to the through-line GIO_TSV to the first global line GIO_S. Specifically, when the first input control signal WTEN_SD is enabled to a logic high level and the signal transmitted to the through-line GIO_TSV is at a logic high level, the first receiver 132 can drive the first global line GIO_S at the power supply voltage (VDD) level.

[0060] The third conduction control circuit 173 can control the third pull-up transistor P23 to be turned on based on the test signal TBTI. The third conduction control circuit 173 can perform a logical OR operation on the test signal TBTI and the second preliminary input control signal RDEN_M, and output the resulting signal as the second input control signal RDEN_MD. When the test signal TBTI is enabled at a logic high level, the third conduction control circuit 173 can output the second input control signal RDEN_MD at a logic high level. When the second input control signal RDEN_MD is enabled at a logic high level, the second receiver 134 can transmit the signal transmitted to the through-line GIO_TSV to the second global line GIO_M. Specifically, when the second input control signal RDEN_MD is enabled at a logic high level and the signal transmitted to the through-line GIO_TSV is at a logic high level, the second receiver 134 can drive the second global line GIO_M at the power supply voltage (VDD) level.

[0061] The first bias application circuit 174 can fix the drive control signal DRV_C to the power supply voltage (VDD) level based on the test signal TBTI. When the test signal TBTI is enabled at a logic high level, that is, when the inverted signal TBTIB of the test signal TBTI is at a logic low level and is therefore enabled, the first bias application circuit 174 can apply the power supply voltage (VDD) level to the control node NO_C0. The first bias application circuit 174 can be implemented as a PMOS transistor, which is connected between the power supply voltage VDD terminal and the control node NO_C0 and receives the inverted signal TBTIB of the test signal TBTI through its gate.

[0062] The second bias application circuit 175 can fix the second common node C2 and the third common node C3 at the ground voltage (VSS) level according to the test signal TBTI. When the inverting signal TBTIB is enabled to a logic high level, the second bias application circuit 175 can ground the second common node C2 and the third common node C3 to the ground voltage (VSS) level. The second bias application circuit 175 can be implemented as an NMOS transistor N24 and an NMOS transistor N25, wherein the NMOS transistor N24 is connected between the ground voltage VSS terminal and the second common node C2 and receives the inverting signal TBTIB through the gate, and the NMOS transistor N25 is connected between the ground voltage VSS terminal and the third common node C3 and receives the inverting signal TBTIB through the gate.

[0063] The third bias application circuit 176 can fix the through-line GIO_TSV to the ground voltage (VSS) level according to the test signal TBTI. When the inverting signal TBTIB is enabled to a logic high level, the third bias application circuit 176 can ground the through-line GIO_TSV to the ground voltage (VSS) level. The third bias application circuit 176 can be implemented as an NMOS transistor, which is connected between the ground voltage VSS terminal and the through-line GIO_TSV and receives the inverting signal TBTIB through the gate.

[0064] Reference below Figures 5 to 7 A method of operating the semiconductor device 100 will be described.

[0065] Figure 6 It shows Figure 5 FIG. 1 is a diagram illustrating a degradation-accelerating operation of the semiconductor device 100 .

[0066] refer to Figure 6 During the degradation acceleration operation, the test signal TBTI becomes a logic high level and the inversion signal TBTIB becomes a logic low level. In this case, the first bias applying circuit 174 may apply the power supply voltage (VDD) level to the control node NO_C0 according to the test signal TBTI.

[0067] The first conduction control circuit 171 performs a logical OR operation on the test signal TBTI and the preliminary output control signal TX_EN, and outputs the output control signal TX_END at a logic high level. The second conduction control circuit 172 performs a logical OR operation on the test signal TBTI and the first preliminary input control signal WTEN_S, and outputs the first input control signal WTEN_SD at a logic high level. The third conduction control circuit 173 performs a logical OR operation on the test signal TBTI and the second preliminary input control signal RDEN_M, and outputs the second input control signal RDEN_MD at a logic high level. Therefore, all pull-up drive signals PTX, PRX1, and PRX2 become a logic low level, so that the first pull-up transistor P21 to the third pull-up transistor P23 are all controlled to be turned on. To prevent signal conflicts, both the master select signal TSV_S and the slave select signal TSV_M can be disabled to a logic low level.

[0068] That is, during the degradation acceleration operation, stress is applied to the PMOS transistor, thereby causing an NBTI phenomenon and thus increasing the threshold voltage Vth of the PMOS transistor. Therefore, degradation of the PMOS transistor is accelerated.

[0069] Figure 7 It shows Figure 5 FIG. 1 is a view of a normal operation of the semiconductor device 100 .

[0070] refer to Figure 7 During normal operation, the test signal TBTI becomes a logic low level, and the inverted signal TBTIB becomes a logic high level. The preliminary output control signal TX_EN, the first preliminary input control signal WTEN_S, and the second preliminary input control signal RDEN_M are disabled as logic low levels.

[0071] The second bias application circuit 175 can be enabled according to the inverting signal TBTIB, thereby fixing the second common node C2 and the third common node C3 to the ground voltage (VSS) level. The third bias application circuit 176 can be enabled according to the inverting signal TBTIB, thereby fixing the through-line GIO_TSV to the ground voltage (VSS) level. The first conduction control circuit 171 performs a logical OR operation on the test signal TBTI and the preliminary output control signal TX_EN, and outputs the output control signal TX_END at a logic low level. The second conduction control circuit 172 performs a logical OR operation on the test signal TBTI and the first preliminary input control signal WTEN_S, and outputs the first input control signal WTEN_SD at a logic low level. The third conduction control circuit 173 performs a logical OR operation on the test signal TBTI and the second preliminary input control signal RDEN_M, and outputs the second input control signal RDEN_MD at a logic low level.

[0072] Therefore, all pull-up drive signals PTX, PRX1, and PRX2 become logic high, and all pull-down drive signals NTX, NRX1, and NRX2 become logic low. Therefore, both the first pull-up transistor P21 and the first pull-down transistor N21 of the driver circuit 124 are turned off, so that the transmitting circuit 120 remains in an idle state. Similarly, the second pull-up transistor P22 and the third pull-up transistor P23, as well as the second pull-down transistor N22 and the third pull-down transistor N23 of the first receiver 132 and the second receiver 34 are all turned off, so that the receiving circuit 130 remains in an idle state.

[0073] In this case, the through wire GIO_TSV, the second common node C2, and the third common node C3 are all grounded, so that a leakage path occurs only in the first to third pull-up transistors P21 to P23 that have been degraded due to the application of stress. Figure 3 While leakage current occurs in all PMOS and NMOS transistors during normal operation of the SDP or DDP chip described above, leakage current occurs only in the PMOS transistors during normal operation of the SDP or DDP chip according to the embodiment. Therefore, the total off-state current can be reduced.

[0074] Figure 8is a view illustrating a method for operating a semiconductor device according to an embodiment.

[0075] refer to Figure 8 , a method of operating a semiconductor device may include providing a semiconductor device (at operation S810 ), performing a test operation (at operation S820 ), and performing a normal operation (at operation S830 ).

[0076] In providing the semiconductor device (at operation S810 ), the semiconductor device is manufactured. Operation S810 may include: forming a semiconductor substrate (operation S812 ); forming circuit elements such as transistors on the semiconductor substrate (operation S814 ); and forming through electrodes (operation S816 ).

[0077] Specifically, the semiconductor substrate is formed of silicon in the form of a wafer or is divided into chip units (at operation S812). The semiconductor substrate may include a first surface and a second surface. The first surface of the semiconductor substrate may be a surface on which an active region exists (circuit elements are formed on the active region) and may be referred to as the front surface. The second surface of the semiconductor substrate may be a surface opposite to the first surface and may be referred to as the back surface.

[0078] Next, transistors may be formed on and within the first surface of the semiconductor substrate (at operation S814), each having a gate and a source / drain on either side of each gate. In this case, the transistors may include: a first pull-up transistor P21 and a first pull-down transistor N21 that drive a first common node C1 connected to a through-line GIO_TSV; a second pull-up transistor P22 and a second pull-down transistor N22 that receive a signal transmitted via the through-line GIO_TSV and drive a second common node C2 connected to a first global line GIO_S; and a third pull-up transistor P23 and a third pull-down transistor N23 that receive a signal transmitted via the through-line GIO_TSV and drive a third common node C3 connected to a second global line GIO_M. In the case of a DRAM device, in addition to the aforementioned transistors, a bit line and a capacitor may also be formed on the first surface of the semiconductor substrate.

[0079] Then, it can be determined whether a through electrode connected to the through-line GIO_TSV is formed (at operation S816). For example, when the semiconductor device is a QDP type chip or a 3-dimensional stacked (3DS) semiconductor chip, a through electrode needs to be formed, but when the semiconductor device is an SDP type or DDP type chip, a through electrode does not need to be formed. When the semiconductor device is a 3DS type chip, a through electrode is formed (at operation S818). The through electrode may include: a through hole vertically penetrating the semiconductor substrate; a barrier layer formed on the inner sidewall of the through hole; and a metal layer formed on the barrier layer and filling the through hole. The through hole may extend from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate. The barrier layer can inhibit the metal material included in the metal layer from diffusing into the semiconductor substrate. The metal layer may include copper (Cu), but is not particularly limited thereto.

[0080] When the processing of the semiconductor device is completed, a test operation can be performed (at operation S820). The test operation may include an aging test, in which the product is tested in an environment worse than the actual environment by applying excessive stress to the semiconductor device for a short period of time. In the aging test, not only direct current (DC) can be tested, but also read operations and write operations can be tested. In the case of a 3DS type semiconductor device, a general aging test can be performed (at operation S824). In the case of an SDP type or DDP type semiconductor device, a degradation acceleration operation (at operation S822) can be additionally performed during the test operation according to the embodiment. That is, as described above in combination with Figure 6 As described, during the degradation acceleration operation, stress is applied only to the PMOS transistor, thereby causing the NBTI phenomenon and increasing the threshold voltage Vth of the first to third pull-up transistors P21 to P23 as the PMOS transistors, thereby accelerating the degradation of the PMOS transistors.

[0081] Thereafter, normal operation of the semiconductor device, for example, the SDP type or the DDP type, may be performed (at operation S830). The normal operation may include a read operation and / or a write operation. Figure 7 As shown, during normal operation, when the transmitting circuit 120 and the receiving circuit 130 remain in an idle state, the through-line GIO_TSV, the second common node C2, and the third common node C3 are all grounded, creating leakage paths from the degraded first to third pull-up transistors P21 to P23 to the first to third common nodes C1 to C3, respectively. In other words, when an SDP-type or DDP-type chip performs normal operation, leakage current is generated only by the PMOS transistors, thereby reducing the total off-state current.

[0082] In the above embodiments, the transmitting circuit / receiving circuit for the through-electrode has been described as an example, but the embodiments of the present disclosure are not limited thereto. For example, the embodiments of the present disclosure can be widely applied to any circuit that exists only for (one or more) test operations, any input / output (I / O) circuit that should not be used, and / or a clock tree repeater.

[0083] Figure 9 is a view showing a configuration of a semiconductor device 200 according to an embodiment. Figure 9 The semiconductor device 200 may be a memory device.

[0084] refer to Figure 9 , the semiconductor device 200 may include a memory cell array 210 , a first pad group PG1 , a second pad group PG2 , a data alignment circuit 220 , a first driving circuit 230 , a second driving circuit 240 , and a degradation acceleration circuit 250 .

[0085] The first pad group PG1 may include a plurality of first input / output pads LDQ. The second pad group PG2 may include a plurality of second input / output pads UDQ. When the data width option is set to X8 mode or X16 mode, the first input / output pads LDQ may input / output data. The second input / output pads UDQ may input / output data only when the data width option is set to X16 mode, and when the data width option is set to X8 mode, the second input / output pads UDQ may be disabled, that is, not used. For example, when the data width option is set to X8 mode, data may be input / output through the first input / output pads LDQ of the first pad group PG1, and when the data width option is set to X16 mode, data may be input / output through the first input / output pads LDQ of the first pad group PG1 and the second input / output pads UDQ of the second pad group PG2. Figure 9 An example is shown in which each of the first pad group PG1 and the second pad group PG2 includes eight input / output pads.

[0086] The data alignment circuit 220 can align the set burst length (BL, for example, BL=8) of the serial data input through the first pad group PG1 and / or the second pad group PG2. For example, the data alignment circuit 220 may include: an input buffer (not shown) for receiving data input through the first pad group PG1 and / or the second pad group PG2 during a write operation; a deserializer (not shown) for deserializing the received data; and a write pipe latch (not shown) for latching the deserialized data, and can deserialize and latch the serial data to output parallel data. In the x8 mode, the data alignment circuit 220 can provide 64 parallel data segments by aligning the 8-bit serial data input through the eight first input / output pads LDQ. In X16 mode, the data alignment circuit 220 can align the 8-bit serial data input through the 8 first input / output pads LDQ and provide 64 parallel data segments, and then the data alignment circuit 220 can align the 8-bit serial data input through the 8 second input / output pads UDQ and provide 64 parallel data segments.

[0087] The first driver circuit 230 may include a first pull-up transistor P31 and a first pull-down transistor N31, which are connected in series between a power supply voltage VDD terminal and a ground voltage VSS terminal and include a common node C1 connected to the global data line GIO. The first driver circuit 230 can transmit data sent from the first pad group PG1 via the data alignment circuit 220 to the global data line GIO according to the first drive control signal X8_EN. In some embodiments, the first drive control signal X8_EN can be enabled in X8 mode and X16 mode. The first driver circuit 230 may include as many first drivers L_DRV1 to L_DRV64 as the number of global data lines GIO (e.g., 64). For example, the first drivers L_DRV1 to L_DRV64 can be arranged in an array.

[0088] Specifically, each of the first drivers L_DRV1 to L_DRV64 may include a first NAND gate ND31, a first NOR gate NR31, a first pull-up transistor P31, and a first pull-down transistor N31. The first NAND gate ND31 may perform a logical NAND operation on data input from the first drive control signal X8_EN and data input from one of the first input / output pads LDQ, and output the resulting signal as a pull-up drive signal PU_LDQ. The first NOR gate NR31 may perform a logical NOR operation on the data and an inverted signal X8_ENB of the first drive control signal X8_EN, and output the resulting signal as a pull-down drive signal PD_LDQ. The first pull-up transistor P31 may drive the corresponding global data line GIO at a power supply voltage (VDD) level according to the pull-up drive signal PU_LDQ. The first pull-down transistor N31 may drive the corresponding global data line GIO at a ground voltage (VSS) level according to the pull-down drive signal PD_LDQ. In some embodiments, the first pull-up transistor P31 may be configured as a PMOS transistor, and the first pull-down transistor N31 may be configured as an NMOS transistor. Through the above configuration, when the first drive control signal X8_EN is enabled to a logic high level, the first drive circuit 230 may drive the global data line GIO according to data input from the first input / output pad LDQ.

[0089] The second driver circuit 240 may include a second pull-up transistor P32 and a second pull-down transistor N32 connected in series between a power supply voltage VDD terminal and a ground voltage VSS terminal and including a common node C2 connected to the global data line GIO. The second driver circuit 240 may transmit data transmitted from the second pad group PG2 via the data alignment circuit 220 to the global data line GIO according to the second driver control signal X16_END. In some embodiments, the second driver control signal X16_END may be enabled when the second preliminary driver control signal X16_EN or the test signal TBTI is enabled. The second preliminary driver control signal X16_EN may be enabled in X16 mode, and the test signal TBTI may be a signal enabled for degradation acceleration operation during a test operation. The second driver circuit 240 may include as many second drivers U_DRV1 to U_DRV64 as the number of global data lines GIO (e.g., 64). For example, the second drivers U_DRV1 to U_DRV64 may be arranged in an array.

[0090] Specifically, each of the second drivers U_DRV1 to U_DRV64 may include a second NAND gate ND32, a second NOR gate NR32, a second pull-up transistor P32, and a second pull-down transistor N32. The second NAND gate ND32 may perform a logical NAND operation on data input from the second drive control signal X16_END and data input from one of the second input / output pads UDQ, and output a pull-up drive signal PU_UDQ. The second NOR gate NR32 may perform a logical NOR operation on the data and the inverted signal X16_ENB of the second preliminary drive control signal X16_EN, thereby outputting a pull-down drive signal PD_UDQ. The second pull-up transistor P32 may drive the corresponding global data line GIO at a power supply voltage (VDD) level according to the pull-up drive signal PU_UDQ. The second pull-down transistor N32 may drive the corresponding global data line GIO at a ground voltage (VSS) level according to the pull-down drive signal PD_UDQ. In some embodiments, the second pull-up transistor P32 may be configured as a PMOS transistor, and the second pull-down transistor N32 may be configured as an NMOS transistor.

[0091] The degradation acceleration circuit 250 may apply stress only to the second pull-up transistor P32 according to the test signal TBTI. According to an embodiment, the degradation acceleration circuit 250 may apply stress only to the second pull-down transistor N32 according to the test signal TBTI.

[0092] Specifically, the degradation acceleration circuit 250 may include a bias application circuit 251 and a conduction control circuit 252. The bias application circuit 251 can fix the data sent from the second pad group PG2 to the power supply voltage (VDD) level according to the test signal TBTI. When the test signal TBTI is enabled to a logic high level, that is, when the inverted signal TBTIB of the test signal TBTI is at a logic low level, the bias application circuit 251 can apply the power supply voltage (VDD) level to the control node NO_C1 to which the data is transmitted. The bias application circuit 251 can be implemented as a PMOS transistor that is connected between the power supply voltage VDD terminal and the control node NO_C1 and receives the inverted signal TBTIB of the test signal TBTI through the gate of the PMOS transistor. The conduction control circuit 252 can control the second pull-up transistor P32 to be turned on according to the test signal TBTI. The conduction control circuit 252 can perform a logical OR operation on the test signal TBTI and the second preliminary drive control signal X16_EN and output the result signal as the second drive control signal X16_END. When the test signal TBTI is enabled to a logic high level, the conduction control circuit 252 can output the second drive control signal X16_END at a logic high level.

[0093] The memory cell array 210 may include a plurality of memory banks (not shown), each including a plurality of memory cells connected between a plurality of word lines (not shown) and a plurality of bit lines (not shown). The memory cell array 210 may be connected to a first driver circuit 230 and a second driver circuit 240 via a global data line GIO, thereby allowing each memory bank to receive data input via a first pad group PG1 and a second pad group PG2. The semiconductor device 200 may further include a latch circuit 260 for latching data transmitted via the global data line GIO and maintaining a logic level. The latch circuit 260 may include two inverters connected in series.

[0094] For the purpose of cost saving, a configuration supporting all data width options of X8 mode or X16 mode can be implemented in a single semiconductor device. In this case, when the semiconductor device operates only in X8 mode, the circuit configuration related to X16 mode is not used. According to an embodiment, the semiconductor device 200 can be a semiconductor device in which the data width option is set to X8 mode. When the semiconductor device 200 operates only in X8 mode, the off-state current caused by the unused circuit can be reduced by accelerating the degradation of the PMOS transistor in the circuit configuration related to the unused X16 mode.

[0095] A method of operating the semiconductor device 200 is described below.

[0096] During the degradation acceleration operation, the test signal TBTI becomes a logic high level, and the inverting signal TBTIB becomes a logic low level. In this case, the bias application circuit 251 can apply the power supply voltage (VDD) level to the control node NO_C1 according to the test signal TBTI. The conduction control circuit 252 performs a logical OR operation on the test signal TBTI and the second preliminary drive control signal X16_EN, and outputs the second drive control signal X16_END at a logic high level. Therefore, the pull-up drive signal PU_UDQ becomes a logic low level, thereby controlling the second pull-up transistor P32 to be turned on. Therefore, during the degradation acceleration operation, stress is applied to the PMOS transistor of the second drive circuit 240 that is not to be used, thereby causing the NBTI phenomenon and thereby increasing the threshold voltage Vth of the PMOS transistor. Therefore, the degradation of the PMOS transistor is accelerated.

[0097] During normal operation, the test signal TBTI becomes a logic low level, and the inverted signal TBTIB becomes a logic high level. When the semiconductor device 200 operates in the X8 mode, the first drive control signal X8_EN is enabled at a logic high level, and the second preliminary drive control signal X16_EN is disabled at a logic low level. The conduction control circuit 252 performs a logical OR operation on the test signal TBTI and the second preliminary drive control signal X16_EN and outputs the second drive control signal X16_END at a logic low level.

[0098] When the first drive control signal X8_EN is enabled at a logic high level, the first drive circuit 230 can drive the global data line GIO according to the data input from the first input / output pad LDQ. On the other hand, in the second drive circuit 240, when the second drive control signal X16_END is disabled at a logic low level and the inverting signal X16_ENB is disabled at a logic high level, the pull-up drive signal PU_UDQ becomes a logic high level, and the pull-down drive signal PD_UDQ becomes a logic low level. Therefore, both the second pull-up transistor P32 and the second pull-down transistor N32 of the second drive circuit 240 are turned off, so that the second drive circuit 240 remains in an idle state. In this case, the second pull-up transistor P32, which has degraded due to the applied stress, creates a leakage path, thereby reducing the total off-state current.

[0099] As described above, according to embodiments, when various configurations are implemented in one semiconductor chip, a memory device can reduce the off-current caused by (one or more) unused circuits by accelerating the degradation of certain types of transistors in (one or more) unused circuits. According to embodiments, a semiconductor device can reduce the off-current caused by (one or more) unused circuits by accelerating the degradation of certain types of transistors in (one or more) circuits that exist only for testing.

[0100] It should be noted that although the present invention has been described in conjunction with various embodiments thereof, this is for descriptive purposes only and should not be construed as limiting. Those skilled in the art will appreciate that various changes may be made to any of the disclosed embodiments without departing from the technical spirit of the present disclosure. For reference, in the case of a QDP-type chip, when a through-hole electrode TSV is formed and encapsulated but the through-hole electrode TSV is not used, the above-mentioned degradation acceleration circuit may be implemented.

[0101] For example, the logic gates and transistors provided as examples in the above embodiments may be of different types and may be arranged at different positions according to the polarity of an input signal.

Claims

1. A semiconductor device comprising: A transmitting circuit comprising: a first transistor and a second transistor coupled in series between a first voltage terminal and a second voltage terminal; and a first common node coupled between the first transistor and the second transistor and coupled to a pass-through line, wherein the transmitting circuit transmits a signal transmitted from an internal circuit to the first common node according to an output control signal; a receiving circuit comprising: a third transistor and a fourth transistor coupled in series between the first voltage terminal and the second voltage terminal; and a second common node coupled between the third transistor and the fourth transistor and coupled to the internal circuit, the receiving circuit transmitting a signal transmitted via the through-line to the internal circuit according to a first input control signal; and A degradation acceleration circuit is configured to accelerate degradation of the first transistor and the third transistor by applying stress to the first transistor and the third transistor according to a test signal.

2. The semiconductor device according to claim 1, wherein The degradation acceleration circuit includes: a first conduction control circuit configured to control the output control signal according to the test signal to turn on the first transistor; and The second conduction control circuit is configured to control the first input control signal according to the test signal to turn on the third transistor.

3. The semiconductor device according to claim 1, wherein The semiconductor device includes a single-die package type semiconductor chip or a dual-die package type semiconductor chip.

4. The semiconductor device according to claim 1, wherein The sending circuit includes: a drive control circuit for generating a drive control signal by selecting a first transfer signal transferred from the first global line or a second transfer signal transferred from the second global line according to a selection signal; and A driving circuit including the first transistor and the second transistor is configured to drive the first common node by controlling the first transistor and the second transistor according to the driving control signal when the output control signal is enabled.

5. The semiconductor device according to claim 4, wherein The degradation acceleration circuit includes: a first bias applying circuit for fixing the driving control signal to a first level according to the test signal; and The first conduction control circuit is configured to control the output control signal according to the test signal to turn on the first transistor. The semiconductor device according to claim 1 , wherein: The receiving circuit includes: a first receiver including the third transistor, the fourth transistor, and the second common node, the second common node being coupled between the third transistor and the fourth transistor and coupled to the internal circuit via a first global line, the first receiver transmitting a signal transmitted via the pass-through line to the first global line according to the first input control signal; and a second receiver including a fifth transistor and a sixth transistor and a third common node, wherein the third common node is coupled between the fifth transistor and the sixth transistor and coupled to the input / output circuit through a second global line, and the second receiver transmits the signal transmitted through the through line to the second global line according to a second input control signal.

7. The semiconductor device according to claim 6, wherein The degradation acceleration circuit includes: a second bias applying circuit for fixing the second common node and the third common node to a second level according to an inverted signal of the test signal; a third bias applying circuit, configured to fix the through-line to the second potential according to the inverted signal; a second conduction control circuit for controlling the first input control signal to turn on the third transistor according to the test signal; and The third conduction control circuit is configured to control the second input control signal according to the test signal to turn on the fifth transistor.

8. The semiconductor device according to claim 6, wherein The first transistor, the third transistor, and the fifth transistor are PMOS transistors, and wherein the second transistor, the fourth transistor, and the sixth transistor are NMOS transistors.

9. A semiconductor device comprising: a first pull-up transistor and a first pull-down transistor coupled to the through line through a first common node and receiving a driving control signal transmitted from the first global line or the second global line according to an output control signal to drive the first common node; a second pull-up transistor and a second pull-down transistor coupled to the first global line via a second common node and receiving a signal transmitted via the through line according to a first input control signal to drive the second common node; a third pull-up transistor and a third pull-down transistor coupled to the second global line via a third common node and receiving a signal transmitted via the through line according to a second input control signal to drive the third common node; as well as A degradation acceleration circuit is configured to accelerate degradation of the first to third pull-up transistors by applying stress to the first to third pull-up transistors according to a test signal.

10. The semiconductor device according to claim 9, wherein The degradation acceleration circuit includes: a first conduction control circuit, configured to control the output control signal according to the test signal to turn on the first pull-up transistor; a second conduction control circuit configured to control the first input control signal according to the test signal to turn on the second pull-up transistor; and A third conduction control circuit is configured to control the second input control signal according to the test signal to turn on the third pull-up transistor.

11. The semiconductor device according to claim 10, further comprising: A drive control circuit is configured to generate the drive control signal by selecting a first transfer signal transferred from the first global line or a second transfer signal transferred from the second global line according to a selection signal.

12. The semiconductor device according to claim 11, wherein The degradation acceleration circuit includes: a first bias applying circuit, configured to fix the driving control signal to a first level according to the test signal; a second bias applying circuit for fixing the second common node and the third common node to a second level according to an inverted signal of the test signal; and A third bias applying circuit is configured to fix the through-line to the second potential according to the inverted signal.

13. The semiconductor device according to claim 9, wherein The first to third pull-up transistors are PMOS transistors, and wherein The first to third pull-down transistors are NMOS transistors.

14. The semiconductor device according to claim 9, wherein The semiconductor device includes a single-die package type semiconductor chip or a dual-die package type semiconductor chip.

15. A method for operating a semiconductor device, the method comprising: driving a first common node coupled to the first pull-up transistor and the first pull-down transistor and further coupled to a through-line, receiving a signal transmitted via the through-line, driving a second common node coupled to the second pull-up transistor and the second pull-down transistor and further coupled to a first global line, and receiving a signal transmitted via the through-line and driving a third common node coupled to the third pull-up transistor and the third pull-down transistor and further coupled to a second global line; accelerating degradation of the first to third pull-up transistors by performing a degradation acceleration operation to apply stress to the first to third pull-up transistors during a test operation; as well as During normal operation, the first common node to the third common node are driven at a ground voltage level.

16. The method according to claim 15, wherein The semiconductor device includes a single-die package type semiconductor chip or a dual-die package type semiconductor chip.

17. The method according to claim 15, wherein: During the degradation acceleration operation, threshold voltages of the first to third pull-up transistors are increased, thereby accelerating degradation of the first to third pull-up transistors.

18. The method according to claim 15, wherein During the normal operation, a leakage path is formed in each pair of the first to third pull-up transistors and the first to third common nodes.

19. A semiconductor device comprising: a first driving circuit comprising: a first transistor and a second transistor coupled in series between a first voltage terminal and a second voltage terminal; and a first common node coupled between the first transistor and the second transistor and coupled to a predetermined line, wherein the first driving circuit transmits data transmitted from the first pad group to the predetermined line according to a first driving control signal; a second driving circuit comprising: a third transistor and a fourth transistor coupled in series between the first voltage terminal and the second voltage terminal; and a second common node coupled between the third transistor and the fourth transistor and coupled to the predetermined line, wherein the second driving circuit transmits data transmitted from the second pad group to the predetermined line according to a second driving control signal; and A degradation acceleration circuit is configured to accelerate degradation of the third transistor by applying stress to the third transistor according to a test signal.

20. The semiconductor device according to claim 19, wherein The data width option of the semiconductor device is set to a x8 mode, so that the second pad group includes a plurality of unused pads.

21. The semiconductor device according to claim 19, wherein The degradation acceleration circuit includes: a bias applying circuit for fixing data transmitted from the second pad group to a first level according to the test signal; and The conduction control circuit is configured to control the second driving control signal according to the test signal to turn on the third transistor.

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