Memory system

Abstract

The standby time t required for the memory system of the embodiment to perform the process of outputting to the controller WHR2 During this period, the read enable signals RE and / RE are output, and the preset virtual data in the signals DQS and / DQS and the signal DQ are output from the output circuit.

Description

Technical Field

[0001] Embodiments relate to a memory system. Background Art

[0002] A NAND (Not-AND) type flash memory is known as a semiconductor memory device.

[0003] [Previous technical literature]

[0004] [Patent Document]

[0005] Patent Document 1: U.S. Patent No. 8913448 Summary of the invention

[0006] [Problems to be solved by the invention]

[0007] Embodiments provide a memory system capable of improving data read reliability.

[0008] [Technical means to solve the problem]

[0009] The memory system of the embodiment comprises: a semiconductor memory; and a controller, which gives instructions for reading data from the semiconductor memory; and the semiconductor memory comprises: a memory cell transistor, which holds data; an output circuit, which processes the data read from the memory cell transistor for output to the controller; and a data generating circuit, which generates first data; and when reading the data, the controller outputs a first signal to the semiconductor memory during a first period in which the output circuit performs the processing, the semiconductor memory generates a second signal based on the first signal, and outputs the first data together with the second signal to the controller during the first period and the second period, and after the second period ends, the semiconductor memory outputs the data read from the memory cell transistor together with the second signal to the controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a block diagram conceptually showing the overall structure of a memory system according to an embodiment.

[0011] Figure 2 This is a block diagram showing an example of the configuration of a NAND flash memory.

[0012] Figure 3 This is a circuit diagram showing a configuration example of a memory cell array of a NAND flash memory.

[0013] Figure 4 This is a block diagram showing a configuration example of an output circuit.

[0014] Figure 5This is a flowchart of an example to be compared with the embodiment.

[0015] Fig. 6A This is a timing chart for explaining the data output operation of the object example for comparison with the embodiment.

[0016] Figure 6B This is a timing chart for explaining stabilization of power supply output in the data output operation of the first embodiment.

[0017] Figure 7 This is a flowchart for explaining stabilization of power supply output in the data output operation according to the first embodiment.

[0018] Figure 8 This is a timing chart showing the timing of each signal of the standby time and the delay time in the first setting example.

[0019] Fig. 9 This is a timing chart showing the timing of each signal of the standby time and the delay time in the second setting example.

[0020] Fig.10 It is a timing chart showing the timing of each signal of the standby time and the delay time in the third setting example.

[0021] Fig.11 It is a timing chart showing the timing of each signal of the standby time and the delay time in the fourth setting example.

[0022] Fig.12 This is a flowchart for explaining stabilization of power supply output in the data output operation according to the second embodiment.

[0023] Fig.13 This is a flowchart for explaining stabilization of power supply output in the data output operation according to the third embodiment.

[0024] Fig.14 This is a flowchart for explaining stabilization of power supply output in the data output operation according to the fourth embodiment.

[0025] Fig.15 This is a timing chart showing the timing of each signal of the electric standby time and the delay time in the fifth embodiment. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments will be described with reference to the drawings.

[0027] The embodiments illustrate devices used to embody the technical ideas of the invention. The drawings are schematic or conceptual, and the dimensions and proportions of the drawings may not be the same as the actual objects. Moreover, the technical ideas of the present invention are not specified by the shape, structure, and arrangement of the constituent elements. In addition, in the following description, constituent elements having substantially the same functions and structures are marked with the same symbols, and detailed descriptions are omitted.

[0028] [First embodiment]

[0029] The memory system according to the first embodiment will be described.

[0030] <Overall memory system configuration>

[0031] Figure 1 It is a configuration diagram conceptually showing the overall configuration of the memory system 1 according to the present embodiment.

[0032] The memory system 1 of this embodiment includes at least a semiconductor memory 3 and a memory controller (controller) 2 for controlling the semiconductor memory 3. In this embodiment, the semiconductor memory 3 can be any non-volatile memory, and is preferably a NAND flash memory, for example. In the following description, an example in which the semiconductor memory 3 is applied to the NAND flash memory 3 as a semiconductor storage device is described.

[0033] The memory controller 2 and the NAND flash memory 3 can be combined to form a semiconductor device. As an example, there is SD (Secure Digital) TM A memory card such as a card, or an SSD (solid state drive), etc. In addition, the memory controller 2 can use an SoC (system on chip) or the like.

[0034] The NAND flash memory 3 has a plurality of memory cell transistors and stores data in a non-volatile manner. The memory controller 2 is connected to the NAND flash memory 3 via a NAND bus. In addition, the memory controller 2 is also connected to an external host machine 4 via a host bus. The memory controller 2 controls the NAND flash memory 3 and accesses the NAND flash memory 3 in response to commands received from the host machine 4. The host machine 4 is, for example, a digital camera or a personal computer, and the host bus is based on, for example, an SD card. TM The NAND bus is used to send and receive signals based on the NAND interface.

[0035] <Configuration of memory controller 2>

[0036] refer to Figure 1 , the details of the structure of the memory controller 2 are explained.

[0037] The memory controller 2 controls the NAND flash memory 3. As a specific example, the memory controller 2 performs control to write data into the NAND flash memory 3 and read stored data from the NAND flash memory 3.

[0038] The memory controller 2 includes a host interface circuit (host I / F) 5, a built-in memory (RAM: Random Access Memory) 6, a processor (CPU: Central Processing Unit) 7, a buffer memory 8, a NAND interface circuit (NAND I / F) 9, and an ECC (Error Checking and Correcting) circuit 10. In addition, various other components are also mounted according to the design.

[0039] The host interface circuit 5 is connected to the host machine 4 via a host bus, and transfers commands and data received from the host machine 4 to the processor 7 and the buffer memory 8. In addition, the data in the buffer memory 8 is transferred to the host machine 4 according to the command of the processor 7.

[0040] The processor 7 controls the overall operation of the memory controller 2. For example, when the processor 7 receives a command to write data from the host machine 4, it issues a write command to the NAND interface circuit 9 based on the reception. The same applies to reading and erasing data. In addition, the processor 7 performs various processes for managing the NAND flash memory 3, such as wear leveling. In addition, the operation of the memory controller 2 described below can be implemented by the processor 7 executing software (firmware), or can also be implemented by hardware.

[0041] The NAND interface circuit 9 is connected to the NAND flash memory 3 via a NAND bus and is responsible for communication with the NAND flash memory 3. The NAND interface circuit 9 sends and receives various signals to and from the NAND flash memory 3 based on commands received from the processor 7. The buffer memory 8 temporarily stores write data or read data.

[0042] The built-in memory (RAM) 6 is a semiconductor memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), and is used as a work area of ​​the processor 7. The built-in memory 6 holds firmware for managing the NAND flash memory 3 and various management tables.

[0043] The ECC circuit 10 performs error detection and error correction processing on the data stored in the NAND flash memory 3. That is, the ECC circuit 10 generates an error correction code when writing data and applies it to the write data, and decodes the error correction code when reading data.

[0044] <NAND bus of NAND flash memory>

[0045] refer to Figure 2 , the NAND bus is described.

[0046] The memory controller 2 is connected to the NAND flash memory 3 via a NAND bus. The NAND bus includes a plurality of signal lines, which are divided into a signal line group connected to an input / output pad group 21 connected to the input / output circuit 12 and a signal line group connected to a logic control pad group 22 connected to the logic control circuit 13.

[0047] The signal lines transmit and receive chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal / RE, write protection signal / WP, ready / busy signal / RB, data signal DQ, data strobe signal DQS, and / DQS according to the NAND interface. Signals CLE, ALE, / WE, / RE, and / WP are received by the NAND flash memory 3. Moreover, signal / RB and signal / CE are received by the NAND flash memory 3, respectively.

[0048] The chip enable signal / CE is a signal for enabling the NAND flash memory 3. The command latch enable signal CLE can latch the command CMD sent as the data signal DQ into the command register 15A of the register 15 described later. The signal CLE notifies the NAND flash memory 3 that the signal DQ flowing into the NAND flash memory 3 during the period when the signal CLE is at the "H (High)" level is the command CMD. The signal DQ is, for example, an 8-bit signal.

[0049] The address latch enable signal ALE can latch the address ADD sent as the data signal DQ into the address register 15B of the register 15 described later. The signal ALE notifies the NAND flash memory 3 that the signal DQ sent to the NAND flash memory 3 during the period when the signal ALE is at the "H" level is the address ADD. The write enable signal / WE enables writing. The signal / WE instructs to extract the signal DQ sent to the NAND flash memory 3 during the period when the signal / WE is at the "L (Low)" level to the NAND flash memory 3.

[0050] The read enable signal RE and / RE indicate the output of the data signal DQ to the NAND flash memory 3, and are used, for example, to control the operation timing of the NAND flash memory 3 when the signal DQ is output. The write protection signal / WP indicates to the NAND flash memory 3 that data writing and erasing are prohibited. The ready / busy signal / RB indicates whether the NAND flash memory 3 is in the ready state (a state of accepting commands from the outside) or the busy state (a state of not accepting commands from the outside).

[0051] The data signal DQ is, for example, an 8-bit signal. The signal DQ is the entity of the data sent and received between the NAND flash memory 3 and the memory controller 2, and includes a command CMD, an address ADD, and data DAT. The bidirectional data strobe signals DQS and / DQS that can be used as reference signals are used, for example, to control the operation timing of the NAND flash memory 3 under the signal DQ.

[0052] <NAND flash memory structure>

[0053] Next reference Figure 2 , an example of the structure of NAND type flash memory 3 is explained.

[0054] The NAND flash memory 3 has a memory cell array 11, an input / output circuit 12, a logic control circuit 13, a register 15, a sequence generator 16, a voltage generating circuit 17, a driver 18, a row decoder 19, a sense amplifier 20, an input / output pad group 21, a logic control pad group 22, a data generating circuit 14, etc.

[0055] The memory cell array 11 has a plurality of blocks BLK (BLK0, BLK1, ...). The block BLK includes a plurality of non-volatile memory cell transistors (not shown) associated with word lines and bit lines. The block BLK is, for example, a unit for erasing data, and the data in the same block BLK is erased uniformly. Each block BLK has a plurality of string units SU (SU0, SU1, ...). In each string unit SU, there are a plurality of NAND strings NS. In addition, the number of blocks in the memory cell array 11, the number of string units US in one block BLK, and the number of NAND strings in one string unit SU can be set to any number.

[0056] <Memory cell array configuration>

[0057] Next, refer to Figure 3 , the structure of the memory cell array of the NAND type flash memory 3 is explained. Figure 3 The circuit of one block BLK in the memory cell array 11 is shown.

[0058] like Figure 3As shown, each string unit SU is composed of a set of NAND strings NS. Each of the NAND strings NS has, for example, 64 memory cell transistors MT (MT0~MT63), a selection transistor ST1, and a selection transistor ST2. In addition, the number of memory cell transistors MT included in one NAND string NS is not limited to 64, and can also be 8, 16, 96, etc., and its number is not limited. The memory cell transistor MT has a stacked gate including a control gate and a charge storage layer. Each memory cell transistor MT is connected in series between the selection transistors ST1 and ST2. In addition, the connection described below includes not only electrical connections in which the connected elements are in contact with each other, but also includes situations in which other conductive elements, such as wiring (metal wiring, polysilicon wiring, etc.) are interposed between at least two elements.

[0059] In any block BLK, the gates of the selection transistors ST1 of the string units SU0 to SU3 are connected to the selection gate lines SGD0 to SGD3, respectively. Moreover, the gates of the selection transistors ST2 of all the string units SU in the block BLK are commonly connected to the selection gate line SGS. The control gates of the memory cell transistors MT0 to MT7 in the same block BLK are respectively connected to the word lines WL0 to WL7. That is, the word lines WL of the same address are commonly connected to all the string units SU in the same block BLK, and the selection gate line SGS is commonly connected to all the string units SU in the same block BLK. On the other hand, the selection gate line SGD is only connected to one string unit SU in the same block BLK.

[0060] Furthermore, the other end of the selection transistor ST1 of the NAND string NS located in the same row among the NAND strings NS arranged in a matrix in the memory cell array 11 is connected to any one of the m bit lines BL (BL0 to BL(m-1) (m is a natural number)). Furthermore, the bit line BL spans across a plurality of blocks BLK and is commonly connected to the NAND strings NS in the same column.

[0061] Furthermore, the other end of the selection transistor ST2 is connected to a source line SL. The source line SL extends across a plurality of blocks BLK and is commonly connected to a plurality of NAND strings NS.

[0062] As described above, data erasure is performed uniformly on the memory cell transistors MT located in the same block BLK, for example. In this regard, the data read operation and the data write operation can be performed uniformly on a plurality of memory cell transistors MT commonly connected to any word line WL in any string unit SU of any block BLK. Such a group of memory cell transistors MT that share a word line WL in one string unit SU is called, for example, a unit unit CU. In other words, the unit unit CU is a group of memory cell transistors MT that can uniformly perform a write operation or a read operation.

[0063] In addition, one memory cell transistor MT can hold, for example, multiple bits of data. And, in the same unit unit CU, a set of 1 bits held in the same bit by each of the memory cell transistors MT is called a "page". That is, a "page" can also be defined as a part of the memory space of a group of memory cell transistors MT formed in the same unit unit CU. One page is, for example, 128Kbit (16KByte).

[0064] Return to Figure 2 The description continues. The input-output circuit 12 includes at least an input circuit 12A, an output circuit 12B, and a control circuit 12C. The input-output circuit 12 transmits and receives a data signal DQ to and from the memory controller 2. The input-output circuit 12 transmits the command CMD and the address ADD included in the signal DQ input to the input-output pad group 21 to the command register 15A and the address register 15B of the register 15, respectively. Furthermore, the input-output circuit 12 transmits the write data DAT included in the signal DQ input to the input-output pad group 21 to the data register 20B of the sense amplifier 20, and transmits the read data DAT transmitted from the data register 20B of the sense amplifier 20 to the input-output pad group 21.

[0065] Figure 4 This is a circuit diagram of the output circuit 12B. As shown in the figure, the output circuit 12B includes a shift register unit 31A and a multiplexer (MUX) 31D [selection circuit]. The shift register unit 31A has a shift register 31B [holding circuit] composed of a plurality of flip-flops 31C connected in series. The shift register 31B is arranged on each of the signal lines DQ0 to DQ7 and temporarily holds data. The number of flip-flops 31C is appropriately set according to the timing control of the signal DQ, for example, 8.

[0066] In the first paragraph ( Figure 4 The input terminal D of the flip-flop 31C (on the rightmost side of the paper) is connected to one of the multiple input terminals of the multiplexer 31D, and its output terminal Q is connected to the input terminal D of the next stage of the flip-flop 31C. The output terminal Q of the next stage of the flip-flop 31C is connected to the input terminal D of the next stage of the flip-flop 31C, and the same connection is made below. The output terminal Q of the last stage of the flip-flop 31C is connected to one of the signal lines DQ0 to DQ7 ( Figure 4 In the example, it is the signal line DQ0). For example, an internal clock iCLK having a different period is input to the clock terminal of each flip-flop 31C from the sequencer 16. Each flip-flop 31C latches the input data at the timing when the internal clock iCLK input to the clock terminal rises.

[0067] The multiplexer 31D selects, for example, 8 bits of the read data DAT of 1 page (16KByte) read from the memory cell array 11 to the sense amplifier unit 20A and stored in the data register 20B and transmits it to the shift register unit 31A. The 8-bit data to be transmitted is sequentially held and transmitted by the flip-flop 31C functioning as a buffer. For example, if the memory controller 2 switches the read enable signal RE and / RE after the read data is temporarily held by the shift register 31B, the read data held by the shift register 31B is output as DQ data in units of 8 bits from the output terminal Q of the flip-flop 31C in the last stage. That is, the 16KByte parallel data is converted into 8-bit serial data by the output circuit 12B.

[0068] Return to Figure 2 To continue the description, the logic control circuit 13 receives the signals / CE, CLE, ALE, / WE, / RE, and / WP from the memory controller 2. Furthermore, the logic control circuit 13 transmits the signal / RB to the memory controller 2 to inform the memory controller 2 whether the NAND flash memory 3 is in the ready state or the busy state.

[0069] The logic control circuit 13 includes a correction circuit 13a having a phase-locked loop (PLL) circuit or a delay-locked loop (DLL) circuit. The correction circuit 13a has a function of correcting the duty ratio of the input signals RE and / RE, etc., respectively, through the pads in the logic control pad group. The correction circuit 13a corrects the duty ratio of the signals RE and / RE based on the control signal from the sequencer 16, and generates the corrected signals RE and / RE. The corrected signals RE and / RE are sent to, for example, the input-output circuit 12, and the input-output circuit 12 switches the signals DQS and / DQS at the timing corresponding to the corrected signals RE and / RE.

[0070] The register 15 includes a command register 15A for holding a command CMD and an address register 15B for holding an address ADD. The register 15 transmits the address ADD to the row decoder 19 and the sense amplifier 20, and transmits the command CMD to the sequencer 16.

[0071] The sequencer 16 receives the command CMD and controls the entire NAND flash memory 3 according to a sequence based on the received command CMD. The sequencer 16 sends temperature information received from a temperature sensor or the like to the memory controller 2 via the input / output circuit 12 .

[0072] The voltage generating circuit 17 generates a voltage required for operations such as writing, reading, and erasing data based on an instruction from the sequencer 16. The voltage generating circuit 17 supplies the generated voltage to a driver (driver group) 18.

[0073] The driver 18 supplies various voltages from the voltage generating circuit 17 to the row decoder 19 and the sense amplifier 20 based on the address ADD transmitted from the address register 15B of the register 15. The driver 18 supplies various voltages to the row decoder 19 based on, for example, a row address of the address.

[0074] The row decoder 19 receives the row address included in the address ADD transmitted from the address register 15B of the register 15 and selects the memory cell transistors of the row based on the row address. The voltage from the driver 18 is transmitted to the memory cell transistors of the selected row through the row decoder 19.

[0075] The sense amplifier 20 includes a sense amplifier unit 20A and a data register 20B. When reading data, for example, the sense amplifier unit 20A reads (senses) the read data DAT read from the memory cell transistor to the bit line, and transfers the read data DAT to the data register 20B. The read data DAT held in the data register 20B is transferred to the output circuit 12B. When writing data, for example, the write data DAT transferred from the input circuit 12A to the data register 20B is written to the memory cell transistor via the bit line by the sense amplifier unit 20A. The sense amplifier 20 receives the column address included in the address ADD from the address register 15B of the register 15, and outputs the column data based on the column address.

[0076] For example, in response to a read instruction given from the memory controller 2, the sense amplifier unit 20A reads data from the memory cell transistor and transfers it to the data register 20B, and in response to a data output instruction given from the memory controller 2, transfers the data held in the data register 20B to the output circuit 12B.

[0077] The period from when the memory controller 2 issues a read command to when the sense amplifier 20A reads data from the memory cell array 11 and holds the read data in the data register 20B is referred to as "period tR". During the period tR, both the ready / busy signal R / Bn and the internal busy signal are at "L" level (ready state).

[0078] The input / output pad group 21 transmits data signals DQ, DQS, and / DQS received from the memory controller 2 to the input / output circuit 12. The input / output pad group 21 also transmits the signal DQ sent from the input / output circuit 12 to the outside of the NAND flash memory 3.

[0079] Logic control pad group 22 transmits signals / CE, CLE, ALE, / WE, / RE, and / WP received from memory controller 2 to logic control circuit 13. Logic control pad group 22 also transmits / RB sent from logic control circuit 13 to the outside of NAND flash memory 3.

[0080] The data generation circuit 14 outputs dummy data from the output circuit 12B according to the signals DQS and / DQS based on, for example, instructions from the sequencer 16. Specifically, the memory controller 2 switches the read enable signals RE and / RE, and the NAND flash memory 3 receives the signals RE and / RE and generates the signals DQS and / DQS. The data generation circuit 14 receives the signals DQS and / DQS, generates preset dummy data, and outputs it from the output circuit 12B to the memory controller 2. When the memory controller 2 determines that the received data is dummy data, it does not process it or processes it as invalid data.

[0081] The dummy data may be, for example, a random pattern. Alternatively, the dummy data may be a pattern in which each signal of the signal lines DQ0 to DQ7 repeatedly switches between the "H" level and the "L" level, such as 55h-AAh-55h-AAh..., or may be a data pattern of a fixed value. Furthermore, the data generation circuit 14 may also be included in the logic control circuit 13 or the input / output circuit 12. For example, the control circuit 12C of the input / output circuit 12 may also have the function of serving as the data generation circuit 14.

[0082] Next, refer to Figures 1 to 4 , and FIG. 6 , the stabilization of the data output operation from the NAND flash memory 3 to the memory controller 2 using the dummy data output of the data generating circuit 14 of the present embodiment will be described. Figure 4 A configuration example of the output circuit 12B is shown. Fig. 6A A timing chart showing data readout of a comparative example is shown. Figure 6B A timing chart showing data readout in this embodiment.

[0083] Fig. 6A The standby time t set in the NAND flash memory 3 in the comparative example is shown in FIG. WHR2 The NAND flash memory 3 of the comparative example has the same circuit configuration as the NAND flash memory 3 of the present embodiment, but has a different standby time t WHR2 The actions associated with the delay time are different.

[0084] For example, if a read command is issued from the memory controller 2 to the NAND flash memory 3, the sense amplifier unit 20A of the sense amplifier 20 reads out data of one page (e.g., 16 KByte) from the memory cell array 11, and the data register 20B stores the read data. Next, for example, a data output command is issued from the memory controller 2 to the NAND flash memory 3. The data output command is a command group including, for example, one or more command signals ("05h" and "E0h") given as an 8-bit signal DQ, and one or more address signals (column address ADD and row address ADD) given as an 8-bit signal DQ.

[0085] If a data output instruction is issued from the memory controller 2 to the NAND flash memory 3, then Figure 4 As shown, data of one page is transmitted from the data register 20B to the output circuit 12B. The multiplexer 31D of the output circuit 12B selects 8-bit data from the transmitted 16KByte data in sequence and transmits it to the shift register unit 31A. The shift register unit 31A holds the 8-bit data through the flip-flop 31C functioning as a buffer while transmitting. Thus, the read data is temporarily held in the shift register 31B. If the signals RE and / RE are toggled in the state, the 8-bit DQ data is output to the memory controller 2 from the output terminal Q of the flip-flop 31C in the last stage via the input / output pad group 21.

[0086] Standby time t WHR2 [The first period] is, for example, the time required from the time when the memory controller 2 issues a data output command to the NAND flash memory 3 to the time when the 16KByte read data from the memory cell array 11 is transferred from the data register 20B to the output circuit 12B and the first 8 bits of the data are output as DQ data in the output circuit 12B to the memory controller 2. Therefore, for example, during the standby time t WHR2 During the period of t, the first 8 bits of the data in the data register 20B are transferred to the flip-flop 31C of the last stage of the shift register unit 31A of the output circuit 12B, and after the waiting time t WHR2 After that, the memory controller 2 starts switching the signals RE and / RE, thereby starting to output 8-bit DQ data to the signal lines DQ0 to DQ7. Assuming that the standby time t is not waited WHR2 , the memory controller 2 starts switching the signals RE and / RE, and it is possible that incomplete data is output while the storage of 8-bit data to the output buffer (not shown) connected to the signal lines DQ0 to DQ7 is incomplete, or unexpected data is output.

[0087] That is, in the comparative example, after the memory controller 2 issues a data output command to the NAND flash memory 3, if the memory controller 2 does not wait for the standby time t WHR2 , then the signals RE and / RE used to instruct the NAND flash memory 3 to output data cannot be switched.

[0088] Moreover, if Fig. 6A As shown, in the comparative example, after the waiting time t WHR2 After [the first period], a delay time (latency) [the second period] is added.

[0089] If the memory controller 2 starts switching the signals RE and / RE, the delay period t DQSRE , and also starts switching the signals DQS and / DQS sent from the NAND flash memory 3. For example, the correction circuit 13a of the logic control circuit 13 corrects the duty ratio of the signals RE and / RE input from the memory controller 2 via the logic control pad group 22, and the input / output circuit 12 generates the signals DQS and / DQS based on the corrected signals RE and / RE.

[0090] The signals DQS and / DQS are used, for example, to control the operation timing of the NAND flash memory 3 under the signal DQ. Therefore, the NAND flash memory 3 can start outputting valid data immediately after the signals DQS and / DQS start switching, for example.

[0091] However, the power supply VDD of the NAND flash memory 3 may become unstable immediately after the memory controller 2 starts switching the signals RE and / RE. Therefore, the delay time is set, for example, to hold the output of valid data until the power supply VDD that becomes unstable due to the start of switching of the signals RE and / RE stabilizes. The timing of starting the output of valid data is delayed by the delay time from the timing of starting the switching of the signals DQS and / DQS.

[0092] The delay time is preferably long in order to stabilize the power supply VDD, but is preferably short in order to increase the speed of operation. In addition, the delay time may be set to ensure the time required for correction processing such as duty cycle correction or timing correction by a phase-locked loop (PLL) or a delay locked loop (DLL) provided in the correction circuit (DCC) 13a.

[0093] For example, the sequencer 16 counts either the signal RE or / RE or either the signal DQS or / DQS, and starts outputting the data (valid data) transferred from the data register 20B to the output circuit 12B after reaching a specific count number.

[0094] Figure 5 : is a flowchart showing data output of a comparative example.

[0095] First, in the comparative example, the sense amplifier unit 20A of the sense amplifier 20 reads data from the memory cell array 11, for example, 1 page of 16KByte data, through a read command issued in advance from the memory controller 2, and the read data is stored in the data register 20B. In the state, the memory controller 2 switches the signal / WE and issues a data output command via the data signal lines DQ0 to DQ7 (step S1). The command is output to the sense amplifier 20, and the preset time measurement starts from the point when the switching of the signal / WE stops (step S2). In parallel with this, in the NAND flash memory 3, the read data is transmitted from the data register 20B to the multiplexer 31D in the output circuit 12B (step S3). During the standby time t WHR2 During the standby time t, the multiplexer 32D selects 16KByte of data in units of, for example, 8 bits, and transmits it to the shift register unit 31A. WHR2 During the period of t (step S4: NO), there is no guarantee that the output circuit 12B is ready to output data to the memory controller 2. Therefore, the memory controller 2 is idle for the time t WHR2 During this period, the read enable signals RE and / RE do not start switching.

[0096] Then, if the standby time t WHR2 The period ends (step S4: YES), then the output circuit 12B is ready to output data to the memory controller 2, so the memory controller 2 starts switching the read enable signals RE and / RE (step S5). The NAND flash memory 3 that receives the switching signals RE and / RE starts switching the signals DQS and / DQS. The data generation circuit 14 that receives the switching signals DQS and / DQS outputs the preset dummy data from the output circuit 12B.

[0097] The output circuit 12B outputs invalid dummy data to the signal lines DQ0 to DQ7 during a preset delay time, and outputs the data stored in the shift register unit 31A to the signal lines DQ0 to DQ7 after the preset delay time (step S6). In conjunction with the output, data can be continuously transmitted from the data register 20B to the multiplexer 31D of the output circuit 12B (step S7). In addition, data is output from the output circuit 12B to the memory controller 2.

[0098] In the comparative example, the time from when the memory controller 2 issues a data output command to when the first valid 8-bit data is output from the NAND flash memory 3 includes at least the waiting time t required for the internal data transfer processing of the NAND flash memory 3. WHR2, and the delay time required to wait for the power supply VDD that becomes unstable in response to the switching of the signals RE and / RE to stabilize. For example, if the delay time is short, data output starts before the output of the power supply VDD stabilizes, so the level of the output data may become unstable.

[0099] Next, refer to Figure 6B The timing diagram shown and Figure 7 The flowchart shown in FIG. 1 is used to explain the data output of the data generation circuit 14 of the first embodiment. Fig. 6A The timing diagram shown and Figure 5 The same operations as those in the flowcharts shown are sometimes given the same step numbers and the description is simplified.

[0100] In this embodiment, the memory controller 2 waits for a longer time t than the standby time t required for the internal data transfer process of the NAND flash memory 3. WHR2 Short standby time WHR2 ', the switching of the signals RE and / RE begins. Furthermore, in the NAND flash memory 3, the input-output circuit 12 generates the signals DQS and / DQS based on the signals RE and / RE received from the memory controller 2 and outputs them to the output circuit 12B, and the data generating circuit 14 generates the virtual data based on the signals DQS and / DQS and outputs it to the output circuit 12B. During the delay time, the output circuit 12B outputs the virtual data to the memory controller 2. The memory controller 2 does not respond to the received virtual data. Not responding can ensure the stability of the power output. The virtual data may be, for example, a random pattern or a preset data pattern, and is not particularly limited.

[0101] In the present embodiment, when describing the data output operation, it is also assumed that the memory controller 2 issues a read command, reads desired data from the memory cell array 11, and stores the data in the data register 20B.

[0102] First, the memory controller 2 issues a data output command to the NAND flash memory 3 (step S1). The data output command is a command group including a first command signal "05h" given as an 8-bit signal DQ, a column address signal ADD, a row address signal ADD, and a second command signal "E0h". The memory controller 2 cooperates with the issuance of the data output command, with a time t WC The periodic switching signal / WE.

[0103] Next, the memory controller 2 issues a data output command and starts time measurement at the same time (step S2). WHR2 During the period, that is, after a waiting time t WHR2 Short T WHR2'After time t RC The periodic switching signal RE and / RE (step S5). Waiting time t WHR2 The number of switching times of the signals RE and / RE within the period and the switching start timing can be appropriately set using, for example, a set feature.

[0104] In parallel, after the NAND flash memory 3 receives the data output command, the data register 20B transfers the stored data, for example, 16KByte, to the multiplexer 31D in the input / output circuit 12 (step S3). The multiplexer 31D transfers the 16KByte data, for example, in units of 8 bits to each shift register 31B of the shift register unit 31A.

[0105] After the switching of the signals RE and / RE starts, in the NAND flash memory 3, a delay period t DQSRE ', and starts switching the signals DQS and / DQS. After the switching of the signals DQS and / DQS starts, the data generation circuit 14 generates dummy data and outputs it to the output circuit 12B (step S8). The output circuit 12B outputs the dummy data together with the signals DQS and / DQS to the memory controller 2 during the preset delay time (step S11). Figure 6B In the embodiment shown, the example in which the switching of the signals DQS and / DQS starts and the output of the dummy data starts at the same time is shown. However, the timing is not limited. As described above, the memory controller 2 does not process the dummy data. Moreover, by advancing the timing of the switching start of the signals RE and / RE, the output of the power supply VDD is more stable at the timing of starting to output valid data instead of dummy data.

[0106] Then, for example, if the number of switching of the signal DQS reaches the set number of times (step S12: Yes), the read data signal DQ is output from the shift register unit 31A of the output circuit 12B to the memory controller 2 (step S6). In conjunction with the output, data can be continuously transmitted from the data register 20B to the multiplexer 31D of the output circuit 12B (step S7). Data is also output from the output circuit 12B to the memory controller 2. In addition, the output time or the number of cycles (number of switching times) of the dummy data of the signal DQ is appropriately set and is not limited.

[0107] exist Fig. 6A In the comparative example shown, after the waiting time t WHR2After that, the signals RE and / RE start to be switched (toggle), and then the signals DQS and / DQS start to be switched. Moreover, the timing of starting to output valid data is delayed by the delay time from the timing of starting to switch the signals DQS and / DQS. In the case where the power supply VDD becomes unstable due to the start of switching the signals RE and / RE, the delay time can be set longer to start outputting valid data after the power supply VDD stabilizes. On the other hand, in the comparative example, the time from when the memory controller 2 issues a data output command to when the first valid 8-bit data is output from the NAND flash memory 3 is at least longer than the standby time t WHR2 and length of delay time.

[0108] In this regard, the present embodiment Figure 6B The standby time t WHR2 During the [first period], the signals RE and / RE [first signal] start toggling (toggle), and then the signals DQS and / DQS [second signal] start toggling. Moreover, after the signals DQS and / DQS are switched any number of times, the data generation circuit 14 generates virtual data [first data] and outputs it from the output circuit 12B to the memory controller 2. The memory controller 2 does not process the virtual data as valid data (data read from the memory cell array 11 and stored in the data register 20B) and does not perform data processing. The memory controller 2 can determine whether it is virtual data based on, for example, the number of switching of the signal DQS. In the case where the virtual data is a repeated switching pattern such as 55h-AAh-55h-AAh..., it is also possible to judge whether it is virtual data based on the number of switching of the virtual data instead of the number of switching of the signal DQS.

[0109] As described above, in this embodiment, during the standby time t WHR2 During the period, the switching signals RE and / RE and the switching signals DQS and / DQS are continuously started, and then the dummy data is output, thereby making the standby time t WHR2 The delay time overlaps with the delay time, and the output of the power supply VDD can be stabilized from a period earlier than the comparative example. Fig. 6A In the case of the same timing as the comparative example described above, the delay time (latency) for stabilizing the power output can be set longer. Figure 6B As shown, after the output of the power supply VDD is stabilized, valid data can be output, thereby improving the reliability of data reading.

[0110] Alternatively, if the output of the power supply VDD is stabilized to the same extent as in the comparative example and there is no problem with the reliability of data reading, by switching the signals RE and / RE from an earlier period, the delay time for simultaneously outputting virtual data by switching the signals DQS and / DQS ends at an earlier period, thereby enabling the timing for starting to output valid data to be earlier than in the comparative example, thereby achieving substantial speed-up of the data reading time.

[0111] Relative to the standby time t WHR2 The timing of switching the memory controller 2 start signals RE and / RE, or the timing of ending the output of dummy data and starting the output of valid data, is not limited to the timing shown in the first embodiment. Figure 6B , can be appropriately set according to the design or device specifications. The following describes an example of setting the timing.

[0112] [First setting example]

[0113] Figure 8 The first setting example shown sets the waiting time t WHR2 The switching end of the delay time (latency) and the output end of the virtual data are set to the same timing. In other words, the waiting time t is set WHR2 Once completed, data can be exported.

[0114] First, during the standby time t WHR2 The RE and / RE signals are switched during the period, and then the DQS and / DQS signals are switched immediately to start outputting the dummy data in the DQ signal. The switching of the RE and / RE signals and the switching of the DQS and / DQS signals continue until at least the output of the dummy data in the DQ signal is completed.

[0115] In the first setting example, the waiting time t WHR2 Set to 300nsec, the switching signal RE and / RE one cycle time t RC The time setting is set to 2.5 nsec. Of course, the time setting is not limited and can be set appropriately by the memory controller 2. In addition, other setting examples can also perform the time setting in the same manner.

[0116] [Second setting example]

[0117] Fig. 9 The second setting example shown is set to set the standby time t WHR2 After the switching is completed, the timing of the virtual data of the delay time (latency) is ended. It is the same as the first embodiment described above. Compared with the first setting example, the timing setting of the second setting example is easier. In the second setting example, the waiting time t WHR2Set to 300nsec, and change the cycle time t of the switching signal RE and / RE RC At this time, the switching of the signals RE and / RE and the switching of the signals DQS and / DQS are in the standby time t WHR2 It starts during the period and continues until the output of the dummy data of the signal DQ is completed.

[0118] [3rd setting example]

[0119] Fig.10 The third setting example shown is in the standby time t WHR2 During the period, the switching between the RE and / RE signals and the DQS and / DQS signals is temporarily stopped, and then the standby time t WHR2 When the switching is completed, the switching is restarted. The output of the dummy data in the signal DQ of the delay time (latency) is completed simultaneously with the restart of the switching.

[0120] Specifically, during the standby time t WHR2 During the period of t, the switching of the RE and / RE signals and the switching of the DQS and / DQS signals start, and the output of dummy data begins. WHR2 During the period, the switching of the signals RE and / RE and the signals DQS and / DQS, which have reached the set switching times, ends, but the output of the dummy data in the signal DQ continues. And, the switching of the signals RE and / RE for starting data output is waited.

[0121] After that, with the standby time t WHR2 At the same time as the completion, the switching of the signals RE and / RE and the signals DQS and / DQS is restarted, and the output of the dummy data in the signal DQ is completed.

[0122] In the third setting example, the standby time t WHR2 Set to 300nsec, the switching signal RE and / RE one cycle time t RC Set to 2.5nsec.

[0123] In the third setting example, since the switching of the signals RE and / RE and the switching of the signals DQS and / DQS are interrupted, power consumption can be suppressed.

[0124] [4th setting example]

[0125] Fig.11 The 43rd setting example shown is set to set the standby time t WHR2 During the period, the switching signals RE and / RE start, and the standby time t WHR2After the delay time (latency) ends, the switching of the signals DQS and / DQS and the output of the dummy data in the signal DQ are started. In the fourth setting example, the waiting time t WHR2 Set to 300nsec, the switching signal RE and / RE one cycle time t RC The fourth setting example can also suppress power consumption similarly to the third setting example.

[0126] [Second embodiment]

[0127] Next, refer to Fig.12 The flowchart shown in FIG. 1 is used to explain the data output operation from the NAND flash memory 3 to the memory controller 2 in the second embodiment. Figure 7 The same steps as those in the flowcharts are denoted by the same step numbers for simplified description.

[0128] This embodiment performs output of dummy data and correction processing of the duty ratio of the PLL / DLL of the correction circuit within the delay time of the first embodiment.

[0129] First, the memory controller 2 starts switching the signal / WE and issues the address ADD and the data output command (step S1). After the NAND flash memory 3 receives the data output command, the data stored in the data register 20B is transmitted to the multiplexer 31D in the input / output circuit 12 (step S3). The multiplexer 31D stores, for example, 16KByte of data in units of 8 bits t in each shift register 31B.

[0130] Then, the memory controller 2 starts time measurement from the point in time when the data output command is issued and the switching of the signal / WE stops (step S2). WHR2 During the period, the memory controller 2 starts the signal RE and / RE for one cycle as the standby time t RC After the switching of the signals RE and / RE starts, the NAND flash memory 3 starts switching the signals DQS and / DQS after a set time. After the switching of the signals DQS and / DQS starts, the data generation circuit 14 generates dummy data and outputs it to the output circuit 12B (step S8).

[0131] The output circuit 12B outputs the dummy data together with the signals DQS and / DQS to the memory controller 2 via the signal lines DQ0 to DQ7 (step S11). In parallel with the output of the dummy data, that is, during the standby time and delay time (latency), the duty ratio correction process of the PLL / DLL provided in the correction circuit 13a of the logic control circuit 13 is performed (step S13).

[0132] In the dummy data output, the data stored in the data register 20B is transmitted to the multiplexer 31D (step S3). The multiplexer 31D stores, for example, 16 KByte of data in units of 8 bits in each shift register 31B.

[0133] Then, when, for example, the switching of the signal DQS reaches a set number of times (or, the switching output time) (step S12: Yes), that is, when the delay time (latency) ends, the data read to the shift register 31B starts to be output to the memory controller 2 (step S6). In conjunction with the output, data can be continuously transmitted from the data register 20B to the multiplexer 31D of the output circuit 12B (step S7). Data is also output from the output circuit 12B to the memory controller 2.

[0134] In this embodiment, by seeking to stabilize the power output from an earlier period than in the comparative example, the output of data can be started after the power output is stabilized. In addition, because the power output is stabilized from an earlier period, the delay time (latency) can be set longer. Therefore, time for other processing such as duty cycle correction processing can be ensured within the delay time. Moreover, by using the standby time or delay time to perform the correction processing time, sufficient processing time can be used, and the accuracy of the correction can be improved.

[0135] [Third Embodiment]

[0136] Next, refer to Fig.13 The flowchart shown in FIG. 1 is used to explain the data output operation from the NAND flash memory 3 to the memory controller 2 in the third embodiment. Figure 7 The same steps as those in the flowcharts are denoted by the same step numbers for simplified description.

[0137] This embodiment is a flow in which the steps of issuing the data output command and starting the switching of the signals RE and / RE of the first embodiment are reversed. That is, the switching of the signals RE and / RE is started first, and then the data output command is issued.

[0138] First, the memory controller 2 starts switching the signals RE and / RE (step S5). Then, the memory controller 2 issues an address ADD and a data output command (step S1). After issuing the data output command, the memory controller 2 starts time measurement (step S2).

[0139] After the measurement starts, the memory controller 2 waits for a period of time t WHR2After a preset time or the number of switching times of the signals RE and / RE has passed within the period, the signals DQS and / DQS start to switch. After the signals DQS and / DQS start to switch, the data generating circuit 14 generates dummy data and outputs it to the output circuit 12B (step S8).

[0140] During the delay time, the output circuit 12B outputs dummy data together with the signals DQS and / DQS to the memory controller 2 via the signal lines DQ0 to DQ7 (step S11). In this embodiment, the memory controller 2 also determines that the received data is dummy data and does not process it.

[0141] After receiving the data output command, the NAND flash memory 3 transmits the data stored in the data register 20B to the multiplexer 31D in the input / output circuit 12 (step S3). The multiplexer 31D stores, for example, 16KByte of data in 8-bit units in each shift register 31B.

[0142] After that, for example, when the switching of the signal DQS reaches the set number of times (step S12: Yes), that is, when the delay time (latency) ends, the shift register unit 31A of the output circuit 12B outputs data to the memory controller 2 (step S6). In conjunction with the output, the data register 20B can continuously transmit data to the multiplexer 31D of the output circuit 12B (step S7). The output circuit 12B also outputs data to the memory controller 2.

[0143] As described above, the present embodiment can obtain the same effects as those of the first embodiment. In addition, in the present embodiment, the issuance of the data output command and the switching start timing of the signals RE and / RE are not limited, and the data output command can be issued after the switching of the signals RE and / RE is started. In the present embodiment, the multiplexer 31D that reads data from the memory cell array 11 by the sense amplifier 20 and transmits it to the output circuit 12B can also process it simultaneously or in parallel during the standby time and the output of dummy data, so that the power supply can be stabilized and appropriate data can be output.

[0144] [Fourth embodiment]

[0145] Next, refer to Fig.14 The flowchart shown in FIG. 1 is used to explain the data output operation from the NAND flash memory 3 to the memory controller 2 in the fourth embodiment. Figure 7 The same steps as those in the flowcharts are denoted by the same step numbers for simplified description.

[0146] This embodiment is an example in which, when data is read from a memory cell transistor by issuing a read command, switching of the signals RE and / RE is started, and thereafter a data output command is issued.

[0147] First, the memory controller 2 issues a read command together with an address ADD and the like to the NAND flash memory 3 (step S14).

[0148] According to the read command, the sense amplifier unit 20A reads data from the memory cell array 11 and stores it in the data register 20B (step S15). In parallel, the memory controller 2 starts switching the signals RE and / RE (step S5).

[0149] Furthermore, after the NAND flash memory 3 starts switching the signals RE and / RE, it starts switching the signals DQS and / DQS. After the switching of the signals DQS and / DQS starts, the data generation circuit 14 generates dummy data and outputs it to the output circuit 12B (step S8). The output circuit 12B outputs the dummy data together with the signals DQS and / DQS to the memory controller 2 via the signal lines DQ0 to DQ7 (step S11). In the present embodiment, even if the dummy data is output from the output circuit 12B to the memory controller 2, it is judged as invalid data and is not processed.

[0150] Next, the memory controller 2 issues a data output command to the NAND flash memory 3 (step S1). After issuing the data output command, the memory controller 2 starts time measurement (step S2). WHR2 During the period of , the data stored in the data register 20B is transferred to the multiplexer 31D of the output circuit 12B (step S3). The multiplexer 31D initially stores, for example, 16KByte of data in units of 8 bits in each shift register 31B.

[0151] Afterwards, for example, when the switching of the signal DQS reaches the set number of times (step S12: Yes), that is, when the delay time (latency) ends, the shift register unit 31A of the output circuit 12B outputs data to the memory controller 2 (step S6). In conjunction with the output, the data register 20B can continuously transmit data to the multiplexer 31D of the output circuit 12B (step S7). The output circuit 12B also outputs data to the memory controller 2.

[0152] As described above, the present embodiment can obtain the same effects as those of the first embodiment. In addition, the present embodiment can start switching the signals RE and / RE during the period after the read command is issued and before the data output command is issued.

[0153] [Fifth embodiment]

[0154] refer to Fig.15 The timing chart shown in the figure explains the data output operation from the NAND flash memory 3 to the memory controller 2 in the fifth embodiment.

[0155] This embodiment replaces the read output instruction used in the above embodiments and uses the get feature instruction to make the NAND flash memory 3 output a preset setting value. Fig.15 As shown, after issuing the read command XXh of the acquisition feature command, the waiting time t WHR2 The period (time t WB + Set time t FEAT + time t RP ), the signals RE and / RE start to be switched, and accordingly, the NAND flash memory 3 starts to switch the signals DQS and / DQS. After the switching of the signals DQS and / DQS starts, the data generation circuit 14 generates dummy data and outputs it to the output circuit 12B. The output circuit 12B outputs the dummy data to the memory controller 2 via the signal lines DQ0 to DQ7. After the output of the dummy data is completed, the NAND flash memory 3 outputs the set value to the memory controller 2.

[0156] The NAND flash memory 3 of this embodiment sets the time t FEAT , the timing of starting and ending the switching of signals RE and / RE, the timing of starting and ending the switching of signals DQS and / DQS, the number of switching times of each, and / or the output time of virtual data (the number of switching times when the virtual data is a repeated switching pattern such as 55h-AAh-55h-AAh...), each of which has a set value that is pre-stored in a feature register not shown in the figure, and when an action instruction is received, action is performed based on the set value.

[0157] This embodiment can also produce the same effects as those of the first embodiment described above.

[0158] Although several embodiments of the present invention have been described, the embodiments are presented as examples and are not intended to limit the scope of the invention. The embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The embodiments or their variations are included in the scope or spirit of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

1. A memory system comprising: Semiconductor memories; and a controller that gives an instruction to read data from the semiconductor memory; and The semiconductor memory has: Memory cell transistors, which hold data; an output circuit that processes the data read out from the memory cell transistor to output the data to the controller; and A data generating circuit generates first data; and When reading the data, The controller outputs a first signal to the semiconductor memory during a first period in which the output circuit performs the processing; The semiconductor memory generates a second signal based on the first signal, and outputs the first data together with the second signal to the controller during the first period and the second period; After the second period ends, the semiconductor memory outputs the data read from the memory cell transistor together with the second signal to the controller.

2. The memory system according to claim 1, wherein the output circuit comprises a selection circuit and a holding circuit; and The processing performed by the output circuit is an internal data transfer, comprising: The selection circuit selects a plurality of bits of data read from the memory cell transistor, and the holding circuit holds the plurality of bits selected by the selection circuit; and The processing is performed during the first period.

3. The memory system according to claim 1, wherein when reading the data, The controller issues an address storing the data and a data output command, and sends them to the semiconductor memory; The semiconductor memory becomes busy in response to the data output instruction and reads data from the memory cell transistor; The controller issues the first signal after the semiconductor memory becomes ready, and sends the first signal to the semiconductor memory; The data generating circuit generates the first data based on the data output instruction; and The output circuit outputs the first data together with the second signal to the controller during the second period. 4 . The memory system according to claim 1 , wherein the controller arbitrarily changes a switching frequency of each of the first signal and the second signal and an output time of the first data. 5 . The memory system according to claim 1 , wherein the controller selects, for the first data generated by the data generating circuit, either a data pattern having a preset switching number or a pattern including a fixed value.

6. The memory system according to claim 1, wherein the semiconductor memory comprises: a correction circuit to correct the duty cycle and timing of the clock signal; and The controller executes correction by the correction circuit during the first period and the second period. 7 . The memory system according to claim 3 , wherein the controller starts outputting the first signal before or during issuance of the data output command.

8. The memory system according to claim 1, wherein the semiconductor memory comprises: a register for temporarily holding the read data; and When reading the data, After the controller issues an address storing the data and a read command to the semiconductor memory, the controller starts the first period, issues the first signal and sends it to the semiconductor memory; The semiconductor memory reads data from the memory cell transistor in response to the first signal and temporarily holds the data in the register; The data generating circuit outputs the first data to the output circuit; The controller issues an address storing the data and a data output command during the second period of outputting the first data, and sends them to the semiconductor memory; and The output circuit outputs the first data together with the second signal to the controller during the second period.

9. The memory system according to claim 1, wherein when reading the data, The controller is configured to terminate the output of the first data at the same time as the end time of the first period of outputting the first signal, or to terminate the output of the first data after the first period ends.

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