Display panel and manufacturing method thereof, display device and manufacturing method thereof

Abstract

A display panel and a manufacturing method thereof, and a display device and a manufacturing method thereof. The display panel comprises a display area and a peripheral area arranged on a substrate, the display panel further comprising a plurality of effective driving circuits and a plurality of redundant driving circuits; at least one effective driving circuit is electrically connected to at least one pixel unit among a plurality of pixel units, and the redundant driving circuit comprises at least one electrode layer arranged on the substrate; the peripheral area comprises a plane area and a curved area, and at least part of the redundant driving circuits are located in a flat redundant driving circuit area (71) included in the plane area; the flat redundant driving circuit area (71) comprises at least two alignment mark areas (70); in the alignment mark area (70), at least one electrode layer is hollowed out, and / or at least one electrode layer is filled; the minimum distance between the edges of the orthographic projections of two adjacent alignment mark areas (70) on the substrate is the alignment mark distance, and at least one alignment mark distance is greater than a predetermined alignment mark distance.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device and a manufacturing method thereof. Background Art

[0002] As the demand for display devices increases, the number of circuits and wirings in the display panel is also increasing. In this case, pad bending (circuit board bending) technology can be used on the upper or lower frame of the display panel. The circuit board bending technology is to bend part of the circuit board included in the display device (the circuit board can be a flexible circuit board) to the back of the display panel, and a heat dissipation film will be attached to the surface of the circuit board bent to the back of the display panel to reduce the heat generated when the circuit is working. In order to improve the accuracy of bending alignment and heat dissipation film attachment, it is necessary to achieve alignment by identifying the alignment marks in the display panel. In the related art, it is not possible to provide a technical solution that can accurately perform alignment marks on a four-sided curved display panel without increasing the frame. Summary of the invention

[0003] An object of the present invention is to provide a display panel and a manufacturing method thereof, and a display device and a manufacturing method thereof.

[0004] In one aspect, an embodiment of the present invention provides a display panel, comprising a display area and a peripheral area arranged on a substrate, the display panel comprising a plurality of pixel units arranged in the display area, the peripheral area comprising an area between the display area and an edge of the display panel, the display panel further comprising a plurality of effective driving circuits and a plurality of redundant driving circuits, the plurality of effective driving circuits and the plurality of redundant driving circuits being arranged in the peripheral area; wherein,

[0005] At least one of the plurality of effective driving circuits is electrically connected to at least one of the plurality of pixel units to drive the pixel unit to display, and the redundant driving circuit includes at least one electrode layer disposed on a substrate;

[0006] The peripheral area includes a plane area and a curved area, wherein at least part of the redundant driving circuit is located in a flat redundant driving circuit area included in the plane area;

[0007] The flat redundant driving circuit area includes at least two alignment mark areas;

[0008] In the alignment mark area, at least one of the electrode layers is hollowed out, and / or at least one of the electrode layers is filled;

[0009] The minimum distance between the edges of the orthographic projections of two adjacent alignment mark areas on the substrate is an alignment mark distance, and at least one of the alignment mark distances is greater than a predetermined alignment mark distance.

[0010] Optionally, the predetermined alignment mark distance is 10 times the maximum pixel edge length;

[0011] The maximum pixel edge length is the maximum value among the pixel edge lengths of the plurality of pixel units;

[0012] The pixel edge length is the length of the edge of the orthographic projection of the pixel unit on the substrate.

[0013] Optionally, the area of ​​the orthographic projection of the alignment mark region on the substrate is larger than a predetermined area;

[0014] The predetermined area is the maximum pixel area;

[0015] The maximum pixel area is a maximum value among pixel areas of the plurality of pixel units, and the pixel area is an area of ​​a positive projection of the pixel unit on a substrate.

[0016] Optionally, in the alignment mark area, at least one of the electrode layers is filled; in the first area, the electrode layer is hollowed out;

[0017] The first area is an area surrounding the alignment mark area and included in the flat redundant driving circuit area.

[0018] Optionally, the display panel includes an upper surface, a lower surface, a first side surface, a second side surface, a third side surface and a fourth side surface;

[0019] The upper surface and the lower surface are both planes;

[0020] The first side surface, the second side surface, the third side surface and the fourth side surface are all curved side surfaces;

[0021] The orthographic projection of the first side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane;

[0022] The orthographic projection of the second side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane;

[0023] The orthographic projection of the third side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane;

[0024] The orthographic projection of the fourth side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane;

[0025] The first plane is parallel to the lower surface.

[0026] Optionally, the first side surface is a left side surface, the second side surface is a lower side surface, the third side surface is an upper side surface, and the fourth side surface is a right side surface; the display panel further includes a circuit board disposed on the lower surface, and the circuit board is disposed on the lower side of the display panel;

[0027] The longest distance between the orthographic projection of the alignment mark area on the first plane and the lower left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the lower right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

[0028] Optionally, the first side surface is a left side surface, the second side surface is a lower side surface, the third side surface is an upper side surface, and the fourth side surface is a right side surface; the display panel further includes a circuit board disposed on the lower surface, and the circuit board is disposed on an upper side edge of the display panel;

[0029] The longest distance between the orthographic projection of the alignment mark area on the first plane and the upper left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

[0030] Optionally, the first side surface is a left side surface, the second side surface is a lower side surface, the third side surface is an upper side surface, and the fourth side surface is a right side surface; the display panel further includes a circuit board disposed on the lower surface, and the circuit board is disposed on the lower side of the display panel;

[0031] The longest distance between the orthographic projection of the alignment mark area on the first plane and the upper left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

[0032] Optionally, the first side surface is a left side surface, the second side surface is a lower side surface, the third side surface is an upper side surface, and the fourth side surface is a right side surface; the display panel further includes a circuit board disposed on the lower surface, and the circuit board is disposed on an upper side edge of the display panel;

[0033] The longest distance between the orthographic projection of the alignment mark area on the first plane and the lower left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the lower right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

[0034] Optionally, an edge of an orthographic projection of the alignment mark area on the substrate is circular, polygonal, L-shaped or T-shaped.

[0035] Optionally, the display panel includes a semiconductor layer, a gate metal layer and a source-drain metal layer sequentially arranged on a substrate;

[0036] In the alignment mark region, the gate metal layer and the source / drain metal layer are hollowed out.

[0037] Optionally, in the alignment mark area, the semiconductor layer is also hollowed out, or the semiconductor layer is filled.

[0038] Optionally, the display panel further comprises an anode layer arranged on a side of the source / drain metal layer away from the gate metal layer;

[0039] In the alignment mark area, the anode layer is not provided with an opening and the anode layer is filled.

[0040] Optionally, the display panel further comprises an anode layer arranged on a side of the source / drain metal layer away from the gate metal layer;

[0041] The anode layer is hollowed out in the alignment mark region.

[0042] Optionally, in the first region, the anode layer is hollowed out;

[0043] The first area is an area surrounding the alignment mark area and included in the flat redundant driving circuit area.

[0044] Optionally, the display panel further comprises an anode layer arranged on a side of the source / drain metal layer away from the gate metal layer;

[0045] In the alignment mark area, the anode layer includes an alignment mark pattern.

[0046] Optionally, the orthographic projection of the alignment mark pattern on the substrate is circular, L-shaped, T-shaped or polygonal.

[0047] Optionally, in an area of ​​the driving circuit area except the alignment mark area, the anode layer is provided with a plurality of openings arranged at intervals.

[0048] Optionally, the gate metal layer includes a first gate metal layer and a second gate metal layer which are sequentially arranged on a side of the semiconductor layer away from the substrate;

[0049] In the alignment mark region, both the first gate metal layer and the second gate metal layer are hollowed out.

[0050] Optionally, in the alignment mark area, the display panel further includes an anode layer disposed on a side of the source-drain metal layer away from the gate metal layer; the display panel further includes a first insulating layer disposed between the semiconductor layer and the first gate metal layer, a second insulating layer disposed between the first gate metal layer and the second gate metal layer, a third insulating layer disposed between the second gate metal layer and the source-drain metal layer, and a fourth insulating layer disposed between the source-drain metal layer and the anode layer;

[0051] In the alignment mark area, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are not hollowed out.

[0052] Optionally, the peripheral area includes a fan-out area, a driving circuit area and a signal line area which are sequentially arranged in a direction away from the display area;

[0053] The flat redundant driving circuit area is included in the driving circuit region.

[0054] Optionally, the redundant driving circuit includes a multi-stage redundant shift register unit, and the redundant shift register unit is not coupled to the pixel unit.

[0055] Optionally, at least one level of the redundant shift register unit includes the alignment mark area, and the at least one level of the redundant shift register unit is different from other redundant shift register units.

[0056] Optionally, in the alignment mark area, at least one film layer included in the output transistor in the redundant driving circuit is hollowed out.

[0057] Optionally, the redundant driving circuit includes a redundant gate driving circuit and a redundant light emitting control circuit;

[0058] The redundant light emitting control circuit is arranged at a side of the redundant gate driving circuit away from the display area, and the redundant light emitting control circuit comprises a redundant light emitting control signal output line;

[0059] In the alignment mark area, the redundant light emitting control signal output line is hollowed out.

[0060] Optionally, a first plate of a storage capacitor is provided in an area included in the flat redundant driving circuit area except the alignment mark area;

[0061] In a region included in the planar redundant driving circuit region except the alignment mark region, the second plate of the storage capacitor is not coupled to an output transistor included in the redundant driving circuit.

[0062] Optionally, the effective driving circuit includes a multi-stage shift register unit;

[0063] The shift register unit is coupled to the corresponding row of pixel units and is used to provide a gate driving signal and / or a light emitting control signal to the corresponding row of pixel units.

[0064] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a display panel, wherein the display panel includes a display area and a peripheral area disposed on a substrate, wherein the peripheral area includes an area between the display area and an edge of the display panel, and the peripheral area includes a flat area and a curved area; the flat area includes a flat redundant driving circuit area;

[0065] The manufacturing method of the display panel includes:

[0066] A plurality of pixel units are arranged in the display area, and a plurality of effective driving circuits and a plurality of redundant driving circuits are arranged in the peripheral area;

[0067] Disposing at least part of the redundant driving circuit in the flat redundant driving circuit area, the redundant driving circuit comprising at least one electrode layer disposed on the substrate;

[0068] Setting an alignment mark area in the flat redundant driving circuit area;

[0069] In the alignment mark area, at least one of the electrode layers is hollowed out, and / or at least one of the electrode layers is filled;

[0070] The minimum distance between the edges of the orthographic projections of two adjacent alignment mark areas on the substrate is an alignment mark distance, and at least one of the alignment mark distances is greater than a predetermined alignment mark distance.

[0071] Optionally, the predetermined alignment mark distance is 10 times the maximum pixel edge length;

[0072] The maximum pixel edge length is the maximum value among the pixel edge lengths of the plurality of pixel units;

[0073] The pixel edge length is the length of the edge of the orthographic projection of the pixel unit on the substrate.

[0074] In a third aspect, an embodiment of the present invention further provides a display device, characterized in that it includes the above-mentioned display panel.

[0075] Optionally, the display panel includes an upper surface, a lower surface, a first side surface, a second side surface, a third side surface and a fourth side surface; the first side surface, the second side surface, the third side surface and the fourth side surface are all curved side surfaces; an orthographic projection of the first side surface on the first plane does not overlap with an orthographic projection of the plane area on the first plane; an orthographic projection of the second side surface on the first plane does not overlap with an orthographic projection of the plane area on the first plane; an orthographic projection of the third side surface on the first plane does not overlap with an orthographic projection of the plane area on the first plane; an orthographic projection of the fourth side surface on the first plane does not overlap with an orthographic projection of the plane area on the first plane; and the first plane is parallel to the lower surface;

[0076] The first side surface is a left side surface, the second side surface is a lower side surface, the third side surface is an upper side surface, and the fourth side surface is a right side surface; the display panel further comprises a circuit board disposed on the lower surface; the circuit board is disposed on the lower side edge of the display panel or the upper side edge of the display panel;

[0077] The display device further includes a heat dissipation film, and the heat dissipation film is attached to the lower surface, the first side surface, the second side surface, the third side surface, and the fourth side surface.

[0078] Optionally, the display device further includes a packaging cover plate;

[0079] The package cover plate includes a first surface, and a fifth side surface, a sixth side surface, a seventh side surface and an eighth side surface respectively adjacent to the first surface;

[0080] The fifth side surface, the sixth side surface, the seventh side surface and the eighth side surface are all curved side surfaces;

[0081] The first surface is attached to the upper surface, the fifth side surface is attached to the first side surface, the sixth side surface is attached to the second side surface, the seventh side surface is attached to the third side surface, and the eighth side surface is attached to the fourth side surface.

[0082] In a fourth aspect, an embodiment of the present invention further provides a method for manufacturing a display device, which is used to manufacture a display device, wherein the display device includes a display panel, a heat dissipation film, and a packaging cover plate, wherein the display panel includes a display area and a peripheral area arranged on a substrate, wherein the peripheral area includes an area between the display area and an edge of the display panel, and wherein the peripheral area includes a flat area and a curved area; the flat area includes a flat redundant driving circuit area;

[0083] The manufacturing method of the display device comprises:

[0084] A plurality of pixel units are arranged in the display area, and a plurality of effective driving circuits and a plurality of redundant driving circuits are arranged in the peripheral area;

[0085] Disposing at least part of the redundant driving circuit in the flat redundant driving circuit area, the redundant driving circuit comprising at least one electrode layer disposed on the substrate;

[0086] Setting an alignment mark area in the flat redundant driving circuit area;

[0087] In the alignment mark area, at least one of the electrode layers is hollowed out, and / or at least one of the electrode layers is filled;

[0088] Using the alignment mark area, the display panel and the packaging cover plate are aligned and bonded, and the display panel and the heat dissipation film are aligned and bonded;

[0089] The minimum distance between the edges of the orthographic projections of two adjacent alignment mark areas on the substrate is an alignment mark distance, and at least one of the alignment mark distances is greater than a predetermined alignment mark distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] Figure 1A , Figure 1B and Figure 1C It is a top view of the four sides of the four-sided curved display panel before being bent after the circuit board is bent;

[0091] Figure 1D is a schematic diagram when the alignment mark area 70 is disposed at the lower left side of the four-sided bent display panel;

[0092] Figure 2A is a top view of a four-sided curved display panel before the circuit board is bent;

[0093] Figure 2B is a top view of the four-sided curved display panel after the four side surfaces are bent;

[0094] Figure 2C is a left side view of the four-sided curved display panel after the four side surfaces are bent;

[0095] Figure 2D is a bottom view of the four-sided curved display panel after the four side surfaces are bent;

[0096] Figure 3 yes Figure 1B Schematic diagram of the area division of the lower left rounded corner of the display panel;

[0097] Figure 4 is a schematic diagram of a portion of the area included in the driving circuit area and a portion of the area included in the fan-out area 31;

[0098] Figure 5A is a top view of an embodiment of an active pattern 81 included in a semiconductor layer disposed on a substrate in a flat redundant driving circuit region;

[0099] Figure 5B is a top view of an embodiment of a first gate metal pattern 82 included in a first gate metal layer disposed above the semiconductor layer in a flat redundant driving circuit region;

[0100] Figure 5C It is in the flat redundant drive circuit area, Figure 5A and Figure 5B Schematic diagram after superposition;

[0101] Figure 5D is in the flat redundant drive circuit area, in Figure 5C A schematic diagram of a second gate metal pattern 83 including a second gate metal layer is added on the basis of FIG.

[0102] Figure 5E It is a schematic diagram of providing a plurality of via holes H0 after the semiconductor layer, the first gate metal layer and the second gate metal layer are provided in sequence in the flat redundant driving circuit area;

[0103] Fig. 5F It is a schematic diagram of setting a source-drain metal layer S0 after setting a plurality of via holes H0 in a flat redundant driving circuit area;

[0104] Figure 5G It is a schematic diagram of an embodiment in which an anode layer 90 is provided on a source-drain metal layer in a flat redundant driving circuit region;

[0105] Figure 5H is a schematic diagram of another embodiment in which an anode layer 90 is provided on a source-drain metal layer in a flat redundant driving circuit region;

[0106] Fig.5I is a schematic diagram of another embodiment in which an anode layer 90 is provided on a source-drain metal layer in a flat redundant driving circuit region;

[0107] Figure 5J is a schematic diagram of yet another embodiment in which an anode layer 90 is provided on a source-drain metal layer in a flat redundant driving circuit region;

[0108] Fig. 6A is a schematic diagram of the active layer pattern;

[0109] Figure 6B is a schematic diagram of a first gate metal pattern included in the first gate metal layer;

[0110] Figure 6Cis a schematic diagram of a second gate metal pattern included in the second gate metal layer;

[0111] Fig.6D yes Fig. 6A , Figure 6B , Figure 6C Schematic diagram of setting vias after superposition;

[0112] Fig. 6E is Fig.6D A schematic diagram showing a source-drain metal layer being arranged on the stack diagram shown;

[0113] Fig. 6F is Fig. 6E A schematic diagram of an anode layer being arranged on the top;

[0114] Figure 6G yes Fig. 6E Schematic diagram of source and drain metal layers in FIG.

[0115] Figure 6H is Figure 6B A schematic diagram with numbering based on the above;

[0116] Fig.6I is Figure 6C Based on the schematic diagram labeled. DETAILED DESCRIPTION

[0117] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0118] As the demand for display devices increases, the number of circuits and wirings in the display panel is also increasing. In this case, pad bending (circuit board bending) technology can be used on the upper or lower frame of the display panel. The circuit board bending technology is to bend part of the circuit board (the circuit board can be a flexible circuit board) included in the display device to the back of the display panel, and a heat dissipation film will be attached to the surface of the circuit board bent to the back of the display panel to reduce the heat generated when the circuit is working. In order to improve the accuracy of bending alignment and heat dissipation film attachment, it is necessary to achieve alignment by identifying the alignment mark in the display panel. In a specific implementation, the alignment mark may include a circuit board bending alignment mark and / or a heat dissipation film attachment alignment mark, and the alignment mark can be identified by an alignment camera to lock the position. Since the clarity of the pattern identified by the alignment camera is related to the consistency of the object distance, the alignment mark needs to be set in a plane area, and in the plane area, the surface of the display panel is a plane.

[0119] When the display panel is a four-sided curved display panel, the upper surface of the display panel and the lower surface of the display panel are planes, and the upper side surface of the display panel, the lower side surface of the display panel, the left side surface of the display panel and the right side surface of the display panel are all curved sides, so the area of ​​the plane region is small. Figure 1A , Figure 1B and Figure 1C It is a top view of the four sides of the four-sided curved display panel before being bent after the circuit board is bent.

[0120] exist Figure 1A In the figure, the edge of the display panel is marked with 201, the boundary of the display area is marked with 202, and the display area of ​​the display panel is inside the boundary of the display area 202;

[0121] The peripheral area of ​​the display panel is an area between the display area included in the display panel and the edge 201 of the display panel;

[0122] exist Figure 1B , the edge of the display panel is labeled 201, the left curved surface area of ​​the display panel is labeled 203-1, the lower curved surface area of ​​the display panel is labeled 203-2, the upper curved surface area of ​​the display panel is labeled 203-3, and the right curved surface area of ​​the display panel is labeled 203-4;

[0123] exist Figure 1B In the figure, the line marked with L1 is a first dotted line, and the area on the left side of the display panel enclosed by the first dotted line L1 and the edge of the display panel is a left curved surface area 203 - 1 of the display panel;

[0124] The second dotted line labeled L2 is a second dotted line, and the area on the lower side of the display panel enclosed by the second dotted line L2 and the edge of the display panel is a lower curved surface area 203 - 2 of the display panel;

[0125] The third dotted line is labeled L3, and the area on the upper side of the display panel enclosed by the third dotted line L3 and the edge of the display panel is the upper curved surface area 203-3 of the display panel;

[0126] The fourth imaginary line is labeled L4, and the area on the right side of the display panel enclosed by the fourth imaginary line L4 and the edge of the display panel is the right curved surface area 203-4 of the display panel;

[0127] The plane area in the peripheral area of ​​the display panel may be an area in the peripheral area of ​​the display panel that is not covered by the left curved area 203-1, the lower curved area 203-2, the upper curved area 203-3, and the right curved area 203-4; the curved area may be an area included in the peripheral area except the plane area;

[0128] exist Figure 1B In the figure, the plane area labeled 11 is the first plane area included in the plane area of ​​the display panel, the plane area labeled 12 is the second plane area included in the plane area of ​​the display panel, the plane area labeled 13 is the third plane area included in the plane area of ​​the display panel, and the plane area labeled 14 is the fourth plane area included in the plane area of ​​the display panel, that is, in the four-sided curved display panel, the plane areas are located at the upper left side, lower left side, upper right side and lower right side adjacent to the display area.

[0129] exist Figure 1B In the figure, the first plane area 11 is a plane area located at the lower left side of the display panel, the second plane area 12 is a plane area located at the lower right side of the display panel, the third plane area 13 is a plane area located at the upper left side of the display panel, and the fourth plane area 14 is a plane area located at the upper right side of the display panel;

[0130] The first plane area 11 is close to the lower left corner of the display area boundary 202 , the second plane area 12 is close to the lower right corner of the display area boundary 202 , the third plane area 13 is close to the upper left corner of the display area boundary 202 , and the fourth plane area 14 is close to the upper right corner of the display area boundary 202 .

[0131] In at least one embodiment of the present invention, the orthographic projection of the left side surface of the display panel on the first plane may overlap with the orthographic projection of the left curved surface area 203-1 on the first plane, the orthographic projection of the lower side surface of the display panel on the first plane may overlap with the orthographic projection of the lower curved surface area 203-2 on the first plane, the orthographic projection of the upper side surface of the display panel on the first plane may overlap with the orthographic projection of the upper curved surface area 203-3 on the first plane, and the orthographic projection of the right side surface of the display panel on the first plane may overlap with the orthographic projection of the right curved surface area 203-4 on the first plane;

[0132] The first plane is a plane parallel to the lower surface of the display panel.

[0133] like Figure 1C As shown, the lower left rounded corner of the display area boundary 202 can be the part between the first intersection P1 and the second intersection P2 included in the display area boundary 202; wherein the first intersection P1 is the intersection point where the first dotted line L1 intersects with the lower left part of the display area boundary 202, and the second intersection P2 is the intersection point where the second dotted line L2 intersects with the lower left part of the display area boundary 202.

[0134] like Figure 1CAs shown, the lower right rounded corner of the display area boundary 202 can be the part between the third intersection P3 and the fourth intersection P4 included in the display area boundary 202; wherein the third intersection P3 is the intersection point where the second dotted line L2 intersects with the lower right part of the display area boundary 202, and the fourth intersection P2 is the intersection point where the fourth dotted line L4 intersects with the lower left part of the display area boundary 202.

[0135] like Figure 1C As shown, the upper left rounded corner of the display area boundary 202 can be the part between the fifth intersection P5 and the sixth intersection P6 included in the display area boundary 202; wherein the fifth intersection P5 is the intersection point where the first dotted line L1 intersects with the upper left part of the display area boundary 202, and the sixth intersection P6 is the intersection point where the third dotted line L3 intersects with the upper left part of the display area boundary 202.

[0136] like Figure 1C As shown, the upper right rounded corner of the display area boundary 202 can be the part between the seventh intersection P7 and the eighth intersection P8 included in the display area boundary 202; wherein the seventh intersection P7 is the intersection point where the third imaginary line L3 intersects with the upper right part of the display area boundary 202, and the eighth intersection point P8 is the intersection point where the fourth imaginary line L4 intersects with the upper left part of the display area boundary 202.

[0137] Figure 2A This is a top view of the four-sided curved display panel before the circuit board is bent. Figure 2A In the figure, the reference numeral 20 is a circuit board, and the circuit board 20 may be a flexible circuit board. When manufacturing the four-sided curved display panel, the circuit board 20 needs to be bent to the back side of the display panel.

[0138] In at least one embodiment of the present invention, when the circuit board 20 is bent to the back of the display panel, a heat dissipation film may be attached to the back of the display panel and the four sides of the display panel for heat dissipation.

[0139] In at least one embodiment of the present invention, when the circuit board 20 is disposed on the lower side of the display panel, the circuit board 20 needs to be bent to the back of the display panel, and an alignment mark can be set on the first plane area 11 and / or the second plane area 12 to perform bending alignment and alignment for laminating a heat dissipation film; and when the circuit board 20 is disposed on the lower side of the display panel, since the upper side of the display panel also needs to be laminating a heat dissipation film, an alignment mark can also be set on the third plane area 13 and / or the fourth plane area 14 to perform alignment marks for laminating a heat dissipation film;

[0140] In a specific implementation, when the circuit board 20 is arranged on the lower side of the display panel, a bending alignment mark can also be set on the circuit board. By combining the bending alignment mark set on the circuit board and the alignment mark set in the first plane area 11 and / or the second plane area 12, bending alignment can be performed.

[0141] In at least one embodiment of the present invention, when the circuit board 20 is disposed on the upper side of the display panel, the circuit board 20 needs to be bent to the back of the display panel, and an alignment mark can be set on the third plane area 13 and / or the fourth plane area 14 to perform bending alignment and alignment for laminating a heat dissipation film; and when the circuit board 20 is disposed on the upper side of the display panel, since the lower side of the display panel also needs to be laminating a heat dissipation film, an alignment mark can also be set on the first plane area 11 and / or the second plane area 12 to perform alignment marks for laminating a heat dissipation film;

[0142] In a specific implementation, when the circuit board 20 is disposed on the upper side of the display panel, a bending alignment mark may also be disposed on the circuit board, and bending alignment may be performed by combining the bending alignment mark disposed on the circuit board and the alignment mark disposed on the third plane area 13 and / or the fourth plane area 14. In the peripheral area of ​​the display panel, a fanout area, a drive circuit area, and a signal line area may be disposed in sequence along a direction away from the display area;

[0143] The fan-out area is an area where the connection line between the data line and the source driver in the display area is located, and a high voltage signal line may be arranged in the fan-out area; the high voltage signal line is used to provide a high voltage signal VDD;

[0144] A low voltage signal line may be provided in the signal line area; the low voltage signal line is used to provide a low voltage signal VSS;

[0145] The driving circuit area may include a driving circuit region and a redundant driving circuit region; the redundant driving circuit region may include a flat redundant driving circuit region;

[0146] In the driving circuit area, an effective driving circuit including a multi-stage shift register unit is arranged, and the effective driving circuit may include a gate driving circuit, and the gate driving circuit is used to provide gate driving signals for multiple rows of pixel units in the display area respectively; optionally, the effective driving circuit may also include a light emitting control circuit, and the light emitting control circuit is used to provide light emitting control signals for multiple rows of pixel units in the display area respectively;

[0147] In the redundant driving circuit area, a redundant driving circuit is provided, and the redundant driving circuit may include at least one level of redundant shift register unit. The redundant shift register unit is not coupled to the pixel unit in the display area, but is retained only to maintain etching uniformity and rationality of layout. The signal line in the redundant shift register unit can be connected to a fixed voltage signal to reduce the influence of signal jumps on the effective driving circuit in the driving circuit area.

[0148] In at least one embodiment of the present invention, the driving circuit area may include a blank area between the driving circuit and the fan-out area, and a blank area between the driving circuit and the signal line area, but the present invention is not limited thereto.

[0149] In at least one embodiment of the present invention, in the fan-out region, a gate metal layer and an anode layer may be sequentially arranged on the substrate, the gate metal layer may include a first gate metal layer and a second gate metal layer, and the connecting line between the data line and the source driver may be arranged on the first gate metal layer and the second gate metal layer; and, in the fan-out region, a plurality of openings may also be provided on the anode layer, and the openings are used to release air for the organic film layer.

[0150] In at least one embodiment of the present invention, in the signal line region, a semiconductor layer, a source-drain metal layer and an anode layer may be sequentially arranged on the substrate;

[0151] The source-drain metal layer includes a low voltage signal line;

[0152] In the signal line area, the purpose of setting an anode layer on the source-drain metal layer is to overlap the cathode of the light-emitting element in the display area to the low-voltage signal line (the area of ​​the anode layer covering the source-drain metal layer is determined by the overlap between the low-voltage signal line and the cathode).

[0153] Furthermore, in the signal line region, a plurality of openings may be provided on the anode layer to release gas from the organic film layer.

[0154] Figure 3 yes Figure 1B Schematic diagram of the area division of the lower left rounded corner of the display panel. Figure 3 Among them, the one labeled 30 is the AA area, the one labeled 31 is the fan-out area, the one labeled 32 is the driving circuit area, the one labeled 33 is the signal line area, the one labeled 201 is the edge of the display panel, and the one labeled 202 is the display area boundary.

[0155] like Figure 1B As shown, when the circuit board 20 is disposed on the lower side of the display panel, in a preferred case, the alignment mark area can be disposed in the first plane area 11 and / or the second plane area 12, but not limited thereto.

[0156] In at least one embodiment of the present invention, when the circuit board to be bent is disposed on the upper side of the display panel, the position mark area may preferably be disposed in the third plane area 13 and / or the fourth plane area 14, but is not limited thereto.

[0157] In at least one embodiment of the present invention, the plane area may include at least a portion of the redundant driving circuit area;

[0158] When the planar area includes at least a portion of the redundant driving circuit region, at least a portion of the redundant driving circuit region is a planar redundant driving circuit region.

[0159] In at least one embodiment of the present invention, although a redundant driving circuit is provided in the redundant driving circuit area for process uniformity, the redundant driving circuit is not coupled to the pixel unit in the display area and is not used to provide the pixel unit with a gate driving signal and a light emitting control signal. Therefore, even if at least one layer of the gate metal layer, the source / drain metal layer, the semiconductor layer, and the anode layer is hollowed out in the alignment mark area included in the flat redundant driving circuit area, it will not affect the display of the display panel. Therefore, at least one embodiment of the present invention chooses to set the alignment mark area in the flat redundant driving circuit area to perform accurate alignment without increasing the border and affecting the display.

[0160] Figure 1B is a top view of the four sides of the four-sided curved display panel before being bent. When manufacturing the display panel, the four sides of the four-sided curved display panel need to be bent. Figure 1B In the embodiment, the upper surface is the surface of the four-sided curved display panel for displaying. When the four side surfaces are bent, they are bent along the first imaginary line L1, the second imaginary line L2, the third imaginary line L3 and the fourth imaginary line L4, so that the bent side surfaces are close to the upper surface. Figure 1A In the figure, the portion labeled 202 is the display area boundary, so after bending the four side surfaces, the portion between the display area boundary 202 on the left side of the display area and the first dotted line L1 is bent to the left side, the portion between the display area boundary 202 on the right side of the display area and the fourth dotted line L4 is bent to the right side, the portion between the display area boundary 202 on the lower side of the display area and the second dotted line L2 is bent to the lower side, and the portion between the display area boundary 202 on the upper side of the display area and the third dotted line L3 is bent to the upper side.

[0161] Figure 2B is a top view of the four sides of the four-sided curved display panel after being bent; Figure 2B In the embodiment, the plane region includes a first plane area 11, a second plane area 12, a third plane area 13 and a fourth plane area 14.

[0162] Figure 2C is a left view of the four-sided curved display panel after the four sides are bent; Figure 2C In the figure, the side marked with 21 corresponds to the first dotted line L1, the side marked with 201 is the edge of the display panel, and the side marked with 202 is the boundary of the display area.

[0163] Figure 2D is a bottom view of the four-sided curved display panel after the four sides are bent; Figure 2D In the figure, the side labeled 23 corresponds to the third dotted line L3, the side labeled 201 is the edge of the display panel, and the side labeled 202 is the boundary of the display area.

[0164] The display panel described in at least one embodiment of the present invention comprises a display area and a peripheral area arranged on a substrate; the display panel comprises a plurality of pixel units arranged in the display area, the peripheral area comprises an area between the display area and an edge of the display panel, the display panel further comprises a plurality of effective driving circuits and a plurality of redundant driving circuits, the plurality of effective driving circuits and the plurality of redundant driving circuits being arranged in the peripheral area; wherein,

[0165] At least one of the plurality of effective driving circuits is electrically connected to at least one of the plurality of pixel units to drive the pixel unit to display, and the redundant driving circuit includes at least one electrode layer disposed on the substrate;

[0166] The peripheral area includes a plane area and a curved area, wherein at least part of the redundant driving circuit is located in a flat redundant driving circuit area included in the plane area;

[0167] The flat redundant driving circuit area includes at least two alignment mark areas;

[0168] In the alignment mark area, at least one of the electrode layers is hollowed out, and / or at least one of the electrode layers is filled;

[0169] The minimum distance between the edges of the orthographic projections of two adjacent alignment mark areas on the substrate is the alignment mark distance, and at least one of the alignment mark distances is greater than the predetermined alignment mark distance. The display panel according to at least one embodiment of the present invention is provided with an alignment mark area in the flat redundant driving circuit area, and in the alignment mark area,

[0170] At least one of the electrode layers is hollowed out so that in the alignment mark area, the transmittance of the alignment mark area is higher than the transmittance of the surrounding area, so that the alignment mark can be accurately performed; and / or,

[0171] In the alignment mark area, at least one of the electrode layers is filled, and light reflection by the electrode layer can form a strong light-dark contrast with other areas, thereby achieving alignment mark.

[0172] In at least one embodiment of the present invention, the surrounding area may be an area included in the peripheral area and closer to the alignment mark area.

[0173] The display panel described in at least one embodiment of the present invention does not need to be provided with a dedicated alignment mark pattern, but is aligned by hollowing out at least one electrode layer and / or filling at least one electrode layer in the alignment mark area, thereby greatly saving space.

[0174] In at least one embodiment of the present invention, the alignment mark area can be set at at least one of the lower left corner, lower right corner, upper left corner, and upper right corner of the display panel, so at least one of the alignment mark distances is set to be greater than the predetermined alignment mark area.

[0175] In at least one embodiment of the present invention, the electrode layer may be at least one of a gate metal layer, a source / drain metal layer, and an anode layer, but is not limited thereto.

[0176] Optionally, the predetermined alignment mark distance may be 10 times the maximum pixel edge length;

[0177] The maximum pixel edge length is the maximum value among the pixel edge lengths of the plurality of pixel units;

[0178] The pixel edge length is the length of the edge of the orthographic projection of the pixel unit on the substrate.

[0179] In at least one embodiment of the present invention, the area of ​​the orthographic projection of the alignment mark region on the substrate may be larger than the predetermined area;

[0180] The predetermined area is the maximum pixel area;

[0181] The maximum pixel area is a maximum value among pixel areas of the plurality of pixel units, and the pixel area is an area of ​​an orthographic projection of the pixel unit on the substrate.

[0182] Optionally, the redundant driving circuit may further include at least one semiconductor layer disposed on the substrate;

[0183] In the alignment mark region, the at least one semiconductor layer is hollowed out, or the at least one semiconductor layer is filled.

[0184] In a specific implementation, the redundant driving circuit may further include a semiconductor layer, and in the alignment mark area, the semiconductor layer is hollowed out or filled; in the alignment mark area, when the semiconductor layer is hollowed out, the transmittance of the alignment mark area is further improved to enable accurate alignment marking.

[0185] Optionally, in the alignment mark area, at least one of the electrode layers is filled; in the first area, the electrode layer is hollowed out;

[0186] The first area is an area surrounding the alignment mark area and included in the flat redundant driving circuit area.

[0187] In a specific implementation, there is a first area around the alignment mark area, in which at least one of the electrode layers is filled, and in the first area, the electrode layer is hollowed out, so as to improve the transmittance of the alignment mark area and form a strong light-dark contrast with other areas through the reflection of at least one of the electrode layers located in the alignment mark area, thereby achieving alignment marking.

[0188] In at least one embodiment of the present invention, the first area is a partial area included in the flat redundant area circuit area, and the first area surrounds the alignment mark area.

[0189] In a specific implementation, in the plane area, the surface of the display panel is a plane.

[0190] Optionally, the display panel includes an upper surface, a lower surface, a first side surface, a second side surface, a third side surface and a fourth side surface;

[0191] The upper surface and the lower surface are both planes;

[0192] The first side surface, the second side surface, the third side surface and the fourth side surface are all curved side surfaces;

[0193] The orthographic projection of the first side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane;

[0194] The orthographic projection of the second side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane;

[0195] The orthographic projection of the third side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane;

[0196] The orthographic projection of the fourth side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane;

[0197] The first plane is parallel to the lower surface.

[0198] In at least one embodiment of the present invention, the display panel may be a four-sided curved display panel. Figure 1B A top view of a four-sided curved display panel is shown, wherein the first side surface may be Figure 1B The left side surface in the embodiment of the present invention, the second side surface may be Figure 1B The lower side surface in the third side surface may be Figure 1B The upper side surface in the fourth side surface may be Figure 1B The right side of, but not limited to, the right side of

[0199] According to a specific embodiment, the first side surface may be a left side surface, the second side surface may be a lower side surface, the third side surface may be an upper side surface, and the fourth side surface may be a right side surface; the display panel may further include a circuit board disposed on the lower surface, and the circuit board is disposed on the lower side of the display panel;

[0200] The longest distance between the orthographic projection of the alignment mark area on the first plane and the lower left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the lower right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

[0201] In a specific implementation, the predetermined distance may be selected according to actual conditions; for example, the predetermined distance may be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited thereto.

[0202] In at least one embodiment of the present invention, when the circuit board is disposed on the lower side of the display panel, the alignment mark area can be disposed at the lower left corner close to the boundary of the display area and / or the lower right corner close to the boundary of the display area.

[0203] like Figure 1D As shown, when the alignment mark area 70 is close to the lower left corner of the display area boundary 202, the longest distance between the orthographic projection of the alignment mark area 70 on the first plane and the lower left corner of the display area boundary 202 is: the longest distance between any point on the boundary line of the orthographic projection of the alignment mark 70 on the first plane and any point on the lower left corner of the display area boundary 202. Figure 1D In the embodiment, the alignment mark area 70 is L-shaped, but not limited thereto.

[0204] In at least one embodiment of the present invention, when the alignment mark area is close to the lower right corner of the display area boundary, the longest distance between the orthographic projection of the alignment mark area on the first plane and the lower right corner of the orthographic projection of the display area boundary of the display panel on the first plane may refer to: the longest distance between any point on the boundary line of the orthographic projection of the alignment mark area on the first plane and any point on the lower right corner of the display area boundary.

[0205] According to another specific embodiment, the first side surface may be a left side surface, the second side surface may be a lower side surface, the third side surface may be an upper side surface, and the fourth side surface may be a right side surface; the display panel may further include a circuit board disposed on the lower surface, and the circuit board is disposed on the upper side of the display panel;

[0206] The longest distance between the orthographic projection of the alignment mark area on the first plane and the upper left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

[0207] In at least one embodiment of the present invention, when the alignment mark area is close to the upper left corner of the display area boundary, the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper left corner of the orthographic projection of the display area boundary of the display panel on the first plane refers to: the longest distance between any point on the boundary line of the orthographic projection of the alignment mark area on the first plane and any point on the upper left corner of the display area boundary.

[0208] In at least one embodiment of the present invention, when the alignment mark area is close to the upper right rounded corner of the display area boundary, the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane refers to: the longest distance between any point on the boundary line of the orthographic projection of the alignment mark area on the first plane and any point on the upper right rounded corner of the display area boundary.

[0209] In a specific implementation, the predetermined distance may be selected according to actual conditions; for example, the predetermined distance may be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited thereto.

[0210] In at least one embodiment of the present invention, when the circuit board is disposed on the upper side of the display panel, the alignment mark area can be disposed at the upper left corner close to the boundary of the display area and / or the upper right corner close to the boundary of the display area.

[0211] In at least one embodiment of the present invention, the first side surface may be a left side surface, the second side surface may be a lower side surface, the third side surface may be an upper side surface, and the fourth side surface may be a right side surface; the display panel further includes a circuit board disposed on the lower surface, and the circuit board is disposed on the lower side of the display panel;

[0212] The longest distance between the orthographic projection of the alignment mark area on the first plane and the upper left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

[0213] In a specific implementation, the predetermined distance may be selected according to actual conditions; for example, the predetermined distance may be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited thereto.

[0214] In at least one embodiment of the present invention, when the circuit board is disposed on the lower side of the display panel, the alignment mark area can be disposed at the upper left corner close to the boundary of the display area and / or the upper right corner close to the boundary of the display area.

[0215] In at least one embodiment of the present invention, the first side surface may be a left side surface, the second side surface may be a lower side surface, the third side surface may be an upper side surface, and the fourth side surface may be a right side surface; the display panel further includes a circuit board disposed on the lower surface, and the circuit board is disposed on the upper side of the display panel;

[0216] The longest distance between the orthographic projection of the alignment mark area on the first plane and the lower left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the lower right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

[0217] In a specific implementation, the predetermined distance may be selected according to actual conditions; for example, the predetermined distance may be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited thereto.

[0218] In at least one embodiment of the present invention, when the circuit board is disposed on the upper side of the display panel, the alignment mark area can be disposed at the lower left corner close to the boundary of the display area and / or the lower right corner close to the boundary of the display area.

[0219] In a specific implementation, the display panel includes a semiconductor layer, a gate metal layer and a source-drain metal layer sequentially arranged on a substrate;

[0220] In the alignment mark region, the gate metal layer and the source / drain metal layer are hollowed out.

[0221] In at least one embodiment of the present invention, the at least one electrode layer included in the redundant driving circuit may include a gate metal layer and a source-drain metal layer, but is not limited thereto.

[0222] In a preferred embodiment, the semiconductor layer is also hollowed out in the alignment mark region.

[0223] In a specific implementation, the alignment mark area can be included in a flat redundant driving circuit area; in addition to the alignment mark area, the circuit wiring is densely distributed in the peripheral area close to the alignment mark area. Since the wiring is opaque to visible light, under certain backlight conditions, it will appear black in the field of view of the alignment camera. However, there is no wiring arrangement in the alignment mark area, and the backlight can almost completely pass through the alignment mark area to enter the alignment camera, forming a strong contrast with the surrounding area, so the alignment camera can identify the alignment mark area.

[0224] In a specific implementation, the semiconductor layer may also be filled in the alignment mark area.

[0225] In a specific implementation, the display panel further includes an anode layer disposed on a side of the source / drain metal layer away from the gate metal layer;

[0226] In the alignment mark area, the anode layer is not provided with an opening, and the anode layer is filled so that the alignment camera can identify the alignment mark area.

[0227] In at least one embodiment of the present invention, the at least one electrode layer included in the redundant driving circuit may further include an anode layer, but the present invention is not limited thereto.

[0228] Optionally, the anode layer may be a stacked structure, and the anode layer may include a first indium tin oxide layer, a silver layer, and a second indium tin oxide layer arranged in sequence, but is not limited thereto.

[0229] Optionally, an edge of an orthographic projection of the alignment mark area on the substrate is circular, polygonal, L-shaped or T-shaped.

[0230] In at least one embodiment of the present invention, the gate metal layer may include a first gate metal layer and a second gate metal layer which are sequentially arranged on a side of the semiconductor layer away from the substrate.

[0231] Figure 43 shows a partial area included in the driving circuit area, a partial area included in the fan-out area 31, and a partial area included in the signal line area 33.

[0232] like Figure 4 As shown, the plane area may include a flat redundant driving circuit area 71; the alignment mark area 70 is included in the flat redundant driving circuit area 71;

[0233] The flat redundant driving circuit area 71 may be included in the driving circuit area. In addition to the flat redundant driving circuit area 71, the driving circuit area may also include a first driving circuit area 721 and a second driving circuit area 722. The flat redundant driving circuit area 71 includes an alignment mark area 70.

[0234] The display panel comprises a semiconductor layer, a first gate metal layer, a second gate metal layer, a source-drain metal layer and an anode layer which are sequentially arranged on a substrate;

[0235] In the area of ​​the flat redundant driving circuit area 71 except the alignment mark area 70, at least one level of redundant shift register unit is arranged; in the first driving circuit area 721 and the second driving circuit area 722, an effective driving circuit including a plurality of shift register units is arranged;

[0236] In the alignment mark area 70, the semiconductor layer, the gate metal layer and the source-drain metal layer are all hollowed out, so that the light transmittance of the alignment mark area 70 is much higher than the light transmittance of the area adjacent to the alignment mark area 70 included in the driving circuit area, so that the alignment camera can accurately identify the alignment mark area; and there is no need to place the alignment mark in a separate space, which can reduce the frame of the display panel and achieve accurate alignment of the process;

[0237] In the alignment mark area 70 , the anode layer is not provided with an opening, and the anode layer is filled so that the alignment camera can identify the alignment mark area 70 ;

[0238] In the driving circuit area except the alignment mark area 70, the anode layer may be provided with a plurality of openings arranged at intervals to release gas from the organic film layer.

[0239] like Figure 4 As shown, the shape of the edge of the orthographic projection of the alignment mark area 70 on the substrate is L-shaped, but the present invention is not limited thereto. In a specific implementation, the shape of the edge of the orthographic projection of the alignment mark area 70 on the substrate may also be other shapes.

[0240] Figure 5Ais a top view of at least one embodiment of an active pattern 81 included in a semiconductor layer disposed on a substrate in a flat redundant driving circuit region;

[0241] Figure 5B A top view of at least one embodiment of a first gate metal pattern 82 included in a first gate metal layer disposed above the semiconductor layer in a flat redundant driving circuit region;

[0242] Figure 5C It is in the flat redundant drive circuit area, Figure 5A and Figure 5B Schematic diagram after superposition;

[0243] Figure 5D is in the flat redundant drive circuit area, in Figure 5C A schematic diagram of a second gate metal pattern 83 including a second gate metal layer is added on the basis of FIG.

[0244] Figure 5E It is a schematic diagram of providing a plurality of via holes H0 after the semiconductor layer, the first gate metal layer and the second gate metal layer are provided in sequence in the flat redundant driving circuit area;

[0245] Fig. 5F It is a schematic diagram of setting a source-drain metal layer S0 after setting a plurality of via holes H0 in a flat redundant driving circuit area;

[0246] like Fig. 5F As shown, in the alignment mark area 70 , the first gate metal layer, the second gate metal layer, the semiconductor layer and the source / drain metal layer are all hollowed out.

[0247] Figure 5G It is a schematic diagram of an anode layer 90 provided on a source-drain metal layer in a flat redundant driving circuit region; in an alignment mark region 70, the anode layer 90 is not provided with an opening, and the anode layer 90 is filled up so that an alignment camera can identify the alignment mark region 70; in regions other than the alignment mark region 70, the anode layer 90 is provided with a plurality of openings 9g1.

[0248] exist Fig. 5F and Figure 5G In the figure, the area surrounded by the dotted line is the alignment mark area 70, and the shape of the edge of the orthographic projection of the alignment mark area 70 on the substrate is L-shaped, but not limited thereto.

[0249] exist Figure 5G In the illustrated embodiment, in the alignment mark region, the anode pattern included in the anode layer may be a whole anode pattern.

[0250] Optionally, the display panel further comprises an anode layer arranged on a side of the source / drain metal layer away from the gate metal layer;

[0251] In the alignment mark area, the anode layer may also be hollowed out.

[0252] like Figure 5H As shown, in the flat redundant driving circuit area, an anode layer 90 is provided on the source and drain metal layer; Figure 5H In a corresponding embodiment, in the alignment mark area 70, the anode layer 90 is hollowed out to further improve the light transmittance of the alignment mark area and form a strong light-dark contrast with other areas, so that alignment marking can be performed.

[0253] Optionally, the display panel further comprises an anode layer arranged on a side of the source / drain metal layer away from the gate metal layer;

[0254] In the alignment mark region, the anode layer is not provided with an opening, the anode layer is filled, and the gate metal layer and the source-drain metal layer are hollowed out.

[0255] In at least one embodiment of the present invention, in a first region, the anode layer, the gate metal layer and the source / drain metal layer are hollowed out; the first region is a region surrounding the alignment mark region and included in the flat redundant driving circuit region.

[0256] In a specific implementation, in the alignment mark area, the anode layer is not provided with an opening and is filled. In the first area, the anode layer, the gate metal layer and the source / drain metal layer are all hollowed out, so as to improve the transmittance of the alignment mark area and form a strong contrast between light and dark in other areas through the reflection of a whole anode pattern with high reflectivity in the alignment mark area, so as to achieve alignment marking.

[0257] like Fig.5I As shown, in the flat redundant driving circuit area, an anode layer 90 is set on the source-drain metal layer, in the alignment mark area 70, the anode layer 90 is filled, and a first area 91 is set around the alignment mark area 70, in the first area 91, the anode layer 90 is hollowed out.

[0258] Optionally, the display panel may further include an anode layer disposed on a side of the source / drain metal layer away from the gate metal layer;

[0259] In the alignment mark area, the anode layer includes an alignment mark pattern.

[0260] In a specific implementation, the anode layer may include an alignment mark pattern disposed in the alignment mark area, so that an alignment camera can accurately capture the alignment mark pattern for alignment.

[0261] In at least one embodiment of the present invention, the orthographic projection of the alignment mark pattern on the substrate may be L-shaped, T-shaped or polygonal, but is not limited thereto.

[0262] like Figure 5J As shown, in the flat redundant driving circuit area, an anode layer 90 is set on the source and drain metal layer. In the alignment mark area 70, the anode layer 90 includes a T-shaped alignment mark pattern 92 to facilitate the alignment camera to accurately capture the alignment mark pattern 92 for alignment.

[0263] In a specific implementation, a redundant driving circuit is provided in an area of ​​the redundant driving circuit area except the alignment mark area; the redundant driving circuit may include at least one output transistor.

[0264] In the embodiment of the present invention, Figure 5A-5F As shown, in the alignment mark area, the active layer in the output transistor, the first gate metal layer in the output transistor, the second gate metal layer in the output transistor and the source and drain metal layer can all be hollowed out, that is, the alignment mark area can be the area where the output transistor is originally set, but is not limited to this.

[0265] In a specific implementation, in the flat redundant driving circuit area, a first insulating layer may be provided between the semiconductor layer and the first gate metal layer, a second insulating layer may be provided between the first gate metal layer and the second gate metal layer, a third insulating layer may be provided between the second gate metal layer and the source-drain metal layer, and a fourth insulating layer may be provided between the source-drain metal layer and the anode layer. Since the transmittance of the first insulating layer, the transmittance of the second insulating layer, the transmittance of the third insulating layer and the transmittance of the fourth insulating layer are relatively high, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may not be hollowed out in the alignment mark area.

[0266] In at least one embodiment of the present invention, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be made of silicon oxide or silicon nitride, but the present invention is not limited thereto.

[0267] In specific implementation,

[0268] The redundant driving circuit includes a multi-stage redundant shift register unit, and the redundant shift register unit is not coupled to the pixel unit.

[0269] In at least one embodiment of the present invention, the shift register unit included in the redundant driving circuit is not coupled to the pixel unit in the display area.

[0270] In at least one embodiment of the present invention, at least one level of the redundant shift register unit includes the alignment mark area, and the at least one level of the redundant shift register unit is different from other redundant shift register units. The other redundant shift register units are: the redundant shift register units included in the redundant driving circuit except for the at least one level of the redundant shift register unit.

[0271] In at least one embodiment of the present invention, the effective driving circuit may include a multi-stage shift register unit;

[0272] The shift register unit is coupled to the corresponding row of pixel units and is used to provide a gate driving signal and / or a light emitting control signal to the corresponding row of pixel units.

[0273] In at least one embodiment of the present invention, an effective driving circuit may be provided in the driving circuit region, wherein the effective driving circuit includes a shift register unit for providing a gate driving signal and / or a light emitting control signal for a corresponding row of pixel units in the display region.

[0274] Optionally, in the alignment mark area, at least one film layer included in the output transistor in the redundant driving circuit is hollowed out.

[0275] Optionally, the redundant driving circuit may include a redundant gate driving circuit and a redundant light emitting control circuit, wherein the redundant light emitting control circuit is arranged on a side of the redundant gate driving circuit away from the display area; the redundant light emitting control circuit includes a redundant light emitting control signal line;

[0276] In the alignment mark area, the redundant light emitting control signal output line is hollowed out.

[0277] Optionally, a first plate of a storage capacitor is provided in an area included in the redundant driving circuit area except the alignment mark area;

[0278] In an area included in the redundant driving circuit area except the alignment mark area, the second plate of the storage capacitor is not coupled to an output transistor included in the redundant driving circuit.

[0279] exist Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Figure 6H and Fig.6I In the figure, the area labeled 61 is a partial area included in the flat redundant driving circuit area, the area labeled 70 is an alignment mark area, and the area labeled 62 is a partial area included in the driving circuit area.

[0280] Fig. 6A is a schematic diagram of the active layer graphics, Figure 6B is a schematic diagram of a first gate metal pattern included in the first gate metal layer, Figure 6C is a schematic diagram of a second gate metal pattern included in the second gate metal layer, Fig.6D yes Fig. 6A , Figure 6B , Figure 6C Schematic diagram of setting vias after superposition. Fig. 6E is Fig.6D A schematic diagram of setting a source-drain metal layer on the stack diagram shown in FIG. Fig. 6F is Fig. 6E A schematic diagram of setting an anode layer on the top. Fig. 6F As shown, in the alignment mark area 70, the anode layer is not provided with an opening so that the alignment camera can identify the alignment mark area 70; in the area other than the alignment mark area 70, the anode layer is provided with a plurality of openings 9g1.

[0281] Figure 6G yes Fig. 6E Schematic diagram of the source and drain metal layers in .

[0282] exist Figure 6A-Figure 6I In a corresponding embodiment, the effective driving circuit may include a gate driving signal output line, a first storage capacitor, a second storage capacitor, a first output transistor and a second output transistor; the effective driving circuit is used to provide a gate driving signal;

[0283] The first electrode of the first output transistor may be coupled to the gate drive signal line;

[0284] The first electrode of the first output transistor may be reused as the first electrode of the second output transistor; the first electrode may be a source or a drain;

[0285] The first plate of the first storage capacitor is coupled to the gate of the first output transistor, the first plate of the second storage capacitor is coupled to the gate of the second output transistor, the second plate of the first storage capacitor is coupled to the first voltage signal line, and the second plate of the second storage capacitor is coupled to the gate drive signal line;

[0286] In at least one embodiment of the present invention, the first output transistor can be used to control the output of a first voltage signal through the gate drive signal line, and the second output transistor can be used to control the output of a second voltage signal through the gate drive signal line, but is not limited thereto.

[0287] Optionally, the first voltage signal may be a high voltage signal, and the second voltage signal may be a low voltage signal, but is not limited thereto.

[0288] exist Figure 6G In the figure, the gate drive signal output line is labeled G0, and the first voltage signal line is labeled V1; Figure 6C In the partial area 62 included in the driving circuit area, the line labeled E0 is a light emitting control signal output line, such as Figure 6G As shown, the gate drive signal output line G0 is coupled to the first electrode S1 of the first output transistor. Figure 6G , the second electrode of the first output transistor is labeled D1;

[0289] exist Figure 6C In the partial area 61 included in the flat redundant driving circuit area, the line labeled E1 is the first redundant light emitting control signal output line, and the line labeled E2 is the second redundant light emitting control signal output line; in the area other than the alignment mark area 70 in the partial area 61 included in the flat redundant driving circuit area, the first redundant light emitting control signal output line E1 and the second redundant light emitting control signal output line E2 extend in the partial area 61 included in the flat redundant driving circuit area along the first direction, but the first redundant light emitting control signal output line E1 and the second redundant light emitting control signal output line E2 are not coupled to the pixel unit located in the display area; in at least one embodiment of the present invention, the first direction may be a horizontal direction, but is not limited thereto;

[0290] exist Figure 6G In the embodiment, S1 is multiplexed as an electrode pattern included in a second electrode of a second output transistor;

[0291] In at least one embodiment of the present invention, the first electrode is a source electrode or a drain electrode, and the second electrode can be a drain electrode or a source electrode.

[0292] like Figure 6H As shown, in Figure 6B On the basis of, C1a is the first plate of the first storage capacitor, C2a is the first plate of the second storage capacitor, G1 is the gate of the first output transistor, G2 is the gate of the second output transistor, G1 and C1a are coupled to each other, and G2 and C2a are coupled to each other;

[0293] like Fig.6I As shown, in Figure 6C Based on the above, the second plate of the first storage capacitor is labeled C1b, and the second plate of the second storage capacitor is labeled C2b. Figure 6A-Figure 6I As shown, the second plate C1b of the first storage capacitor is coupled to the first voltage signal line V1 through a via hole, and the second plate C2b of the second storage capacitor is coupled to the gate drive signal output line G0 through a via hole;

[0294] exist Figure 6A-Figure 6I In a corresponding embodiment, in the partial area 62 included in the driving circuit area, the light emitting control signal output line E0 transversely passes through the shift register unit included in the gate driving circuit to provide a light emitting control signal for the pixel unit in the display area.

[0295] Depend on Figure 6A-Figure 6I It can be seen that a redundant driving circuit is provided in the area other than the alignment mark area in the redundant driving circuit area, and an effective driving circuit is provided in the driving circuit area; a first output transistor and a second output transistor are also provided in the redundant driving circuit; Figure 6H As shown, the gate of the first output transistor in the redundant driving circuit in the partial area 61 included in the flat redundant driving circuit area is labeled G01, and the gate of the second output transistor in the redundant driving circuit in the partial area 61 included in the flat redundant driving circuit area is labeled G02;

[0296] The structure of the redundant drive circuit differs from that of the effective drive circuit as follows:

[0297] like Figure 6H As shown, C1a1 is the first plate of the first storage capacitor in the redundant driving circuit, and C2a1 is the first plate of the second storage capacitor in the redundant driving circuit; in the redundant driving circuit, C1a1 and C2a1 are coupled to each other, and C1a1 is not coupled to G01, and C2a1 is not coupled to G02; and the area of ​​C1a1 is smaller than that of C1a, and the area of ​​C2a1 is smaller than that of C2a;

[0298] like Fig.6I As shown, C1b1 is the first plate of the first storage capacitor in the redundant drive circuit, and C2b1 is the first plate of the second storage capacitor in the redundant drive circuit; in the redundant drive circuit, C1b1 and C2b1 are coupled to each other, and C2b1 is not coupled to the gate drive signal output line; and, the area of ​​C1b1 is smaller than that of C1b, and the area of ​​C2b1 is smaller than that of C2b.

[0299] like Fig.6D As shown, the orthographic projection of C1b on the substrate may overlap with the orthographic projection of C1b1 on the substrate, and the orthographic projection of C2b on the substrate may overlap with the orthographic projection of C2b1 on the substrate.

[0300] like Fig. 6A -like Fig.6I As shown, in the alignment mark area 70, the electrode layer in at least one output transistor in the redundant driving circuit and the active layer in the at least one output transistor are hollowed out, and in the alignment mark area 70, the redundant light emitting control signal output line is hollowed out.

[0301] Specifically, Fig. 6E As shown, in the alignment mark area 70, the electrode layer and the active layer in some devices in the two-stage redundant shift register unit included in the redundant driving circuit are hollowed out;

[0302] In the alignment mark area 70, in the first-stage redundant shift register unit included in the redundant driving circuit, the electrode layer in the first output transistor, the active layer in the first output transistor, the electrode layer in the second output transistor, and the active layer in the second output transistor are hollowed out;

[0303] In the alignment mark area 70, in the second-stage redundant shift register unit included in the redundant driving circuit, the electrode layer of the right half of the first output transistor, the active layer of the right half of the first output transistor, the electrode layer of the right half of the second output transistor, and the active layer of the right half of the second output transistor are hollowed out;

[0304] Furthermore, in the alignment mark region 70 , the redundant light emitting control signal output line provided between the first-stage redundant shift register unit included in the redundant driving circuit and the second-stage redundant shift register unit included in the redundant driving circuit is hollowed out.

[0305] like Fig. 6A As shown, in order to prevent problems with transistor characteristics caused by self-heating due to the active layer pattern being too large, the active layer pattern of the first output transistor is divided into two left and right parts, and the active layer pattern of the second output transistor is also divided into two left and right parts.

[0306] In a specific implementation, a redundant driving circuit and an effective driving circuit are simultaneously manufactured in a flat redundant driving circuit region and a driving circuit region;

[0307] First, in the driving circuit area, a semiconductor layer is fabricated on the substrate, and a patterning process is performed on the semiconductor layer to form an active layer of each transistor in the redundant driving circuit, and in the alignment mark area 70, the semiconductor layer is hollowed out to form an active layer of each transistor in the effective driving circuit;

[0308] Forming a first insulating layer on a side of the active layer facing away from the substrate;

[0309] Afterwards, in the driving circuit area, a first gate metal layer is formed on a side of the semiconductor layer facing away from the substrate, and the first gate metal layer is subjected to a patterning process to form the gates of each transistor in the redundant driving circuit and the first plates of each capacitor in the redundant driving circuit, and to form the gates of each transistor in the effective driving circuit and the first plates of each capacitor in the effective driving circuit, and the first gate metal layer is hollowed out in the alignment mark area 70;

[0310] Using the gates of the transistors as masks, doping the portion of the active layer not covered by the gates, so that the portion of the active layer not covered by the gates forms a conductive portion, and the portion of the active layer covered by the gates forms a channel portion; the conductive portion is used as an input electrode or an output electrode of the transistor; or the conductive portion is coupled to the input electrode or the output electrode of the transistor;

[0311] Disposing a second insulating layer on a side of the first gate metal layer facing away from the first gate metal layer;

[0312] A second gate metal layer is disposed on a side of the second insulating layer facing away from the first gate metal layer, and a patterning process is performed on the second gate metal layer to form a second plate of each capacitor in the redundant driving circuit and an output signal line in the redundant driving circuit, and to form a second plate of each capacitor in the effective driving circuit and an output signal line in the effective driving circuit, and the second gate metal layer is hollowed out in the alignment mark area 70;

[0313] Disposing a third insulating layer on a side of the second gate metal layer facing away from the second gate insulating layer;

[0314] A plurality of via holes are provided on a substrate provided with an active layer, a first insulating layer, a first gate metal layer, a second insulating layer, a second gate metal layer and a third insulating layer;

[0315] Disposing a source-drain metal layer on a side of the third insulating layer facing away from the second gate metal layer, performing a patterning process on the source-drain metal layer to form a signal line and a conductive connection portion, and hollowing out the source-drain metal layer in the alignment mark area 70;

[0316] Disposing a fourth insulating layer on a side of the source / drain metal layer facing away from the third insulating layer;

[0317] An anode layer is arranged on a side of the fourth insulating layer facing away from the source-drain metal layer, and the anode layer is not provided with an opening in the alignment mark area 70 so that the alignment camera can identify the alignment mark area 70; in the area included in the driving circuit area except the alignment mark area 70, the anode layer is provided with a plurality of openings 9g1.

[0318] In at least one embodiment of the present invention, the number of the source-drain metal layers may be two, and a first source-drain metal layer, a fifth insulating layer, a second source-drain metal layer, a sixth insulating layer and an anode layer may be sequentially arranged on a side of the third insulating layer facing away from the second gate metal layer; in the alignment mark area, the first source-drain metal layer and the second source-drain metal layer may both be hollowed out, and each insulating layer may not be hollowed out.

[0319] The method for manufacturing a display panel according to at least one embodiment of the present invention is used to manufacture a display panel, wherein the display panel comprises a display area and a peripheral area arranged on a substrate, wherein the peripheral area comprises an area between the display area and an edge of the display panel, and the peripheral area comprises a flat area and a curved area; the flat area comprises a flat redundant driving circuit area;

[0320] The manufacturing method of the display panel includes:

[0321] A plurality of pixel units are arranged in the display area, and a plurality of effective driving circuits and a plurality of redundant driving circuits are arranged in the peripheral area;

[0322] Disposing at least part of the redundant driving circuit in the flat redundant driving circuit area, the redundant driving circuit comprising at least one electrode layer disposed on the substrate;

[0323] Setting an alignment mark area in the flat redundant driving circuit area;

[0324] In the alignment mark area, at least one of the electrode layers is hollowed out, and / or at least one of the electrode layers is filled;

[0325] The minimum distance between the edges of the orthographic projections of two adjacent alignment mark areas on the substrate is an alignment mark distance, and at least one of the alignment mark distances is greater than a predetermined alignment mark distance.

[0326] In the method for manufacturing a display panel according to at least one embodiment of the present invention, an alignment mark area is provided in the flat redundant driving circuit area, and in the alignment mark area,

[0327] At least one of the electrode layers is hollowed out so that in the alignment mark area, the transmittance of the alignment mark area is higher than the transmittance of the surrounding area, so that the alignment mark can be accurately performed; and / or,

[0328] In the alignment mark area, at least one of the electrode layers is filled, and light reflection by the electrode layer can form a strong light-dark contrast with other areas, thereby achieving alignment mark.

[0329] In at least one embodiment of the present invention, the surrounding area may be an area included in the peripheral area and closer to the alignment mark area.

[0330] Optionally, the predetermined alignment mark distance may be 10 times the maximum pixel edge length;

[0331] The maximum pixel edge length is the maximum value among the pixel edge lengths of the plurality of pixel units;

[0332] The pixel edge length is the length of the edge of the orthographic projection of the pixel unit on the substrate.

[0333] Optionally, the area of ​​the orthographic projection of the alignment mark region on the substrate may be larger than the predetermined area;

[0334] The predetermined area is the maximum pixel area;

[0335] The maximum pixel area is a maximum value among a plurality of pixel areas, and the pixel area is an area of ​​a positive projection of the pixel unit on a substrate.

[0336] Optionally, the redundant driving circuit further includes at least one semiconductor layer disposed on the substrate; and the method for manufacturing the display panel further includes:

[0337] In the alignment mark region, the at least one semiconductor layer is hollowed out, or the at least one semiconductor layer is filled.

[0338] In a specific implementation, the redundant driving circuit may further include a semiconductor layer, and in the alignment mark area, the semiconductor layer is hollowed out or filled; in the alignment mark area, when the semiconductor layer is hollowed out, the transmittance of the alignment mark area is further improved to enable accurate alignment marking.

[0339] Optionally, in the alignment mark area, at least one of the electrode layers is filled, and the method for manufacturing the display panel further includes:

[0340] In the first region, the electrode layer is hollowed out;

[0341] The first area is an area surrounding the alignment mark area and included in the flat redundant driving circuit area.

[0342] In a specific implementation, there is a first area around the alignment mark area, in which at least one of the electrode layers is filled, and in the first area, the electrode layer is hollowed out, so as to improve the transmittance of the alignment mark area and form a strong light-dark contrast with other areas through the reflection of at least one of the electrode layers located in the alignment mark area, thereby achieving alignment marking.

[0343] In a specific implementation, in the plane area, the surface of the display panel is a plane.

[0344] Optionally, the display panel includes an upper surface, a lower surface, a first side surface, a second side surface, a third side surface and a fourth side surface;

[0345] The first side surface, the second side surface, the third side surface and the fourth side surface are all curved side surfaces;

[0346] The orthographic projection of the first side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane;

[0347] The orthographic projection of the second side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane;

[0348] The orthographic projection of the third side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane;

[0349] The orthographic projection of the fourth side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane;

[0350] The first plane is parallel to the lower surface.

[0351] In at least one embodiment of the present invention, the first side surface may be a left side surface, the second side surface may be a lower side surface, the third side surface may be an upper side surface, and the fourth side surface may be a right side surface; the display panel may further include a circuit board disposed on the lower surface, and the circuit board is disposed on the lower side of the display panel;

[0352] The longest distance between the orthographic projection of the alignment mark area on the first plane and the lower left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and the longest distance between the orthographic projection of the alignment mark area on the first plane and the lower right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

[0353] In a specific implementation, the predetermined distance may be selected according to actual conditions; for example, the predetermined distance may be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited thereto.

[0354] In at least one embodiment of the present invention, when the circuit board is disposed on the lower side of the display panel, the alignment mark area can be disposed at the lower left corner close to the boundary of the display area and / or the lower right corner close to the boundary of the display area.

[0355] In at least one embodiment of the present invention, the first side surface may be a left side surface, the second side surface may be a lower side surface, the third side surface may be an upper side surface, and the fourth side surface may be a right side surface; the display panel may further include a circuit board disposed on the lower surface, and the circuit board is disposed on the upper side of the display panel;

[0356] The longest distance between the orthographic projection of the alignment mark area on the first plane and the upper left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

[0357] In a specific implementation, the predetermined distance may be selected according to actual conditions; for example, the predetermined distance may be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited thereto.

[0358] In at least one embodiment of the present invention, when the circuit board is disposed on the upper side of the display panel, the alignment mark area can be disposed at the upper left corner close to the boundary of the display area and / or the upper right corner close to the boundary of the display area.

[0359] In at least one embodiment of the present invention, the first side surface may be a left side surface, the second side surface may be a lower side surface, the third side surface may be an upper side surface, and the fourth side surface may be a right side surface; the display panel further includes a circuit board disposed on the lower surface, and the circuit board is disposed on the lower side of the display panel;

[0360] The longest distance between the orthographic projection of the alignment mark area on the first plane and the upper left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

[0361] In a specific implementation, the predetermined distance may be selected according to actual conditions; for example, the predetermined distance may be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited thereto.

[0362] In at least one embodiment of the present invention, when the circuit board is disposed on the lower side of the display panel, the alignment mark area can be disposed at the upper left corner close to the boundary of the display area and / or the upper right corner close to the boundary of the display area.

[0363] In at least one embodiment of the present invention, the first side surface may be a left side surface, the second side surface may be a lower side surface, the third side surface may be an upper side surface, and the fourth side surface may be a right side surface; the display panel further includes a circuit board disposed on the lower surface, and the circuit board is disposed on the upper side of the display panel;

[0364] The longest distance between the orthographic projection of the alignment mark area on the first plane and the lower left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the lower right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

[0365] In a specific implementation, the predetermined distance may be selected according to actual conditions; for example, the predetermined distance may be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited thereto.

[0366] In at least one embodiment of the present invention, when the circuit board is disposed on the upper side of the display panel, the alignment mark area can be disposed at the lower left corner close to the boundary of the display area and / or the lower right corner close to the boundary of the display area.

[0367] According to a specific embodiment, the step of setting an alignment mark area in a plane area of ​​a peripheral area of ​​the display panel may include: in the flat redundant driving circuit area,

[0368] Arranging a semiconductor layer on a substrate, and performing a patterning process on the semiconductor layer to form an active pattern;

[0369] Disposing a gate metal layer on a side of the semiconductor layer away from the substrate, performing a patterning process on the gate metal layer to form a gate metal pattern, and making the gate metal layer hollow in the alignment mark area;

[0370] A source-drain metal layer is disposed on a side of the gate metal layer away from the semiconductor layer, and a patterning process is performed on the source-drain metal layer to form a source-drain metal pattern, and the source-drain metal layer is hollowed out in the alignment mark area.

[0371] According to another specific embodiment, the step of setting an alignment mark area in the plane area of ​​the peripheral area of ​​the display panel includes: in the flat redundant driving circuit area,

[0372] A semiconductor layer is provided on the substrate, and a patterning process is performed on the semiconductor layer to form an active pattern, and the semiconductor layer is hollowed out in the alignment mark area;

[0373] Disposing a gate metal layer on a side of the semiconductor layer away from the substrate, performing a patterning process on the gate metal layer to form a gate metal pattern, and making the gate metal layer hollow in the alignment mark area;

[0374] A source-drain metal layer is disposed on a side of the gate metal layer away from the semiconductor layer, and a patterning process is performed on the source-drain metal layer to form a source-drain metal pattern, and the source-drain metal layer is hollowed out in the alignment mark area.

[0375] In a specific implementation, the alignment mark area can be included in a flat redundant driving circuit area; in addition to the alignment mark area, the circuit wiring is densely distributed in the peripheral area close to the alignment mark area. Since the wiring is opaque to visible light, under certain backlight conditions, it will appear black in the field of view of the alignment camera. However, there is no wiring arrangement in the alignment mark area, and the backlight can almost completely pass through the alignment mark area to enter the alignment camera, forming a strong contrast with the surrounding area, so the alignment camera can identify the alignment mark area.

[0376] The display device described in at least one embodiment of the present invention may include the display panel described in the embodiment of the present invention.

[0377] In a specific implementation, the display panel may include an upper surface, a lower surface, a first side surface, a second side surface, a third side surface and a fourth side surface; the first side surface, the second side surface, the third side surface and the fourth side surface are all curved side surfaces; the orthographic projection of the first side surface on the first plane does not overlap with the orthographic projection of the plane area on the first plane; the orthographic projection of the second side surface on the first plane does not overlap with the orthographic projection of the plane area on the first plane; the orthographic projection of the third side surface on the first plane does not overlap with the orthographic projection of the plane area on the first plane; the orthographic projection of the fourth side surface on the first plane does not overlap with the orthographic projection of the plane area on the first plane; the first plane is parallel to the lower surface;

[0378] The first side surface is a left side surface, the second side surface is a lower side surface, the third side surface is an upper side surface, and the fourth side surface is a right side surface; the display panel further comprises a circuit board disposed on the lower surface; the circuit board is disposed on the lower side edge of the display panel or the upper side edge of the display panel;

[0379] The display device further includes a heat dissipation film, which is attached to the lower surface, the first side surface, the second side surface, the third side surface, and the fourth side surface to dissipate heat.

[0380] In a specific implementation, the alignment mark area can be used to align and bond the display panel and the heat dissipation film.

[0381] In at least one embodiment of the present invention, the display device may further include a packaging cover plate;

[0382] The package cover plate includes a first surface, and a fifth side surface, a sixth side surface, a seventh side surface and an eighth side surface respectively adjacent to the first surface;

[0383] The fifth side surface, the sixth side surface, the seventh side surface and the eighth side surface are all curved side surfaces;

[0384] The first surface is attached to the upper surface, the fifth side surface is attached to the first side surface, the sixth side surface is attached to the second side surface, the seventh side surface is attached to the third side surface, and the eighth side surface is attached to the fourth side surface.

[0385] In a specific implementation, the display panel and the packaging cover plate can be attached by utilizing the alignment mark area.

[0386] Optionally, the first surface may be a plane, the upper surface may be a surface of the display panel used for display, and the upper surface may be a plane;

[0387] Optionally, the packaging cover plate may be a glass cover plate, but is not limited thereto.

[0388] The display device provided in at least one embodiment of the present invention may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.

[0389] A method for manufacturing a display device according to at least one embodiment of the present invention is used to manufacture a display device, wherein the display device comprises a display panel, a heat dissipation film and a packaging cover plate, wherein the display panel comprises a display area and a peripheral area arranged on a substrate, wherein the peripheral area comprises an area between the display area and an edge of the display panel, and wherein the peripheral area comprises a flat area and a curved area; and the flat area comprises a flat redundant driving circuit area;

[0390] The manufacturing method of the display device may include:

[0391] A plurality of pixel units are arranged in the display area, and a plurality of effective driving circuits and a plurality of redundant driving circuits are arranged in the peripheral area;

[0392] Disposing at least part of the redundant driving circuit in the flat redundant driving circuit area, the redundant driving circuit comprising at least one electrode layer disposed on the substrate;

[0393] Setting an alignment mark area in the flat redundant driving circuit area;

[0394] In the alignment mark area, at least one of the electrode layers is hollowed out, and / or at least one of the electrode layers is filled;

[0395] Using the alignment mark area, the display panel and the packaging cover plate are aligned and bonded, and the display panel and the heat dissipation film are aligned and bonded;

[0396] The minimum distance between the edges of the orthographic projections of two adjacent alignment mark areas on the substrate is an alignment mark distance, and at least one of the alignment mark distances is greater than a predetermined alignment mark distance.

[0397] In at least one embodiment of the present invention, the alignment mark area is utilized to enable the display panel and the packaging cover plate to be accurately aligned and bonded, and to enable the display panel and the heat dissipation film to be accurately aligned and bonded.

[0398] Optionally, the predetermined alignment mark distance may be 10 times the maximum pixel edge length;

[0399] The maximum pixel edge length is the maximum value among the pixel edge lengths of the plurality of pixel units;

[0400] The pixel edge length is the length of the edge of the orthographic projection of the pixel unit on the substrate.

[0401] Optionally, the area of ​​the orthographic projection of the alignment mark region on the substrate may be larger than the predetermined area;

[0402] The predetermined area is the maximum pixel area;

[0403] The maximum pixel area is a maximum value among a plurality of pixel areas, and the pixel area is an area of ​​a positive projection of the pixel unit on a substrate.

[0404] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0405] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0406] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0407] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: The display panel comprises a display area and a peripheral area arranged on a substrate, wherein the display panel comprises a plurality of pixel units arranged in the display area, the peripheral area comprises an area between the display area and an edge of the display panel, the display panel further comprises a plurality of effective driving circuits and a plurality of redundant driving circuits, and the plurality of effective driving circuits and the plurality of redundant driving circuits are arranged in the peripheral area; wherein, At least one of the plurality of effective driving circuits is electrically connected to at least one of the plurality of pixel units to drive the pixel unit to display, and the redundant driving circuit includes at least one electrode layer disposed on a substrate; The peripheral area includes a plane area and a curved area, wherein at least part of the redundant driving circuit is located in a flat redundant driving circuit area included in the plane area; The flat redundant driving circuit area includes at least two alignment mark areas; In the alignment mark area, at least one of the electrode layers is hollowed out, and / or at least one of the electrode layers is filled; The minimum distance between the edges of the orthographic projections of two adjacent alignment mark areas on the substrate is an alignment mark distance, and at least one of the alignment mark distances is greater than a predetermined alignment mark distance.

2. The display panel according to claim 1, wherein: The predetermined alignment mark distance is 10 times the maximum pixel edge length; The maximum pixel edge length is the maximum value among the pixel edge lengths of the plurality of pixel units; The pixel edge length is the length of the edge of the orthographic projection of the pixel unit on the substrate.

3. The display panel according to claim 1, wherein: The orthographic projection area of ​​the alignment mark region on the substrate is larger than a predetermined area; The predetermined area is the maximum pixel area; The maximum pixel area is a maximum value among pixel areas of the plurality of pixel units, and the pixel area is an area of ​​a positive projection of the pixel unit on a substrate.

4. The display panel according to claim 1, wherein: In the alignment mark area, at least one of the electrode layers is filled; in the first area, the electrode layer is hollowed out; The first area is an area surrounding the alignment mark area and included in the flat redundant driving circuit area.

5. The display panel according to claim 1, wherein: The display panel includes an upper surface, a lower surface, a first side surface, a second side surface, a third side surface and a fourth side surface; The upper surface and the lower surface are both planes; The first side surface, the second side surface, the third side surface and the fourth side surface are all curved side surfaces; The orthographic projection of the first side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane; The orthographic projection of the second side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane; The orthographic projection of the third side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane; The orthographic projection of the fourth side surface on the first plane does not overlap with the orthographic projection of the planar area on the first plane; The first plane is parallel to the lower surface.

6. The display panel according to claim 5, wherein: The first side surface is a left side surface, the second side surface is a lower side surface, the third side surface is an upper side surface, and the fourth side surface is a right side surface; the display panel further includes a circuit board disposed on the lower surface, and the circuit board is disposed on the lower side of the display panel; The longest distance between the orthographic projection of the alignment mark area on the first plane and the lower left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the lower right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

7. The display panel according to claim 5, wherein: The first side surface is a left side surface, the second side surface is a lower side surface, the third side surface is an upper side surface, and the fourth side surface is a right side surface; the display panel further includes a circuit board disposed on the lower surface, and the circuit board is disposed on the upper side edge of the display panel; The longest distance between the orthographic projection of the alignment mark area on the first plane and the upper left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

8. The display panel according to claim 5, wherein: The first side surface is a left side surface, the second side surface is a lower side surface, the third side surface is an upper side surface, and the fourth side surface is a right side surface; the display panel further includes a circuit board disposed on the lower surface, and the circuit board is disposed on the lower side of the display panel; The longest distance between the orthographic projection of the alignment mark area on the first plane and the upper left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

9. The display panel according to claim 5, wherein: The first side surface is a left side surface, the second side surface is a lower side surface, the third side surface is an upper side surface, and the fourth side surface is a right side surface; the display panel further includes a circuit board disposed on the lower surface, and the circuit board is disposed on the upper side edge of the display panel; The longest distance between the orthographic projection of the alignment mark area on the first plane and the lower left rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than a predetermined distance, and / or the longest distance between the orthographic projection of the alignment mark area on the first plane and the lower right rounded corner of the orthographic projection of the display area boundary of the display panel on the first plane is less than the predetermined distance.

10. The display panel according to claim 1, wherein: The edge of the orthographic projection of the alignment mark area on the substrate is circular, polygonal, L-shaped or T-shaped.

11. The display panel according to any one of claims 1 to 10, characterized in that: The display panel comprises a semiconductor layer, a gate metal layer and a source-drain metal layer which are sequentially arranged on a substrate; In the alignment mark region, the gate metal layer and the source / drain metal layer are hollowed out.

12. The display panel according to claim 11, wherein: In the alignment mark region, the semiconductor layer is also hollowed out, or the semiconductor layer is filled.

13. The display panel according to claim 11, wherein: The display panel further comprises an anode layer disposed on a side of the source / drain metal layer away from the gate metal layer; In the alignment mark area, the anode layer is not provided with an opening and the anode layer is filled.

14. The display panel according to claim 11, wherein: The display panel further comprises an anode layer disposed on a side of the source / drain metal layer away from the gate metal layer; The anode layer is hollowed out in the alignment mark region.

15. The display panel according to claim 13, wherein: In the first region, the anode layer is hollowed out; The first area is an area surrounding the alignment mark area and included in the flat redundant driving circuit area.

16. The display panel according to claim 11, wherein: The display panel further comprises an anode layer disposed on a side of the source / drain metal layer away from the gate metal layer; In the alignment mark area, the anode layer includes an alignment mark pattern.

17. The display panel according to claim 16, wherein: The orthographic projection of the alignment mark pattern on the substrate is circular, L-shaped, T-shaped or polygonal.

18. The display panel according to claim 13, wherein: In the area of ​​the driving circuit area except the alignment mark area, the anode layer is provided with a plurality of openings arranged at intervals.

19. The display panel according to claim 11, wherein: The gate metal layer comprises a first gate metal layer and a second gate metal layer which are sequentially arranged on a side of the semiconductor layer away from the substrate; In the alignment mark region, both the first gate metal layer and the second gate metal layer are hollowed out.

20. The display panel according to claim 19, wherein: In the alignment mark area, the display panel further includes an anode layer disposed on a side of the source-drain metal layer away from the gate metal layer; the display panel further includes a first insulating layer disposed between the semiconductor layer and the first gate metal layer, a second insulating layer disposed between the first gate metal layer and the second gate metal layer, a third insulating layer disposed between the second gate metal layer and the source-drain metal layer, and a fourth insulating layer disposed between the source-drain metal layer and the anode layer; In the alignment mark area, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are not hollowed out.

21. The display panel according to any one of claims 1 to 10, characterized in that: The peripheral area includes a fan-out area, a driving circuit area and a signal line area which are arranged in sequence in a direction away from the display area; The flat redundant driving circuit area is included in the driving circuit region.

22. The display panel according to claim 21, wherein: The redundant driving circuit includes a multi-stage redundant shift register unit, and the redundant shift register unit is not coupled to the pixel unit.

23. The display panel according to claim 22, wherein: At least one level of the redundant shift register unit includes the bit alignment mark area, and the at least one level of the redundant shift register unit is different from other redundant shift register units.

24. The display panel according to claim 22, wherein: In the alignment mark region, at least one film layer of the output transistor in the redundant driving circuit is hollowed out.

25. The display panel according to claim 22, wherein: The redundant driving circuit includes a redundant gate driving circuit and a redundant light emitting control circuit; The redundant light emitting control circuit is arranged at a side of the redundant gate driving circuit away from the display area, and the redundant light emitting control circuit comprises a redundant light emitting control signal output line; In the alignment mark area, the redundant light emitting control signal output line is hollowed out.

26. The display panel according to claim 22, wherein: A first plate of a storage capacitor is disposed in an area included in the flat redundant driving circuit area except the alignment mark area; In a region included in the planar redundant driving circuit region except the alignment mark region, the second plate of the storage capacitor is not coupled to an output transistor included in the redundant driving circuit.

27. The display panel according to claim 21, wherein: The effective driving circuit includes a multi-stage shift register unit; The shift register unit is coupled to the corresponding row of pixel units and is used to provide a gate driving signal and / or a light emitting control signal to the corresponding row of pixel units.

28. A method for manufacturing a display panel, used for manufacturing a display panel, characterized in that: The display panel comprises a display area and a peripheral area arranged on a substrate, wherein the peripheral area comprises an area between the display area and an edge of the display panel, and the peripheral area comprises a flat surface area and a curved surface area; the flat surface area comprises a flat redundant driving circuit area; The manufacturing method of the display panel includes: A plurality of pixel units are arranged in the display area, and a plurality of effective driving circuits and a plurality of redundant driving circuits are arranged in the peripheral area; Disposing at least part of the redundant driving circuit in the flat redundant driving circuit area, the redundant driving circuit comprising at least one electrode layer disposed on the substrate; Setting an alignment mark area in the flat redundant driving circuit area; In the alignment mark area, at least one of the electrode layers is hollowed out, and / or at least one of the electrode layers is filled; The minimum distance between the edges of the orthographic projections of two adjacent alignment mark areas on the substrate is an alignment mark distance, and at least one of the alignment mark distances is greater than a predetermined alignment mark distance.

29. The method for manufacturing a display panel according to claim 28, wherein: The predetermined alignment mark distance is 10 times the maximum pixel edge length; The maximum pixel edge length is the maximum value among the pixel edge lengths of the plurality of pixel units; The pixel edge length is the length of the edge of the orthographic projection of the pixel unit on the substrate.

30. A display device, characterized in that: Comprising a display panel as claimed in any one of claims 1 to 27.

31. The display device according to claim 30, characterized in that The display panel comprises an upper surface, a lower surface, a first side surface, a second side surface, a third side surface and a fourth side surface; the first side surface, the second side surface, the third side surface and the fourth side surface are all curved side surfaces; the orthographic projection of the first side surface on the first plane does not overlap with the orthographic projection of the plane area on the first plane; the orthographic projection of the second side surface on the first plane does not overlap with the orthographic projection of the plane area on the first plane; The orthographic projection of the third side surface on the first plane does not overlap with the orthographic projection of the plane area on the first plane; the orthographic projection of the fourth side surface on the first plane does not overlap with the orthographic projection of the plane area on the first plane; the first plane is parallel to the lower surface; The first side surface is a left side surface, the second side surface is a lower side surface, the third side surface is an upper side surface, and the fourth side surface is a right side surface; the display panel further comprises a circuit board disposed on the lower surface; the circuit board is disposed on the lower side edge of the display panel or the upper side edge of the display panel; The display device further includes a heat dissipation film, and the heat dissipation film is attached to the lower surface, the first side surface, the second side surface, the third side surface, and the fourth side surface.

32. The display device according to claim 31, characterized in that Also included is a packaging cover plate; The package cover plate includes a first surface, and a fifth side surface, a sixth side surface, a seventh side surface and an eighth side surface respectively adjacent to the first surface; The fifth side surface, the sixth side surface, the seventh side surface and the eighth side surface are all curved side surfaces; The first surface is attached to the upper surface, the fifth side surface is attached to the first side surface, the sixth side surface is attached to the second side surface, the seventh side surface is attached to the third side surface, and the eighth side surface is attached to the fourth side surface.

33. A method for manufacturing a display device, used for manufacturing a display device, characterized in that: The display device comprises a display panel, a heat dissipation film and a packaging cover plate, wherein the display panel comprises a display area and a peripheral area arranged on a substrate, wherein the peripheral area comprises an area between the display area and an edge of the display panel, and the peripheral area comprises a flat surface area and a curved surface area; the flat surface area comprises a flat redundant driving circuit area; The manufacturing method of the display device comprises: A plurality of pixel units are arranged in the display area, and a plurality of effective driving circuits and a plurality of redundant driving circuits are arranged in the peripheral area; Disposing at least part of the redundant driving circuit in the flat redundant driving circuit area, the redundant driving circuit comprising at least one electrode layer disposed on the substrate; Setting an alignment mark area in the flat redundant driving circuit area; In the alignment mark area, at least one of the electrode layers is hollowed out, and / or at least one of the electrode layers is filled; Using the alignment mark area, the display panel and the packaging cover plate are aligned and bonded, and the display panel and the heat dissipation film are aligned and bonded; The minimum distance between the edges of the orthographic projections of two adjacent alignment mark areas on the substrate is an alignment mark distance, and at least one of the alignment mark distances is greater than a predetermined alignment mark distance.

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