A method, system, device, and medium for testing an FPGA

Abstract

The application discloses a kind of FPGA's test method, comprising the following steps: according to the size of the debugging information generated in the test process of the module to be verified in FPGA, send the request of applying large page memory;According to the address of the large page memory of the corresponding size in the request, write into the register corresponding to the module to be verified;According to the address of the large page memory in the register, the debugging information actually generated in the test process of the module to be verified is saved into the host connected with the FPGA.The application also discloses a kind of system, computer equipment and readable storage medium.The scheme presented in the application stores debugging information by using large page memory allocated by host, which can be directly operated when analyzing, improves the prototype verification efficiency and shortens the chip FPGA prototype verification period, and the storage capacity of large page memory can be flexibly adjusted according to needs, and the host side memory is generally plug-in memory, and maintenance is convenient.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of testing, in particular to a FPGA testing method, system, device and storage medium. BACKGROUND

[0002] As a kind of semi-custom circuit in the field of application-specific integrated circuit, FPGA not only can provide RTL verification function for chip hardware developer, but also can improve simulation speed, and can provide platform for software developer to develop embedded and related application software in advance.

[0003] As shown in Figure 1 Many traditional chip FPGA prototype verification methods with PCIe interface are basically as follows: according to the complexity of the chip to be verified and the debugging difficulty and other debugging requirements, the address range of the debugging memory is planned when designing the chip FPGA prototype verification architecture, a certain amount of DDR is integrated on the FPGA prototype verification environment, the debugging information is written into the debugging DDR planned in the FPGA prototype verification device according to the needs during the FPGA prototype verification process, when the debugging data needs to be analyzed, the FPGA prototype verification personnel imports the debugging information from the debugging DDR of the FPGA verification device to the host through PCIe interface, and then analyzes the exported debugging information, so as to achieve the purpose of chip FPGA prototype verification.

[0004] From the above, integrating DDR into the chip FPGA prototype verification environment for prototype verification can quickly record debugging information, but has the following shortcomings:

[0005] (1) Due to the consideration of FPGA prototype verification device area, power consumption, cost and other factors, the capacity of DDR used for debugging is usually limited.

[0006] (2) The debugging DDR inside the FPGA prototype verification device is usually directly mounted, and once damaged, it is more troublesome to replace, and it is not convenient to dynamically increase the capacity.

[0007] (3) When the debugging personnel analyzes, the debugging information needs to be imported from the debugging DDR of the FPGA prototype verification device to the host through PCIe interface first, and then the analysis can be carried out, which reduces the debugging efficiency and prolongs the chip FPGA prototype verification period. SUMMARY

[0008] Therefore, in order to overcome at least one aspect of the above problems, the embodiment of the present application provides a FPGA testing method, which comprises the following steps:

[0009] According to the size of the debugging information expected to be generated by the to-be-verified module in the FPGA during the testing process, a request for large page memory is sent;

[0010] write, according to the request, an address of a corresponding size of the huge page memory into a register corresponding to the to-be-verified module;

[0011] save, according to the address of the huge page memory in the register, debugging information actually generated by the to-be-verified module in a test process into a host connected with the FPGA.

[0012] In some embodiments, further comprising:

[0013] start Hugetlbfs of the host;

[0014] obtain configuration parameters including a size and a number of the huge page memory;

[0015] generate a configuration command according to the configuration parameters, so as to generate a corresponding number and a corresponding size of the huge page memory on the host by using the configuration command.

[0016] In some embodiments, further comprising:

[0017] send the address of each of the generated huge page memories to a control module of the FPGA, so as to allocate, by the control module, the address of each of the huge page memories to a corresponding to-be-verified module.

[0018] In some embodiments, further comprising:

[0019] in response to the host receiving a request for querying the debugging information, obtain and return the debugging information saved by the to-be-verified module from the huge page memory.

[0020] Based on the same inventive concept, according to another aspect of the present application, embodiments of the present application further provide a test system of an FPGA, comprising:

[0021] a request module configured to send a request for applying for a huge page memory according to a size of debugging information expected to be generated by a to-be-verified module in the FPGA in a test process;

[0022] a write module configured to write, according to the request, an address of a corresponding size of the huge page memory into a register corresponding to the to-be-verified module;

[0023] a save module configured to save, according to the address of the huge page memory in the register, debugging information actually generated by the to-be-verified module in a test process into a host connected with the FPGA.

[0024] In some embodiments, further comprising a configuration module configured to:

[0025] start Hugetlbfs of the host;

[0026] Obtaining configuration parameters including a large page memory size and a number;

[0027] Generating a configuration command according to the configuration parameters, to generate a corresponding number and a corresponding size of large page memories on the host by using the configuration command.

[0028] In some embodiments, the configuration module is further configured to:

[0029] Send an address of each of the generated large page memories to a control module of the FPGA, to allocate the address of each of the large page memories to a corresponding to-be-verified module by the control module.

[0030] In some embodiments, further comprising a query module configured to:

[0031] In response to a request of the host to receive query debugging information, obtain and return the debugging information saved by the to-be-verified module from the large page memory.

[0032] Based on the same inventive concept, according to another aspect of the present application, embodiments of the present application further provide a computer device, comprising:

[0033] at least one processor; and

[0034] a memory, the memory storing a computer program capable of running on the processor, characterized in that the processor executes the program to execute the steps of any of the test methods of the FPGA as described above.

[0035] Based on the same inventive concept, according to another aspect of the present application, embodiments of the present application further provide a computer readable storage medium, the computer readable storage medium storing a computer program, the computer program being executed by a processor to execute the steps of any of the test methods of the FPGA as described above.

[0036] The present application has one of the following beneficial technical effects: the scheme provided by the present application stores debugging information by using large page memories allocated by a host, which can be directly operated when analyzed, improving the prototype verification efficiency and shortening the chip FPGA prototype verification period, while the storage capacity of the large page memory can be flexibly adjusted according to needs, and the host side memory is generally a plug-in memory stick, which is convenient to maintain. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other embodiments can be obtained from these drawings without creative labor.

[0038] Figure 1 a structural schematic diagram of a test system of an FPGA in the prior art;

[0039] Figure 2 a flowchart of a test method of an FPGA provided by an embodiment of the present application;

[0040] Figure 3 a flowchart of a test method of an FPGA provided by an embodiment of the present application;

[0041] Figure 4 a schematic diagram of memory page information before and after Hugepage configuration;

[0042] Figure 5 a structural schematic diagram of a test system of an FPGA provided by an embodiment of the present application;

[0043] Figure 6 a structural schematic diagram of a computer device provided by an embodiment of the present application;

[0044] Figure 7 a structural schematic diagram of a computer readable storage medium provided by an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the objects, technical solutions and advantages of the present application clearer, the embodiments of the present application are further described in detail below with reference to the drawings.

[0046] It should be noted that all the expressions of "first" and "second" in the embodiments of the present application are used to distinguish two same-named different entities or different parameters, and it can be seen that "first" and "second" are only used for the convenience of description, and should not be understood as a limitation of the embodiments of the present application. The subsequent embodiments will not be described one by one.

[0047] In the embodiments of the present application, HugePage represents a large page memory, and using the large page memory can reduce the number of page table entries, thereby reducing the probability of TLB Miss and improving the system memory access performance.

[0048] Hugetlbfs represents a special file system provided by Linux to users for HugePage service. The file system enables users to select the size of the virtual memory page as needed.

[0049] According to one aspect of the present application, an embodiment of the present application provides a test method of an FPGA, as shown in Figure 2 which can include the following steps:

[0050] S1, based on the expected size of the debug information generated by the module to be verified in the FPGA during the testing process, sends a request to request large page memory;

[0051] S2, according to the request, write the address of the large page memory of the corresponding size into the register corresponding to the module to be verified;

[0052] S3, save the debugging information actually generated by the module to be verified during the test to the host connected to the FPGA according to the address of the large page memory in the register.

[0053] To address the aforementioned shortcomings of traditional FPGA prototyping methods with PCIe interfaces, this invention proposes a PCIe interface FPGA prototyping method based on large page memory. Typically, host-side memory is very large, and its replacement or dynamic addition is very convenient and quick. Based on these principles, such as... Figure 3 As shown, this solution proposes to replace the DDR integrated inside the FPGA prototyping device with host-side memory. In this way, the FPGA verification device no longer needs to consider DDR memory for debugging, thus not increasing the area or power consumption of the FPGA prototyping device. In addition, since host-side memory is used, FPGA prototyping personnel can directly read debugging information without importing debugging information from the DDR on the FPGA prototyping device side, which significantly improves debugging efficiency and shortens the chip FPGA prototyping cycle.

[0054] Linux provides the HugePage large page memory management mechanism, introduced to improve the memory access performance of the Linux system. Currently, mainstream processor platforms such as x86 and ARM can provide 1GB of physically contiguous large page memory, meaning a single page can reach 1GB in size. Users can pre-allocate this memory to ensure a stable supply of contiguous physical memory to meet debugging needs. This solution leverages these features, mapping the HugePage large page memory allocated on the host side to the chip side, allowing the chip to directly access the 1GB of large page memory on the host side.

[0055] By utilizing the large page memory features of the processor and Linux system and replacing the integrated DDR memory within the FPGA prototyping device with host-side memory, the shortcomings of traditional PCIe interface chip FPGA prototyping methods can be perfectly solved.

[0056] In some embodiments, it also includes:

[0057] Enable Hugetlbfs on the host;

[0058] Retrieve configuration parameters including the size and number of large page memory;

[0059] generate a configuration command according to the configuration parameter, to generate a corresponding number and a corresponding size of large page memories on the host by using the configuration command.

[0060] Specifically, first, a proper number of HugePages can be configured and applied according to requirements before the system of the host is started. The configuration of the proper number of HugePages includes: first, hugetlbfs needs to be activated (CONFIG_HUGETLB_PAGE and CONFIG_HUGETLBFS options are configured when compiling the kernel makemenuconfig) and mounted; second, a certain amount of memory needs to be reserved as large page memory for use in the command line, for example: using the command default_hugepagesz=1G hugepagesize=1G hugepages=8 can achieve pre-allocation of 8GB of memory as large page memory, and the size of the large page is 1GB. After the above configuration, the memory pages of the Host CPU will change as shown in the following table. Figure 4

[0061] In some embodiments, further comprising:

[0062] The address of each of the generated large page memories is sent to the control module of the FPGA, so as to allocate the address of each of the large page memories to the corresponding to-be-verified module through the control module.

[0063] Specifically, the Host initializes the verification device, and maps the HugePage allocated in advance to the FPGA, that is, the address of the large page memory is sent to the control module of the FPGA. In this way, when the to-be-tested module is tested, the control module can be applied for a corresponding memory size according to the expected memory size. The chip prototype verification starts, and in the process, the to-be-tested module writes the debugging information directly into the HugePage memory of the Host mapped to the chip according to needs.

[0064] In some embodiments, further comprising:

[0065] In response to the request of the host to query the debugging information, the debugging information saved by the to-be-verified module is obtained from the large page memory and returned

[0066] Specifically, when the debugging information needs to be read, the debugging information in the HugePage memory of the Host can be directly read, and then the verification personnel analyzes the read debugging information to locate and solve the problem.

[0067] ​In some embodiments, the HugePage on the Host side can be used for temporary access of certain large data in the to-be-verified module in addition to saving the chip debugging information, that is, the HugePage on the Host side is used as a temporary cache of data in the to-be-verified module. Due to context environment switching, certain data in the to-be-verified module needs to be temporarily saved for subsequent processing, and at this time, the data can be temporarily saved in the HugePage on the Host side, at which time the to-be-verified module can continue to perform other operations, and wait for an appropriate time to read the previously saved data from the HugePage on the Host side to continue the operation that has not been completed.

[0068] The scheme provided by the application stores the debugging information in the HugePage memory allocated by the host, and the debugging information can be directly operated when being analyzed, thereby improving the prototype verification efficiency and shortening the FPGA prototype verification period of the chip, the storage capacity of the HugePage memory can be flexibly adjusted according to needs, and the memory on the host side is generally a plug-in memory, which is convenient to maintain.

[0069] Based on the same inventive concept, according to another aspect of the application, embodiments of the application also provide a test system 400 of an FPGA, as shown in Figure 5 The test system 400 comprises:

[0070] a request module 401 configured to send a request for allocating a HugePage memory according to a size of debugging information expected to be generated by a to-be-verified module in the FPGA during a test process;

[0071] a write module 402 configured to write an address of a HugePage memory of a corresponding size into a register corresponding to the to-be-verified module according to the request;

[0072] a save module 403 configured to save debugging information actually generated by the to-be-verified module during the test process into a host connected to the FPGA according to the address of the HugePage memory in the register.

[0073] In some embodiments, the test system 400 further comprises a configuration module configured to:

[0074] start Hugetlbfs of the host;

[0075] obtain configuration parameters comprising a size and a number of HugePage memories;

[0076] generate a configuration command according to the configuration parameters, so as to generate a corresponding number and a corresponding size of HugePage memories on the host by using the configuration command.

[0077] In some embodiments, the configuration module is further configured to:

[0078] Send the address of each of the generated large page memory to the control module of the FPGA, so as to allocate the address of each of the large page memory to the corresponding to-be-verified module through the control module.

[0079] In some embodiments, further comprising a query module configured to:

[0080] In response to the host receiving a request for querying the debugging information, acquire and return the debugging information saved by the to-be-verified module from the large page memory.

[0081] The scheme provided by the application stores the debugging information in the large page memory allocated by the host, and the debugging information can be directly operated when being analyzed, thereby improving the prototype verification efficiency and shortening the chip FPGA prototype verification period, the storage capacity of the large page memory can be flexibly adjusted according to the requirement, and the memory on the host side is generally a plug-in memory bar, which is convenient to maintain.

[0082] Based on the same inventive concept, according to another aspect of the application, as shown in the accompanying drawings, the embodiments of the application further provide a computer device 501, which comprises: Figure 6

[0083] at least one processor 520; and

[0084] a memory 510, the memory 510 storing a computer program 511 capable of running on the processor, and the processor 520 executes the following steps when executing the program:

[0085] According to the size of the debugging information expected to be generated by the to-be-verified module in the FPGA in the test process, send a request for applying for a large page memory;

[0086] According to the request, write the address of the large page memory of the corresponding size into the register corresponding to the to-be-verified module;

[0087] According to the address of the large page memory in the register, save the debugging information actually generated by the to-be-verified module in the test process into the host connected with the FPGA.

[0088] In some embodiments, further comprising:

[0089] Start the Hugetlbfs of the host;

[0090] Acquire configuration parameters including the size and quantity of the large page memory;

[0091] According to the configuration parameters, generate a configuration command, so as to generate the large page memory of the corresponding quantity and the corresponding size on the host by using the configuration command.

[0092] In some embodiments, further comprising:

[0093] ​send the address of each of the generated huge page memories to a control module of the FPGA, so as to allocate the address of each of the huge page memories to the corresponding to-be-verified module through the control module.

[0094] In some embodiments, the method further comprises:

[0095] In response to the host receiving a request to query the debugging information, the debugging information saved by the to-be-verified module is obtained from the huge page memory and returned.

[0096] The scheme provided by the application stores the debugging information in the huge page memory allocated by the host, and the debugging information can be directly operated when being analyzed, thereby improving the prototype verification efficiency and shortening the FPGA prototype verification period of the chip, the storage capacity of the huge page memory can be flexibly adjusted according to the requirement, and the memory on the host side is generally a plug-in memory bar, which is convenient to maintain.

[0097] Based on the same inventive concept, according to another aspect of the application, as Figure 7 The embodiment of the application also provides a computer readable storage medium 601, which stores computer program instructions 610, and the computer program instructions 610 are executed by a processor to perform the following steps:

[0098] According to the size of the debugging information expected to be generated by the to-be-verified module in the FPGA during the test process, a request for applying for a huge page memory is sent;

[0099] According to the request, the address of the huge page memory of a corresponding size is written into a register corresponding to the to-be-verified module;

[0100] According to the address of the huge page memory in the register, the debugging information actually generated by the to-be-verified module during the test process is saved into a host connected to the FPGA.

[0101] In some embodiments, the method further comprises:

[0102] Starting Hugetlbfs of the host;

[0103] Obtaining configuration parameters including the size and the number of the huge page memories;

[0104] Generating a configuration command according to the configuration parameters, so as to generate the corresponding number and the corresponding size of the huge page memories on the host by using the configuration command.

[0105] In some embodiments, the method further comprises:

[0106] send the address of each of the generated huge page memories to a control module of the FPGA, so as to allocate the address of each of the huge page memories to the corresponding to-be-verified module through the control module.

[0107] In some embodiments, further comprising:

[0108] In response to the host receiving the request to query the debugging information, obtaining and returning the debugging information saved by the to-be-verified module from the large page memory.

[0109] The scheme provided by the application stores the debugging information in the large page memory allocated by the host, which can be directly operated when analyzing, thereby improving the prototype verification efficiency and shortening the FPGA prototype verification period of the chip, the storage capacity of the large page memory can be flexibly adjusted according to the requirement, and the memory on the host side is generally a plug-in memory bar, which is convenient to maintain.

[0110] Finally, it should be noted that those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by a computer program to instruct related hardware to complete, and the program can be stored in a computer readable storage medium, and when the program is executed, the processes of the above-mentioned embodiments can be included.

[0111] In addition, it should be understood that the computer readable storage medium (for example, the memory) herein can be a volatile memory or a non-volatile memory, or can include both volatile memory and non-volatile memory.

[0112] Those skilled in the art will also appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

[0113] The above is the exemplary embodiment disclosed by the application, but it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the application defined by the claims. The functions, steps and / or acts of the method claims described herein need not be performed in any particular order. Furthermore, although the elements of the embodiments disclosed by the application can be described in individual form or claimed as such, they can also be understood to be plural unless explicitly limited to a single instance.

[0114] It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0115] The above-mentioned embodiment serial number of the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0116] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or can be instructed by programs to complete relevant hardware, and the programs can be stored in a computer readable storage medium, such as read-only memory, magnetic disk or optical disk.

[0117] Those skilled in the art should understand that the above discussion of any embodiment is only exemplary, and is not intended to imply that the scope of the embodiments of the present application (including claims) is limited to these examples; under the idea of the embodiments of the present application, the above embodiments or technical features in different embodiments can also be combined, and there are many other changes of different aspects of the embodiments of the present application as above. In order to be brief, they are not provided in details. Therefore, any omission, modification, equivalent replacement, improvement, etc. made in the spirit and principle of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A testing method for an FPGA, characterized in that, Includes the following steps: A request for large page memory is sent based on the expected size of the debug information generated during testing by the module to be verified in the FPGA; Write the address of the corresponding large page memory into the register corresponding to the module to be verified according to the request; The debugging information actually generated by the module to be verified during the test is saved to the host connected to the FPGA based on the address of the large page memory in the register. In response to the host receiving a request to query debugging information, the debugging information stored by the module to be verified is retrieved from the large page memory and returned. The method also includes: Enable Hugetlbfs on the host; Retrieve configuration parameters including the size and number of large page memory; Based on the configuration parameters, a configuration command is generated to generate a corresponding number and size of large page memory on the host.

2. The method as described in claim 1, characterized in that, Also includes: The address of each of the generated large page memories is sent to the control module of the FPGA, so that the control module can assign the address of each of the large page memories to the corresponding module to be verified.

3. A test system for an FPGA, characterized in that, include: The request module is configured to send a request for large page memory based on the size of the debug information expected to be generated during testing by the module to be verified in the FPGA; The write module is configured to write the address of a large page of memory of the corresponding size into the register corresponding to the module to be verified, according to the request. The storage module is configured to save the debugging information actually generated by the module to be verified during the test to the host connected to the FPGA based on the address of the large page memory in the register. The query module is configured as follows: In response to the host receiving a request to query debugging information, the debugging information stored by the module to be verified is retrieved from the large page memory and returned. It also includes a configuration module, configured as follows: Enable Hugetlbfs on the host; Retrieve configuration parameters including the size and number of large page memory; Based on the configuration parameters, a configuration command is generated to generate a corresponding number and size of large page memory on the host.

4. The system as described in claim 3, characterized in that, The configuration module is also configured as follows: The address of each of the generated large page memories is sent to the control module of the FPGA, so that the control module can assign the address of each of the large page memories to the corresponding module to be verified.

5. A computer device, comprising: At least one processor; as well as A memory storing a computer program executable on the processor, characterized in that the processor executes the program by performing the steps of the method as described in any one of claims 1-2.

6. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it performs the steps of the method as described in any one of claims 1-2.

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