Simulation verification method, device and computing equipment

Abstract

The embodiment of the present application provides a simulation verification method, apparatus and computing device. Among them, the method includes: determining the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script; obtaining multiple target verification modules related to the algorithm to be verified from the verification platform; generating a file to be verified based on the multiple target verification modules and the top-level simulation file; sending the file to be verified to the hardware accelerator so that the hardware accelerator can use the multiple target verification modules to simulate and verify the algorithm to be verified. By sending the algorithm to be verified and multiple target verification modules to the hardware accelerator together, the embodiment of the present application can use multiple target verification modules on the hardware accelerator to verify the target algorithm module, thereby improving the efficiency of verification.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to a simulation verification method, apparatus, and computing device. Background Art

[0002] As the number of gates in large-scale integrated circuits increases, the simulation and verification time of system-on-chip (SOC) is getting slower and slower. In order to solve this problem, hardware accelerators are usually used to simulate and verify the system-on-chip to increase the simulation and verification speed.

[0003] When the simulation verification script calls the hardware accelerator to verify the algorithm of the system-level chip, the top-level simulation file containing the algorithm is sent to the hardware accelerator. The hardware accelerator needs to use the verification modules of the verification platform, such as the reset module and the clock module, to verify the algorithm in the top-level simulation file. Therefore, during the verification process, the hardware accelerator needs to interact with the verification platform multiple times, resulting in low verification efficiency. Summary of the Invention

[0004] The embodiments of the present application provide a simulation verification method, apparatus, and computing device to solve the problem in the prior art that a hardware accelerator needs to interact with a verification platform multiple times, resulting in low verification efficiency.

[0005] In a first aspect, an embodiment of the present application provides a simulation verification method, which is applied to a simulation verification script, and the method includes:

[0006] Determine the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script;

[0007] Acquire multiple target verification modules related to the algorithm to be verified from the verification platform;

[0008] Generate a file to be verified based on the multiple target verification modules and the top-level simulation file;

[0009] The file to be verified is sent to the hardware accelerator, so that the hardware accelerator uses the multiple target verification modules to perform simulation verification on the algorithm to be verified.

[0010] In a second aspect, an embodiment of the present application provides a simulation verification method applied to a hardware accelerator, the method comprising:

[0011] Receiving a file to be verified including a plurality of target verification modules and the top-level simulation file, wherein the top-level simulation file includes an algorithm to be verified;

[0012] Verifying the algorithm to be verified using the multiple target verification modules;

[0013] Returns the corresponding verification result.

[0014] In a third aspect, an embodiment of the present application provides a simulation verification device, which is applied to a simulation verification script, including:

[0015] A determination module is used to determine the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script;

[0016] An acquisition module, used for acquiring multiple target verification modules related to the algorithm to be verified from the verification platform;

[0017] A generating module, configured to generate a file to be verified based on the multiple target verification modules and the top-level simulation file;

[0018] The sending module is used to send the file to be verified to the hardware accelerator, so that the hardware accelerator can use the multiple target verification modules to simulate and verify the algorithm to be verified.

[0019] In a fourth aspect, an embodiment of the present application provides a simulation verification device, which is applied to a hardware accelerator, including:

[0020] A receiving module, configured to receive a file to be verified comprising a plurality of target verification modules and the top-level simulation file, wherein the top-level simulation file includes an algorithm to be verified;

[0021] A verification module, configured to verify the algorithm to be verified using the multiple target verification modules;

[0022] Return module, used to return the corresponding verification results.

[0023] In a fifth aspect, an embodiment of the present application provides a computing device, comprising a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component; the processing component is used to:

[0024] Determine the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script;

[0025] Acquire multiple target verification modules related to the algorithm to be verified from the verification platform;

[0026] Generate a file to be verified based on the multiple target verification modules and the top-level simulation file;

[0027] The file to be verified is sent to the hardware accelerator, so that the hardware accelerator uses the multiple target verification modules to perform simulation verification on the algorithm to be verified.

[0028] In a sixth aspect, an embodiment of the present application provides a computing device, comprising a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component;

[0029] The processing component is used to:

[0030] Receiving a file to be verified including a plurality of target verification modules and the top-level simulation file, wherein the top-level simulation file includes an algorithm to be verified;

[0031] Verifying the algorithm to be verified using the multiple target verification modules;

[0032] Returns the corresponding verification result.

[0033] In the seventh aspect, an embodiment of the present application provides a non-temporary machine-readable storage medium, on which executable code is stored. When the executable code is executed by a processor of an electronic device, the processor can at least implement the simulation verification method described in the first aspect.

[0034] In an eighth aspect, an embodiment of the present application provides a non-temporary machine-readable storage medium on which executable code is stored. When the executable code is executed by a processor of an electronic device, the processor can at least implement the simulation verification method described in the second aspect.

[0035] The embodiment of the present application provides a simulation verification method, apparatus and computing device. The method includes: determining the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script; obtaining multiple target verification modules related to the algorithm to be verified from the verification platform; generating a file to be verified based on the multiple target verification modules and the top-level simulation file; sending the file to be verified to the hardware accelerator so that the hardware accelerator can use the multiple target verification modules to simulate and verify the algorithm to be verified. By sending the algorithm to be verified and multiple target verification modules to the hardware accelerator together, the embodiment of the present application can use multiple target verification modules on the hardware accelerator to verify the target algorithm module, thereby improving the efficiency of verification.

[0036] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 A schematic diagram showing a flow chart of an embodiment of the simulation verification method provided by the present application is shown;

[0039] Figure 2 A schematic diagram showing a flow chart of another embodiment of the simulation verification method provided by the present application is shown;

[0040] Figure 3 A schematic diagram showing a flow chart of another embodiment of the simulation verification method provided by the present application is shown;

[0041] Figure 4 A schematic structural diagram of an embodiment of a simulation verification device provided by the present application is shown;

[0042] Figure 5 A schematic structural diagram of another embodiment of the simulation verification device provided by the present application is shown;

[0043] Figure 6 Shown with Figure 4 A schematic diagram of the structure of a computing device corresponding to the simulation verification device shown;

[0044] Figure 7 Shown with Figure 5 The schematic diagram of the structure of the computing device corresponding to the simulation verification device shown is shown. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0046] In some of the processes described in the specification and claims of this application and the above-mentioned figures, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this document or may be executed in parallel. The serial numbers of the operations, such as 101, 102, etc., are only used to distinguish between different operations, and the serial numbers themselves do not represent any order of execution. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this document are used to distinguish different messages, devices, modules, etc., and do not represent a sequential order, nor do they limit "first" and "second" to being different types.

[0047] As described in the background art, as the number of gates in large-scale integrated circuits increases, the simulation and verification time of SOC chips becomes slower and slower. To solve this problem, hardware accelerators are usually used to simulate and verify the system-on-chip to increase the simulation and verification speed.

[0048] Currently, the general process of using hardware accelerators to simulate and verify chip algorithms is as follows: the simulation verification script calls the hardware accelerator to verify the algorithm of the system-level chip, and sends the top-level simulation file containing the algorithm to the hardware accelerator. The hardware accelerator needs to use the verification modules of the verification platform, such as the reset module, clock module, etc., to verify the algorithm in the top-level simulation file.

[0049] Since the verification of the verification platform does not exist on the hardware accelerator, the hardware accelerator needs to interact with the verification platform where the verification module is located multiple times during the verification process, resulting in low verification efficiency.

[0050] In order to solve the above technical problems, the embodiments of the present application provide a simulation verification method, device and computing equipment. The method includes: determining the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script; obtaining multiple target verification modules related to the algorithm to be verified from the verification platform; generating a file to be verified based on the multiple target verification modules and the top-level simulation file; sending the file to be verified to the hardware accelerator so that the hardware accelerator can use the multiple target verification modules to simulate and verify the algorithm to be verified. By sending the algorithm to be verified and multiple target verification modules to the hardware accelerator together, the embodiment of the present application can use multiple target verification modules on the hardware accelerator to verify the target algorithm module, thereby improving the efficiency of verification.

[0051] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0052] Figure 1 The flowchart of an embodiment of the simulation verification method provided by the present application is shown, wherein the execution subject of the embodiment of the present application can be a simulation verification script, or a simulation verification system that can call the simulation verification script. Figure 1 As shown, the method includes:

[0053] 101. Determine the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script.

[0054] Among them, the algorithm to be verified can be the algorithm corresponding to a system in the chip to be verified, for example, it can be the algorithm corresponding to the image signal processing (Image Signal Processing, referred to as ISP) system, or it can be the algorithm corresponding to the neural network processor (Neural-network Processing Unit, referred to as NPU) system, etc.

[0055] The process of determining the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script can be implemented as follows: receiving the algorithm input by the user in the simulation verification script, and determining the algorithm as the algorithm to be verified.

[0056] 102. Acquire multiple target verification modules related to the algorithm to be verified from the verification platform.

[0057] Optionally, the verification platform may be a verification platform corresponding to a hardware accelerator, and the multiple target verification modules may be a reset module, a clock module, a master device verification component, a slave device verification component, and the like.

[0058] The process of obtaining multiple target verification modules related to the algorithm to be verified can be implemented as follows: calling the multiple target verification modules in the simulation verification script through the calling interfaces corresponding to the multiple target verification modules.

[0059] The process of obtaining multiple target verification modules related to the algorithm to be verified may also be implemented as: determining multiple verification modules input by the user as multiple target verification modules.

[0060] 103. Generate a file to be verified based on multiple target verification modules and a top-level simulation file.

[0061] Optionally, generating the file to be verified based on the multiple target verification modules and the top-level simulation file includes: adding an outer layer outside the top-level simulation file; and adding the multiple target verification modules in the outer layer to generate the file to be verified.

[0062] 104. Send the file to be verified to the hardware accelerator, so that the hardware accelerator can use multiple target verification modules to simulate and verify the algorithm to be verified.

[0063] The execution steps of the verification process for the file to be verified can be: instantiating the master device verification component and the slave device verification component required by the verification platform. Since the algorithm to be verified includes multiple algorithms, the algorithm to be verified in this simulation verification can be determined by the master device verification component and the slave device verification component. The address of the memory can also be determined by the master device verification component and the slave device verification component, so that the corresponding data can be obtained from the memory during the verification algorithm. Furthermore, the clock module and the reset module are defined and assigned, that is, the clock frequency of the simulation verification operation and the reset frequency and time are determined; the bus signal is cut off, that is, other signals are prohibited from being transmitted to the file to be verified, so as to ensure the accuracy of the simulation of the algorithm to be verified; the user interface function is encapsulated, that is, the algorithm to be verified can be changed through the user interface function.

[0064] An embodiment of the present application provides a simulation verification method. The method includes: determining the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script; obtaining multiple target verification modules related to the algorithm to be verified from the verification platform; generating a file to be verified based on the multiple target verification modules and the top-level simulation file; sending the file to be verified to the hardware accelerator so that the hardware accelerator can use the multiple target verification modules to simulate and verify the algorithm to be verified. By sending the algorithm to be verified and multiple target verification modules to the hardware accelerator together, the embodiment of the present application can use multiple target verification modules on the hardware accelerator to verify the target algorithm module, thereby improving the efficiency of verification.

[0065] Furthermore, since the hardware accelerator takes about 8 hours to compile once, which is relatively slow, once problems occur in multiple target verification modules, the error correction process is relatively complicated and wastes a lot of time. Therefore, before simulating and verifying the verification module through the hardware accelerator, multiple target verification modules need to be verified.

[0066] Figure 2 A flow chart of another embodiment of the simulation verification method provided by the present application is shown, and the method includes:

[0067] 201. Determine a verification mode according to simulation options pre-configured in the simulation verification script.

[0068] 202. If the verification mode is the common simulator mode, multiple verification modules and test algorithms are sent to the common simulator so that the common simulator verifies the functions of the multiple verification modules.

[0069] Among them, the multiple verification modules are multiple verification modules included in the verification platform corresponding to the hardware accelerator

[0070] Before sending the file to be verified to the hardware accelerator and verifying the algorithm to be verified in the file to be verified, the simulation verification script needs to verify the connectivity of multiple verification modules. Since the compilation time of an ordinary simulator is relatively short, the simulation verification script determines the verification mode to be the ordinary simulator mode through the pre-configured simulation options, thereby sending multiple verification modules and test algorithms to the ordinary simulator so that the ordinary simulator can verify the functions of multiple verification modules.

[0071] The test algorithm is a relatively simple algorithm and will not have any errors. Therefore, the process of using multiple verification modules to verify the test algorithm by an ordinary simulator is relatively simple, so that it can be determined in a shorter time whether the functions of multiple verification modules are normal and whether the connectivity of multiple verification modules is normal.

[0072] 203. Receive the verification result returned by the common simulator.

[0073] 204. If the verification result is correct, the multiple verification modules are determined as multiple target verification modules.

[0074] When the functions of the multiple verification modules are normal and the connectivity of the multiple verification modules is normal, the multiple verification modules are determined as multiple target verification modules for verifying the algorithm to be verified in the hardware accelerator.

[0075] 205. If the verification mode is the accelerator mode, the file to be verified is sent to the hardware accelerator, so that the hardware accelerator can use multiple target verification modules to simulate and verify the algorithm to be verified.

[0076] In an embodiment of the present application, by verifying multiple verification modules included in the verification platform corresponding to the hardware accelerator in a common accelerator, the efficiency of verifying the multiple verification modules is effectively improved. When the functions of the multiple verification modules are normal and the connectivity of the multiple verification modules is normal, the multiple verification modules are determined as multiple target verification modules for verifying the algorithm to be verified in the hardware accelerator, thereby avoiding the situation where multiple target verification modules fail during the process of verifying the algorithm to be verified using multiple target verification modules in the hardware accelerator.

[0077] Figure 3 A flowchart of another embodiment of the simulation verification method provided by the present application is shown. The execution subject of the embodiment of the present application is a hardware accelerator. The method includes:

[0078] 301. Receive a file to be verified that includes multiple target verification modules and a top-level simulation file, where the top-level simulation file includes an algorithm to be verified.

[0079] 302. Utilize multiple target verification modules to verify the algorithm to be verified.

[0080] 303. Return the corresponding verification result.

[0081] Figure 3 The execution process of the simulation verification method shown is the same as Figure 1-2 The execution process of the simulation verification method shown is generally the same and will not be repeated here.

[0082] Figure 4 A schematic diagram of the structure of an embodiment of the simulation verification device provided by the present application is shown in FIG. Figure 4 The device includes: a determination module 41 , an acquisition module 42 , a generation module 43 , and a sending module 44 .

[0083] A determination module 41 is used to determine the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script;

[0084] An acquisition module 42 is configured to acquire a plurality of target verification modules related to the algorithm to be verified from a verification platform;

[0085] A generating module 43, configured to generate a file to be verified based on the multiple target verification modules and the top-level simulation file;

[0086] The sending module 44 is configured to send the file to be verified to the hardware accelerator, so that the hardware accelerator can use the multiple target verification modules to simulate and verify the algorithm to be verified.

[0087] Optionally, the determination module 41 is further configured to determine a verification mode according to simulation options pre-configured in the simulation verification script.

[0088] Optionally, the determination module 41 is further configured to, if the verification mode is a common simulator mode, send the plurality of verification modules and the test algorithm to the common simulator so that the common simulator verifies the functions of the plurality of verification modules;

[0089] receiving a verification result returned by the common simulator;

[0090] If the verification result is correct, the multiple verification modules are determined as multiple target verification modules.

[0091] Optionally, if the verification mode is the accelerator mode, the determination module 41 sends the file to be verified to the hardware accelerator, so that the hardware accelerator uses the multiple target verification modules to perform simulation verification on the algorithm to be verified.

[0092] Figure 4 The simulation verification device can perform Figure 1-Figure 2The implementation principle and technical effects of the simulation verification method described in the embodiment are not described in detail. The specific manner in which each module and unit performs operations in the simulation verification device in the above embodiment has been described in detail in the embodiment of the method, and will not be elaborated here.

[0093] Figure 5 The schematic diagram of another embodiment of the simulation verification device provided by the present application is shown, which is applied to an application in an Android car system, such as Figure 5 The device includes: a receiving module 51, a verification module 52, and a returning module 53.

[0094] A receiving module 51 is configured to receive a file to be verified that includes multiple target verification modules and the top-level simulation file, wherein the top-level simulation file includes an algorithm to be verified;

[0095] A verification module 52, configured to verify the algorithm to be verified using the multiple target verification modules;

[0096] The return module 53 is used to return the corresponding verification result.

[0097] Figure 5 The simulation verification device can perform Figure 3 The implementation principle and technical effects of the simulation verification method described in the embodiment are not described in detail. The specific manner in which each module and unit performs operations in the simulation verification device in the above embodiment has been described in detail in the embodiment of the method, and will not be elaborated here.

[0098] In one possible design, Figure 4 The simulation verification apparatus of the embodiment shown can be implemented as a computing device, such as Figure 6 As shown, the computing device may include a storage component 601 and a processing component 602;

[0099] The storage component 601 stores one or more computer instructions, wherein the one or more computer instructions are called and executed by the processing component 602 .

[0100] The processing component 602 is used to:

[0101] Determine the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script;

[0102] Acquire multiple target verification modules related to the algorithm to be verified from the verification platform;

[0103] Generate a file to be verified based on the multiple target verification modules and the top-level simulation file;

[0104] Sending the file to be verified to the hardware accelerator so that the hardware accelerator can use the multiple target verification modules to simulate and verify the algorithm to be verified. Determining the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script;

[0105] Acquire multiple target verification modules related to the algorithm to be verified from the verification platform;

[0106] Generate a file to be verified based on the multiple target verification modules and the top-level simulation file;

[0107] The file to be verified is sent to the hardware accelerator, so that the hardware accelerator uses the multiple target verification modules to perform simulation verification on the algorithm to be verified.

[0108] In one possible design, Figure 5 The simulation verification apparatus of the embodiment shown can be implemented as a computing device, such as Figure 7 As shown, the computing device may include a storage component 701 and a processing component 702;

[0109] The storage component 701 stores one or more computer instructions, wherein the one or more computer instructions are called and executed by the processing component 702 .

[0110] The processing component 702 is used to:

[0111] Receiving a file to be verified including a plurality of target verification modules and the top-level simulation file, wherein the top-level simulation file includes an algorithm to be verified;

[0112] Verifying the algorithm to be verified using the multiple target verification modules;

[0113] Returns the corresponding verification result.

[0114] In addition, an embodiment of the present application provides a non-transitory machine-readable storage medium, wherein the non-transitory machine-readable storage medium stores executable code, and when the executable code is executed by a processor of an electronic device, the processor can at least implement the aforementioned Figure 1-Figure 2 The simulation verification method provided in the illustrated embodiment.

[0115] The embodiment of the present application provides a non-transitory machine-readable storage medium, wherein the non-transitory machine-readable storage medium stores executable code. When the executable code is executed by a processor of an electronic device, the processor can at least implement the aforementioned Figure 3 The simulation verification method provided in the illustrated embodiment.

[0116] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0117] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0118] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A simulation verification method, characterized in that: Applied to simulation verification scripts, the method includes: Determine the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script; Determining a verification mode according to simulation options pre-configured in the simulation verification script; If the verification mode is a common simulator mode, multiple verification modules and a test algorithm are sent to the common simulator so that the common simulator verifies the functions and connectivity of the multiple verification modules; a verification result returned by the common simulator is received; if the verification result is correct, the multiple verification modules are determined as multiple target verification modules; the multiple target verification modules include a reset module, a clock module, a master device verification component, and a slave device verification component; if the functions of the multiple verification modules are normal and the connectivity of the multiple verification modules is normal, the verification result is correct; Generate a file to be verified based on the multiple target verification modules and the top-level simulation file; The file to be verified is sent to a hardware accelerator, so that the hardware accelerator uses the multiple target verification modules to perform simulation verification on the algorithm to be verified.

2. The method according to claim 1, characterized in that The method further comprises: If the verification mode is the accelerator mode, the file to be verified is sent to the hardware accelerator, so that the hardware accelerator uses the multiple target verification modules to perform simulation verification on the algorithm to be verified.

3. The method according to claim 1, characterized in that The generating a file to be verified based on the multiple target verification modules and the top-level simulation file includes: Adding an outer layer outside the top-level simulation file; The multiple target verification modules are added to the outer layer to generate a file to be verified.

4. A simulation verification device, characterized in that: Applied to simulation verification scripts, the device includes: A determination module, configured to determine a top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script; An acquisition module is configured to determine a verification mode according to simulation options pre-configured in the simulation verification script; if the verification mode is a common simulator mode, multiple verification modules and a test algorithm are sent to the common simulator so that the common simulator verifies the functions and connectivity of the multiple verification modules; and a verification result returned by the common simulator is received; if the verification result is correct, the multiple verification modules are determined as multiple target verification modules; the multiple target verification modules include a reset module, a clock module, a master device verification component, and a slave device verification component; and if the functions of the multiple verification modules are normal and the connectivity of the multiple verification modules is normal, the verification result is correct. A generating module, configured to generate a file to be verified based on the multiple target verification modules and the top-level simulation file; The sending module is used to send the file to be verified to the hardware accelerator, so that the hardware accelerator can use the multiple target verification modules to simulate and verify the algorithm to be verified.

5. A computing device, characterized in that including processing components and storage components; The storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component; The processing component is used to: Determine the top-level simulation file corresponding to the algorithm to be verified in the chip to be verified in the simulation verification script; Determining a verification mode according to simulation options pre-configured in the simulation verification script; If the verification mode is a common simulator mode, the plurality of verification modules and the test algorithm are sent to the common simulator so that the common simulator verifies the functions and connectivity of the plurality of verification modules; the verification results returned by the common simulator are received; and if the verification results are correct, the plurality of verification modules are determined as a plurality of target verification modules; The multiple target verification modules include a reset module, a clock module, a master device verification component, and a slave device verification component; if the functions of the multiple verification modules are normal and the connectivity of the multiple verification modules is normal, the verification result is correct; Generate a file to be verified based on the multiple target verification modules and the top-level simulation file; The file to be verified is sent to a hardware accelerator, so that the hardware accelerator uses the multiple target verification modules to perform simulation verification on the algorithm to be verified.

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