A Convolution Feature Caching Method, Device, Electronic Device, and Readable Storage Medium

Abstract

The present application discloses a convolutional feature caching method, device, electronic device and computer-readable storage medium. The method includes: obtaining a plurality of convolutional features and writing the convolutional features into a cache space; wherein, the cache space includes a plurality of cache units, and each cache unit is arranged in a two-dimensional matrix, and each cache unit is used to store a convolutional feature; if it is detected that the cache space is read, then according to the horizontal circular direction, the convolutional features in each matrix row are horizontally offset; if it is detected that the number of horizontal offset times is in the first interval, then according to the vertical circular direction, the convolutional features in each matrix column are vertically offset, and the number of horizontal offset times is cleared; if it is detected that the number of vertical offset times is in the second interval, it is determined that the data call is completed; it is possible to avoid frequently obtaining convolutional features from an external storage medium, cache a relatively large number of convolutional features at one time, and maximize their utilization, and efficiently provide a large number of convolutional features for convolutional calculations.

Description

Technical Field

[0001] This application relates to the technical field of neural networks, and particularly relates to a convolutional feature caching method, a convolutional feature caching device, an electronic device, and a computer-readable storage medium. Background Art

[0002] Currently, the research in the field of deep learning mainly focuses on CNN (Convolutional Neural Network). Due to different processing scenarios, different performance requirements are imposed on CNN, thus developing various network structures. However, the basic composition of CNN is fixed, which are respectively the input layer, the convolutional layer, the activation layer, the pooling layer, and the fully connected layer. Among them, the part with the largest amount of computation is the convolutional layer, and its main function is to complete the convolution operation between the image (feature) and the neuron (filter). For different CNN neural network structures, the length of the processed data is different. For common CNN network structures, the amount of input and output data is very large. For example, one layer of the ResNet50 network can have 512 input channels and 512 output channels. Multiplying by the size of the image, the number of bytes of the data can reach the million level. At the same time, the convolution calculation rate is an important indicator to measure the performance of the CNN network. This requires a large amount of calculation data to be provided for the calculation kernel in a short time. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a convolutional feature caching method, a convolutional feature caching device, an electronic device, and a computer-readable storage medium, which can efficiently provide calculation data for the calculation kernel.

[0004] To solve the above technical problems, this application provides a convolutional feature caching method, including:

[0005] Obtain a plurality of convolutional features and write the convolutional features into a cache space; wherein, the cache space includes a plurality of cache units, and each of the cache units is arranged in a two-dimensional matrix, and each cache unit is used to store one of the convolutional features;

[0006] If it is detected that the cache space is read, then perform a horizontal offset on the convolutional features in each matrix row in the horizontal circular direction;

[0007] If it is detected that the number of horizontal offset times is in the first interval, then perform a vertical offset on the convolutional features in each matrix column in the vertical circular direction and clear the number of horizontal offset times;

[0008] If it is detected that the number of vertical offset times is in the second interval, then determine that the data call is completed.

[0009] Optionally, writing the convolution features into the cache space includes:

[0010] Determine target convolution features, and determine target cache units according to the pixel positions of the target convolution features;

[0011] Write the target convolution features into the target cache units.

[0012] Optionally, performing horizontal offset on the convolution features in each matrix row in the horizontal circular direction includes:

[0013] Determine the data flow directions between the row cache units in the cache space in the horizontal circular direction; the row cache units are in the same matrix row in the two-dimensional matrix;

[0014] Send the first convolution features of the row cache units to corresponding subsequent units according to the data flow directions, and save the second convolution features sent by the previous units into the row cache units.

[0015] Optionally, sending the first convolution features of the row cache units to corresponding subsequent units according to the data flow directions includes:

[0016] According to the data flow directions, respectively use a preset step size to determine the corresponding subsequent units of the row cache units with each row cache unit as a base point;

[0017] Send the first convolution features of the row cache units to the corresponding subsequent units.

[0018] Optionally, it further includes:

[0019] If it is detected that the cache space needs to be updated, offset the convolution features in the cache space in the non-circular direction corresponding to the horizontal circular direction or the vertical circular direction;

[0020] Obtain updated convolution features, and write the updated convolution features into blank storage units in the cache space.

[0021] Optionally, detecting that the cache space is read includes:

[0022] If a read request is detected, based on a preset read coordinate, read target convolution features from the cache space according to a preset convolution kernel size;

[0023] Send the target convolution features to the many-core computing array, and determine that the cache space has been read completely.

[0024] Optionally, the cache space includes a plurality of line data cache units connected in sequential communication. The previous output port corresponding to the previous line data cache unit is communicatively connected to the subsequent input port corresponding to the subsequent line data cache unit;

[0025] Each of the line data cache units has a plurality of the cache units connected in series. Each cache unit is communicatively connected to the input port and the output port of its own unit; The cache units corresponding to the same position in two adjacent line data cache units are communicatively connected through the previous line output port and the subsequent input port.

[0026] This application also provides a convolutional feature cache device, including:

[0027] A writing module, configured to obtain a plurality of convolutional features and write the convolutional features into the cache space; wherein, the cache space includes a plurality of cache units, and each of the cache units is arranged in a two-dimensional matrix, and each cache unit is used to store one of the convolutional features;

[0028] A horizontal offset module, configured to, if it is detected that the cache space is read, offset the convolutional features in each matrix row in the horizontal circular direction;

[0029] A vertical offset module, configured to, if it is detected that the number of horizontal offset times is in the first interval, offset the convolutional features in each matrix column in the vertical circular direction and clear the number of horizontal offset times;

[0030] An end determination module, configured to, if it is detected that the number of vertical offset times is in the second interval, determine that the data call is completed.

[0031] This application also provides an electronic device, including a memory and a processor, wherein:

[0032] The memory is used to store a computer program;

[0033] The processor is configured to execute the computer program to implement the above-mentioned convolutional feature caching method.

[0034] This application also provides a computer-readable storage medium, used to store a computer program, wherein the computer program, when executed by a processor, implements the above-mentioned convolutional feature caching method.

[0035] The convolution feature caching method provided by this application obtains multiple convolution features and writes the convolution features into a cache space. The cache space includes multiple cache units, and each cache unit is arranged in a two-dimensional matrix. Each cache unit is used to store a convolution feature. If it is detected that the cache space is read, the convolution features in each matrix row are horizontally offset in the horizontal cyclic direction. If it is detected that the horizontal offset times are within the first interval, the convolution features in each matrix column are vertically offset in the vertical cyclic direction, and the horizontal offset times are cleared. If it is detected that the vertical offset times are within the second interval, it is determined that the data call is completed.

[0036] It can be seen that this method uses a special cache space to cache convolution features. There are multiple cache units in this cache space, and the number of cache units is greater than the number of convolution kernels. Each cache unit is arranged in a two-dimensional matrix, and each cache unit is used to store a convolution feature. The process of convolution calculation can be regarded as a process in which the convolution range composed of convolution kernels slides horizontally and vertically in the matrix composed of convolution features to select part of the data and use it for calculation. Therefore, after the convolution features are stored in the cache space, every time the cache space is read, a part of the convolution features is selected for calculation. The next convolution calculation requires new convolution features. In this case, the data in the cache space is not cleared, but the convolution features in each matrix row in the matrix composed of convolution features are horizontally offset in the horizontal cyclic direction, that is, the horizontal offset of the elements in the matrix is used to replace the horizontal sliding of the convolution range composed of convolution kernels in the matrix composed of convolution features, so that the data cached once can be used for multiple convolutions. When the horizontal offset times are within the first interval, it means that from the horizontal perspective, the convolution range composed of convolution kernels has selected all valid data for calculation. In this case, the convolution features in each matrix column are vertically offset once in the vertical cyclic direction to update one row of data, and the horizontal offset times are cleared to start the horizontal offset again. If it is detected that the vertical offset times are within the second interval, it means that all valid data combinations in the cache space have been selected in both the horizontal and vertical directions, and there is no longer valid data in the current cache space. Therefore, it can be determined that the data call is completed. Through the above method, it is possible to avoid frequently obtaining convolution features from an external storage medium, cache more convolution features at one time, and maximize their utilization. The reading speed and bandwidth of the cache are much greater than those of the external storage medium. Therefore, a large number of convolution features for convolution calculation can be provided in a short time, improving the calculation speed.

[0037] In addition, this application also provides a convolution feature caching device, an electronic device, and a computer-readable storage medium, which also have the above beneficial effects. Description of the Drawings

[0038] To more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the accompanying drawings required for the description of the embodiments or related technologies. Obviously, the accompanying drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on the provided drawings.

[0039] Figure 1 Flowchart of a convolutional feature caching method provided by an embodiment of the present application;

[0040] Figure 2 Structural diagram of a cache space provided by an embodiment of the present application;

[0041] Figure 3 Structural diagram of a row data cache unit provided by an embodiment of the present application;

[0042] Figure 4 Another structural diagram of a cache space provided by an embodiment of the present application;

[0043] Figure 5 Schematic diagram of cache space data update provided by an embodiment of the present application;

[0044] Figure 6 Structural diagram of a convolutional feature caching device provided by an embodiment of the present application;

[0045] Figure 7 Structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part rather than all of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

[0047] Please refer to Figure 1 , Figure 1 Flowchart of a convolutional feature caching method provided by an embodiment of the present application.

[0048] The method includes:

[0049] S101: Obtain multiple convolutional features and write the convolutional features into the cache space.

[0050] Among them, the cache space includes multiple cache units, and each cache unit is arranged in a two-dimensional matrix. Each cache unit is used to store a convolutional feature. That is, each cache unit serves as an element in the two-dimensional matrix, forming a cache space in the form of a two-dimensional matrix. Please refer to Figure 2 , Figure 2 which is a cache space structure diagram provided by an embodiment of the present application. Each cube therein represents a cache unit. Figure 2 The black arrow and the horizontal and vertical white arrows in

[0051] constitute the horizontal cyclic direction and the vertical cyclic direction, and these two directions are used to guide the offset of the convolutional feature in the cache space. The present embodiment does not limit the hardware manifestation of the cache space. In a specific implementation, the cache units in the same row of the two-dimensional matrix can be integrated to obtain row data cache units, and multiple row data cache units are connected longitudinally to construct the cache space. Please refer to Figure 3 and Figure 4 , Figure 3 which is a structure diagram of a row data cache unit provided by an embodiment of the present application. Figure 4 is another cache space structure diagram provided by an embodiment of the present application. As can be seen from Figure 4 , the cache space includes multiple sequentially communication-connected row data cache units (i.e., Figure 4 the row data cyclic cache units in

[0052] ). The pre-order output port corresponding to the pre-order row data cache unit is communicatively connected to the post-order input port corresponding to the post-order row data cache unit. Among them, the pre-order row data cache unit and the post-order row data cache unit are relative relationships. That is, among a group of two row data cache units connected by an output port and an input port, the row data cache unit with the output port is the pre-order row data cache unit, and the output port is the pre-order port. Correspondingly, the row data cache unit with the input port is the post-order row data cache unit. Figure 3 As can be seen from Figure 3As can be seen, the input part of the storage unit has a three-way selector. The input channels of the selector are respectively the external input, the input of the corresponding cache unit in the previous row data cache unit, and the input of the previous unit determined by the horizontal cyclic order in the current row data cache unit. By setting the above three input channels, any storage unit can obtain data from the external, or can obtain the data sent by the previous unit during horizontal offset, or can obtain the data sent by the cache unit corresponding to the position in the previous row data cache unit through the previous row output port and the subsequent input port during vertical offset.

[0053] In addition, as can also be seen from Figure 3 each cache unit has two output channels, namely the channel for sending data to the subsequent unit during horizontal offset, and the channel for sending data to the cache unit corresponding to the position in the subsequent row data cache unit during vertical offset.

[0054] Based on the above cache space, the present application proposes a special cache method. Before the convolution calculation starts, it is necessary to obtain multiple convolution features for convolution calculation and write the convolution features into the cache space. It can be understood that one convolution feature is stored in each cache unit, so the convolution features are also arranged in a two-dimensional matrix.

[0055] Generally, convolution calculation is performed on image data. In this case, there is a corresponding relationship between the convolution features and the pixels in the image. In order to perform convolution calculation effectively, the process of writing the convolution features into the cache space may include the following steps:

[0056] Step 11: Determine the target convolution feature and determine the target cache unit according to the pixel position of the target convolution feature.

[0057] Step 12: Write the target convolution feature into the target cache unit.

[0058] Among them, the target convolution feature can be any convolution feature. When inputting the convolution features into the cache space, since the pixels in the images have a position correlation relationship, the convolution features corresponding to the pixels also have a position correlation relationship. In this case, each convolution feature should be determined as the target convolution feature respectively, and its position in the two-dimensional cache space, that is, the target cache unit, should be determined according to the pixel position where its corresponding pixel is located.

[0059] It can be understood that pixels are arranged in a two-dimensional manner to form an image, and cache units are arranged in a two-dimensional manner to form a cache space. Therefore, convolution features can be arranged in the cache space in the form of a two-dimensional matrix according to the positions of the pixels in the image, so that the storage state of the convolution features in the cache space conforms to the position correlation relationship between the pixels, thereby ensuring that the read data can represent the state of the image and making the result of the convolution calculation effective. It should be noted that the pixel position can be the same as the coordinate position of the target cache unit in the cache space, or can have a relationship where the horizontal and vertical coordinates are opposite to the coordinate position of the target cache unit in the cache space. That is, when the pixel position is (X, Y), the coordinate position of the target cache unit in the cache space can be (X, Y), or can be (Y, X).

[0060] S102: If it is detected that the cache space is read, the convolution features in each matrix row are horizontally offset in the horizontal circular direction.

[0061] After the convolution features are stored, they are used to provide the data required for convolution calculation to the computing core. The data scale required for the computing core during calculation is limited by the scale of the computing core (also known as the convolution kernel size). For example, if the scale of the computing core is 3*3, it means that nine convolution features in three rows and three columns are used for calculation each time. In this application, the two-dimensional matrix scale of the cache space is larger than the scale of the computing core, so that the data read in at one time can support multiple convolution calculations as much as possible, reduce the number of times of obtaining convolution features from external storage, and give full play to the advantage of the fast read and write speed of the cache space as much as possible to improve the calculation efficiency.

[0062] It can be understood that the process of convolution calculation can be understood as a square with the size of the computing core scale translating horizontally and vertically on the matrix composed of convolution features, and the convolution features covered by the square are extracted for calculation each time after translation to obtain the calculation result. In this application, the square can remain stationary, and the horizontal and vertical offsets of the convolution features in the cache space are used to replace the horizontal and vertical translations of the square. Specifically, detecting that the cache space is read includes:

[0063] Step 21: If a read request is detected, based on the preset read coordinates, the target convolution features are read from the cache space according to the preset convolution kernel size.

[0064] Step 22: Send the target convolution features to the many-core computing array and determine that the cache space has been read completely.

[0065] Among them, the preset read coordinates refer to the basic coordinates used to set the read range, and there is no specific limitation. For example, it can be the upper left corner coordinates of the cache space. The preset convolution kernel size refers to the size of the computing core used by the computing core, and this parameter can be preset according to the situation of the computing core.

[0066] During each read operation, according to the preset read coordinates and the preset convolution kernel size, a data read range can be delimited in the cache space, which is the square for calculating the kernel scale size in the above description, and the convolution features covered by this square are determined as the target convolution features. After sending the target convolution features to the many-core computing array (i.e., the array composed of computing kernels), it can be determined that this read is completed.

[0067] After detecting that the cache space has been read completely, in order to provide new convolution features for the next convolution calculation, it is necessary to imitate the process of horizontal and vertical translation of the square on the matrix composed of convolution features to re-obtain new convolution features. In this application, the horizontal and vertical translation of the square can be replaced by the way of circularly shifting data horizontally or vertically in the data. Specifically, please refer to Figure 2 , Figure 2 The schematic diagram of the cache space shown in also shows the horizontal circular direction and the vertical circular direction therein. Among them, the white arrows in each horizontal direction form a closed direction, which is the horizontal circular direction. Similarly, the white arrows and black arrows in the vertical direction also form a closed direction, which is the vertical circular direction.

[0068] After detecting that the cache space has been read, first, according to the horizontal circular direction, perform a horizontal offset on each matrix row in the matrix composed of convolution features, that is, perform a horizontal offset on the convolution features in each matrix row. The specific process of the horizontal offset can include the following steps:

[0069] Step 31: Determine the data flow direction between each row cache unit in the cache space according to the horizontal circular direction; the row cache units are in the same matrix row in the two-dimensional matrix.

[0070] Step 32: Send the first convolution feature of each row cache unit to the corresponding subsequent unit according to the data flow direction, and save the second convolution feature sent by the previous unit to the row cache unit.

[0071] Among them, according to the horizontal circular direction, the data flow direction can be determined between each row cache unit in the same matrix row in the two-dimensional matrix. A row cache unit refers to a cache unit in the same matrix row, which is a relative concept, that is, several cache units in the same matrix row are row cache units for each other, and cache units in different matrix rows are not row cache units for each other. Or it can be said that each cache unit in the same matrix row is the row cache unit corresponding to this matrix row. The data flow direction refers to the data sending direction between each row cache unit.

[0072] After determining the data flow direction, in accordance with this direction, send the first convolutional features originally stored in each row buffer unit to the subsequent unit determined according to the data flow direction. At the same time, obtain the second convolutional features sent by the previous unit as the new convolutional features stored in this storage unit.

[0073] Further, usually, the convolution stride is 1, that is, when the above-mentioned square moves horizontally and vertically on the matrix composed of convolutional features, it moves one pixel each time (that is, moves one row or one column). However, in some cases, the convolution stride may be other than 1, for example, it can be 2 or 3. Therefore, when determining the subsequent unit, the following steps can be executed:

[0074] Step 41: In accordance with the data flow direction, respectively use each row buffer unit as a base point, and use a preset stride to determine the subsequent unit corresponding to each row buffer unit.

[0075] Step 42: Send the first convolutional features of each row buffer unit to the corresponding subsequent unit.

[0076] After determining the data flow direction, use a row buffer unit as the base point for determining its subsequent unit. On this basis, push backward the preset stride according to the data flow direction to determine the subsequent unit corresponding to this row buffer unit, and then send the first convolutional features currently stored in itself to the subsequent unit. Executing the above steps for each row buffer unit can complete the horizontal offset.

[0077] S103: If it is detected that the number of horizontal offset times is in the first interval, then perform vertical offset on the convolutional features in each matrix column in the vertical loop direction, and clear the number of horizontal offset times.

[0078] After each horizontal offset is completed, update the number of horizontal offset times, which is used to record the number of consecutive horizontal offsets. If it is detected that the number of horizontal offset times is in the first interval, it means that the convolutional features have been horizontally offset continuously enough times so that they have returned to the state before continuous horizontal offset. In this case, continuing the horizontal offset can no longer provide new convolutional features for the computing core. Therefore, vertical offset can be performed on the convolutional features in each matrix column in the vertical loop direction, and at the same time, the number of horizontal offset times is cleared. It should be noted that the specific size of the first interval is not limited and can be set as needed. Exemplarily, the minimum value of the first interval can be the number of columns of the two-dimensional matrix of the cache space.

[0079] The processes of vertical offset and horizontal offset are the same, except that their directions are different, and the specific offset processes are not limited. After vertical offset, at least one new row of the convolutional feature matrix can be provided for data reading, so that new convolutional features can be provided for the computing kernel. The process of vertical offset can be regarded as the process of the above-mentioned square translating vertically on the matrix composed of convolutional features. After one vertical offset, the number of horizontal offset times is cleared to start a new round of horizontal offset again.

[0080] S104: If it is detected that the number of vertical offset times is in the second interval, it is determined that the data call is completed.

[0081] After each vertical offset is completed, the number of vertical offset times is updated, and the number of vertical offset times is used to record the number of vertical offsets. When the number of vertical offset times is in the second interval, it means that the convolutional features have been vertically offset enough times to return to the state before the first vertical offset. In this case, whether continuing with horizontal offset or vertical offset, no new convolutional features can be provided for the computing kernel, so it can be determined that the current data call is completed.

[0082] After determining that the current data call is completed, generally, the data in the cache space needs to be cleared to re-store new convolutional features, and then new convolutional features can be provided for the computing kernel again. However, in one implementation, the convolutional features rewritten into the cache space have overlapping parts with the cleared convolutional features. In this case, to improve the speed of data update, the following steps can be executed:

[0083] Step 51: If it is detected that the cache space needs to be updated, offset the convolutional features in the cache space in the non-cyclic direction corresponding to the horizontal cyclic direction or the vertical cyclic direction.

[0084] Step 52: Obtain the updated convolutional features and write the updated convolutional features into the blank storage units in the cache space.

[0085] Among them, the non-cyclic direction refers to the unclosed horizontal cyclic direction or vertical cyclic direction, and the end point of this direction is the last object in the matrix row or matrix column. Please refer to Figure 2 , where the non-cyclic direction corresponding to the vertical direction refers to the direction composed of white arrows vertically, which does not include black arrows. The non-cyclic direction corresponding to the horizontal direction refers to the direction composed of white arrows between two adjacent cache units horizontally, and does not include white arrows between non-adjacent cache units.

[0086] When it is detected that the cache space needs to be updated, the convolutional features in the cache space are offset in a non-circular direction. It can be understood that the offset in the non-circular direction will inevitably cause the convolutional features originally stored in the cache units at the end of the non-circular direction to be discarded, and at the same time, no new convolutional features will be stored in the cache units at the beginning of the non-circular direction, which are called blank storage units. These blank storage units are used to store the obtained updated convolutional features.

[0087] Please refer to Figure 5 , Figure 5 FIG. 2 is a schematic diagram of data update in a cache space provided by an embodiment of the present application. Among them, Data 1 and Data 2 are the convolutional features originally stored in the cache space. When it is detected that the cache space needs to be updated, the offset is performed according to the above steps, Data 1 in the cache space is discarded, Data 2 is retained, and at the same time, Data 3 is obtained and written into the blank storage unit to complete the data update process.

[0088] Applying the convolutional feature caching method provided by the embodiment of the present application, a special cache space is used to cache convolutional features. There are multiple cache units in this cache space, the number of cache units is greater than the number of convolutional kernels, and each cache unit is arranged in a two-dimensional matrix. Each cache unit is used to store a convolutional feature. The process of convolutional calculation can be regarded as a process in which the convolutional range composed of convolutional kernels slides horizontally and vertically in the matrix composed of convolutional features to select some data and use it for calculation. Therefore, after the convolutional features are stored in the cache space, every time the cache space is read, a part of the convolutional features is selected for calculation. The next convolutional calculation requires new convolutional features. In this case, the data in the cache space is not cleared, but the rows of the matrix composed of convolutional features are horizontally offset in the horizontal circular direction, that is, the horizontal offset of the elements in the matrix is used to replace the horizontal sliding of the convolutional range composed of convolutional kernels in the matrix composed of convolutional features, so that the data cached once can be used for multiple convolutions. When the number of horizontal offsets is in the first interval, it means that from the horizontal perspective, the convolutional range composed of convolutional kernels has selected all valid data for calculation. In this case, the convolutional features in each matrix column are vertically offset once in the vertical circular direction, a row of data is updated, and the number of horizontal offsets is cleared to start horizontal offset again. If it is detected that the number of vertical offsets is in the second interval, it means that all valid data combinations in the cache space have been selected in both horizontal and vertical directions, and there is no valid data in the current cache space. Therefore, it can be determined that the data call is completed. Through the above method, it is not necessary to frequently obtain convolutional features from an external storage medium, a large number of convolutional features can be cached at one time and maximally utilized. The reading speed and bandwidth of the cache are much greater than those of the external storage medium. Therefore, a large number of convolutional features for convolutional calculation can be provided in a short time, improving the calculation speed.

[0089] The convolutional feature caching device provided in the embodiments of the present application will be introduced below. The convolutional feature caching device described below can be correspondingly referred to the convolutional feature caching method described above.

[0090] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of a convolutional feature caching device provided in the embodiments of the present application, including:

[0091] A writing module 110, configured to obtain a plurality of convolutional features and write the convolutional features into a cache space; wherein, the cache space includes a plurality of cache units, and each cache unit is arranged in a two-dimensional matrix, and each cache unit is used to store one convolutional feature;

[0092] A horizontal offset module 120, configured to, if it is detected that the cache space is read, perform a horizontal offset on the convolutional features in each matrix row in the horizontal circular direction;

[0093] A vertical offset module 130, configured to, if it is detected that the number of horizontal offset times is in a first interval, perform a vertical offset on the convolutional features in each matrix column in the vertical circular direction and clear the number of horizontal offset times;

[0094] An end determination module 140, configured to, if it is detected that the number of vertical offset times is in a second interval, determine that the data call is completed.

[0095] Optionally, the writing module 110 includes:

[0096] A target determination unit, configured to determine a target convolutional feature and determine a target cache unit according to the pixel position of the target convolutional feature;

[0097] A writing unit, configured to write the target convolutional feature into the target cache unit.

[0098] Optionally, the horizontal offset module 120 includes:

[0099] A flow direction determination unit, configured to determine the data flow direction between each row cache unit in the cache space in the horizontal circular direction; the row cache units are in the same matrix row in the two-dimensional matrix;

[0100] A sending and receiving unit, configured to send the first convolutional feature of each row cache unit to the corresponding subsequent unit according to the data flow direction and save the second convolutional feature sent by the previous unit to the row cache unit.

[0101] Optionally, the sending and receiving unit includes:

[0102] A subsequent determination subunit, configured to determine subsequent units corresponding to each row buffer unit respectively with each row buffer unit as a base point and using a preset step length according to the data flow direction;

[0103] A sending subunit, configured to send the first convolution features of each row buffer unit to the corresponding subsequent unit.

[0104] Optionally, it further includes:

[0105] An update offset module, configured to, if it is detected that the cache space needs to be updated, offset the convolution features in the cache space in the non-cyclic direction corresponding to the horizontal cyclic direction or the vertical cyclic direction;

[0106] An update writing module, configured to obtain updated convolution features and write the updated convolution features into blank storage units in the cache space.

[0107] Optionally, the horizontal offset module 120 includes:

[0108] A target determination unit, configured to, if a read request is detected, read target convolution features from the cache space based on a preset read coordinate according to a preset convolution kernel size;

[0109] A data sending unit, configured to send the target convolution features to the many-core computing array and determine that the cache space has been read out.

[0110] Optionally, the cache space includes multiple row data buffer units connected in sequence for communication, and the previous output port corresponding to the previous row data buffer unit is communicatively connected to the subsequent input port corresponding to the subsequent row data buffer unit;

[0111] Each row data buffer unit has multiple cache units connected in series, and each cache unit is communicatively connected to the input port and output port of this unit respectively; the cache units corresponding to the same position in two adjacent row data buffer units are communicatively connected through the previous row output port and the subsequent input port.

[0112] Next, the electronic device provided by the embodiment of the present application will be introduced, and the electronic device described below can be mutually corresponding and referred to with the convolution feature caching method described above.

[0113] Please refer to Figure 7 , Figure 7 , which is a schematic structural diagram of an electronic device provided by an embodiment of the present application. The electronic device 100 may include a processor 101 and a memory 102, and may further include one or more of a multimedia component 103, an information input / output (I / O) interface 104, and a communication component 105.

[0114] Among them, the processor 101 is used to control the overall operation of the electronic device 100 to complete all or part of the steps in the above-mentioned convolutional feature caching method; the memory 102 is used to store various types of data to support the operation of the electronic device 100. These data may include, for example, instructions for any application or method operating on the electronic device 100, as well as application-related data. The memory 102 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic memory, flash memory, a hard disk, or an optical disc, or one or more of them.

[0115] The multimedia component 103 may include a screen and an audio component. The screen may be, for example, a touch screen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in the memory 102 or sent through the communication component 105. The audio component further includes at least one speaker for outputting audio signals. The I / O interface 104 provides an interface between the processor 101 and other interface modules, and the other interface modules may be a keyboard, a mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component 105 is used for wired or wireless communication between the electronic device 100 and other devices. Wireless communication, such as Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, or 4G, or a combination of one or more of them. Accordingly, the communication component 105 may include: a Wi-Fi component, a Bluetooth component, and an NFC component.

[0116] The electronic device 100 can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components, and is used to execute the convolution feature caching method given in the above embodiments.

[0117] The computer-readable storage medium provided by the embodiments of the present application will be introduced below. The computer-readable storage medium described below can be correspondingly referred to the convolution feature caching method described above.

[0118] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above convolution feature caching method are implemented.

[0119] The computer-readable storage medium may include: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks or optical discs.

[0120] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, refer to the description of the method part.

[0121] Those skilled in the art can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been generally described according to functions in the above description. Whether these functions are executed in the form of hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0122] The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be implemented directly in hardware, in software modules executed by a processor, or in a combination of both. The software modules may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0123] Finally, it should also be noted that in this document, relationships such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "including", "comprising" or any other variant are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article or device.

[0124] Specific examples have been used in this text to illustrate the principles and implementation methods of the present application. The descriptions of the above embodiments are only for helping to understand the method of the present application and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A convolutional feature caching method, characterized in that Including: Obtain multiple convolution features and write the convolution features into a cache space; wherein, the cache space includes multiple cache units, the number of cache units is greater than the number of convolution kernels, each of the cache units is arranged in a two-dimensional matrix, each cache unit is an element in the two-dimensional matrix, and each cache unit is used to store one of the convolution features; If it is detected that the cache space is read, then, in accordance with the horizontal circular direction, perform a horizontal offset on the convolution features in each matrix row, and use the horizontal offset of the elements in the two-dimensional matrix formed by the cache units to replace the convolution range formed by the convolution kernels, and slide horizontally in the matrix formed by the convolution features; If it is detected that the number of horizontal offset times is within a first interval, then, in accordance with the vertical circular direction, perform a vertical offset on the convolution features in each matrix column, use the vertical offset of the elements in the two-dimensional matrix formed by the cache units to replace the convolution range formed by the convolution kernels, and slide vertically in the matrix formed by the convolution features, and clear the number of horizontal offset times; wherein, the minimum value of the first interval is the total number of consecutive horizontal offsets of the current convolution feature when the convolution feature has returned to the state before consecutive horizontal offsets; If it is detected that the number of vertical offset times is within a second interval, then determine that the data call is completed; wherein, the minimum value of the second interval is the total number of consecutive vertical offsets of the current convolution feature when the convolution feature has returned to the state before the first vertical offset.

2. The convolution feature caching method according to claim 1, wherein The writing the convolution features into the cache space includes: Determine a target convolution feature and determine a target cache unit according to the pixel position of the target convolution feature; Write the target convolution feature into the target cache unit.

3. The convolution feature caching method according to claim 1, wherein The performing a horizontal offset on the convolution features in each matrix row in accordance with the horizontal circular direction includes: In accordance with the horizontal circular direction, determine the data flow direction between each row cache unit in the cache space; the row cache units are in the same matrix row in the two-dimensional matrix; In accordance with the data flow direction, send the first convolution feature of each row cache unit to the corresponding subsequent unit, and save the second convolution feature sent by the previous unit to the row cache unit.

4. The convolutional feature caching method according to claim 3, wherein The sending the first convolution feature of each row cache unit to the corresponding subsequent unit in accordance with the data flow direction includes: In accordance with the data flow direction, respectively, with each row cache unit as a base point, use a preset step size to determine the corresponding subsequent unit of each row cache unit; Send the first convolution feature of each row cache unit to the corresponding subsequent unit.

5. The convolution feature caching method according to claim 1, wherein It further includes: If it is detected that the cache space needs to be updated, then offset the convolution features in the cache space in the non-circular direction corresponding to the horizontal circular direction or the vertical circular direction; Obtain updated convolution features and write the updated convolution features into the blank storage units in the cache space.

6. The convolution feature caching method according to claim 1, wherein The detecting that the cache space is read includes: If a read request is detected, then, based on a preset read coordinate, read a target convolution feature from the cache space according to a preset convolution kernel size; Send the target convolution features to the many-core computing array and determine that the reading of the cache space is completed.

7. The convolution feature caching method according to claim 1, wherein The cache space includes multiple row data cache units connected in sequential communication. The previous output port corresponding to the previous row data cache unit is communicatively connected to the subsequent input port corresponding to the subsequent row data cache unit. Each of the row data cache units has multiple cascaded cache units, and each cache unit is communicatively connected to the input port and output port of its own unit; the cache units corresponding in position in two adjacent row data cache units are communicatively connected through the previous row output port and the subsequent input port.

8. A convolutional feature caching device, characterized in that, It includes: A writing module, configured to obtain multiple convolution features and write the convolution features into the cache space; wherein, the cache space includes multiple cache units, the number of cache units is greater than the number of convolution kernels, each of the cache units is arranged in a two-dimensional matrix, each cache unit is used as an element in the two-dimensional matrix, and each cache unit is used to store one of the convolution features. A horizontal offset module, configured to, if it is detected that the cache space is read, offset the convolution features in each matrix row in the horizontal cyclic direction, use the horizontal offset of the elements in the two-dimensional matrix formed by the cache units to replace the convolution range formed by the convolution kernels, and slide horizontally in the matrix formed by the convolution features. A vertical offset module, configured to, if it is detected that the number of horizontal offset times is in the first interval, offset the convolution features in each matrix column in the vertical cyclic direction, use the vertical offset of the elements in the two-dimensional matrix formed by the cache units to replace the convolution range formed by the convolution kernels, and slide vertically in the matrix formed by the convolution features, and clear the number of horizontal offset times; wherein, the minimum value of the first interval is the total number of consecutive horizontal offsets of the current convolution features when the convolution features have returned to the state before consecutive horizontal offsets. An end determination module, configured to, if it is detected that the number of vertical offset times is in the second interval, determine that the data call is completed; wherein, the minimum value of the second interval is the total number of consecutive vertical offsets of the current convolution features when the convolution features have returned to the state before the first vertical offset.

9. An electronic device, characterized in that, It includes a memory and a processor, wherein: The memory is used to store a computer program. The processor is configured to execute the computer program to implement the convolution feature caching method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store a computer program, wherein the computer program, when executed by the processor, implements the convolution feature caching method according to any one of claims 1 to 7.

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