Electronic device element manufacturing method, related element, electronic device, and electronic apparatus

Abstract

Embodiments of the present disclosure relate to electronic device element manufacturing methods, related elements, electronic devices, and electronic apparatuses. A method of fabricating an anchoring element of a passivation layer includes forming a first implant region having a first maximum dimension along a first axis in a semiconductor body made of SiC and at a distance from a top surface of the semiconductor body; forming a second implant region in the semiconductor body, the second implant region overlapping the first implant region and having a second maximum dimension along the first axis that is less than the first maximum dimension; performing a thermal oxidation process of the first implant region and the second implant region to form an oxidation region; removing the oxidation region to form a cavity; and forming the passivation layer on the top surface to protrude into the cavity to form the anchoring element that secures the passivation layer to the semiconductor body.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a manufacturing method of an anchoring element of an electronic device, an anchoring element, an electronic device and an electronic apparatus. The present disclosure relates to an anchoring element suitable to improve the reliability of silicon carbide (SiC) electronic power devices during thermal cycling tests. BACKGROUND

[0002] As is known, semiconductor materials (having a wide band gap (for example with an energy value E g of greater than 1.1 eV), a low on-state resistance (R ON ), a high thermal conductivity value, a high operating frequency and a high saturation speed of the charge carriers) are used for the production of electronic components, such as diodes or transistors, in particular for power applications. A material having such characteristics and designed for the manufacture of electronic components is silicon carbide (SiC). In particular, silicon carbide in various polytypes (for example 3C-SiC, 4H-SiC, 6H-SiC) is superior to silicon in terms of the previously listed properties.

[0003] Electronic devices arranged on a silicon carbide substrate have numerous advantages, such as low on-state output resistance, low leakage current, high output power, high operating temperature and high operating frequency, compared to similar devices arranged on a silicon substrate.

[0004] However, the development and manufacture of SiC-based electronic devices are limited by factors such as the electrical and mechanical properties of the passivation layer (included in the electronic device and which, for example, extends above the SiC semiconductor body of the electronic device). In particular, it is known to provide the passivation layer using a polymeric material (for example polyimide), which makes it possible to withstand the high operating temperature of the electronic device and has a high dielectric strength, for example higher than 400 kV / mm. In detail, the high dielectric strength of the polymeric material guarantees that the passivation layer will withstand high electric fields and, therefore, high potential differences therebetween, without electrical breakdown occurring and, therefore, without becoming conductive.

[0005] However, polymeric materials have a high coefficient of thermal expansion (CTE) (for example, for the material polybenzoxazole— PIX, CTE = 43 e -6 1 / K) and this causes adhesion problems of the passivation layer with SiC, which has a lower coefficient of thermal expansion (CTE = 3.8 e-6 1 / K).

[0006] In particular, the above-mentioned adhesion problems between the passivation layer and the SiC can arise during thermal cycling tests (for example carried out between about -50°C and about +150°C) or during the use of the electronic device, when the SiC is subjected to large temperature variations (for example, it is subjected to operating temperature differences equal to or greater than about 200°C). Due to the large difference in CTE between the passivation layer and the SiC, said large temperature variations generate mechanical stresses at the interface between the passivation layer and the SiC, which can cause (at least partial) delamination of the passivation layer with respect to the SiC semiconductor body.

[0007] In the case where said delamination is sufficiently extensive (for example, in such a way that there is no longer any portion of the passivation layer interposed between the two metallizations of the electronic device at different electrical potentials, so that these metallizations are separated from each other only by air), discharges can be generated at the interface, causing damage to the electronic device itself. In particular, when the electronic device is used in the case of reverse bias, the risk of damaging the electronic device increases due to the high voltage differences (for example greater than 1000 V) to be withstood.

[0008] Known solutions to the above-mentioned problems include the use of dielectric layers of a plurality of materials different from each other (for example, silicon nitride, silicon oxide and polyimide in succession) to form a passivation multilayer suitable for limiting the mechanical stresses at the interface with the SiC semiconductor body. However, these solutions prove to be ineffective when the electronic device is subjected to large temperature variations and high voltage differences in the case of reverse bias. SUMMARY

[0009] The present disclosure provides a manufacturing method of an anchoring element of an electronic device, an anchoring element, an electronic device and an electronic apparatus that overcome the drawbacks of the prior art.

[0010] In at least one embodiment of the present disclosure, an apparatus includes a semiconductor body including silicon carbide (SiC). A passivation layer extends over a first surface of the semiconductor body and has a first anchoring element protruding at the first surface into a first cavity in the semiconductor body. The first anchoring element secures the passivation layer to the semiconductor body, the first anchoring element including a first portion at a first distance from the first surface in the semiconductor body in a first direction transverse to the first surface and having a first maximum dimension in a second direction transverse to the first direction, and a second portion overlapping the first portion, extending from the first surface to the first portion in the semiconductor body, and having a second maximum dimension in the second direction and smaller than the first dimension, the second portion being closer to the first surface than the first portion.

[0011] In at least one embodiment of the disclosure, a device comprises a semiconductor body. A first anchoring element, a passivation layer protruding into a first surface of the semiconductor body, the passivation layer extending over the first surface of the semiconductor body and into a first cavity in the semiconductor body and the first surface. The first anchoring element comprises: a first portion at a first distance from the first surface in a first direction transverse to the first surface in the semiconductor body, and the first portion has a first dimension in a second direction transverse to the first direction; and a second portion overlapping the first portion, extending from the first surface to the first portion in the first direction in the semiconductor body, and having a second dimension in the second direction smaller than the first dimension, the second portion being closer to the first surface than the first portion, wherein the first anchoring element fixes the passivation layer to the semiconductor body. BRIEF DESCRIPTION OF DRAWINGS

[0012] For a better understanding of the present disclosure, preferred embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings in which:

[0013] Figure 1 and Figure 2 shows a cross-sectional view of an electronic device according to respective embodiments of the disclosure;

[0014] Figure 3A and Figure 3B shows a top view of an electronic device according to respective embodiments of the disclosure Figure 1 ; and

[0015] Figures 4A to 4H shows respective manufacturing steps of an electronic device according to embodiments of the disclosure Figure 1 in a cross-sectional view. DETAILED DESCRIPTION

[0016] Elements common to the various embodiments of the disclosure described hereinafter are indicated with the same reference numerals.

[0017] Figure 1 An electronic device 50 (in detail, a merged PiN- Schottky, MPS device or junction barrier Schottky, JBS device) according to aspects of the disclosure is shown in a lateral cross-sectional view in a (three-axial) Cartesian reference system of axes X, Y, Z. In particular, the MPS device 50 is shown in Figure 1 the plane XZ defined by the axes X and Z, and is comprised in an electronic apparatus (not shown, such as a notebook, a mobile phone, a photovoltaic system, a traction inverter for an electric car, etc.).

[0018] The MPS device 50 comprises: a substrate 53 of N-type SiC, having a first doping concentration, provided with a surface 53a opposite a surface 53b, and having a thickness comprised, for example, between 50 and 350 pm, more particularly between 160 and 200 pm, for example 180 pm, between the surface 53a and the surface 53b; a drift layer 52 of N-type SiC (grown in epitaxial manner), having a second doping concentration lower than the first doping concentration and having a top surface 52a and a bottom surface 52b opposite each other, the drift layer 52 extending over the surface 53a of the substrate 53 (in detail, the surfaces 53a and 52b are in contact with each other) and having a thickness comprised, for example, between 5 and 15 pm, between the surfaces 52a and 52b; an ohmic contact region or layer 56 (for example with nickel silicide), which extends on and along the surface 53b of the substrate 53; a cathode metallization 57, for example of Ti / NiV / Ag or Ti / NiV / Au, which extends on and along the ohmic contact region 56; at least one P-type doped region 59' in the drift layer 52, exposed from the top surface 52a of the drift layer 52 and for each doped region 59' a respective ohmic contact (not shown and of known type; for example, each ohmic contact extends in depth along the axis Z for a depth comprised between 1 nanometer and tens of nanometers, measured from the top surface 52a, so as to physically isolate the doped region 59' from the drift layer 52), so that each doped region 59' will form a respective junction barrier (JB) element 59 with the drift layer 52; an edge termination region or guard ring 60, in particular a further doped region of P-type, which extends in the drift layer 52 and completely surrounds (parallel to the plane XY defined by the axes X and Y) the JB elements 59, the drift layer being exposed from and at the top surface 52a of the drift layer 52; an insulating layer 61 (optional), which extends over the top surface 52a of the drift layer 52 so as to completely surround (parallel to the plane XY) the JB elements 59 and so as to at least partially overlap the guard ring 60; an anode metallization 58, for example of Ti / AlSiCu or Ni / AlSiCu, which extends over a first portion of the top surface 52a, delimited externally by the insulating layer 61, and which in addition optionally extends partially over the insulating layer 61; and a passivation layer 69 of polymeric material (such as polyimide, for example PIX), which extends over the anode metallization 58, over the insulating layer 61 and over a second portion of the top surface 52a, which is not aligned with the anode metallization 58 or with the insulating layer 61.

[0019] One or more Schottky diodes 62 are formed at the interface between the drift layer 52 and the anode metallization 58, alongside the doped regions 59'. In particular, a (semiconductor-metal) Schottky junction is formed by the portion of the drift layer 52 that is in direct electrical contact with the corresponding portion of the anode metallization 58.

[0020] Additionally, each ohmic contact extending in a respective doped region 59' provides an electrical connection having a resistivity value lower than the resistivity value of the doped region 59' hosting each ohmic contact. Thus, the JB element 59 is a P-i-N diode formed by the doped regions 59', by the drift layer 52 and by the substrate 53.

[0021] The region of the MPS device 50 comprising the JB element 59 and the Schottky diodes 62, i.e. the region externally delimited by the guard ring 60, is the active area 54 of the MPS device 50.

[0022] The substrate 53 and the drift layer 52 form a semiconductor body 80 of the MPS device 50.

[0023] Outside the active area 54, and at a distance (along the axis X) from the insulating layer 61, there is a lateral surface 80a of the semiconductor body 80, which extends, for example, in a direction substantially transversal (e.g. orthogonal) to the top surface 52a of the drift layer 52. The lateral surface 80a is provided during the manufacturing of the MPS device 50, in particular during the cutting of the SiC wafer in which the MPS device 50 is provided. In other words, the lateral surface 80a is arranged at the scribe line (not shown) of the SiC wafer in which the MPS device 50 is made; said scribe line encloses the active area 54, the guard ring 60 and the insulating layer 61 at a distance in the XY plane.

[0024] Furthermore, the passivation layer 69 has an anchoring element 82 that protrudes and extends into the drift layer 52, beyond the top surface 52a, so as to anchor and fix the passivation layer 69 to the semiconductor body 80.

[0025] Parallel to the axis X, the anchoring element 82 is interposed between the active area 54 and the lateral surface 80a (more in detail, between the insulating layer 61 and the lateral surface 80a).

[0026] The anchoring element 82 is shaped so as to fix the passivation layer 69 to the semiconductor body 80 (in particular, to the drift layer 52) and is adapted to prevent delamination and separation of the passivation layer 69 with respect to the semiconductor body 80 at the active area 54.

[0027] In particular, the anchoring element 82 is housed and arranged by interlocking into a cavity 83 which extends in the drift layer 52 starting from the top surface 52a, so as to couple and jointly fix the passivation layer 69 and the semiconductor body 80 to each other. The cavity 83 is externally delimited by a wall portion 83a of the drift layer 52, which has a shape complementary to that of the anchoring element 82.

[0028] In particular, the anchoring element 82 comprises a plurality of portions (in particular, Figure 1 a first portion 82a and a second portion 82b) which are arranged in succession with respect to each other along the axis Z and have respective dimensions which are measured parallel to the axis X, which increase in a direction away from the top surface 52a (and therefore towards the bottom surface 52b).

[0029] In detail, with reference to the embodiment of Figure 1 , the passivation layer 69 comprises a main body 69' (extending above the top surface 52a of the drift layer 52, above the insulating layer 61 and above the anodic metallization 58) and the anchoring element 82 (extending in the drift layer 52). Parallel to the axis Z, said second portion 82b is interposed between the main body 69' of the passivation layer 69 and the first connecting portion 82a. In other words, the first portion 82a is at a distance (measured parallel to the axis Z starting from the centroid of the first portion 82a) from the bottom surface 52b of the drift layer 52 which is less than the distance (measured parallel to the axis Z starting from the respective centroid of the second portion 82b) of the second portion 82b from said bottom surface 52b. In other words, the second portion 82b is closer to the surface 52b with respect to the first portion 82a. The first portion 82a has a first maximum dimension, measured parallel to the axis X and having a first value dl, and the second portion 82b has a second maximum dimension, measured parallel to the axis X and having a second value d2 which is less than the first value dl. In detail, the first value dl is measured parallel to the axis X between a surface 82a' and a surface 82a" of the first portion 82a opposite each other along the axis X, and the second value d2 is measured parallel to the axis X between a surface 82b' and a surface 82b" of the second portion 82b opposite each other along the axis X.

[0030] In Figure 1In particular, the first and second portions 82a, 82b each have a substantially rectangular shape (alternatively, each have a polygonal shape, such as an elliptical shape) in the plane XZ, with respective long sides arranged parallel to the axis X, and with respective short sides (i.e. the surfaces 82a', 82a", 82b', 82b") arranged parallel to the axis Z; the two rectangular shapes are joined together at two of said long sides (more in detail, the first portion 82a is joined together with the second portion 82b between one long side of the first portion 82a and one long side of the second portion 82b, which long sides face each other and are in contact with each other). In other words, the anchoring element 82 is substantially T-shaped, with a small base facing the top surface 52a and a large base facing the bottom surface 52b.

[0031] According to Figure 2 different embodiments of the MPS device 50 shown in Figs. 1-3, the anchoring element 82 has more portions than the anchoring element 82 shown in Figs. 4-6. Figure 1 In particular, the anchoring element has four portions 82c-82f in Fig. 7. Figure 2 The portions 82c-82f are similar to the portions 82a, 82b and have a dimension d3-d6 measured parallel to the axis X, respectively, with d3>d4>d5>d6. In other words, the anchoring element 82 has a substantially pyramidal shape (in particular, a shape of a stepped truncated pyramid) and a small base facing the top surface 52a and a large base facing the bottom surface 52b.

[0032] Additionally, optionally, the MPS device 50 comprises an equipotential ring (EQR) metallization 75 (shown by way of example in Fig. 6) which extends over the insulating layer 61 and optionally over the top surface 52a so as to oppose the anode metallization 58 parallel to the axis X with respect to the insulating layer 61. In detail, in Fig. 6, the insulating layer 61 has surfaces 61a and 61b opposite each other in a direction parallel to the axis X; the anode metallization 58 extends from the surface 61a and the EQR metallization 75 extends from the surface 61b. For example, in a top view and parallel to the plane XY, the EQR metallization 75 extends outwardly to the insulating layer 61 and the active area 54 so as to enclose the insulating layer 61. Additionally, the EQR metallization 75 and the anode metallization 58 are physically and electrically separated from each other by the passivation layer 69. In use, the EQR metallization 75 is set at the same voltage as the cathode metallization 57. Figure 2 Figure 2

[0033] Figure 3A and Figure 3B MPS devices 50 according to respective embodiments are shown in a top view (parallel to the plane XY).

[0034] Reference is made to Figure 3A ​​The anchoring element 82 extends in the plane XY to completely surround the anodized metallization 58. Figure 3A In the XY plane view, the anchoring element 82 is annular and defines a closed polygonal shape and more specifically a square shape with chamfers (although different shapes are possible, such as circles, rectangles or triangles).

[0035] refer to Figure 3B The MPS device 50 includes at least one other anchoring element (similar to anchoring element 82 and therefore indicated by the same reference numerals). Anchoring element 82 and at least one other anchoring element 82 extend at a distance from each other on the top surface 52a, i.e., they extend separately from each other in corresponding regions of the top surface 52a. For example, Figure 3B The XY plane view shows four anchoring elements 82 arranged around the anodized metallization 58 so as to be angularly equidistant from the anodized metallization 58, and more specifically arranged at the corners of a square having the chamfer of the anodized metallization 58.

[0036] The following text is for reference only. Figures 4A to 4H Described Figure 1 The manufacturing steps of MPS equipment 50.

[0037] refer to Figure 4A The wafer is arranged as a substrate 53 comprising SiC (specifically, 4H-SiC, however other polymorphs may be used, such as, but not exclusively, 2H-SiC, 3C-SiC, and 6H-SiC). For example, the substrate 53 has a 1.10 19 at / cm 3 With 1.10 22 at / cm 3 The N-type dopant concentration included between surfaces 53a and 53b, and having a thickness measured along the Z-axis between surfaces 53a and 53b, is between 300 μm and 450 μm, specifically approximately 360 μm. A drift layer 52 is formed, for example, on surface 53a of substrate 53 by epitaxial growth. The drift layer 52 is SiC, specifically 4H-SiC, but other SiC polytypes such as 2H, 6H, 3C, or 15R can also be used. The drift layer 52 and substrate 53 form a semiconductor body 80. A doped region 59′ and a guard ring 60 with corresponding ohmic contacts are then formed in the drift layer 52 according to known techniques and at the top surface 52a. Additionally, a first hard mask 71 is formed on the top surface 52a of the drift layer 52, for example, by depositing photoresist or tetraethoxysilane (TEOS) or another material designed for this purpose. The first hard mask 71 has a thickness between 0.5 μm and 2 μm, or in any case, to shield the references below. Figure 4BThe described injection thickness. A first hard mask 71 extends above the top surface 52a to expose a first region 71' of the semiconductor body 80 in a top view in the XY plane, in which an anchoring element 82 will be formed in a subsequent step. Specifically, parallel to the Z axis, the first region 71' overlaps with a region of the drift layer 52, in which a first portion 82a of the anchoring element 82 will be formed in that region of the drift layer 52 in a subsequent step. The first region 71' extends parallel to the X axis between the guard ring 60 and the lateral surface 80a of the semiconductor body 80, and the first region 71' has a first maximum width l1 measured parallel to the X axis, which is equal to or approximately equal to a first value d1.

[0038] refer to Figure 4B Then, a high-energy implantation step of the dopant (having P- or N-type conductivity, such as boron, arsenic, or aluminum) is performed using a first hard mask 71 (implantation is indicated by arrow 70 in the figures). In the embodiment provided by way of example, the implantation step 70 includes using an implantation energy ranging from 200 keV to 500 keV and using an implantation energy of 1.10 keV. 12 at / cm 2 With 1.10 16 at / cm 2 One or more dopants are implanted at doses between 1.10 to form a first implantation region 84, the first implantation region having a dopant concentration greater than 1.10. 18 at / cm 3 The dopant concentration is set at a certain value, and the depth is between 0.4 μm and 1 μm, measured from the top surface 52a. Therefore, the first implantation region 84 extends in depth into the drift layer 52 at a distance from the top surface 52a (parallel to the Z-axis). The first hard mask 71 is then removed, leaving the exposed top surface 52a.

[0039] refer to Figure 4C A second hard mask 72 is formed on the top surface 52a of the drift layer 52, for example by depositing photoresist or TEOS, or another material designed for this purpose. The second hard mask 72 has a thickness between 0.5 μm and 2 μm or, in any case, to shield the area referred to below. Figure 4D The described injection thickness. A second hard mask 72 extends above the top surface 52a to expose a second region 72' of the semiconductor body 80 in a top view in the XY plane, in which a second portion 82b of the anchoring element 82 will be formed in a subsequent step. The second region 72' overlaps with the first injection region 84 parallel to the Z axis and has a second maximum width l2 measured in a direction parallel to the X axis, which is less than the first width l1 and equal to or approximately equal to a second value d2.

[0040] refer toFigure 4D Then, a low-energy implantation step of the doped material (having the same conductivity as in implantation step 70) is performed using a second hard mask 72 (implantation is indicated by arrow 73 in the diagram). In the embodiment provided by way of example, implantation step 73 includes using implantation energies ranging from 30 keV to 200 keV and using energies ranging from 1.10 keV to 1.10 keV. 12 at / cm 2 With 1.10 16 at / cm 2 One or more dopants of a dose between 1.10 are implanted to form a second implantation region 85 at the top surface 52a, the second implantation region having a dopant concentration higher than 1.10. 18 at / cm 3 The dopant concentration is specified and the maximum depth, measured from the top surface 52a, is between 0.4 μm and 1 μm. Therefore, the second injection region 85 extends from the top surface 52a until it reaches the first injection region 84; thus, the first injection region 84 and the second injection region 85 combine to form an injection anchoring region 86 having the same shape as the anchoring element 82.

[0041] refer to Figure 4E At the second hard mask 72 and the implantation anchor region 84, a thermal oxidation step is performed to oxidize the implantation anchor region 86, converting the implantation anchor region 86 into silicon oxide (SiO2) and forming a corresponding oxide anchor region 86′ that coincides with the implantation anchor region 86. In fact, it has been shown that the more the oxidation rate of SiC increases, the more the SiC lattice is damaged, for example, by the implantation of dopant.

[0042] Therefore, the injection anchoring region 86 is oxidized during the oxidation step, while the drift layer 52 (which is further protected due to the presence of the second hard mask 72) is essentially not oxidized. The thermal oxidation step is performed, for example, at a temperature of 1000°C or higher (e.g., between 1150°C and 1250°C) for a time between 60 and 300 minutes.

[0043] In addition, refer to Figure 4E Etching (not shown) of the second hard mask 72 is performed to selectively remove a portion of the second hard mask 72 to expose the active region 54. Specifically, the etching exposes a portion of the top surface 52a defined externally by the guard ring 60 in the XY plane (i.e., the portion of the top surface 52a including the doped region 59′ and the portion of the guard ring 60, hereinafter referred to as the first portion 87) and at least partially exposes the guard ring 60.

[0044] refer to Figure 4F Anode metallization 58 is formed through Figure 4Eon a first portion 87 of the top surface 52a exposed by the etching of the second hard mask 72 and on a portion of the second hard mask 72. Thus, the anodic metallization 58 contacts the doped region 59' (through a respective ohmic contact) and the drift layer 52 so as to form, respectively, the JB element 59 and the Schottky diode 62; moreover, the anodic metallization 58 extends over the portion of the protective ring 60 exposed by the etching of the second hard mask 72 and over the second hard mask 72 at the protective ring 60. For example, the anodic metallization 58 is formed by deposition of Ti / AlSiCu or Ni / AlSiCu. Figure 4E on a first portion 87 of the top surface 52a exposed by the etching of the second hard mask 72 and on a portion of the second hard mask 72. Thus, the anodic metallization 58 contacts the doped region 59' (through a respective ohmic contact) and the drift layer 52 so as to form, respectively, the JB element 59 and the Schottky diode 62; moreover, the anodic metallization 58 extends over the portion of the protective ring 60 exposed by the etching of the second hard mask 72 and over the second hard mask 72 at the protective ring 60. For example, the anodic metallization 58 is formed by deposition of Ti / AlSiCu or Ni / AlSiCu.

[0045] With reference to Figure 4G A further etching (not shown) of the second hard mask 72 is carried out to remove a further portion of the second hard mask 72 (placed at the oxide anchoring region 86' and, moreover, extending between the oxide anchoring region 86' and the lateral surface 80a of the semiconductor body 80) and the oxide anchoring region 86' so as to form the cavity 83. In detail, the wall 83a of the drift layer 52 (exposed by etching due to the removal of the oxide anchoring region 86' and delimiting the cavity 83) has a shape complementary to that of the oxide anchoring region 86' and, therefore, to that of the anchoring element 82. Additionally, the portion of the second hard mask 72 not removed by said etching forms said insulating layer 61 of the MPS device 50. Figure 4G The etching of the oxide anchoring region 86' is of the isotropic type and is carried out with hydrofluoric acid - HF.

[0046] With reference to Figure 4H Then, the passivation layer 69 is formed: a polymeric material is applied on the semiconductor body 80 and is distributed by spinning over the anodic metallization 58, the insulating layer 61 and the exposed portions of the drift layer 52, and a thermal treatment is subsequently carried out, which will cause the polymeric material to harden to form the passivation layer 69 (curing process). In particular, during the spinning step, the polymeric material penetrates into the cavity 83 and fills it, thus forming the anchoring element 82.

[0047] Next, a grinding (not shown) step of the substrate 53 is carried out on the surface 53b so as to reduce the thickness of the substrate 53. For example, at the end of the grinding step, the substrate 53 has a thickness, measured along the axis Z between the surface 53a and the surface 53b, comprised between 100 pm and 250 pm and, in particular, of about 180 pm. The ohmic contact layer 56 starting from the surface 53b of the substrate 53 and the cathodic metallization 57 starting from the ohmic contact layer 56 are then formed according to known techniques and consecutively with respect to each other, thus obtaining the MPS device 50 shown in Figure 1 in Figure 1.

[0048] The advantages provided by the present disclosure are evident from the inspection of the features of the present disclosure provided according to the present disclosure.

[0049] In particular, the anchoring element 82 guarantees the adhesion of the passivation layer 69 to the semiconductor body 80. In this way, the passivation layer 69 can be made with a polymeric material, thus guaranteeing a high level of electrical performance of the electronic device 50 (due to the high dielectric strength of the passivation layer 69) and, at the same time, eliminating the risk of delamination of the passivation layer 69 after thermal cycles or use of the electronic device 50.

[0050] Therefore, the risk of damaging the electronic device 50 after a discharge between metallizations set at different potentials (for example between the EQR metallization 75 and the anode metallization 58) is prevented, and therefore the reliability of the electronic device 50 is increased, in particular when the electronic device is subjected to high temperature variations and operates in reverse bias conditions.

[0051] In particular, with reference to Figures 4A to 4H The manufacturing steps described make it possible to provide an electronic device 50 comprising an anchoring element 82 starting from a SiC wafer.

[0052] Additionally, with reference to Figure 4G The etching carried out is of the isotropic type and this case makes it possible to pattern the cavity 83 and the anchoring element 82 without any limitations from the anisotropic etching process and from the crystal orientation of the SiC wafer from which the electronic device 50 is obtained.

[0053] Finally, it is clear that modifications and changes can be made to the disclosure described and illustrated herein, without departing from the scope of the present disclosure.

[0054] In particular, even if reference has been made to Figure 2 The EQR metallization 75 has been described, which can equally exist in the embodiment of the MPS device 50 illustrated in Figure 1 In particular, the anchoring element 82 is arranged on the outside of the extension area of the power device (for example on the outside of the active area 54 in the plane XY) so as to guarantee the adhesion of the passivation layer 69 at the power device.

[0055] Additionally, the SiC-based electronic device 50 can not be of the MPS type as previously described; in particular, it can comprise at least one of the following: a Schottky diode, a PN diode, a SiC-based MOSFET, a SiC-based IGBT and a SiC-based power electronic element. The anchoring element 82 is arranged on the outside of the extension area of the power device (for example on the outside of the active area 54 in the plane XY) so as to guarantee the adhesion of the passivation layer 69 at the power device.

[0056] A method of manufacturing an anchoring element (82) of a passivation layer (69) of an electronic device (50) can be summarized as comprising: arranging a semiconductor body (80) of silicon carbide, SiC; forming, in the semiconductor body (80) and at a distance from a top surface (52a) of the semiconductor body (80), a first implantation region (84) having a maximum dimension parallel to a first axis (X) having a first value (dl); forming, in the semiconductor body (80), a second implantation region (85) overlapped to the first implantation region (84) parallel to a second axis (Z) orthogonal to the first axis (X), extending from the top surface (52a) to the first implantation region (84) and having a respective maximum dimension parallel to the first axis (X) having a second value (d2) smaller than the first value (dl); carrying out a thermal oxidation process of the first implantation region (84) and of the second implantation region (85) to form an oxidation region (86') at the first implantation region (84) and at the second implantation region (85); removing said oxidation region (86') to form a cavity (83) in the semiconductor body (80) and at the oxidation region (86'); and forming, on the top surface (52a), a passivation layer (69) protruding into the cavity (83) to form said anchoring element (82) fixing the passivation layer (69) to the semiconductor body (80).

[0057] The step of forming the first implantation region (84) can comprise: forming, at the top surface (52a) of the semiconductor body (80), a first hard mask (71) exposing a first region (71') of the top surface (52a), the first region (71') having a first maximum width (ll) parallel to the first axis (X); and carrying out, in the semiconductor body (80) at said first region (71'), a first implantation of a dopant species so as to form the first implantation region (84).

[0058] The step of carrying out the first implantation can comprise carrying out one or more implantations of said dopant species at an implantation energy comprised between 200 keV and 500 keV and at a dose comprised between 1 · 1014 at / cm2 and 1 · 1016 at / cm2. 12 at / cm 2 and 1 · 1016 at / cm2. 16 at / cm 2 The step of carrying out the first implantation can comprise carrying out one or more implantations of said dopant species at an implantation energy comprised between 200 keV and 500 keV and at a dose comprised between 1 · 1014 at / cm2 and 1 · 1016 at / cm2.

[0059] The step of forming the second implanted region (85) can comprise forming a second hard mask (72) of a second region (72') of the top surface (52a) of the semiconductor body (80) exposed by the top surface (52a), the second region (72') being overlapped to the first implanted region (84) parallel to the second axis (Z) and having a second maximum width (12) parallel to the first axis (X) smaller than the first maximum width (11); and carrying out a second implant of a dopant species in the semiconductor body (80) at said second region (72') so as to form the second implanted region (85).

[0060] The step of carrying out the second implant can comprise carrying out one or more further implants of the dopant species at an implant energy comprised between 30 keV and 200 keV and at a dose comprised between 1 · 1012 at / cm2 and 1 · 1014 at / cm2. 12 at / cm2 2 at / cm2 16 at / cm2 2 The step of carrying out the second implant can comprise carrying out one or more further implants of the dopant species at an implant energy comprised between 30 keV and 200 keV and at a dose comprised between 1 · 1012 at / cm2 and 1 · 1014 at / cm2.

[0061] The step of removing the oxidation region (86') can comprise carrying out an isotropic etching of the oxidation region (86').

[0062] The manufacturing method can further comprise forming at least one third implanted region (82c; 82d) in the semiconductor body (80) and at a distance from the top surface (52a) so that the first implanted region (84) and the second implanted region (85) are interposed between the at least one third implanted region (82c; 82d) and the top surface (52a) parallel to the second axis (Z) and so that the first implanted region (84) is in contact with the at least one third implanted region (82c; 82d), the at least one third implanted region having a respective maximum dimension parallel to the first axis (X) having a third value (d3; d4) greater than the first value (dl) and the second value (d2).

[0063] The step of carrying out the thermal oxidation process can comprise thermally oxidizing the first implanted region (84), the second implanted region (85) and the at least one third implanted region (82c; 82d) to form an oxidation region (86') at the first implanted region (84), the second implanted region (85) and the at least one third implanted region (82c; 82d).

[0064] The step of forming the passivation layer (69) can comprise depositing a polymeric material on the top surface (52a).

[0065] An anchoring element (82) of a passivation layer (69) of an electronic device (50) comprising a semiconductor body (80) of silicon carbide, SiC, and said passivation layer (69) extending on a top surface (52a) of the semiconductor body (80) and protruding at the top surface (52a) into a cavity (83) of the semiconductor body (80) to form said anchoring element (82), which can be summarized as comprising: a first portion (82a) extending in the semiconductor body (80) at a distance from the top surface (52a) and having a maximum dimension parallel to a first axis (X) having a first value (dl); and a second portion (82b) overlapped to the first portion (82a) parallel to a second axis (Z) orthogonal to the first axis (X), extending in the semiconductor body (80) from the top surface (52a) to the first portion (82a) and having a respective maximum dimension parallel to the first axis (X) having a second value (d2) smaller than the first value (dl), so that the anchoring element (82) fixes the passivation layer (69) to the semiconductor body (80).

[0066] The anchoring element (82) can further comprise at least one third implantation region (82c; 82d) extending in the semiconductor body (80) and at a distance from the top surface (52a), so that the first implantation region (84) and the second implantation region (85) are interposed parallel to the second axis (Z) between the at least one third implantation region (82c; 82d) and the top surface (52a), and so that the first implantation region (84) is in contact with the at least one third implantation region (82c; 82d) having a respective maximum dimension parallel to the first axis (X) having a third value (d3; d4) greater than the first value (dl) and the second value (d2).

[0067] The annular type can be at the top surface (52a) of the semiconductor body (80) and define a closed polygonal shape.

[0068] The passivation layer (69) can protrude at the top surface (52a) into at least one other cavity (83) of the semiconductor body (80) to form for each other cavity (83) a respective other anchoring element (82) that fixes the passivation layer (69) to the semiconductor body (80) and can comprise: a further first portion (82a) extending in the semiconductor body (80) at a distance from the top surface (52a) and having a respective maximum dimension parallel to the first axis (X) having a first value (dl); and a further second portion (82b) overlapped to the further first portion (82a) parallel to a second axis (Z) extending in the semiconductor body (80) from the top surface (52a) to the further first portion (82a) and having a respective maximum dimension parallel to the first axis (X) having a second value (d2) smaller than the first value (dl), and wherein the anchoring element (82) and the at least one other anchoring element (82) extend at a distance from each other at the top surface (52a) of the semiconductor body (80).

[0069] The electronic device (50) can be summarized as comprising a semiconductor body (80) of silicon carbide (SiC) and a passivation layer (69) extending over a top surface (52a) of the semiconductor body (80) and protruding at the top surface (52a) into a cavity (83) of the semiconductor body (80) to form an anchoring element (82) that fixes the passivation layer (69) to the semiconductor body (80), the anchoring element (82) comprising: a first portion (82a) extending in the semiconductor body (80) at a distance from the top surface (52a) and having a maximum dimension parallel to a first axis (X) having a first value (dl); and a second portion (82b) overlapped to the first portion (82a) parallel to a second axis (Z) orthogonal to the first axis (X), extending in the semiconductor body (80) from the top surface (52a) to the first portion (82a) and having a respective maximum dimension parallel to the first axis (X) having a second value (d2) smaller than the first value (dl).

[0070] The cavity (83) can be externally delimited by a wall portion (83a) of the semiconductor body (80) having a shape complementary to that of the anchoring element (82) so that the anchoring element (82) can be fixed by interlocking in the semiconductor body (80) at the cavity (83).

[0071] The merged PiN- Schottky MPS type, wherein the semiconductor body (80) can comprise: a SiC substrate (53) having a first conductivity; and a SiC drift layer (52) extending over the substrate (53) and having the first conductivity, and the top surface (52a) being opposite the substrate (53), the electronic device (50) further comprising: at least one first doped region (59') having a second conductivity opposite the first conductivity and extending in the drift layer (52) and at the top surface (52a) of the drift layer (52) so as to form at least one respective junction barrier (JB) diode (59) with the drift layer (52); a first electrical terminal (58) in ohmic contact with a respective first surface (59a) of the at least one first doped region (59'), coplanar with the top surface (52a) of the drift layer (52), and further in direct electrical contact with the top surface (52a) of the drift layer (52) alongside the first doped region (59') so as to form a Schottky diode (62) with the drift layer (52); and a second electrical terminal (57, 56) in ohmic contact with a backside (53b) of the substrate (53), opposite the drift layer (52), wherein the JB diodes (59) and the Schottky diodes (62) alternate with each other along a first axis (X) at the first electrical terminal (58).

[0072] The anchoring element (82) can be of the ring type at the top surface (52a) of the semiconductor body (80), can define a closed polygonal shape, and can enclose the first electrical terminal (58).

[0073] The passivation layer (69) can project in at least one other cavity (83) of the semiconductor body (80) at the top surface (52a) to form, for each other cavity (83), a respective other anchoring element (82) fixing the passivation layer (69) to the semiconductor body (80) and can comprise: a further first portion (82a) extending in the semiconductor body (80) and at a distance from the top surface (52a) and having a respective maximum dimension parallel to the first axis (X) having a first value (dl); and a further second portion (82b) overlapped to the further first portion (82a) parallel to the second axis (Z), extending in the semiconductor body (80) from the top surface (52a) to the further first portion (82a) and having a respective maximum dimension parallel to the first axis (X) having a second value (d2), wherein the anchoring element (82) and the at least one other anchoring element (82) extend at a distance from each other at the top surface (52a) of the semiconductor body (80).

[0074] The electronic device (50) can comprise at least one of: a Schottky diode; a PN diode; a SiC-based MOSFET; and a SiC-based IGBT.

[0075] The electronic device can include an electronic apparatus (50).

[0076] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications, and publications to provide yet further embodiments.

[0077] These and other changes can be made to the embodiments in light of the above detailed description. In general, the selected terms employed in the following claims are not to be construed as limiting the claims to the specific embodiments that can be described in the specification and claims. Rather, the terms are to be construed as encompassing all embodiments falling within the scope of the claims and their equivalents. Accordingly, the claims are not limited to the above disclosure.

Claims

1. A method comprising: forming a first implant region in a semiconductor body at a first distance from a first surface of the semiconductor body in a first direction transverse to the first surface, the first implant region having a first dimension in a second direction transverse to the first direction; forming a second implant region in the semiconductor body, the second implant region overlapping the first implant region, extending from the first surface to the first implant region, and the second implant region having a second dimension in the second direction and smaller than the first dimension; forming an oxide region at the first implant region and the second implant region by performing thermal oxidation on the first implant region and the second implant region; forming a cavity by removing the oxide region in the semiconductor body; and forming a passivation layer on the first surface in the cavity, an anchoring element of the passivation layer securing the passivation layer to the semiconductor body.

2. The method of claim 1, wherein forming the first implant region comprises: forming a first hard mask at the first surface of the semiconductor body exposing a first region of the first surface, the first region having a third dimension in the second direction; and forming the first implant region by performing a first implant of a dopant species in the semiconductor body at the first region.

3. The method of claim 2, wherein performing the first injection comprises: at / cm 12 at / cm 2 at / cm 16 at / cm 2 one or more implants of the dopant species are performed at an implant energy comprised between 200 keV and 500 keV and at a dose comprised between 1 · 1013 at / cm2and 1 · 1015 at / cm2.

4. The method of claim 2, wherein forming the second implant region comprises: forming a second hard mask at the first surface of the semiconductor body exposing a second region of the first surface, the second region overlapping the first implant region, and the second region having a fourth dimension in the second direction and smaller than the third dimension; and forming the second implant region by performing a second implant of a dopant species in the semiconductor body at the second region.

5. The method of claim 4, wherein performing the second injection comprises: one or more further implants of the dopant species are performed at an implant energy comprised between 30 keV and 200 keV and at a dose comprised between 1 · 1010 12 at / cm 2 and 1 · 1012 16 at / cm 2 .

6. The method of claim 1, wherein removing the oxide region comprises performing an isotropic etch on the oxide region.

7. The method of claim 1, further comprising: forming at least one third implant region in the semiconductor body and at a second distance from the first surface such that the first implant region and the second implant region are interposed between the at least one third implant region and the top surface in the first direction, the first implant region is in contact with the at least one third implant region, and the at least one third implant region has a third dimension in the second direction greater than the first dimension and the second dimension.

8. The method of claim 7, wherein performing the thermal oxidation comprises: forming the oxide region at the first implant region, the second implant region, and the at least one third implant region by performing thermal oxidation on the first implant region, the second implant region, and the at least one third implant region.

9. The method of claim 1, wherein forming the passivation layer comprises depositing a polymeric material on the first surface.

10. An apparatus comprising: a semiconductor body; a first anchoring element of a passivation layer directly disposed on a portion of a first surface of the semiconductor body, the first anchoring element protruding at the first surface into a first cavity formed in the semiconductor body, and the first anchoring element comprising: a first portion in the semiconductor body at a first distance from the first surface in a first direction transverse to the first surface, and the first portion having a first dimension in a second direction transverse to the first direction; and a second portion overlapping the first portion, extending in the semiconductor body from the first surface to the first portion in the first direction, and the second portion having a second dimension smaller than the first dimension in the second direction, the second portion being closer to the first surface than the first portion, wherein the first anchoring element fixes the passivation layer to the semiconductor body.

11. The apparatus of claim 10, further comprising: at least one third implantation region in the semiconductor body and at a second distance from the first surface in the first direction, the first and second implantation regions being interposed between the at least one third implantation region and the first surface in the first direction, and the first implantation region being in contact with the at least one third implantation region, the at least one third implantation region having a third dimension larger than the first and second dimensions in the second direction.

12. The device of claim 10, wherein the first anchoring element is of a ring type at the first surface of the semiconductor body, and the first anchoring element defines a closed polygonal shape.

13. The apparatus of claim 10, further comprising: at least one second anchoring element of the passivation layer protruding in at least a second cavity in the semiconductor body at the first surface, the at least one second anchoring element fixing the passivation layer to the semiconductor body, and the at least one second anchoring element comprising: a third portion in the semiconductor body at the second distance from the first surface in the first direction, and the third portion having the first dimension; and a fourth portion overlapping the third portion, extending in the semiconductor body from the first surface to the third portion, and the fourth portion having the second dimension, and wherein the first anchoring element and the at least one second anchoring element are spaced apart from each other by a third distance in the second direction at the first surface of the semiconductor body.

14. A device, comprising: a semiconductor body comprising silicon carbide, SiC; and a passivation layer extending over a first surface of the semiconductor body, directly disposed on a portion of the first surface, and having a first anchoring element protruding at the first surface into a first cavity in the semiconductor body, the first anchoring element fixing the passivation layer to the semiconductor body, the first anchoring element comprising: a first portion in the semiconductor body at a first distance from the first surface in a first direction transverse to the first surface, and the first portion having a first dimension in a second direction transverse to the first direction; and a first portion at a first distance from the first surface in the semiconductor body in a first direction transverse to the first surface and having a first maximum dimension in a second direction transverse to the first direction; and a second portion overlapping the first portion, extending from the first surface to the first portion in the semiconductor body and having a second maximum dimension in the second direction and smaller than the first dimension, the second portion being closer to the first surface than the first portion.

15. The device of claim 14, wherein: the first cavity is delimited by a wall portion of the semiconductor body and has a shape complementary to a shape of the anchoring element; and the anchoring element is fixed in the semiconductor body at the cavity by interlocking.

16. The device of claim 14, wherein the semiconductor body comprises: a SiC substrate having a first conductivity; and a SiC drift layer extending over the substrate, comprising the first surface and having the first conductivity, the first surface being opposite the substrate.

17. The device of claim 16, further comprising: at least one first doped region having a second conductivity opposite the first conductivity, the at least one first doped region being in the drift layer and at the first surface of the drift layer, the at least one first doped region and the drift layer forming at least one respective junction barrier JB diode; a first electrical terminal in ohmic contact with a second surface of the at least one first doped region, the first electrical terminal comprising a third surface coplanar with the first surface of the drift layer and the first electrical terminal being in direct electrical contact with the first surface of the drift layer so as to form a Schottky diode, the first surface of the drift layer being alongside the at least one first doped region; and a second electrical terminal in ohmic contact with a backside of the substrate, opposite the drift layer, wherein the JB diode and the Schottky diode are adjacent to each other at the first electrical terminal in the second direction.

18. The device of claim 17, wherein the first anchoring element is of a ring type at the first surface of the semiconductor body, defining a closed polygonal shape and encircling the first electrical terminal.

19. The apparatus of claim 17, further comprising: at least one second anchoring element of the passivation layer protruding in at least a second cavity in the semiconductor body at the first surface, the at least one second anchoring element fixing the passivation layer to the semiconductor body.

20. The device of claim 19, wherein the second anchoring element comprises: a third portion at a second distance from the first surface in the first direction in the semiconductor body and having the first maximum dimension; and a fourth portion overlapping the third portion, extending from the first surface to the third portion in the semiconductor body and having the second maximum dimension, wherein said first and said at least one second anchoring element are spaced apart from each other by a third distance in said second direction at said first surface of said semiconductor body.

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