A method for fabricating a floating gate

Abstract

The present invention provides a method for fabricating a floating gate. A substrate is provided, and a plurality of floating gates are formed on the substrate. At least a first protective layer, an auxiliary layer, and a second protective layer are sequentially deposited on the surface of the floating gate from bottom to top, wherein the first protective layer and the second protective layer can prevent the auxiliary layer from being oxidized. And through subsequent processes, the second protective layer and the auxiliary layer in the non-treatment area on the floating gate are removed, and part or all of the auxiliary layer in the treatment area is retained. The present invention can protect TiN and the like in the auxiliary layer when the auxiliary layer such as TiN undergoes a high-temperature process, and the auxiliary layer is not easily granulated, ensuring the uniformity and stability of the produced devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for fabricating a floating gate. Background Art

[0002] Compared with the current third-generation Nor flash in the industry, super flash memory (as Figure 9 shown) has higher erasure efficiency, higher write-erase durability, higher write efficiency, faster write speed, lower write-erase voltage, lower power consumption, no read-write interference, the storage cell size is only half of that of super flash memory 1.0, the manufacturing process is simple, the test time is short, and thus the cost is greatly reduced, etc. High speed, low power consumption, and low voltage are the highlights of super flash memory technology.

[0003] Super flash memory utilizes a write operation with a horizontal electric field and an erase operation with a tip TiN without voltage coupling, which greatly improves the write-erase efficiency and reduces the operating voltage. The new structure can increase the nesting window of EG for FG and better tip control, and has better durability performance. The cell area is only 60% of that of the same-generation SF, and the number of newly added masks for embedding is only half of that of super flash memory, and can be reduced to less than 20 nm. It can cover a capacity of 4 Mb to 4 Gb and has NOR and NOVRAM functions (Internet of Things, AI, automotive electronics, etc.).

[0004] The floating gate FG TiN process is a very important process part of the device electrical properties, and has extremely high requirements for growth uniformity and stability. Especially in terms of electrical parameters, the continuity of the floating gate FG TiN process is more important. If discontinuity occurs, it will affect the electrical parameters and the normal operation of the process device. The growth and etching of each subsidiary layer of the floating gate have extremely high requirements for uniformity and stability. However, due to the easy granulation of subsidiary layers such as TiN after high-temperature processes, discontinuity occurs. The floating gate FG TiN plays a key role, so discontinuity caused during the process will affect the electrical properties and reliability. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for fabricating a floating gate, which is used to solve the problem that the TiN subsidiary layer on the floating gate is prone to oxidation granulation and discontinuity after high-temperature processes in the prior art.

[0006] To achieve the above purpose and other related purposes, the present invention provides a method for fabricating a floating gate, which at least includes:

[0007] Step 1: Provide a substrate, form an active region on the substrate, and form a plurality of floating gate structures in the active region;

[0008] Step 2: Sequentially form a first protective layer, an auxiliary layer, and a second protective layer covering the upper surface of the substrate and the multiple floating gate structures, wherein the first protective layer and the second protective layer are used to prevent the auxiliary layer from being oxidized;

[0009] Step 3: Etch all of the second protective layer and the auxiliary layer outside the floating gate structure region and a part of the second protective layer on the floating gate structure, so that the remaining auxiliary layer and the remaining second protective layer that are not etched at the active region are retained.

[0010] Preferably, the etching of the second protective layer and the auxiliary layer outside the floating gate region and on the multiple floating gates in Step 3 at least includes:

[0011] Step A: Cover a photoresist on the second protective layer, and then expose the second protective layer outside the floating gate structure through photolithography;

[0012] Step B: Etch the second protective layer to expose the auxiliary layer outside the floating gate structure, and then remove the photoresist;

[0013] Step C: Etch the auxiliary layer exposed in Step B;

[0014] Step D: Re-form a second protective layer on the surface of the auxiliary layer in Step C, and etch the second protective layer of the floating gate structure part, wherein the remaining area is the target area, so that the second protective layer at the target area is retained, and the auxiliary layer below the etched second protective layer is exposed;

[0015] Step E: Etch the auxiliary layer exposed in Step D.

[0016] Preferably, the etching of the second protective layer in Step B for the second protective layer in Step A is dry isotropic etching.

[0017] Preferably, the etching of the auxiliary layer in Step C and Step E is wet etching.

[0018] Preferably, the etching of the third protective layer of the local active region in Step D is dry anisotropic etching.

[0019] Preferably, the target area in Step D is a part or all of the bottom of the trench area and all of the side walls in the active region.

[0020] Preferably, the first protective layer is hafnium dioxide.

[0021] Preferably, the second protective layer is hafnium dioxide.

[0022] Preferably, the auxiliary layer includes TiN.

[0023] Preferably, the thickness of the auxiliary layer is 20 angstroms to 100 angstroms.

[0024] As described above, the method for manufacturing a floating gate of the present invention has the following beneficial effects: When the auxiliary layer such as TiN undergoes a high-temperature process, it can protect the TiN, and the auxiliary layer is not easily granulated, ensuring the uniformity and stability of the manufactured devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It shows a flowchart of the method for manufacturing a metal gate according to an embodiment of the present invention;

[0026] Figure 2 It shows a schematic diagram of etching a floating gate according to an embodiment of the present invention;

[0027] Figure 3 It shows a schematic diagram of forming a sandwich structure according to an embodiment of the present invention;

[0028] Figure 4 It shows an enlarged structural view of part A of the present invention;

[0029] Figure 5 It shows a schematic structural view of the present invention after removing the second protective layer in the non-processing area;

[0030] Figure 6 It shows an enlarged structural view of part B of the present invention;

[0031] Figure 7 It shows a schematic structural view of the present invention after removing the auxiliary layer in the non-processing area;

[0032] Figure 8 It shows an enlarged structural view of part C of the present invention;

[0033] Figure 9 It shows a schematic structural view of a floating gate in the prior art.

[0034] Wherein, 1 - substrate, 2 - floating gate structure, 3 - first protective layer, 4 - auxiliary layer, 5 - second protective layer. DETAILED DESCRIPTION OF THE INVENTION

[0035] The following specifically illustrates the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] Please refer to Figure 1 , which shows a method for manufacturing a floating gate, including at least:

[0037] Step 1: Provide a substrate 1, form an active region on the substrate 1, and form a plurality of floating gate structures 2 in the active region;

[0038] Step 2: Refer to Figure 3 , and sequentially form a first protective layer 3, an auxiliary layer 4, and a second protective layer 5 covering the upper surface of the substrate 1 and the plurality of floating gate structures 2, so as to form a sandwich-like interlayer on the surface of the trench region (as shown in Figure 4 ), wherein the first protective layer 3 and the second protective layer 5 can prevent the auxiliary layer 4 from being oxidized. In the prior art, the auxiliary layer 4 is prone to granulation and discontinuity after high-temperature processes. The sandwich-like interlayer can protect the auxiliary layer 4 in subsequent high-temperature processes; it should be understood that the number of layers of the sandwich structure here can also be set to different numbers according to actual processes, and no specific limitation is made here;

[0039] Specifically, in a possible embodiment, the first protective layer 3 is hafnium oxide (Hf oxide).

[0040] In a possible embodiment, the second protective layer 5 is hafnium oxide (Hf oxide).

[0041] Among them, hafnium oxide (Hf oxide) can further improve the flatness of the auxiliary layer 4 after high-temperature processes compared with conventional oxides in the prior art.

[0042] In a possible embodiment, the auxiliary layer 4 includes TiN. It should be understood that TiN here is a material that has been experimentally verified to improve the erase / write efficiency and reduce the operating voltage. Here, a combination of TiN and other types of materials can also be used, or different materials can be used.

[0043] In a possible embodiment, the thickness of the auxiliary layer 4 is between 20 angstroms and 100 angstroms. It should be understood that the thickness of the auxiliary layer 4 is the preferred solution in this embodiment, and it can also be adjusted according to actual situations, and no specific limitation is made here.

[0044] Step 3: Etch all of the second protective layer 5 and the auxiliary layer 4 outside the floating gate structure 2 region and the upper part of the floating gate structure 2, so that the remaining auxiliary layer 4 and the remaining second protective layer 5 that are not etched at the active region are retained.

[0045] Refer to Figure 2 , in order to remove the second protective layer 5 and the auxiliary layer 4 outside the floating gate structure 2 region and on the plurality of floating gates in Step 3, the following method can be used:

[0046] Step A: Cover a photoresist on the second protective layer 5, and then expose the second protective layer 5 outside the floating gate structure 2 through photolithography;

[0047] Step B: Refer toFigure 5 and Figure 6 Using the high selectivity of the second protective layer 5 relative to the photoresist, etch the second protective layer 5. The etching here is preferably dry isotropic etching to expose the auxiliary layer 4 outside the floating gate structure 2. Then, remove the photoresist by at least one of dry or wet methods. When removing the photoresist here, a suitable selectivity should be selected so as not to damage the second protective layer 5 and the auxiliary layer 4;

[0048] Step C: Using the high selectivity of the auxiliary layer 4 relative to the second protective layer 5, etch the auxiliary layer 4 exposed in Step B. The etching here is preferably wet etching;

[0049] Step D: Please refer to Figure 7 and Figure 8 and, on the surface of the auxiliary layer 4 in Step C, reform the second protective layer 5, and etch the second protective layer 5 of the floating gate structure 2 part. The etching here is preferably dry anisotropic etching, where the rest of the area is the target area, so that the second protective layer 5 at the target area is retained and the auxiliary layer 4 below the etched second protective layer 5 is exposed;

[0050] Specifically, in the structure of the super flash memory (as shown in Figure 9 ), the retained part is the local or entire area on the side wall and bottom of the trench area at the floating gate structure 2. In Step D, etch the top of the active area, and the bottom of the trench area at the floating gate structure 2 is retained or removed as needed.

[0051] Step E: Etch the auxiliary layer 4 exposed in Step D, so as to preserve the sandwich structure on the target area.

[0052] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and ratios of the actual components in implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0053] In summary, in the present invention, the auxiliary layer 4 such as TiN is not easily granulated after experiencing a high-temperature process, ensuring the uniformity and stability of the production device. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0054] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a floating gate, characterized in that, it at least includes: Step 1: Provide a substrate, form an active region on the substrate, and form a plurality of floating gate structures in the active region; Step 2: Sequentially form a first protective layer, an auxiliary layer, and a second protective layer covering the upper surface of the substrate and the floating gate structures, wherein the first protective layer and the second protective layer are used to prevent the auxiliary layer from being oxidized, the first protective layer is hafnium dioxide, the second protective layer is hafnium dioxide, and the auxiliary layer is TiN; Step 3: Etch all of the second protective layer and the auxiliary layer outside the floating gate structure region and a part of the second protective layer on the floating gate structure, so that the remaining auxiliary layer and the remaining second protective layer that are not etched at the active region are retained.

2. The method for fabricating a floating gate according to claim 1, characterized in that, the etching of the second protective layer and the auxiliary layer outside the floating gate structure region and on the plurality of floating gates in Step 3 at least includes: Step A: Cover a photoresist on the second protective layer, and then expose the second protective layer outside the floating gate structure through photolithography; Step B: Etch the second protective layer in Step A, expose the auxiliary layer outside the floating gate structure, and then remove the photoresist; Step C: Etch the exposed auxiliary layer in Step B; Step D: Re-form a second protective layer on the surface of the auxiliary layer in Step C, etch the second protective layer of the floating gate structure part, wherein the remaining region is the target region, so that the second protective layer at the target region is retained, and the auxiliary layer under the etched second protective layer is exposed; Step E: Etch the exposed auxiliary layer in Step D.

3. The method for fabricating a floating gate according to claim 2, characterized in that: The etching of the second protective layer in Step A in Step B is dry isotropic etching.

4. The method for fabricating a floating gate according to claim 2, characterized in that: The etching of the auxiliary layer in Step C and Step E is wet etching.

5. The method for fabricating a floating gate according to claim 2, characterized in that: The etching of the second protective layer of the local active region in Step D is dry anisotropic etching.

6. A method for fabricating a floating gate according to claim 2, characterized in that: The target region in Step D is a part or all of the bottom of the trench region and all of the sidewalls in the active region.

7. The method for fabricating a floating gate according to claim 1, characterized in that: The thickness of the auxiliary layer is 20 Å to 100 Å.

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