A window self-aligned split-gate semi-floating gate transistor and its manufacturing method

Abstract

The present invention discloses a window self-aligned split-gate semi-floating gate transistor and a preparation method thereof. By embedding the basic functions of the semi-floating gate transistor into a silicon substrate, a vertical structure of the device is formed, which greatly reduces the area of ​​the semi-floating gate transistor unit. In addition, when forming the semi-floating gate region, the self-alignment of the window is formed by controlling the etching depth of the polysilicon, which helps to regulate the programming efficiency at the window and the magnitude of the reverse bias leakage current.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a window self-aligned split-gate semi-floating gate transistor and a preparation method thereof. Background Art

[0002] At present, DRAM devices with 1T1C structure are the mainstream in integrated circuit chips, but as the device size becomes smaller and smaller, devices with this structure are facing more and more problems. For example, DRAM devices need to be refreshed once every 64ms, so the capacitance of the capacitor must be kept above a certain value to ensure a sufficiently long charge retention time. However, as the feature size of integrated circuits decreases, the manufacture of large capacitors has become increasingly difficult and has occupied a large manufacturing cost.

[0003] As a new type of capacitor-free memory device, the semi-floating gate transistor (SFGT) has the advantages of fast operation speed, small unit area, and high chip density. The split-gate structure of the semi-floating gate transistor divides the control gate into two parts, and the retention ability of the device can be greatly improved through appropriate operating voltage.

[0004] According to the actual process, the size of the semi-floating gate transistor window is greatly affected by the process deviation, and the size of the window affects the reverse leakage current at the window of the semi-floating gate transistor and the programming efficiency. Therefore, accurately controlling the window size of the semi-floating gate transistor is of great significance to the performance of the device. Summary of the invention

[0005] The invention discloses a method for preparing a window self-aligned split-gate semi-floating gate transistor, comprising the following steps: performing N-type ion implantation in a device manufacturing area of ​​a substrate to form a device source end, then epitaxially growing a P-type silicon layer and performing N-type ion implantation to form a P-type channel area and an N-well area; etching to form a U-shaped groove, wherein the U-shaped groove penetrates the N-well area and the P-type channel area; forming a first gate oxide layer at the bottom and sidewall of the U-shaped groove, so that the top of the first gate oxide layer located on the sidewall is higher than the top of the P-type channel area; depositing a first polysilicon layer to fill the U-shaped groove, and etching to make the upper surface higher than the height of the first gate oxide layer, so as to form a contact window between the semi-floating gate and the N-well area; etching the middle area of ​​the first polysilicon layer to expose a part of the first gate oxide layer located at the bottom of the U-shaped groove, so as to form a control The invention relates to a method for manufacturing a gate fabrication area; depositing a second gate oxide layer to cover the surface of the semi-floating gate, and then depositing an N-type second polysilicon layer to form a control gate to fill the control gate fabrication area, and the upper surface of the control gate is flush with the upper surface of the semi-floating gate; etching the second gate oxide layer above the control gate, and then depositing a third gate oxide layer to cover the surfaces of the semi-floating gate and the control gate, and extending to cover the surface of the N-well region; forming a separation gate dielectric layer on the third gate oxide layer, depositing a third polysilicon layer on the surface of the separation gate dielectric, and etching the third polysilicon layer, the separation gate dielectric layer and the third gate oxide layer to expose the surface of the N-well region at the edge to form a separation gate structure; forming side walls on both sides of the separation gate structure, and performing N-type ion implantation to form a drain terminal and a separation gate, and completing the fabrication of a split-gate semi-floating gate transistor.

[0006] In the preparation method of the window self-aligned split-gate semi-floating gate transistor of the present invention, preferably, the step of forming the first gate oxide layer specifically includes: depositing the first gate oxide layer on the surface of the device and filling the second silicon nitride layer in the U-shaped groove; then chemically and mechanically polishing the second silicon nitride layer to the height of the first gate oxide layer at the top; then etching back the second silicon nitride layer to a height higher than the P-type channel region; then isotropically etching the first gate oxide layer located on the sidewall and top of the U-shaped groove reserved above the second silicon nitride layer, and then removing the second silicon nitride layer to complete the preparation of the first gate oxide layer.

[0007] The present invention also discloses a window self-aligned split-gate semi-floating gate transistor, comprising: a substrate, which is N-type and serves as a source end of the device, on which a P-type channel region and an N-well region are formed; a U-shaped groove, which runs through the N-well region and the P-type channel region; a first gate oxide layer, which is formed on the bottom and sidewalls of the U-shaped groove, and the top of the first gate oxide layer located on the sidewall is higher than the top of the P-type channel region; a semi-floating gate and a control gate, which are formed in the U-shaped groove, wherein the control gate is centered and the semi-floating gate is located on the outside, a second gate oxide layer is formed between the control gate and the semi-floating gate, and the control gate The height of the semi-floating gate is the same as that of the semi-floating gate, the semi-floating gate covers the first gate oxide layer of the side wall of the U-shaped groove and forms a contact window with the N-well region; the third gate oxide layer covers the U-shaped groove and extends to cover a portion of the surface of the N-type well region; a separation gate dielectric layer and a separation gate, the separation gate dielectric covers the third gate oxide layer, the separation gate covers the separation gate dielectric and completely fills the U-shaped groove; sidewalls are formed on both sides of the separation gate; a drain terminal is formed on both sides of the sidewalls and in the N-type well region, wherein the control gate adopts N-type polysilicon and the separation gate adopts N-type polysilicon.

[0008] Beneficial effects:

[0009] By embedding the traditional semi-floating gate transistor into the silicon substrate to form a vertical structure of the semi-floating gate transistor, the area of ​​the semi-floating gate transistor unit can be greatly reduced (miniaturized to 4F2) while ensuring the excellent characteristics of the device, thereby achieving a higher chip density.

[0010] By controlling the polysilicon etching depth of the semi-floating gate region in the vertical direction, self-alignment of the semi-floating gate window is formed, which can achieve precise control of the window size and help regulate the programming efficiency and reverse bias leakage current at the window. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a flow chart of a method for preparing a window self-aligned split-gate semi-floating-gate transistor.

[0012] Figure 2 to Figure 17 It is a structural schematic diagram of each step of a method for preparing a window self-aligned split-gate semi-floating gate transistor. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0014] In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0015] In addition, many specific details of the present invention are described below, such as the structure, materials, dimensions, processing technology and techniques of the device, so that the present invention can be more clearly understood. However, as can be understood by those skilled in the art, the present invention can be implemented without following these specific details. Unless otherwise specified below, the various parts of the device can be made of materials known to those skilled in the art, or can be made of materials with similar functions developed in the future.

[0016] Figure 1 The flowchart of the method for preparing a window self-aligned split-gate semi-floating gate transistor is shown in FIG. Figure 1 As shown, in step S1, a pad oxide layer 101 is first deposited in the device manufacturing area of ​​the substrate 100, and N-type ion implantation is performed to form the device source terminal. The resulting structure is as shown in FIG. Figure 2 Then, the pad oxide 101 is removed, and a P-type silicon layer 102 of a certain thickness is epitaxially grown. The resulting structure is as shown in FIG. Figure 3 Afterwards, N-type ion implantation is performed to push the p-type silicon layer down to a certain depth to form a P-type channel region 102 and an N-well region 103. The resulting structure is shown in FIG. Figure 4 shown.

[0017] In step S2, if Figures 5 to 9As shown, a first silicon oxide layer 104 and a first silicon nitride layer 105 are deposited to form a hard mask, and a U-shaped groove is etched to form a manufacturing area for a semi-floating gate, a control gate, and a separation gate. Subsequently, a first gate oxide layer 106 is deposited, and a second silicon nitride layer 107 is filled in the groove, and then the second silicon nitride layer 107 is chemically mechanically polished (CMP) to the height of the top first gate oxide layer 106, and then the second silicon nitride layer 107 is back-etched to the top of the P-type channel region 102, that is, the upper surface of the second silicon nitride layer 107 is higher than the upper surface of the P-type channel region 102. Then, the first gate oxide layer 106 located on the sidewall and the top of the second silicon nitride layer 107 is reserved by isotropic etching, and then the second silicon nitride layer 107 is removed to complete the preparation of the first gate oxide layer.

[0018] In step S3, if Figure 10-11 As shown, the first polysilicon layer 108 is filled in the U-shaped groove, and chemical mechanical polishing and etching are performed on the first polysilicon layer 108. By accurately controlling the etching depth of the first polysilicon layer 108, the first polysilicon layer 108 is etched to a position slightly higher than the first gate oxide layer 106 reserved on the sidewall, and the self-alignment of the semi-floating gate window is completed to form a semi-floating gate region and a desired contact window size between the semi-floating gate and the N-well region 103. In the vertical direction, by controlling the etching depth of the polysilicon in the semi-floating gate region, the self-alignment of the semi-floating gate window is formed, and the precise control of the window size can be completed, which is helpful to regulate the programming efficiency at the window and the size of the reverse bias leakage current.

[0019] In step S4, the first polysilicon layer 108 is etched to expose a portion of the first gate oxide layer 106 at the bottom of the U-shaped trench to form a control gate fabrication region, and a second gate oxide layer 109 is deposited. The resulting structure is as shown in FIG. Fig.12 Then, a second polysilicon layer 110 with an N-type doping type is deposited, and CMP and etching are performed on the second polysilicon layer 110 to etch the second polysilicon layer 110 to the same height as the first polysilicon layer 108, that is, to make the upper surface of the semi-floating gate and the control gate flush. The resulting structure is as shown in FIG. Fig.13 Then, the second gate oxide layer 109 on the second polysilicon layer 110 is removed by isotropic etching to complete the fabrication of the control gate.

[0020] In step S5, Figure 14-15 As shown, a third gate oxide layer 111 of a certain thickness is first deposited, and then a third silicon nitride layer is deposited to form a separation gate dielectric layer 112. Then, a third polysilicon layer 113 is filled to cover the separation gate dielectric layer 112 and completely fill the U-shaped groove, and then the third polysilicon layer 113 is chemically and mechanically polished. Then, edge etching is performed to remove the edge third polysilicon layer 113, the separation gate dielectric layer 112 and the third gate oxide layer 112, so that part of the N-well region 103 is exposed to form a separation gate structure. The resulting structure is shown in FIG. Fig.16shown.

[0021] In step S6, a fourth silicon oxide layer and a fourth silicon nitride layer are then isotropically deposited and anisotropically etched to form a sidewall 115. Then, the third polysilicon layer 113 and the N-well region 103 are N-type ion implanted to form a separation gate 114 and a drain terminal 116, thereby completing the preparation of a vertically structured window self-aligned split-gate semi-floating gate transistor. The resulting structure is as shown in FIG. Fig.17 shown.

[0022] like Fig.17 As shown, the window self-aligned split-gate semi-floating gate transistor includes an N-type substrate 100, which serves as a source terminal of the device, on which a P-type channel region 102 and an N-well region 103 are formed; a U-shaped trench, which penetrates the N-well region 103 and the P-type channel region 102; a first gate oxide layer 106, which is formed on the bottom and sidewalls of the U-shaped trench, and the top of the first gate oxide layer 106 located on the sidewall is higher than the top of the P-type channel region 102;

[0023] A semi-floating gate 108 and a control gate 110 are formed in a U-shaped groove, wherein the control gate 110 is in the middle and the semi-floating gate 108 is located on the outside, a second gate oxide layer 109 is formed between the control gate 110 and the semi-floating gate 108, and the height of the control gate 110 is the same as that of the semi-floating gate 108, the semi-floating gate 108 covers the first gate oxide layer 106 on the sidewall of the U-shaped groove, and forms a contact window with the N-type well region 103; a third gate oxide layer 111 covers the U-shaped groove and extends to cover a portion of the surface of the N-type well region 103;

[0024] A separation gate dielectric layer 112 and a separation gate 114, wherein the separation gate dielectric layer 112 covers the third gate oxide layer 111, and the separation gate 114 covers the separation gate dielectric layer 112 and completely fills the U-shaped groove; sidewalls 115 are formed on both sides of the separation gate; a drain terminal 116 is formed in the N-type well region 103 on both sides of the sidewalls, wherein the control gate 110 adopts N-type polysilicon and the separation gate 114 adopts N-type polysilicon.

[0025] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for preparing a window self-aligned split-gate semi-floating gate transistor, characterized in that: The following steps are involved: Performing N-type ion implantation in the device fabrication area of ​​the substrate to form a device source terminal, then epitaxially growing a P-type silicon layer and performing N-type ion implantation to form a P-type channel region and an N-well region; Etching to form a U-shaped groove, wherein the U-shaped groove runs through the N-well region and the P-type channel region; forming a first gate oxide layer at the bottom and sidewalls of the U-shaped trench, so that the top of the first gate oxide layer located on the sidewall is higher than the top of the P-type channel region; Depositing a first polysilicon layer to fill the U-shaped groove, and etching to make its upper surface higher than the height of the first gate oxide layer, so as to form a contact window between the semi-floating gate and the N-well region; Etching the middle area of ​​the first polysilicon layer to expose a portion of the first gate oxide layer located at the bottom of the U-shaped trench to form a control gate manufacturing area; Depositing a second gate oxide layer to cover the surface of the semi-floating gate, and then depositing an N-type second polysilicon layer to form a control gate to fill the control gate manufacturing area, and the upper surface of the control gate is flush with the upper surface of the semi-floating gate; Etching the second gate oxide layer above the control gate, and then depositing a third gate oxide layer to cover the surfaces of the semi-floating gate and the control gate, and extending to cover the surface of the N-well region; forming a separation gate dielectric layer on the third gate oxide layer, depositing a third polysilicon layer on the surface of the separation gate dielectric, and etching the third polysilicon layer, the separation gate dielectric layer and the third gate oxide layer to expose the surface of the N-well region at the edge, thereby forming a separation gate structure; Sidewalls are formed on both sides of the split gate structure, and N-type ion implantation is performed to form a drain terminal and a split gate, thereby completing the manufacture of a split-gate type semi-floating gate transistor.

2. The method for preparing a window self-aligned split-gate semi-floating gate transistor according to claim 1, characterized in that: The step of forming the first gate oxide layer specifically includes: Depositing a first gate oxide layer on the device surface and filling a second silicon nitride layer in the U-shaped groove; Then chemically mechanically polish the second silicon nitride layer to the height of the first gate oxide layer on top; Then, etching back the second silicon nitride layer to a height higher than the P-type channel region; Then, the first gate oxide layer located on the sidewall and top of the U-shaped groove above the second silicon nitride layer is reserved by isotropic etching, and then the second silicon nitride layer is removed to complete the production of the first gate oxide layer.

3. A window self-aligned split-gate semi-floating gate transistor, characterized in that: include: The substrate is of N type and serves as the source terminal of the device, and has a P type channel region and an N well region formed thereon; A U-shaped groove running through the N-well region and the P-type channel region; A first gate oxide layer is formed on the bottom and sidewalls of the U-shaped trench, and the top of the first gate oxide layer located on the sidewall is higher than the top of the P-type channel region; A semi-floating gate and a control gate are formed in the U-shaped groove, wherein the control gate is centered and the semi-floating gate is located on the outside, a second gate oxide layer is formed between the control gate and the semi-floating gate, and the height of the control gate is the same as that of the semi-floating gate, the semi-floating gate covers the first gate oxide layer on the sidewall of the U-shaped groove, and forms a contact window with the N-well region; a third gate oxide layer, covering the U-shaped groove and extending to cover a portion of the surface of the N-type well region; A separation gate dielectric layer and a separation gate, wherein the separation gate dielectric covers the third gate oxide layer, and the separation gate covers the separation gate dielectric and completely fills the U-shaped trench; Side walls formed on both sides of the separation gate; The drain terminal is formed on both sides of the sidewall and in the N-type well region. Wherein, the control gate is made of N-type polysilicon, and the separation gate is made of N-type polysilicon.

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