Encapsulated Chip, Circuit Board Assembly and Electronic Device

Abstract

The present application provides a packaged chip, a circuit board assembly and an electronic device. The packaged chip includes: a dielectric layer, a redistribution layer and a switchable power supply line group. The dielectric layer is provided with at least one functional circuit unit and at least one power switch unit. The redistribution layer is stacked with the dielectric layer. The switchable power supply line group includes at least one first switchable power supply line and at least one second switchable power supply line. The first switchable power supply line is arranged on the dielectric layer, and the second switchable power supply line is arranged on the redistribution layer. The resistance of the second switchable power supply line is less than that of the first switchable power supply line. The first switchable power supply line and the second switchable power supply line are electrically connected, and both the first switchable power supply line and the second switchable power supply line are electrically connected between the output end of the power switch unit and the power supply end of the functional circuit unit. The packaged chip, the circuit board assembly and the electronic device provided by the present application have a smaller voltage drop.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and particularly to a packaged chip, a circuit board assembly, and an electronic device. Background Art

[0002] Chips can be applied to electronic devices in various fields such as IT, new energy, communication, robotics, and household appliances. The power gating technology can be applied to chips to improve the leakage power consumption problem of the chips. However, in related technologies, the introduction of the power gating technology causes an increase in the voltage drop (IR drop) of the chips, affecting the performance of the chips. Therefore, how to improve the voltage drop of the chips has become a technical problem to be solved. Summary of the Invention

[0003] The present application provides a packaged chip, a circuit board assembly, and an electronic device that can improve the voltage drop.

[0004] On the one hand, the present application provides a packaged chip, including:

[0005] A dielectric layer provided with at least one functional circuit unit and at least one power switch unit;

[0006] A redistribution layer stacked with the dielectric layer; and

[0007] A turn-off power supply line group including at least one first turn-off power supply line and at least one second turn-off power supply line. The first turn-off power supply line is arranged on the dielectric layer, the second turn-off power supply line is arranged on the redistribution layer, the resistance of the second turn-off power supply line is less than that of the first turn-off power supply line, the first turn-off power supply line and the second turn-off power supply line are electrically connected, and both the first turn-off power supply line and the second turn-off power supply line are electrically connected between the output end of the power switch unit and the power supply end of the functional circuit unit.

[0008] On the other hand, the present application further provides a circuit board assembly, including a circuit board, a power supply module, a control module, and the packaged chip. The power supply module, the control module, and the packaged chip are all arranged on the circuit board. The power supply module is electrically connected to the packaged chip through the circuit board for supplying power to the functional circuit unit, and the control module is electrically connected to the packaged chip through the circuit board for controlling the conduction and cut-off of the power switch unit.

[0009] On still another hand, the present application further provides an electronic device including the circuit board assembly.

[0010] Since the dielectric layer of the encapsulated chip provided by the present application is provided with a functional circuit unit and a power switch unit, the functional circuit unit and the power switch unit are electrically connected through a turn-off power line group. When the power switch unit is turned on, the functional circuit unit is in a powered-on state, and when the power switch unit is turned off, the functional circuit unit is in a powered-off state, so that the power supply of the functional circuit unit can be dynamically controlled to reduce power loss in some application scenarios. The resistance of the second turn-off power line of the turn-off power line group is less than that of the first turn-off power line. Therefore, the second turn-off power line can improve part of the voltage drop caused by the current fluctuation when the power switch unit switches between on and off. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments.

[0012] Figure 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0013] Figure 2 is Figure 1 a disassembled schematic diagram of the electronic device shown, wherein the electronic device includes a circuit board assembly;

[0014] Figure 3 is Figure 2 a plan schematic diagram of the circuit board assembly in the electronic device shown, wherein the circuit board assembly includes a circuit board, an encapsulated chip, a power supply module, and a control module.

[0015] Figure 4 is Figure 3 a cross-sectional schematic diagram of the encapsulated chip in the circuit board assembly shown, and the encapsulated chip includes a dielectric layer, a redistribution layer, and a turn-off power line group;

[0016] Figure 5 is Figure 4 a cross-sectional schematic diagram of the turn-off power line group of the encapsulated chip shown, and the turn-off power line group includes a first turn-off power line and a second turn-off power line electrically connected through a conductive via;

[0017] Figure 6 is Figure 4 a plan schematic diagram of the turn-off power line group of the encapsulated chip shown, wherein the turn-off power line group includes a first turn-off power line and a second turn-off power line;

[0018] Figure 7 is Figure 4 a cross-sectional schematic diagram of the first turn-off power line of the encapsulated chip shown, and the first turn-off power line includes a first sub-turn-off power line and a second sub-turn-off power line;

[0019] Figure 8 is Figure 4A planar schematic diagram of the encapsulated chip shown, including multiple first switchable power supply lines and multiple second switchable power supply lines;

[0020] Figure 9 is Figure 4 A planar schematic diagram of the functional circuit unit of the encapsulated chip shown, including a first sub-circuit unit and a second sub-circuit unit;

[0021] Figure 10 is Figure 9 A planar schematic diagram of the encapsulated chip shown, further including a power supply line group;

[0022] Figure 11 is Figure 10 A planar schematic diagram of the power supply line group of the encapsulated chip shown, including a first power supply line and a second power supply line;

[0023] Figure 12 is Figure 10 A planar schematic diagram of the encapsulated chip shown, further including a ground line group;

[0024] Figure 13 is Figure 10 A planar schematic diagram of the ground line group of the encapsulated chip shown, including a first ground line and a second ground line;

[0025] Figure 14 is Figure 4 A planar schematic diagram of the encapsulated chip shown, further including a storage circuit unit;

[0026] Figure 15 is Figure 12 A planar schematic diagram of the encapsulated chip shown, further including a storage power supply line group;

[0027] Figure 16 is Figure 10 A planar schematic diagram of the storage power supply line group of the encapsulated chip shown, including a first storage power supply line and a second storage power supply line;

[0028] Figure 17 is Figure 15 A planar schematic diagram of the encapsulated chip shown, with second switchable power supply lines provided between the power supply line group and the ground line group, and between the ground line group and the storage power supply line group;

[0029] Figure 18 is Figure 15 A planar schematic diagram of the encapsulated chip shown, with second switchable power supply lines provided between multiple second power supply lines and multiple second ground lines;

[0030] Figure 19 is Figure 4 A cross-sectional schematic diagram of the encapsulation layer of the encapsulated chip shown;

[0031] Figure 20Yes Figure 3 The figure also shows a planar schematic diagram of the control lines of the encapsulated chip shown above. Detailed implementation manners

[0032] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are only a part rather than all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present application belong to the scope of protection of the present application.

[0033] Referring to "embodiments" in the present application means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described in the present application can be combined with other embodiments.

[0034] The terms "first", "second", etc. in the specification and claims of the present application and the above accompanying drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0035] As Figure 1 shown Figure 1 As shown, it is a schematic structural diagram of an electronic device 100 provided by an embodiment of the present application. The electronic device 100 can be a mobile phone, a tablet computer, a laptop computer, a computer, a watch, a communication satellite, a radar, an electric vehicle, a robot, a television, and other devices. In the embodiments of the present application, a mobile phone is taken as an example.

[0036] As Figure 2 shown, the electronic device 100 includes a circuit board assembly 1. Specifically, the electronic device 100 further includes a display screen 2 and a housing 3. Among them, the housing 3 includes a middle frame 31 and a back plate 32. The middle frame 31 and the back plate 32 can be integrally formed or connected as a whole. The display screen 2 is connected to a side of the middle frame 31 facing away from the back plate 32. A receiving space 33 is formed among the display screen 2, the middle frame 31, and the back plate 32. The circuit board assembly 1 is disposed in the receiving space 33.

[0037] As Figure 3 shown Figure 3 As shown, it is a planar schematic diagram of a circuit board assembly 1 provided by an embodiment of the present application. The circuit board assembly 1 includes a circuit board 20, an encapsulated chip 10, a power supply module 30, and a control module 40.

[0038] Please refer to Figure 2 and Figure 3, the circuit board 20 can be the main board of the electronic device 100. The circuit board 20 includes a first surface 201 and a second surface which are opposite to each other. The first surface 201 faces the display screen 2, and the second surface faces the back plate 32. The power supply module 30, the control module 40 and the packaged chip 10 are all disposed on the circuit board 20. Optionally, the power supply module 30, the control module 40 and the packaged chip 10 can all be disposed on the first surface 201; or, the power supply module 30, the control module 40 and the packaged chip 10 can all be disposed on the second surface; or, one or two of the power supply module 30, the control module 40 and the packaged chip 10 are disposed on the first surface 201, and the other two or one of the power supply module 30, the control module 40 and the packaged chip 10 are disposed on the second surface.

[0039] The power supply module 30 is electrically connected to the packaged chip 10 through the circuit board 20 and is used to supply power to the packaged chip 10. Optionally, the power supply module 30 and the packaged chip 10 are electrically connected through a metal wire disposed on the circuit board 20. The power supply module 30 includes a power supply battery 301 and a power supply circuit 302. Among them, the power supply battery 301 can be one of a lithium battery, a nickel-chromium battery, a nickel-metal hydride battery, etc. The power supply circuit 302 can include one or more of an input circuit, a drive circuit, a buck / boost circuit, a voltage stabilizing circuit, a power distribution circuit, a voltage detection circuit, an output circuit, a protection circuit, etc.

[0040] The control module 40 is electrically connected to the packaged chip 10 through the circuit board 20 and is used to control the packaged chip 10. Optionally, the control module 40 and the packaged chip 10 are electrically connected through a metal wire disposed on the circuit board 20. The way the control module 40 controls the packaged chip 10 can be: the control module 40 controls the packaged chip 10 according to the foreground running program of the electronic device 100; or, the control module 40 controls the packaged chip 10 by obtaining the signal of the user operating the electronic device 100 and according to the user's operation; or, the control module 40 controls the packaged chip 10 by obtaining the detection signal of the detector and according to the detection signal.

[0041] The packaged chip 10 can be one of a processor chip, a graphics processing chip, a display chip, a digital signal processing chip, an application specific integrated circuit chip, a system-on-chip, a baseband chip, a radio frequency chip, etc. The packaged chip 10 includes at least one functional circuit unit 114 and at least one power switch unit 115. The power supply module 30 is used to supply power to the functional circuit unit 114. The control module 40 is used to control the conduction and cut-off of the power switch unit 115. In one application scenario, the packaged chip 10 can be a system-on-chip (a chip integrated with functional circuit units such as display, processing, storage, and communication); the control module 40 controls the packaged chip 10 by obtaining the detection signal of the detector. For example: the detector is used to detect whether the display screen 2 is in the display mode. When the detector detects that the display screen 2 is in the non-display mode, it sends the detection signal to the control module 40, and the control module 40 can control the power switch unit 115 electrically connected to the functional circuit unit 114 corresponding to the display function in the packaged chip 10 to cut off according to the detection signal.

[0042] As Figure 4 shown, Figure 4 FIG. is a cross-sectional schematic diagram of a packaged chip 10 provided by an embodiment of the present application. The packaged chip 10 includes a dielectric layer 101, a redistribution layer 102, and a turn-off power supply line group 103.

[0043] At least one functional circuit unit 114 and at least one power switch unit 115 are disposed in the dielectric layer 101. In one embodiment, the dielectric layer 101 includes a substrate layer 110, a functional circuit layer 112, and a connection layer 113 that are stacked in sequence. Among them, the substrate layer 110 can be one of a silicon substrate, a sapphire substrate, a glass substrate, an organic substrate, a composite substrate, etc. At least one functional circuit unit 114 and at least one power switch unit 115 are disposed in the functional circuit layer 112. The connection layer 113 includes a plurality of stacked metal layers and an insulating layer disposed between two adjacent metal layers. In the present application, only the top metal layer is illustrated in the drawings for the convenience of description, and other metal layers and insulating layers are not illustrated. It can be understood that in this embodiment, the substrate layer 110, the functional circuit layer 112, the connection layer 113, the functional circuit unit 114 disposed in the functional circuit layer 112, the power switch unit 115, and the connection circuit disposed in the connection layer 113 form a bare chip.

[0044] This application does not specifically limit the number of functional circuit units 114 and power switch units 115. The number of functional circuit units 114 can be one or more. The number of power switch units 115 can be one or more. The number of functional circuit units 114 and power switch units 115 can be the same or different. When the number of functional circuit units 114 is the same as the number of power switch units 115, one functional circuit unit 114 can be electrically connected to one power switch unit 115. When the number of functional circuit units 114 is greater than the number of power switch units 115, multiple functional circuit units 114 can be electrically connected to the same power switch unit 115, or some of the multiple functional circuit units 114 can be electrically connected to the power switch unit 115. When the number of functional circuit units 114 is less than the number of power switch units 115, one functional circuit unit 114 can be electrically connected to multiple power switch units 115. In the following embodiments, one functional circuit unit 114 and one power switch unit 115 are taken as examples without special instructions.

[0045] Please refer to Figure 3 and Figure 4 , the functional circuit unit 114 can be understood as a circuit unit in the packaged chip 10 that can support a specific function (such as one of taking pictures, networking, gaming, shooting videos, listening to music, etc.). The power switch unit 115 is electrically connected between the power supply module 30 and the functional circuit unit 114, and is a switch unit used to control whether the power supply module 30 supplies power to the functional circuit unit 114. Specifically, the input end of the power switch unit 115 is used to be electrically connected to the power supply module 30, and the output end of the power switch unit 115 is used to be electrically connected to the functional circuit unit 114. It can be understood that when the power switch unit 115 is turned on, the power supply module 30 can supply power to the functional circuit unit 114; when the power switch unit 115 is turned off, the power supply module 30 cannot supply power to the functional circuit unit 114. Among them, when the power switch unit 115 switches between the on state and the off state, the current fluctuation on the electrical connection line between the output end of the power switch unit 115 and the functional circuit unit 114 is relatively large. Therefore, improving the voltage drop generated by the electrical connection line between the output end of the power switch unit 115 and the functional circuit unit 114 can better improve the performance of the packaged chip 10.

[0046] The redistribution layer 102 and the dielectric layer 101 are stacked. Specifically, the redistribution layer 102 is disposed on the side of the connection layer 113 away from the functional circuit layer 112. In other words, the substrate layer 110, the functional circuit layer 112, the connection layer 113, and the redistribution layer 102 are stacked in sequence. The redistribution layer 102 is the electrical connection interface between the bare chip and the package.

[0047] The turn-off power supply line group 103 is electrically connected between the output terminal of the power switch unit 115 and the power supply terminal of the functional circuit unit 114. The turn-off power supply line group 103 includes at least one first turn-off power supply line 130 and at least one second turn-off power supply line 131. The first turn-off power supply line 130 can be a metal wire or a conductive wire made of other materials (such as alloys, conductive polymers, carbon fibers, etc.). The second turn-off power supply line 131 can be a metal wire or a conductive wire made of other materials (such as alloys, conductive polymers, carbon fibers, etc.). In the embodiments of the present application, without special explanation, the first turn-off power supply line 130 and the second turn-off power supply line 131 are taken as metal wires. The present application does not specifically limit the number of the first turn-off power supply line 130 and the second turn-off power supply line 131. The number of the first turn-off power supply line 130 can be one or more, and the number of the second turn-off power supply line 131 can be one or more. When the functional circuit unit 114 and the power switch unit 115 are one, the number of the first turn-off power supply line 130 can be one or more, and the number of the second turn-off power supply line 131 can be one or more. When the functional circuit unit 114 and the power switch unit 115 are multiple, the number of the first turn-off power supply line 130 is multiple, and the number of the second turn-off power supply line 131 is multiple.

[0048] The first turn-off power supply line 130 is arranged on the dielectric layer 101. In one embodiment, the first turn-off power supply line 130 is arranged on the connection layer 113. The second turn-off power supply line 131 is arranged on the redistribution layer 102. The first turn-off power supply line 130 and the second turn-off power supply line 131 are electrically connected.

[0049] Optionally, as Figure 5 shown, an intermediate layer 116 is provided between the connection layer 113 and the redistribution layer 102, and the first turn-off power supply line 130 and the second turn-off power supply line 131 are electrically connected through a conductive via 1160 provided in the intermediate layer 116. Electrically connecting the first turn-off power supply line 130 and the second turn-off power supply line 131 through the conductive via 1160 can simplify the complexity of the wiring between the redistribution layer 102 and the connection layer 113 and reduce the thickness of the packaged chip 10. Of course, in other embodiments, the first turn-off power supply line 130 and the second turn-off power supply line 131 can be directly electrically connected or capacitively coupled.

[0050] The resistance of the second turn-off power supply line 131 is less than the resistance of the first turn-off power supply line 130. In one embodiment, as Figure 5As shown, the thickness of the second turn-off power supply line 131 is greater than that of the first turn-off power supply line 130. In this embodiment, by making the thickness of the second turn-off power supply line 131 greater than that of the first turn-off power supply line 130, the resistance of the second turn-off power supply line 131 can be made less than that of the first turn-off power supply line 130. In another embodiment, as Figure 6 shown, the width of the second turn-off power supply line 131 is greater than that of the first turn-off power supply line 130. In this embodiment, by making the width of the second turn-off power supply line 131 greater than that of the first turn-off power supply line 130, the resistance of the second turn-off power supply line 131 can be made less than that of the first turn-off power supply line 130. In yet another embodiment, the thickness of the second turn-off power supply line 131 is greater than that of the first turn-off power supply line 130, and the width of the second turn-off power supply line 131 is greater than that of the first turn-off power supply line 130.

[0051] Both the first turn-off power supply line 130 and the second turn-off power supply line 131 are electrically connected between the output terminal of the power switch unit 115 and the power supply terminal of the functional circuit unit 114. Since the resistance of the second turn-off power supply line 131 is smaller, the technical solution of forming an electrical connection line between the output terminal of the power switch unit 115 and the functional circuit unit 114 through the first turn-off power supply line 130 provided in the dielectric layer 101 and the second turn-off power supply line 131 provided in the redistribution layer 102 can reduce at least part of the voltage drop generated when at least part of the power switch unit 115 switches between the on state and the off state compared with the technical solution of forming an electrical connection line between the output terminal of the power switch unit 115 and the functional circuit unit 114 only through the first turn-off power supply line 130 provided in the dielectric layer 101.

[0052] In the packaged chip 10 provided in the present application, since the dielectric layer 101 is provided with the functional circuit unit 114 and the power switch unit 115, the functional circuit unit 114 and the power switch unit 115 are electrically connected through the turn-off power supply line group 103. When the power switch unit 115 is turned on, the functional circuit unit 114 is in the powered-on state, and when the power switch unit 115 is turned off, the functional circuit unit 114 is in the powered-off state, so that the power supply of the functional circuit unit 114 can be dynamically controlled to reduce power loss in some application scenarios. And the resistance of the second turn-off power supply line 131 of the turn-off power supply line group 103 is less than that of the first turn-off power supply line 130. Therefore, the second turn-off power supply line 131 can improve the voltage drop caused by current fluctuations when some power switch units 115 switch between on and off.

[0053] In one embodiment, as Figure 7As shown, at least one first turn-off power supply line 130 includes at least one first sub-turn-off power supply line 130a and at least one second sub-turn-off power supply line 130b. The first sub-turn-off power supply line 130a, the second turn-off power supply line 131, and the second sub-turn-off power supply line 130b are sequentially connected between the output end of the power switch unit 115 and the power supply end of the functional circuit unit 114. Specifically, the first sub-turn-off power supply line 130a is disposed in the connection layer 113. The first end of the first sub-turn-off power supply line 130a is electrically connected to the output end of the power switch unit 115, the second end of the first sub-turn-off power supply line 130a is electrically connected to the first end of the second turn-off power supply line 131, the second end of the second turn-off power supply line 131 is electrically connected to the first end of the second sub-turn-off power supply line 130b, and the second end of the second sub-turn-off power supply line 130b is electrically connected to the power supply end of the functional circuit unit 114. Among them, the first end of the first sub-turn-off power supply line 130a and the output end of the power switch unit 115 can be directly electrically connected. The second end of the second sub-turn-off power supply line 130b and the power supply end of the functional circuit unit 114 can be directly electrically connected. The first end of the second turn-off power supply line 131 is closer to the output end of the power switch unit 115 than the second end of the second turn-off power supply line 131; the second end of the second turn-off power supply line 131 is closer to the power supply end of the functional circuit unit 114 than the first end of the second turn-off power supply line 131.

[0054] Optionally, please refer to Figure 7 and Figure 8 , the number of the first sub-turn-off power supply lines 130a is multiple. The number of the second sub-turn-off power supply lines 130b is multiple. The number of the second turn-off power supply lines 131 is multiple. Each second turn-off power supply line 131 is electrically connected between a first sub-turn-off power supply line 130a and a second sub-turn-off power supply line 130b, and forms a connection trace. It can be understood that a first sub-turn-off power supply line 130a, a second turn-off power supply line 131, and a second sub-turn-off power supply line 130b are sequentially electrically connected and form a connection trace. In this embodiment, multiple first sub-turn-off power supply lines 130a, multiple second turn-off power supply lines 131, and multiple second sub-turn-off power supply lines 130b can form multiple connection traces. The multiple connection traces are connected in parallel between the output end of the power switch unit 115 and the power supply end of the functional circuit unit 114. In this embodiment, by connecting the multiple connection traces in parallel between the output end of the power switch unit 115 and the power supply end of the functional circuit unit 114, when the power switch unit 115 is in the on state, current can be transmitted to the functional circuit unit 114 through the multiple connection traces simultaneously, so as to improve the power supply efficiency of the power supply module 30 to the functional circuit unit 114 and improve the operating speed of the packaged chip 10.

[0055] In one embodiment, as Figure 9As shown, the functional circuit unit 114 includes a first sub-circuit unit 114a and a second sub-circuit unit 114b. It can be understood that the first sub-circuit unit 114a is a part of the logic circuit units in the functional circuit unit 114, and the second sub-circuit unit 114b is another part of the logic circuit units in the functional circuit unit 114. The first sub-circuit unit 114a and the second sub-circuit unit 114b cooperate to implement the functions of the functional circuit unit 114. The power loss of the first sub-circuit unit 114a is greater than that of the second sub-circuit unit 114b. For example, the supply voltage and / or supply current required by the first sub-circuit unit 114a is greater than the supply voltage and / or supply current required by the second sub-circuit unit 114b. The number of the second switchable power supply lines 131 is multiple. Some of the second switchable power supply lines 131 are electrically connected to the power supply terminal of the first sub-circuit unit 114a, and some of the second switchable power supply lines 131 are electrically connected to the power supply terminal of the second sub-circuit unit 114b. Among them, the second switchable power supply line 131 can be directly electrically connected to the power supply terminal of the first sub-circuit unit 114a, or can be electrically connected through the first switchable power supply line 130. The second switchable power supply line 131 can be directly electrically connected to the power supply terminal of the second sub-circuit unit 114b, or can be electrically connected through the first switchable power supply line 130. In the embodiment of the present application, the second switchable power supply line 131 is electrically connected to the power supply terminal of the first sub-circuit board 20 through the first switchable power supply line 130. The second switchable power supply line 131 is electrically connected to the power supply terminal of the second sub-circuit board 20 through the first switchable power supply line 130. The number of the second switchable power supply lines 131 electrically connected to the first sub-circuit unit 114a is greater than the number of the second switchable power supply lines 131 electrically connected to the second sub-circuit unit 114b. Among them, the number of the second switchable power supply lines 131 electrically connected to the first sub-circuit unit 114a can be one or more, and the number of the second switchable power supply lines 131 electrically connected to the second sub-circuit unit 114b can be zero, one or more. In one embodiment, the number of the second switchable power supply lines 131 electrically connected to the first sub-circuit unit 114a is four, and the number of the second switchable power supply lines 131 electrically connected to the second sub-circuit unit 114b is one.

[0056] In this embodiment, since the power loss of the first sub-circuit unit 114a is relatively high and the power loss of the second sub-circuit unit 114b is relatively small, the current on the electrical connection line electrically connected between the output terminal of the power switch unit 115 and the power supply terminal of the first sub-circuit unit 114a fluctuates greatly when the power switch unit 115 switches, and the current on the electrical connection line electrically connected between the output terminal of the power switch unit 115 and the power supply terminal of the second sub-circuit unit 114b fluctuates less when the power switch unit 115 switches. Therefore, by making the number of the second turn-off power supply lines 131 electrically connected to the first sub-circuit unit 114a greater than the number of the second turn-off power supply lines 131 electrically connected to the second sub-circuit unit 114b, the voltage drop generated by the electrical connection line between the output terminal of the power switch unit 115 and the power supply terminal of the first sub-circuit unit 114a can be mainly reduced, while the voltage drop generated by the electrical connection line between the output terminal of the power switch unit 115 and the power supply terminal of the second sub-circuit unit 114b is secondarily reduced or not reduced, so that while improving the voltage drop of the packaged chip 10, the wiring of the redistribution layer 102 can be reduced and the process difficulty can be lowered.

[0057] Optionally, as Figure 9 shown, the redistribution layer 102 has a first region 120 and a second region 121. The first region 120 is opposite to the location of the first sub-circuit unit 114a. The second region 121 is opposite to the location of the second sub-circuit unit 114b. The second turn-off power supply lines 131 electrically connected to the first sub-circuit unit 114a are located in the first region 120. The second turn-off power supply lines 131 electrically connected to the second sub-circuit unit 114b are located in the second region 121. In this embodiment, by arranging the second turn-off power supply lines 131 electrically connected to the first sub-circuit unit 114a close to the first sub-circuit unit 114a, the length of the second turn-off power supply lines 131 electrically connected to the first sub-circuit unit 114a can be reduced, thereby further reducing the resistance of the second turn-off power supply lines 131 electrically connected to the first sub-circuit unit 114a and improving the effect of improving the voltage drop between the power switch unit 115 and the first sub-circuit unit 114a. And by arranging the second turn-off power supply lines 131 electrically connected to the second sub-circuit unit 114b close to the second sub-circuit unit 114b, the length of the second turn-off power supply lines 131 electrically connected to the second sub-circuit unit 114b can be reduced, thereby further reducing the resistance of the second turn-off power supply lines 131 electrically connected to the second sub-circuit unit 114b and improving the effect of improving the voltage drop between the power switch unit 115 and the second sub-circuit unit 114b.

[0058] Further, please refer to Figure 10 and Figure 11, the encapsulated chip 10 further includes a power supply power line group 104. The power supply power line group 104 is electrically connected between the input end of the power switch unit 115 and the power supply module 30 (refer to Figure 3 ). The power supply power line group 104 includes at least one first power supply power line 140 and at least one second power supply power line 141. The first power supply power line 140 can be a metal wire or a conductive wire of other materials (such as alloys, conductive polymers, carbon fibers, etc.). The second power supply power line 141 can be a metal wire or a conductive wire of other materials (such as alloys, conductive polymers, carbon fibers, etc.). In the embodiments of the present application, without special instructions, both the first power supply power line 140 and the second power supply power line 141 are taken as metal wires as an example. The present application does not specifically limit the number of the first power supply power line 140 and the second power supply power line 141. The number of the first power supply power line 140 can be one or more, and the number of the second power supply power line 141 can be one or more. When the functional circuit unit 114 and the power switch unit 115 are one, the number of the first power supply power line 140 can be one or more, and the number of the second power supply power line 141 can be one or more. When the functional circuit unit 114 and the power switch unit 115 are multiple, the number of the first power supply power line 140 is multiple, and the number of the second power supply power line 141 is multiple.

[0059] The first power supply power line 140 is arranged on the dielectric layer 101. In one embodiment, the first power supply power line 140 is arranged on the connection layer 113 (refer to Figure 4 ). The second power supply power line 141 is arranged on the redistribution layer 102. The first power supply power line 140 and the second power supply power line 141 are sequentially electrically connected to the input end of the power switch unit 115 (refer to Figure 4 ). Specifically, the first end of the first power supply power line 140 is electrically connected to the input end of the power switch unit 115, and the second end of the first power supply power line 140 is electrically connected to the first end of the second power supply power line 141. The second end of the second power supply power line 141 is used to be electrically connected to the power supply module 30. Among them, the first power supply power line 140 and the input end of the power switch unit 115 can be directly electrically connected. The first power supply power line 140 and the second power supply power line 141 can be electrically connected through a conductive via. Electrically connecting the first power supply power line 140 and the second power supply power line 141 through a conductive via can simplify the complexity of the wiring between the redistribution layer 102 and the connection layer 113 and reduce the thickness of the encapsulated chip 10. The second power supply power line 141 and the power supply module 30 can be electrically connected through a package interface and / or a conductive wire provided on the circuit board 20.

[0060] In one embodiment, the resistance of the second power supply power line 141 is less than that of the first power supply power line 140. Optionally, the width of the second power supply power line 141 is greater than that of the first power supply power line 140; and / or, the thickness of the second power supply power line 141 is greater than that of the first power supply power line 140.

[0061] In this embodiment, the first power supply power line 140 and the second power supply power line 141 are used to transmit the supply current input by the power supply module 30 to the functional circuit unit 114, so that the power supply module 30 charges the functional circuit unit 114. In addition, the second power supply power line 141 is disposed in the redistribution layer 102. The resistance of the second power supply power line 141 can be reduced by increasing the width and thickness of the second power supply power line 141, thereby improving the voltage drop on the second power supply power line 141.

[0062] Further, please refer to Figure 12 and Figure 13 , the packaged chip 10 further includes a ground wire group 105. The ground wire group 105 is electrically connected between the ground terminal of the functional circuit unit 114 (refer to Figure 4 ) and the reference ground. Among them, the reference ground can be located on the circuit board 20 (refer to Figure 3 ). The ground wire group 105 includes at least one first ground wire 150 and at least one second ground wire 151. The first ground wire 150 can be a metal wire or a conductive wire of other materials (such as alloys, conductive polymers, carbon fibers, etc.). The second ground wire 151 can be a metal wire or a conductive wire of other materials (such as alloys, conductive polymers, carbon fibers, etc.). In the embodiments of the present application, without special instructions, the first ground wire 150 and the second ground wire 151 are taken as metal wires as an example. The present application does not specifically limit the number of the first ground wire 150 and the second ground wire 151. The number of the first ground wire 150 can be one or more, and the number of the second ground wire 151 can be one or more. When there is one functional circuit unit 114, the number of the first ground wire 150 can be one or more, and the number of the second ground wire 151 can be one or more. When there are multiple functional circuit units 114, the number of the first ground wire 150 is multiple, and the number of the second ground wire 151 is multiple. The multiple first ground wires 150 are electrically connected to the ground terminals of different functional circuit units 114.

[0063] The first ground wire 150 is arranged in the dielectric layer 101. In one embodiment, the first ground wire 150 is arranged in the connection layer 113 (refer to Figure 4)。The second ground wire 151 is arranged in the redistribution layer 102. The first ground wire 150 and the second ground wire 151 are sequentially electrically connected to the ground terminal of the functional circuit unit 114. Specifically, the first end of the first ground wire 150 is electrically connected to the ground terminal of the functional circuit unit 114, and the second end of the first ground wire 150 is electrically connected to the first end of the second ground wire 151. The second end of the second ground wire 151 is used for electrically connecting to a reference ground. Among them, the first ground wire 150 can be directly electrically connected to the ground terminal of the functional circuit unit 114. The first ground wire 150 and the second ground wire 151 can be electrically connected through the conductive via 1160 provided in the intermediate layer 116. Electrically connecting the first ground wire 150 and the second ground wire 151 through the conductive via 1160 can simplify the complexity of the wiring between the redistribution layer 102 and the connection layer 113 and reduce the thickness of the packaged chip 10. The second ground wire 151 and the reference ground can be electrically connected through a package interface and / or a conductive wire provided on the circuit board 20.

[0064] In one embodiment, the resistance of the second ground wire 151 is less than that of the first ground wire 150. Optionally, the width of the second ground wire 151 is greater than that of the first ground wire 150; and / or, the thickness of the second ground wire 151 is greater than that of the first ground wire 150.

[0065] In this embodiment, the first ground wire 150 and the second ground wire 151 are used to electrically connect the ground terminal of the functional circuit unit 114 to the reference ground outside the packaged chip 10, so that the functional circuit unit 114 is grounded, which can reduce the interference of the external electric field on the functional circuit unit 114 and prevent electrostatic. The second ground wire 151 is arranged in the redistribution layer 102, and the resistance of the second ground wire 151 can be reduced by increasing the width and thickness of the second ground wire 151, thereby improving the voltage drop on the second ground wire 151.

[0066] Further, please refer to Figures 14 to 16 , the packaged chip 10 further includes at least one storage circuit unit 106 and a storage unit wire group 107. The storage circuit unit 106 is arranged in the dielectric layer 101. In one embodiment, the storage circuit unit 106 is arranged in the functional circuit layer 112. The storage unit wire group 107 is electrically connected to the power supply terminal of the storage circuit unit 106 and the power supply module 30 (refer to Figure 3) Among them. The memory cell line group 107 includes at least one first memory power supply line 170 and at least one second memory power supply line 171. The first memory power supply line 170 can be a metal wire or a conductive wire of other materials (such as alloys, conductive polymers, carbon fibers, etc.). The second memory power supply line 171 can be a metal wire or a conductive wire of other materials (such as alloys, conductive polymers, carbon fibers, etc.). In the embodiments of the present application, without special instructions, the first memory power supply line 170 and the second memory power supply line 171 are taken as metal wires as examples. The present application does not specifically limit the number of the first memory power supply line 170 and the second memory power supply line 171. The number of the first memory power supply line 170 can be one or more, and the number of the second memory power supply line 171 can be one or more. When there is one memory circuit unit 106, the number of the first memory power supply line 170 can be one or more, and the number of the second memory power supply line 171 can be one or more. When there are multiple memory circuit units 106, the number of the first memory power supply line 170 is multiple, and the number of the second memory power supply line 171 is multiple. The multiple first memory power supply lines 170 are electrically connected to the power supply terminals of different memory circuit units 106.

[0067] The first memory power supply line 170 is arranged in the dielectric layer 101. In one embodiment, the first memory power supply line 170 is arranged in the connection layer 113. The second memory power supply line 171 is arranged in the redistribution layer 102. The first memory power supply line 170 and the second memory power supply line 171 are sequentially electrically connected to the power supply terminal of the memory circuit unit 106. Specifically, the first end of the first memory power supply line 170 is electrically connected to the power supply terminal of the memory circuit unit 106, and the second end of the first memory power supply line 170 is electrically connected to the first end of the second memory power supply line 171. The second end of the second memory power supply line 171 is used to be electrically connected to the power supply module 30. Among them, the first memory power supply line 170 and the power supply terminal of the memory circuit unit 106 can be directly electrically connected. The first memory power supply line 170 and the second memory power supply line 171 can be electrically connected through an electro-via. Electrically connecting the first memory power supply line 170 and the second memory power supply line 171 through a conductive via can simplify the complexity of the wiring between the redistribution layer 102 and the connection layer 113 and reduce the thickness of the packaged chip 10. The second memory power supply line 171 and the power supply module 30 (refer to Figure 3 ) can be electrically connected through a packaging interface and / or a conductive wire provided on the circuit board 20 (refer to Figure 3 ).

[0068] In one embodiment, the resistance of the second memory power supply line 171 is less than the resistance of the first memory power supply line 170. Optionally, the width of the second memory power supply line 171 is greater than the width of the first memory power supply line 170; and / or, the thickness of the second memory power supply line 171 is greater than the thickness of the first memory power supply line 170.

[0069] In this embodiment, the first storage power supply line 170 and the second storage power supply line 171 are used to transmit the power supply current input by the power supply module 30 to the storage circuit unit 106, so that the power supply module 30 charges the storage circuit unit 106. In addition, the second storage power supply line 171 is arranged in the redistribution layer 102, and the resistance of the second storage power supply line 171 can be reduced by increasing the width and thickness of the second storage power supply line 171, thereby improving the voltage drop on the second storage power supply line 171.

[0070] Among them, as Figure 17 shown, the number of the second turn-off power supply lines 131 is multiple; the second turn-off power supply lines 131 are arranged between the second power supply line 141 and the second ground line 151; and / or, the second turn-off power supply lines 131 are arranged between the second power supply line 141 and the second storage power supply line 171, and / or, the second turn-off power supply lines 131 are arranged between the second ground line 151 and the second storage power supply line 171.

[0071] In one embodiment, a part of the second turn-off power supply lines 131 are arranged between the second power supply line 141 and the second ground line 151, and another part of the second turn-off power supply lines 131 are arranged between the second ground line 151 and the second storage power supply line 171.

[0072] By arranging the second turn-off power supply lines 131 between the second power supply line 141 and the second ground line 151; and / or, between the second power supply line 141 and the second storage power supply line 171, and / or, between the second ground line 151 and the second storage power supply line 171, the gaps between the second power supply line 141 and the second ground line 151, between the second power supply line 141 and the second storage power supply line 171, and between the second ground line 151 and the second storage power supply line 171 can be effectively utilized, and the length and width dimensions of the packaged chip 10 can be reduced, realizing the miniaturization of the packaged chip 10.

[0073] Among them, as Figure 18 shown, the number of the second turn-off power supply lines 131 is multiple; the number of the second power supply lines 141 is multiple, and at least part of the second turn-off power supply lines 131 are arranged between the multiple second power supply lines 141; and / or, the number of the second ground lines 151 is multiple, and at least part of the second turn-off power supply lines 131 are arranged between the multiple second ground lines 151; and / or, the number of the second storage power supply lines 171 is multiple, and at least part of the second turn-off power supply lines 131 are arranged between the multiple second storage power supply lines 171.

[0074] In one embodiment, the second turn-off power supply line 131 of the fourth part is arranged among a plurality of second power supply lines 141, and the second turn-off power supply line 131 of the fifth part is arranged among a plurality of second ground lines 151. Of course, in other embodiments, there may also be a second turn-off power supply line 131 of a sixth part arranged among a plurality of second storage power supply lines 171.

[0075] By arranging the second turn-off power supply line 131 among a plurality of second power supply lines 141; and / or, among a plurality of second ground lines 151; and / or, among a plurality of second storage power supply lines 171, the arrangement of the second turn-off power supply line 131 can be made more dense, which is beneficial to adjusting the arrangement position of the second turn-off power supply line 131 according to the power consumption density of different functional circuit units 114, so that a relatively dense second turn-off power supply line 131 is arranged in the area of the redistribution layer 102 corresponding to the functional circuit unit 114 with a high power consumption density, and a relatively sparse second turn-off power supply line 131 is arranged in the area of the redistribution layer 102 corresponding to the functional circuit unit 114 with a low power consumption density, or the second turn-off power supply line 131 is not arranged in the area of the redistribution layer 102 corresponding to the functional circuit unit 114 with a low power consumption density, thereby concentrating on improving the voltage drop generated by the electrical connection line between the output end of the power switch unit 115 and the functional circuit unit 114 with a high power consumption density, that is, reducing the voltage drop on the electrical connection line where a large voltage drop is likely to occur and improving the effect of improving the voltage drop.

[0076] Further, please refer to Figures 18 to 20 , the packaged chip 10 further includes a packaging layer 108. The packaging layer 108 is laminated on the side of the redistribution layer 102 facing away from the dielectric layer 101. The packaging layer 108 is provided with at least one conductive part 180. The second power supply line 141 is electrically connected to the power supply module 30 through the conductive part 180. It can be understood that the dielectric layer 101, the redistribution layer 102 and the packaging layer 108 are laminated in sequence. The redistribution layer 102 is the interface between the electrical connection line of the dielectric layer 101 and the conductive part 180 of the packaging layer 108.

[0077] In one embodiment, the packaging layer 108 is provided with at least one first conductive part, at least one second conductive part and at least one third conductive part. The second power supply line 141 is electrically connected to the power supply module 30 through the first conductive part. The second ground line 151 is electrically connected to the reference ground through the second conductive part. The second storage power supply line 171 is electrically connected to the power supply module 30 through the third conductive part. Among them, the second power supply line 141 and the first conductive part can be electrically connected through a conductive bump. The second ground line 151 and the second conductive part can be electrically connected through a conductive bump. The second storage power supply line 171 and the third conductive part can be electrically connected through a conductive bump.

[0078] Among them, as Figure 20As shown, the encapsulated chip 10 further includes at least one control line 109. The control line 109 can be a metal wire or a conductive wire made of other materials (such as alloys, conductive polymers, carbon fibers, etc.). The first end of the control line 109 is electrically connected to the control end of the power switch unit 115, and the second end of the control line 109 is used to be electrically connected to the control module 40. The control line 109 is used to transmit the control signal sent by the control module 40 to control the power switch unit 115 to conduct or cut off. The present application does not make a specific limitation on the number of the control lines 109. The number of the control lines 109 can be one or more. In one embodiment, the number of the control lines 109 is the same as the number of the power switch units 115, and one control line 109 is electrically connected between one power switch unit 115 and the control module 40 to transmit the control signal sent by the control module 40 to the power switch unit 115.

[0079] By setting the control line 109 to be electrically connected between the control module 40 and the power switch unit 115, the control signal can be transmitted to the power switch unit 115, so that the power switch unit 115 can be dynamically controlled to conduct and cut off according to the control signal sent by the control module 40.

[0080] The features mentioned in the above specification, claims and drawings, as long as they are meaningful within the scope of the present application, can be arbitrarily combined with each other. The advantages and features described for the encapsulated chip 10 are applicable to the circuit board assembly 1 and the electronic device 100 in a corresponding manner.

[0081] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present application, and these improvements and refinements are also regarded as the protection scope of the present application.

Claims

1. An encapsulated chip, characterized in that, Comprising: A dielectric layer provided with at least one functional circuit unit and at least one power switch unit. The functional circuit unit includes a first sub-circuit unit and a second sub-circuit unit, and the power loss of the first sub-circuit unit is greater than that of the second sub-circuit unit. A redistribution layer stacked with the dielectric layer; and A turn-off power supply line group including at least one first turn-off power supply line and at least one second turn-off power supply line. The first turn-off power supply line is arranged on the dielectric layer, and the second turn-off power supply line is arranged on the redistribution layer. The resistance of the second turn-off power supply line is less than that of the first turn-off power supply line. The first turn-off power supply line and the second turn-off power supply line are electrically connected, and both the first turn-off power supply line and the second turn-off power supply line are electrically connected between the output end of the power switch unit and the power supply end of the functional circuit unit. The number of the second turn-off power supply lines is multiple. Some of the second turn-off power supply lines are electrically connected to the power supply end of the first sub-circuit unit, and some of the second turn-off power supply lines are electrically connected to the power supply end of the second sub-circuit unit. And the number of the second turn-off power supply lines electrically connected to the first sub-circuit unit is greater than the number of the second turn-off power supply lines electrically connected to the second sub-circuit unit.

2. The encapsulated chip according to claim 1, wherein, At least one of the first turn-off power supply lines includes at least one first sub-turn-off power supply line and at least one second sub-turn-off power supply line. The first sub-turn-off power supply line, the second turn-off power supply line, and the second sub-turn-off power supply line are sequentially connected between the output end of the power switch unit and the power supply end of the functional circuit unit.

3. The encapsulated chip according to claim 2, wherein, The number of the first sub-turn-off power supply lines is multiple, the number of the second sub-turn-off power supply lines is multiple, and the number of the second turn-off power supply lines is multiple. Each of the second turn-off power supply lines is electrically connected between one first sub-turn-off power supply line and one second sub-turn-off power supply line and forms a connection trace. Multiple connection traces are connected in parallel between the output end of the power switch unit and the power supply end of the functional circuit unit.

4. The encapsulated chip according to claim 1, wherein, The redistribution layer has a first region and a second region. The first region is opposite to the position where the first sub-circuit unit is located, and the second region is opposite to the position where the second sub-circuit unit is located. The second turn-off power supply lines electrically connected to the first sub-circuit unit are located in the first region, and the second turn-off power supply lines electrically connected to the second sub-circuit unit are located in the second region.

5. The encapsulated chip according to claim 1, wherein The packaged chip further includes a power supply line group for power supply, which includes at least one first power supply line for power supply and at least one second power supply line for power supply. The first power supply line for power supply is arranged on the dielectric layer, and the second power supply line for power supply is arranged on the redistribution layer. The first power supply line for power supply and the second power supply line for power supply are sequentially electrically connected to the input end of the power switch unit. The second power supply line for power supply is used for electrically connecting a power supply module.

6. The encapsulated chip according to claim 5, wherein The packaged chip also includes a ground wire group, which includes at least one first ground wire and at least one second ground wire, the first ground wire is arranged in the dielectric layer, the second ground wire is arranged in the redistribution layer, the first ground wire and the second ground wire are electrically connected to the ground terminal of the functional circuit unit in sequence, and the second ground wire is used to electrically connect to the reference ground.

7. The encapsulated chip according to claim 6, wherein The packaged chip also includes at least one storage circuit unit and a storage power line group, the storage circuit unit is arranged in the dielectric layer, the storage power line group includes at least one first storage power line and at least one second storage power line, the first storage power line is arranged in the dielectric layer, and the second storage power line is arranged in the redistribution layer, the first storage power line and the second storage power line are electrically connected to the power supply end of the storage circuit unit in sequence, and the second storage power line is used to electrically connect the power supply module.

8. The encapsulated chip according to claim 7, wherein, The number of the second turnable power lines is multiple; the second turnable power lines are arranged between the second power supply line and the second ground line; and / or the second turnable power lines are arranged between the second power supply line and the second storage power line, and / or the second turnable power lines are arranged between the second ground line and the second storage power line.

9. The encapsulated chip according to claim 7, wherein, There are multiple second turnable power lines; there are multiple second power supply lines, and at least some of the second turnable power lines are arranged between the multiple second power supply lines; and / or, there are multiple second grounding lines, and at least some of the second turnable power lines are arranged between the multiple second grounding lines; and / or, there are multiple second storage power lines, and at least some of the second turnable power lines are arranged between the multiple second storage power lines.

10. The encapsulated chip according to claim 5, wherein The packaged chip further includes a packaging layer, which is stacked on a side of the redistribution layer away from the dielectric layer. The packaging layer is provided with at least one conductive portion, and the second power supply line is electrically connected to the power supply module via the conductive portion.

11. The encapsulated chip according to any one of claims 1 to 10, characterized in that, The first turnable power line is electrically connected to the second turnable power line through a conductive via.

12. The encapsulated chip according to any one of claims 1 to 10, characterized in that, The packaged chip also includes at least one control line, a first end of the control line is electrically connected to the control end of the power switch unit, a second end of the control line is used to electrically connect to a control module, and the control line is used to transmit a control signal sent by the control module to control the power switch unit to be turned on or off.

13. A circuit board assembly, characterized in that, It includes a circuit board, a power supply module, a control module and a packaged chip as described in any one of claims 1 to 12, wherein the power supply module, the control module and the packaged chip are all arranged on the circuit board, the power supply module is electrically connected to the packaged chip through the circuit board, and is used to supply power to the functional circuit unit, and the control module is electrically connected to the packaged chip through the circuit board, and is used to control the conduction and cutoff of the power switch unit.

14. An electronic device, characterized in that, Comprising the circuit board assembly of claim 13.

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