time delay

Abstract

Disclosed is a delay timer, the delay timer of the embodiment of the application has a series structure of a current source and a capacitor, and a control circuit changes the topological relation of the capacitor in the circuit according to the state (high level or low level) of an input signal, so that the charging and discharging of the capacitor voltage can be counted after the input signal jumps, and at the same time, the ground end of an inverting circuit used as a buffer circuit is connected to one end of the capacitor instead of a reference ground, so that the pull-up voltage (power supply voltage) can be introduced to affect the delay time of the delay timer, thereby reducing the negative influence of the fluctuation of the threshold voltage inherent in the inverting circuit on the accuracy of the delay time of the delay timer. The circuit structure of the delay timer of the embodiment of the application is simple, the number of components is small, and the delay precision is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a delay timer, especially an analog delay timer with accurate delay time. BACKGROUND

[0002] Delay timer (also known as Timer Delay Cell) is a common device in circuit design, especially in analog integrated circuit design or mixed integrated circuit design. It is used to delay the rising edge and / or falling edge of the input signal for a predetermined time and then output the original signal or the inverted signal.

[0003] The existing delay timer structure is complex, and the accuracy needs to be further improved. SUMMARY

[0004] Therefore, the purpose of the embodiments of the present application is to provide a delay timer to simplify the circuit structure and improve the accuracy of the delay timer.

[0005] The delay timer of the embodiments of the present application comprises:

[0006] A first current source connected to a pull-up voltage terminal;

[0007] A second current source connected to a reference ground;

[0008] A capacitor with a first end connected to the first current source and a second end connected between the second current source;

[0009] A first inverting circuit with an input end connected to the first end of the capacitor, a power supply terminal connected to the pull-up voltage terminal, and a ground terminal connected to the second end of the capacitor; and

[0010] A control circuit configured to receive an input signal, control the first end of the capacitor to be shorted to the reference ground and the second end to be shorted to the pull-up voltage terminal in response to the input signal being in a first state, and control the first end of the capacitor to be disconnected from the reference ground and the second end to be disconnected from the pull-up voltage terminal in response to the input signal being in a second state.

[0011] Further, the control circuit comprises:

[0012] A first switch connected between the reference ground and the first end of the capacitor;

[0013] A second switch connected between the pull-up voltage terminal and the second end of the capacitor;

[0014] An input logic circuit configured to control the first switch and the second switch to be turned on in response to the input signal being in the first state, and control the first switch and the second switch to be turned off in response to the input signal being in the second state.

[0015] Further, the delay timer further comprises:

[0016] a second inverting circuit, an input end of which is connected to an output end of the first direction circuit, a power supply end of which is connected to the pull-up voltage end, and a ground end of which is connected to a reference ground.

[0017] Further, the first current source is a P-type metal oxide semiconductor transistor, and the second current source is an N-type metal oxide semiconductor transistor; or,

[0018] the first current source and the second current source are transistors; or,

[0019] the first current source and the second current source are source degeneration current mirrors; or,

[0020] the first current source comprises and the second current source are voltage-to-current conversion circuits realized by using transistors and error amplifiers.

[0021] Further, the first inverting circuit is a comparator, one input end of the comparator is connected to the first end of the capacitor, and the other input end inputs an inverted threshold voltage.

[0022] Further, the first inverting circuit is a Schmitt trigger.

[0023] Further, a delay time of the delay timer is determined by current values of the first current source and the second current source and a capacitance value of the capacitor.

[0024] Further, the current values of the first current source and the second current source are the same or different.

[0025] Further, the delay timer is formed in an integrated circuit.

[0026] Further, a voltage of the pull-up voltage end is set to be greater than a threshold voltage of the first inverting circuit.

[0027] The technical scheme of the embodiment of the present application changes the topological relationship of the capacitor in the circuit according to different states (high level or low level) of the input signal through the series connection structure of the current source and the capacitor combined with the control circuit, so that the charging and discharging of the capacitor voltage can be counted after the input signal jumps, at the same time, the ground end of the inverting circuit used as a buffer circuit is connected to one end of the capacitor instead of the reference ground, so that the pull-up voltage (power supply voltage) can be introduced to affect the delay time, thereby reducing the negative influence of the fluctuation of the inherent threshold voltage of the inverting circuit on the precision of the delay time of the delay timer. The circuit structure of the delay timer of the embodiment of the present application is simple, the number of components is small, and the delay precision is high. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a circuit schematic diagram of a delay timer of the related art;

[0030] Figure 2 is a circuit schematic diagram of a delay timer of an embodiment of the present application;

[0031] Figure 3 is a working waveform diagram of the delay timer of the embodiment of the present application;

[0032] Figure 4 is a circuit schematic diagram of a delay timer of an alternative embodiment of the present application;

[0033] Figure 5 is a circuit schematic diagram of a delay timer of another alternative embodiment of the present application;

[0034] Figure 6 is a circuit schematic diagram of a delay timer of yet another alternative embodiment of the present application;

[0035] Figure 7 is a circuit schematic diagram of a delay timer of yet another alternative embodiment of the present application;

[0036] Figure 8 is a schematic diagram of a first inverting circuit of the delay timer of the embodiment of the present application;

[0037] Figure 9 is a schematic diagram of another implementation of the first inverting circuit of the delay timer of the embodiment of the present application. DETAILED DESCRIPTION

[0038] The present application is described herein below based on embodiments, but the present application is not limited to only these embodiments. In the following detailed description of the present application, some specific details are described in detail. The present application can be understood without the description of these details by those skilled in the art. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures, elements and circuits are not described in detail.

[0039] In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0040] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0041] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0042] Figure 1 This is a circuit diagram of a delay device based on a related technology. For example... Figure 1 As shown, in this related technology, the delay unit 1 includes resistors R1-R5, comparators CMP1 and CMP2, capacitor C1, RS flip-flop FF, and transistor BJT1. Resistor R1 is connected between the power supply terminal Vcc and the collector of transistor BJT1. The terminal connecting these two terminals can be referred to as the discharge terminal DS. The emitter of transistor BJT1 is connected to reference ground, and its base is connected to the output terminal OUTPUT of the delay unit. Resistor R2 is connected between the discharge terminal DS and the non-inverting input terminal TH of comparator CMP1. Resistors R3 and R4 are connected to the inverting input terminal of comparator CMP1. Resistor R3 is connected between the inverting input terminal of comparator CMP1 and the non-inverting input terminal of comparator CMP2. Resistor R4 is connected to the power supply terminal Vcc. Resistor R5 is connected between the non-inverting input terminal of comparator CMP2 and reference ground. Simultaneously, the non-inverting input terminal of comparator CMP1 and the inverting input terminal of comparator CMP2 are connected and connected to reference ground through capacitor C1. The output of comparator CMP1 is connected to the set terminal of RS flip-flop FF. The output of comparator CMP2 is connected to the reset terminal of RS flip-flop FF. The output of RS flip-flop FF is connected to the output terminal OUTPUT of the delay unit.

[0043] In the circuit of the delay timer 1, the transistor BJT1 is used as a switch. The resistors R4, R3 and R5 are connected in series between the power supply terminal Vcc and the reference ground, forming a voltage divider circuit to provide different threshold voltages for the inverting input terminal of the comparator CMP1 and the non-inverting input terminal of the comparator CMP2. In the initial state, the output terminal OUTPUT of the delay timer 1 is at low level, and the transistor BJT1 is in the off state. The power supply terminal Vcc charges the capacitor C1 through the resistors R1 and R2. The voltage of the capacitor C1 gradually rises. When the voltage of the capacitor C1 rises to the threshold voltage at the non-inverting input terminal of the comparator CMP1, the comparator CMP1 outputs high level, thereby setting the RS flip-flop FF and making the delay timer 1 output high level.

[0044] After the delay timer switches to output high level, the transistor BJT1 switches to the on state due to the change of the base voltage, thereby connecting the discharge terminal DS to the reference ground through the PN junction. The capacitor C1 discharges to the reference ground through the resistor R2, making the voltage at the inverting input terminal of the comparator CMP2 gradually decrease. When the voltage decreases to less than the threshold voltage at the non-inverting input terminal of the comparator CMP2, the comparator CMP2 outputs high level, thereby resetting the RS flip-flop FF and making the delay timer 1 switch to output low level.

[0045] Thus, the delay timer 1 periodically charges and discharges, thereby making the output periodically switch between low level and high level. The period of the output signal of the delay timer 1 can be used for delay operation.

[0046] However, the above delay timer of the related art needs to use multiple comparators, and has complex structure and large area. The delay timer with simpler structure in the prior art has the problem of low precision.

[0047] Therefore, the embodiments of the present application provide a delay timer with simple circuit structure and high precision.

[0048] Figure 2 is a circuit schematic diagram of the delay timer of the embodiments of the present application.

[0049] Reference Figure 2The delay timer 2 of the embodiment includes a first current source Id1, a second current source Id2, a capacitor C2, a first inverter INV1, a second inverter INV2, and a control circuit 21. For the convenience of understanding, the current source is denoted by the same reference numeral as the current value of its output. That is, the first current source Id1 outputs a current with a current value of Id1. The second current source Id2 outputs a current with a current value of Id2. The first current source Id1 is connected between a pull-up voltage terminal VDD and one end of the capacitor C2. The second current source Id2 is connected between the other end of the capacitor C2 and a reference ground. That is, the first current source Id1, the capacitor C2, and the second current source Id2 are actually connected in series between the pull-up voltage terminal VDD and the reference ground in sequence, regardless of the influence of other branches. The pull-up voltage terminal VDD is applied with a relatively constant voltage VDD to drive the delay timer circuit to work when the circuit is running. The input terminal of the first inverter INV1 is connected to the terminal of the capacitor C2 connected with the first current source Id1 (i.e., the first end or positive terminal of the capacitor C2). Meanwhile, the power supply terminal of the first inverter INV1 is connected to the pull-up voltage terminal VDD. Differently, the ground terminal of the first inverter INV1 is not connected to the reference ground, but is connected to the second end of the capacitor C2 (i.e., the negative terminal of the capacitor C2). The control circuit 21 is configured to control the connection state of the circuit between the two ends of the capacitor C2 according to an input signal VIN. In the embodiment, the input signal VIN has two different states, i.e., a low-level state and a high-level state (which can correspond to digital 0 and 1 respectively). In many scenarios (for example, in the control circuit of a switching converter), the input signal needs to be delayed by a delay timer in analog integrated circuits. In the embodiment, the control circuit 21 controls the first end Vcap+ of the capacitor C2 to be shorted to the reference ground and the second end Vcap- to be shorted to the pull-up voltage terminal VDD in response to the input signal being in a first state, and controls the first end Vcap+ of the capacitor C2 to be disconnected from the reference ground and the second end Vcap- to be disconnected from the pull-up voltage terminal VDD in response to the input signal being in a second state. The first state and the second state of the input signal are different states.

[0050] In the following description, the low-level state is referred to as 0 and the high-level state is referred to as 1 for the convenience of understanding. It is easy to understand that, in a specific implementation, the level state corresponding to 0 or 1 can be set in different ways. In some implementations, the first state is a low level and the second state is a high level. In other implementations, the first state is a high level and the second state is a low level.

[0051] When the input signal VIN is in the first state, the terminal Vcap+ in the circuit is connected to the reference ground, and the terminal Vcap- is connected to the pull-up voltage terminal VDD. In this case, the input of the first inverter INV1 is connected to the reference ground (i.e., the input is 0). Thus, the output of the first inverter INV1 is 1.

[0052] When the input signal VIN is switched from the first state to the second state, the control circuit 21 controls the terminal Vcap+ to be disconnected from the reference ground, and also controls the terminal Vcap- to be disconnected from the pull-up voltage terminal VDD. Thus, the capacitor C2 is connected in series between the first current source Idl and the second current source Id2, and the voltage across the capacitor C2 satisfies:

[0053] (boundary condition t=0, Vcap+=0)

[0054] (boundary condition t=0, Vcap-=VDD)

[0055] where c2 is the capacitance value of the capacitor C2. Further, the voltages across the capacitor C2 are respectively:

[0056] Vcap+=Idl*t / c2

[0057] Vcap-=(-Id2*t / c2)+VDD

[0058] Thus, the voltage drop Vcap of the capacitor satisfies:

[0059] Vcap=Vcap+-Vcpa-=(Idl+Id2)*t / c2-VDD

[0060] Since the ground terminal of the first inverter INV1 is referenced to Vcap-, the output of the first inverter INV1 is switched from 1 to 0 after Vcap rises to the inverting threshold voltage Vth of the first inverter. Thus, the output signal of the first inverter INV1 is switched in state after the interval time length tl after the input signal VIN is switched in state. The above time tl satisfies:

[0061] (Idl+Id2)*tl / c2-VDD=Vth

[0062] Thus, tl=(Vth+VDD)*c2 / (Idl+Id2)

[0063] Thus, the circuit of the present embodiment can effectively realize the delay output for the input signal switching. The length of the delay time is determined by the current of the first current source and the second current source, the capacitance value of the capacitor C2, and the inverting threshold voltage of the first inverting circuit INV1 and the power supply voltage VDD of the circuit. Since Idl, Id2 and VDD can be accurately provided in the actual circuit, the delay timer using the circuit structure of the present embodiment can accurately perform the delay operation at the sub-microsecond level.

[0064] A buffer or inverter with a ground terminal normally connected to the reference ground is further connected to the output terminal of the first inverting circuit INV1. Thus, the output signal of the first inverting circuit INV1 can be converted into a voltage signal relative to the reference ground through the device. It is easy to understand that when the device is set, the input voltage range for low level or high level should be basically adapted to the low voltage or high voltage range of the output voltage of the first inverting circuit INV1 to avoid logic errors of the circuit.

[0065] In an optional implementation, the delay timer only delays the rising edge signal of the input. In the delay timer circuit of the present embodiment, the delay timer further includes an odd number of second inverting circuits INV2, which are sequentially connected. The input terminal of the first second inverting circuit INV2 is connected to the output terminal of the first inverting circuit INV1. The input terminal of each subsequent second inverting circuit INV2 is connected to the output terminal of the previous second inverting circuit INV2. The ground terminal of each second inverting circuit INV1 is connected to the reference ground, and the power supply terminal is connected to the pull-up voltage terminal VDD. Figure 2 In the circuit shown, one second inverting circuit INV2 is provided. The input terminal thereof is connected to the output terminal of the first inverting circuit INV1. The output terminal serves as the output terminal of the delay timer, which outputs the delayed signal.

[0066] In another optional implementation, the delay timer can invert the signal while delaying. For example, the rising edge of the input signal is converted into a delayed falling edge. In this case, the delay timer can include an even number of second inverting circuits INV2. These inverting circuits can constitute a buffer to convert the output signal of the first inverting circuit INV1.

[0067] For the delay circuit of the present embodiment, the sum of the voltage VDD and the inverting threshold voltage Vth constitutes the influence on the delay time tl, which can weaken the dependence on the manufacturing accuracy of the first inverting circuit. Even if there is a fluctuation in the threshold voltage Vth of the first inverting circuit due to manufacturing errors, the influence caused by the fluctuation will be weakened by VDD. This improves the accuracy of the delay circuit to some extent. At the same time, the delay circuit device of the present embodiment has a small number of components, and thus can be realized in a very small size on an integrated circuit while maintaining good accuracy.

[0068] In one optional implementation, the control circuit 21 includes an input logic circuit 211, a first switch S1, and a second switch S2. The first switch S1 is connected between the reference ground and the first terminal Vcap+ of the capacitor, controlling the connection between the reference ground and the first terminal Vcap+. The second switch S2 is connected between the reference ground and the second terminal Vcap- of the capacitor, controlling the connection between the two. The input logic circuit 211 receives an input signal VIN. The input logic circuit 211 is configured to, in response to the input signal VIN being in a first state (e.g., 0), control the first switch S1 and the second switch S2 to be turned on, connecting terminal Vcap+ to the reference ground and terminal Vcap- to the pull-up voltage terminal VDD. The input logic circuit 211 is also configured to, in response to the input signal being in a second state (e.g., 1), control the first switch S1 and the second switch S2 to be turned off, disconnecting terminals Vcap+ and Vcap- from the reference ground and the pull-up voltage terminal VDD, respectively. The input logic circuit 211 can be constructed using a small number of logic gates or implemented using various programmable logic devices.

[0069] It should be understood that by setting the input and output logic of the input logic circuit 211, the control circuit 21 can implement different control logics. For example, the input logic circuit 211 can be set to control the first switch S1 and the second switch S2 to turn on when the input signal VIN is 0, and to control the first switch S1 and the second switch S2 to turn on when the input signal VIN is 1. The resulting operating waveform is shown below. Figure 3 As shown. In Figure 3 In the circuit, the input signal VIN has a rising edge s, and the output signal VOUT of the delay circuit is output after a delay of t1. That is, the rising edge of the output signal VOUT lags behind the rising edge of the input signal VIN by a time t1.

[0070] If the logic of input logic circuit 211 is set to turn on the first switch S1 and the second switch S2 when the input signal VIN is 1, and turn off the first switch S1 and the second switch S2 when the input signal VIN is 0, then the falling edge processing can be achieved. Simultaneously, by setting different numbers of second inverters, the level of the output signal VOUT can be made to be the same as or opposite to VIN.

[0071] Therefore, by using switches and flexibly configurable input logic circuits to construct the control circuit, different signals can be processed, making the delay device using the structure of this embodiment applicable to different scenarios and enabling the construction of different types of delay devices.

[0072] In this embodiment, the first current source and the second current source can be implemented in different ways.

[0073] Figure 4 is a circuit schematic diagram of a delay timer according to an optional implementation of an embodiment of the present application. In Figure 4 In the implementation shown, the current sources are implemented by metal-oxide-semiconductor transistors (MOSFETs). Among them, the first current source Idl is implemented by a P-channel MOSFET, and the second current source Id2 is implemented by an N-channel MOSFET. The source of the first current source Idl is connected to the pull-up voltage terminal VDD, and the drain is connected to the terminal Vcap+. The source of the second current source Id2 is connected to the reference ground, and the drain is connected to the terminal Vcap-. By controlling the voltage at the gate of the MOSFET, a relatively constant current flowing through the MOSFET can be achieved. Using MOSFETs to implement current sources has a simple structure and a small number of devices, which can reduce the area of the integrated circuit occupied by the delay timer.

[0074] Figure 5 is a circuit schematic diagram of a delay timer according to another optional implementation of an embodiment of the present application. In Figure 5 In the implementation shown, the current sources are implemented by bipolar junction transistors (BJTs). Among them, the first current source Idl is implemented by a PNP-type transistor, and the emitter is connected to the pull-up voltage terminal VDD, and the collector is connected to the terminal Vcap+. The second current source Id2 is implemented by an NPN-type transistor, and the emitter is connected to the reference ground, and the collector is connected to the terminal Vcap+. By controlling the voltage at the base of the two transistors, the transistors can be controlled to operate in the linear region, and different constant currents flowing through the two transistors can be achieved. Similar to using MOSFETs, using transistors to implement current sources has a simple structure and a small number of devices, which can reduce the area of the integrated circuit occupied by the delay timer.

[0075] Figure 6 is a circuit schematic diagram of a delay timer according to yet another optional implementation of an embodiment of the present application. In Figure 6 In the implementation shown, the current sources are implemented by a voltage-to-current conversion circuit including transistors and an error amplifier. This implementation can provide higher current accuracy, thereby further improving the accuracy of the delay timer. As shown in Figure 6As shown, the first current source Id1 includes a resistor R6, a P-channel metal oxide semiconductor transistor PM and an error amplifier EA1. The resistor R6 is connected between the source of the transistor PM and the pull-up voltage terminal VDD. The drain of the transistor PM is connected to the terminal Vcap+. The non-inverting input terminal of the error amplifier EA1 inputs a first reference voltage VREF1 corresponding to the current Id1, the inverting input terminal is connected to the source of the transistor PM, and the output terminal is connected to the gate of the transistor PM. Thus, when the current flows through the transistor PM, a voltage drop is formed on the resistor R6, and the voltage drop is larger when the current is larger. Since the voltage at one end of the resistor R6 is constant as VDD, the voltage at the other end varies with the current. The error amplifier EA1 compares the voltage at the source of the transistor PM with the first reference voltage VREF1 and outputs the difference between the two, thereby adjusting the gate of the transistor PM, so as to form a negative feedback circuit. Due to the presence of the error amplifier EA1, the voltage at the point where the resistor R6 is connected to the inverting input terminal of the error amplifier is equal to VREF1, so Id1=(VDD-VREF1) / R6, thereby making the current flowing through the transistor substantially constant at the above value.

[0076] Similarly, the second current source Id2 includes a resistor R7, an N-channel metal oxide semiconductor transistor NM and an error amplifier EA2. The resistor R7 is connected between the source of the transistor NM and the reference ground. The drain of the transistor NM is connected to the terminal Vcap-. The non-inverting input terminal of the error amplifier EA2 inputs a second reference voltage VREF2 corresponding to the current Id2, the inverting input terminal is connected to the source of the transistor NM, and the output terminal is connected to the gate of the transistor NM. Thus, a negative feedback circuit can be formed. Due to the presence of the error amplifier EA2, the voltage at the point where the resistor R7 is connected to the inverting input terminal of the error amplifier EA2 is equal to VREF2, so Id2=VREF2 / R7, thereby making the current flowing through the transistor substantially constant at the above value.

[0077] The first current source and the second current source of the present implementation have higher precision, and further improve the precision of the delay timer.

[0078] Figure 7 is a circuit schematic diagram of a delay timer according to another optional implementation of the embodiments of the present application. In the Figure 7 In the implementation shown, the current source is implemented by a source-degeneration current mirror. The source-degeneration current mirror is implemented by connecting a resistor in series to the source of a MOSFET. As shown in Figure 7As shown, the first current source Idl includes resistors R8, R10 and P-channel MOSFETs PMl and PM2. The second current source Id2 includes resistors R9, Rll and N-channel MOSFETs NMl and NM2. Resistor R8 is connected between the source of transistor PMl and the pull-up voltage terminal VDD. Resistor R10 is connected between the source of transistor PM2 and the pull-up voltage terminal VDD. The drain of transistor PMl is connected to terminal Vcap+. The drain of transistor PM2 is connected to its own gate. The gates of transistors PMl and PM2 are connected to each other. The drain of transistor PM2 is connected to one end of the current source.

[0079] Resistor R9 is connected between the source of transistor NMl and the reference ground. The drain of transistor NMl is connected to terminal Vcap-. Resistor Rll is connected between the source of transistor NM2 and the reference ground. The drain of transistor NM2 is connected to its own gate. The gates of transistors NMl and NM2 are connected to each other. The drain of transistor NM2 is connected to the other end of the current source.

[0080] That is, the current mirror composed of transistors PMl and PM2 and resistors R8 and R10 shares the current source with the current mirror composed of transistors NMl, NM2 and resistors R9 and Rll. The current source can be implemented by a MOSFET or other components. The structure of the present implementation utilizes the relationship between the current directions of the first current source and the second current source, so that the two current mirrors can share one current source to output current with higher precision. In this way, the precision of the delay timer can be improved without substantially increasing the number of devices.

[0081] Meanwhile, the first inverting circuit in the present embodiment can also be implemented in different ways. As shown in FIG. 4, the first inverting circuit can be implemented by a comparator. One input terminal of the comparator serves as the input terminal of the first inverting circuit INVl, and the other input terminal inputs a reference voltage VREF. The power supply terminal of the comparator is connected to the pull-up voltage terminal VDD, and the ground terminal is connected to terminal Vcap-. When the signal on the input terminal is 0, the input signal is compared with the reference voltage VREF, and if it is greater than the reference voltage VREF, one level is output, and if it is less than the reference voltage VREF, another level is output. Figure 8 In another implementation, as shown in FIG. 5, the first inverting circuit can be implemented by a transistor. The gate of the transistor is connected to terminal Vcap+, and the drain of the transistor is connected to the input terminal of the first inverting circuit INVl. The source of the transistor is connected to the reference ground.

[0082] Figure 9 ​As shown, the first inverter circuit can also be implemented by a Schmitt inverter. The Schmitt inverter outputs low when the input voltage is higher than a positive threshold voltage, outputs high when the input voltage is lower than a negative threshold voltage, and does not change when the input voltage is between the positive and negative threshold voltages. That is, the threshold voltages corresponding to the output transition from high to low or from low to high are different. The output changes only when the input voltage changes sufficiently. Using the Schmitt inverter as the first inverter circuit is suitable for the case where only the signal change edge in one direction needs to be delayed. In the present embodiment, only the rising edge or the falling edge is actually delayed, and therefore, the same effect as the inverter can be achieved by using the Schmitt inverter.

[0083] Thus, various devices can be used to build the delay circuit of the present embodiment, which is advantageous for integrating the delay circuit of the present embodiment on an integrated circuit chip, and the available devices on the chip can be flexibly used.

[0084] The technical solution of the present embodiment can change the topology of the capacitor in the circuit according to the different states (high or low) of the input signal by the control circuit, so that the charging and discharging of the capacitor voltage can be counted after the input signal jumps. Meanwhile, the ground of the inverter used as a buffer circuit is connected to one end of the capacitor instead of the reference ground, so that the pull-up voltage (power supply voltage) can be introduced to affect the delay time, thereby reducing the negative impact of the fluctuation of the threshold voltage of the inverter on the accuracy of the delay time of the delay device. The delay device of the present embodiment has a simple circuit structure, a small number of components, and high delay accuracy.

[0085] The above description is only the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A time delay device, characterized in that, The delay unit includes: The first current source is connected to the pull-up voltage terminal; The second current source is connected to the reference ground; A capacitor, with its first end connected to the first current source and its second end connected to the second current source; A first inverting circuit has its input terminal connected to the first terminal of the capacitor, its power supply terminal connected to the pull-up voltage terminal, and its ground terminal connected to the second terminal of the capacitor, such that the sum of the voltage at the pull-up voltage terminal and the threshold voltage of the first inverting circuit influences the delay time of the delay unit; and... A control circuit is used to receive an input signal, and in response to the input signal being in a first state, to control the first terminal of the capacitor to be shorted to a reference ground and the second terminal to be shorted to a pull-up voltage terminal; and in response to the input signal being in a second state, to control the first terminal of the capacitor to be disconnected from the reference ground and the second terminal to be disconnected from the pull-up voltage terminal.

2. The delay device according to claim 1, characterized in that, The control circuit includes: A first switch is connected between a reference ground and a first terminal of the capacitor; The second switch is connected between the pull-up voltage terminal and the second terminal of the capacitor; An input logic circuit is used to receive an input signal, and in response to the input signal being in a first state, control the first switch and the second switch to be turned on, and in response to the input signal being in a second state, control the first switch and the second switch to be turned off.

3. The delay device according to claim 1, characterized in that, The delay unit also includes: The second inverting circuit has its input terminal connected to the output terminal of the first inverting circuit, its power supply terminal connected to the pull-up voltage terminal, and its ground terminal connected to the reference ground.

4. The delay device according to claim 1, characterized in that, The first current source is a P-type metal-oxide-semiconductor transistor, and the second current source is an N-type metal-oxide-semiconductor transistor; or... The first current source and the second current source are transistors; or, The first current source and the second current source are source degradation current mirrors; or, The first current source includes and the second current source are voltage-to-current conversion circuits implemented using transistors and error amplifiers.

5. The delay device according to claim 1, characterized in that, The first inverting circuit is a comparator, with one input terminal of the comparator connected to the first terminal of the capacitor and the other input terminal receiving the inverting threshold voltage.

6. The delay device according to claim 1, characterized in that, The first inverting circuit is a Schmitt trigger.

7. The delay device according to claim 1, characterized in that, The delay time of the delay circuit is determined by the current values ​​of the first current source and the second current source, the voltage of the pull-up voltage terminal, the threshold voltage of the first inverting circuit, and the capacitance value of the capacitor.

8. The delay device according to claim 1, characterized in that, The current values ​​of the first current source and the second current source may be the same or different.

9. The delay device according to claim 1, characterized in that, The delay is formed in an integrated circuit.

10. The delay device according to claim 1, characterized in that, The voltage at the pull-up voltage terminal is set to be greater than the threshold voltage of the first inverting circuit.

Images