Comparators and their applications in analog-to-digital converters

Abstract

This invention discloses a comparator and an analog-to-digital converter (ADC) using the same. By employing a two-stage operational amplifier structure, latch offset and noise are reduced, thereby improving the comparator's accuracy. To reduce operational amplifier offset, an offset voltage cancellation stage is added. Simultaneously, a shorting stage is added to each bit of the analog-to-digital conversion, which keeps the output common-mode voltage at a certain value, thus increasing the comparator's speed and achieving a higher-performance comparator.

Description

Technical Field

[0001] This invention relates to power electronics technology, and more specifically, to a comparator and an analog-to-digital converter using the same. Background Technology

[0002] With the rapid development of science and technology, digital signal processing technology is increasingly widely used in various scientific and daily life fields. Digital systems process digital signals; however, signals in nature, such as temperature, pressure, speed, and sound—physical quantities frequently encountered in industrial detection and control and daily life—are continuously changing analog signals. To enable digital systems to process these analog signals, it is necessary to achieve mutual conversion between analog and digital signals. Analog-to-digital converters (ADCs) have become a key component connecting analog and digital systems.

[0003] As is well known, comparators are a crucial component of high-precision analog-to-digital converters (ADCs). Noise and offset are key factors affecting comparator accuracy. Many methods exist to eliminate offset, such as input and output storage techniques. However, these introduce capacitors into the signal path, and the parasitic parameters of the lower plate can reduce the value of the poles in the circuit, thus decreasing the phase margin. To address this, an auxiliary amplifier is typically added to isolate the signal path from the offset storage capacitor, thereby avoiding amplifier offset. However, two stages of amplifiers in the signal path are not ideal in high-speed amplifiers; summing the output voltages of amplifiers A1 and A2 is quite difficult. Furthermore, to increase comparator speed, the amplifier bandwidth also needs to be sufficiently large, thus increasing amplifier noise. Summary of the Invention

[0004] In view of this, the present invention provides a comparator and a high-precision analog-to-digital converter that can not only eliminate offset, but also further reduce noise by adding a short-circuit phase in each bit of the analog-to-digital conversion, thereby eliminating offset voltage and improving the comparison speed and accuracy of the comparator.

[0005] In a first aspect, a comparator is provided for use in an analog-to-digital converter, characterized in that it comprises:

[0006] The pre-amplifier circuit consists of two cascaded operational amplifiers used to amplify the input signal;

[0007] A latching circuit is used to determine the output result of the comparator based on the output voltage of the pre-amplifier circuit.

[0008] Specifically, a short-circuit stage is added to each bit of the analog-to-digital conversion process of the analog-to-digital converter. By short-circuiting and resetting the output of the operational amplifier, the speed of the comparator is improved.

[0009] Preferably, each operational amplifier has an input controllable switch for controlling whether its input signal is connected to the operational amplifier, an input shorting controllable switch for controlling whether its input terminal is shorted, and an output shorting controllable switch for controlling whether its output terminal is shorted.

[0010] Preferably, when the analog-to-digital converter is operating in the sample-and-hold phase, the comparator enters the auto-zero phase and stores the offset voltage on the offset capacitor coupled to the output of the operational amplifier during this phase.

[0011] Preferably, during the automatic zeroing phase of the comparator, the input terminal of the operational amplifier is shorted by the input shorting controllable switch to store the offset voltage on the offset capacitor coupled to the output terminal of the operational amplifier.

[0012] Preferably, during each conversion step of the analog-to-digital converter in the analog-to-digital conversion stage, the comparator has a short-circuit stage in which the output terminal of the operational amplifier is shorted through the output short-circuit controllable switch, so that the output voltage of the operational amplifier can change from a predetermined level at each conversion step, thereby improving the comparison speed of the comparator.

[0013] Preferably, the input controllable switch is turned on during the short-circuit phase of the comparator.

[0014] Preferably, during the conversion of each bit of the analog-to-digital converter in the analog-to-digital conversion stage, and after the short-circuit stage, the comparator has a pre-amplification stage in which the pre-amplification circuit amplifies the input signal to improve the comparison accuracy of the comparator, wherein the duration of the pre-amplification stage is a first time.

[0015] Preferably, during the pre-amplification stage of the comparator, the input controllable switch is turned on, and both the input short-circuit controllable switch and the output short-circuit controllable switch are turned off.

[0016] Preferably, the latch circuit is not operational during the pre-amplification phase of the comparator.

[0017] Preferably, during the conversion of each bit of the analog-to-digital converter in the analog-to-digital conversion stage, and after the large-scale prevention stage, the comparator has a conversion stage in which the latch circuit determines the output result of the comparator based on the output voltage of the pre-amplification circuit, wherein the duration of the conversion stage is a second time.

[0018] Preferably, during the conversion phase of the comparator, the input controllable switch is turned on, and both the input short-circuit controllable switch and the output short-circuit controllable switch are turned off.

[0019] Preferably, when the analog-to-digital converter operates in synchronous timing, the sum of the first time and the second time is fixed; when the analog-to-digital converter operates in asynchronous timing, the sum of the first time and the second time is not fixed.

[0020] Preferably, the operational amplifier further includes a common-mode feedback circuit, which is used to maintain the common-mode level of the operational amplifier output within a predetermined value or a predetermined range.

[0021] Preferably, the common-mode feedback circuit is in operation at least during the short-circuit phase.

[0022] Preferably, the operational amplifier further includes an offset controllable switch that couples the offset capacitor to the output of the operational amplifier, and the offset controllable switch is turned on only when the analog-to-digital converter is operating in the sample-and-hold phase.

[0023] Secondly, an analog-to-digital converter is provided, comprising:

[0024] Capacitor array;

[0025] The comparator mentioned above, and,

[0026] Successive approximation logic circuits.

[0027] The technical solution of the present invention adds a short-circuit stage to each bit of the analog-to-digital conversion, thereby improving the speed of the comparator, obtaining a higher performance comparator, and at the same time eliminating offset voltage, reducing noise, and improving the speed and accuracy of the comparator. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0029] Figure 1 This is a structural diagram of a comparator according to an embodiment of the present invention;

[0030] Figure 2 This is a timing diagram of a comparator according to an embodiment of the present invention;

[0031] Figure 3 This is a circuit diagram of an operational amplifier according to an embodiment of the present invention;

[0032] Figure 4 This is a circuit diagram of an operational amplifier according to another embodiment of the present invention. Detailed Implementation

[0033] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0034] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0035] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0036] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0037] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0038] Figure 1 A schematic diagram of a comparator according to an embodiment of the present invention is shown. Figure 1As shown, comparator 1 includes a pre-amplifier circuit 11 and a latch circuit 12. The pre-amplifier circuit 11 includes a cascaded first operational amplifier AMP1 and a second operational amplifier AMP2, as well as multiple controllable switches. These controllable switches include a pair of first controllable switches S1 (input controllable switches), a pair of second controllable switches S2 (input short-circuit controllable switches), a pair of third controllable switches S3 (input controllable switches), a pair of fourth controllable switches S4 (input short-circuit controllable switches), a fifth controllable switch S5 (output short-circuit controllable switch), and a sixth controllable switch S6 (output short-circuit controllable switch). These controllable switches are controlled to be turned on or off. (Reference) Figure 1 The first operational amplifier AMP1 is used to receive the common-mode voltage Vdac output from the capacitor array in the analog-to-digital converter using the comparator. Specifically, a pair of first controllable switches S1 are respectively connected to the two input terminals of the first operational amplifier AMP1 to control whether the common-mode voltage Vdac is connected to the two input terminals of the first operational amplifier AMP1. One end of a pair of second controllable switches S2 is respectively connected to the two input terminals of the first operational amplifier AMP1, and the other end is connected to the first common-mode voltage VCM1. The fifth controllable switch S5 is connected to the output terminal of the first operational amplifier AMP1 to short-circuit the output of the first operational amplifier AMP1. The second operational amplifier AMP2 is used to receive the signal output by the first operational amplifier AMP1. Specifically, a pair of third controllable switches S3 are respectively connected to the two input terminals of the second operational amplifier AMP2 to control whether the signal output by the first operational amplifier AMP1 is connected to the two input terminals of the second operational amplifier AMP2. One end of a pair of fourth controllable switches S4 is respectively connected to the two input terminals of the second operational amplifier AMP2, and the other end is connected to the second common-mode voltage VCM2. The sixth controllable switch S5 is connected to the output terminal of the second operational amplifier AMP2 to short-circuit the output terminal of the second operational amplifier AMP2.

[0039] In this embodiment, the latch circuit 12 can be a conventional dynamic comparator connected to the output of the pre-amplifier circuit 11. To achieve automatic zeroing to eliminate offset, the input value of the operational amplifier needs to be equal to an appropriate common-mode voltage. Therefore, a first common-mode voltage VCM1 is also connected to the input of the first operational amplifier AMP1, and a second common-mode voltage VCM2 is also connected to the input of the second operational amplifier AMP2. Preferably, the first operational amplifier AMP1 and the second operational amplifier AMP2 have identical circuit structures; for example, both employ... Figure 3 The circuit structure shown is shown in the figure.

[0040] Figure 2 The following is a timing diagram of a comparator according to an embodiment of the present invention. Specifically, it is described below in conjunction with... Figure 1The diagram shown illustrates the structure of the comparator and its four operating stages.

[0041] (a) Automatic Zeroing Stage: When the analog-to-digital converter using the comparator is operating in the sample-and-hold stage, comparator 1 enters the offset voltage elimination stage. At this time, controllable switches S1, S3, S5, and S6 in comparator 1 are open, while controllable switches S2 and S4 are closed. The first common-mode voltage VCM1 is connected to the input terminal of the first operational amplifier AMP1, and the second common-mode voltage VCM2 is connected to the input terminal of the second operational amplifier AMP2. Simultaneously, combined with... Figure 3 The circuit diagram of the first operational amplifier AMP1 is shown. In this stage, Figure 3 When controllable switches S7 and S8 (offset controllable switches) are turned on, the first operational amplifier AMP1 begins to store the offset voltage at its first output terminal on1 and second output terminal op1, i.e., the upper plates of the first offset capacitor C1 and the second offset capacitor C2. Of course, since the first operational amplifier AMP1 and the second operational amplifier AMP2 have identical circuit structures in this embodiment, similarly, switches S9 and S10 in the second operational amplifier AMP2 are turned on (corresponding to controllable switches S7 and S8, not shown in the attached diagram) to begin storing the offset voltage at the first output terminal on2 and second output terminal op2, i.e., the upper plates of the third offset capacitor C3 and the fourth offset capacitor C4 (corresponding to the first offset capacitor C1 and the second offset capacitor C2, not shown in the attached diagram). Controllable switches S7 and S8 in the first operational amplifier AMP1 and S9 and S10 in the second operational amplifier AMP2 are only turned on during this stage to store the offset voltage at the output terminals of the operational amplifiers.

[0042] Then, in the subsequent operating phase of comparator 1 (in phase (c) of this invention), depending on the different input offset voltages, such that... Figure 3 Different currents flow through PMOS transistors M3 and M4, and the negative feedback loop of M3 and M4 is used to offset part of the offset voltage.

[0043] (b) Short-circuit stage: After the sampling and holding period ends, the analog-to-digital converter enters the conversion stage. At this time, controllable switches S1, S3, S5, and S6 in comparator 1 are turned on, and controllable switches S2 and S4 are turned off. The capacitor array C in the analog-to-digital converter... DACUpon startup, the SAR logic (Successive Approximation Logic Circuit) enters the successive approximation state. During this stage, the first output terminal (on1) and the second output terminal (op2) of the first operational amplifier AMP1 are shorted, resetting its output value. Comparator 1 then enters the short-circuit stage. At this time, the common-mode feedback circuit (CMFB) in the first operational amplifier AMP1 begins to operate, maintaining the common-mode level of the first operational amplifier AMP1 output at the first common-mode voltage VCM1. This ensures that the output of the first operational amplifier AMP1 changes from the common-mode level VCM1 at each conversion step. This short-circuit stage is added to each conversion step of the analog-to-digital converter (ADC) to short-circuit and reset the output voltage of the first operational amplifier AMP1. Similarly, the output voltage of the second operational amplifier AMP2 is also short-circuited and reset, thereby improving the comparison speed of comparator 1.

[0044] (c) Pre-amplification stage: When the capacitor array C in the analog-to-digital converter... DAC After stabilization, the pre-amplification circuit 11 in comparator 1 first starts working to amplify the input signals VIP-VIN, enabling the latch circuit 12 to compare faster and more accurately, thereby improving the comparison accuracy of comparator 1. The input signals VIP and VIN are connected to the two input terminals of the first operational amplifier AMP1. During this stage, controllable switches S1 and S3 in comparator 1 are turned on, while S2, S4, S5, and S6 are turned off. Comparator 1 begins amplifying the input signals for the first time, T1. At this time, the dynamic latch circuit 12 is temporarily not working. Throughout the entire ADC conversion cycle, the first time T1 may remain constant or inconsistent during each bit conversion process.

[0045] (d) Conversion stage: Comparator 1 starts to compare. After comparator 1 amplifies for time T1, controllable switches S1 and S3 continue to be turned on, while controllable switches S2, S4, S5 and S6 continue to be turned off. Latch circuit 12 starts to work and determines that the output result of comparator 1 is 1 / 0. The working time of this stage is the second time T2.

[0046] The comparator 1 in this embodiment can be applied in both synchronous and asynchronous sequential analog-to-digital converters. If the SAR logic is synchronous, T1+T2 is fixed; if it is asynchronous, T1+T2 is not fixed because the conversion period of each bit is different. T1 and T2 are defined according to the specific design and are not limited here.

[0047] It should be noted that in one conversion cycle of an analog-to-digital converter, there may be only one auto-zeroing stage (a), but in each conversion process of one conversion cycle, there are (b) shorting stage (b), preamplifier amplification stage (c) and conversion stage (d).

[0048] Furthermore, taking the first operational amplifier AMP1 as an integrating amplifier as an example, Figure 3 A schematic diagram of an integrating amplifier is shown. This circuit is implemented using a folded common-source common-gate operational amplifier. The source of MOSFET M14 is connected to the input power supply voltage Vdd. MOSFETs M13, M14, and M15 are current mirrors, and the drains of MOSFETs M13, M14, and M15 are grounded. The gates of MOSFETs M1 and M2 are connected to the input signals VIP and VIN of the first operational amplifier. The gates of MOSFETs M5 and M6 are connected to a third bias voltage VN1. M5 and M6 are designed to isolate flyback noise and improve comparator gain. MOSFETs M7, M8, M11, and M12 are cascaded loads, which can increase the output impedance R of the integrating amplifier. out To improve its gain, a first bias voltage VBP1 is applied to the gates of MOSFETs M7 and M8, and a second bias voltage VBP2 is applied to the gates of MOSFETs M11 and M12 to ensure normal circuit operation. The first operational amplifier AMP1 also includes a first offset capacitor C1 and a second offset capacitor C2, which are coupled to the first output terminal on1 and the second output terminal op1 of the first operational amplifier AMP1 respectively through the seventh controllable switch S7 and the eighth controllable switch S8. The sources of MOSFETs M3 and M4 are connected to the input power supply voltage Vdd. The current of MOSFETs M3 and M4 flows through MOSFETs M1 and M2. MOSFETs M9 and M10 are cascode transistors, forming a cascode structure to increase output impedance and improve gain. The first operational amplifier AMP1 also includes a common-mode feedback circuit CMFB. The CMFB aims to maintain the common-mode level of the output of the first operational amplifier AMP1 to prevent common-mode level drift after many bit conversions during the conversion stage, thus affecting circuit operation. This integrating amplifier structure does not require the common-mode feedback circuit (CMFB) to operate continuously. The CMFB is used to adjust the common-mode level, and it can operate only in the short-circuit phase, i.e., when... Figure 1 Controllable switches S1, S3, S5, and S6 are on, while S2 and S4 are off. Figure 3 When the controllable switches S7 and S8 are open, the common-mode feedback circuit CMFB is working. By adjusting the current flowing through the MOSFET M15, the output common-mode level is maintained at vdd-vgs3, where vgs3 is the gate-source voltage of the MOSFET M3.

[0049] At the same time, it should be understood that the structure and working principle of the second operational amplifier AMP2 are similar to those of the first operational amplifier AMP1, and will not be described in detail here.

[0050] Furthermore, the offset voltage elimination method of the present invention is specifically as follows: Figure 3Taking the offset voltage elimination method in the structure of the first operational amplifier AMP1 as an example, assuming the offset voltage Vos2 at MOSFETs M3 and M4, the specific calculation method is as follows:

[0051] Output voltage Vout1=[G M1 Vos1-G M3 (Vout1-Vos2)]*R out ,

[0052] Where Vos1 is the offset voltage at the input terminal, R out For the output impedance, G M1 G M3 Let M1 and M3 be the conductances of MOSFETs respectively. After simplifying the above equation, we have:

[0053] Vout1 = (Vos1G) M1 R out +Vos2G M3 R out ) / (1+G M3 R out );

[0054] When the comparator is operating in the auto-zeroing phase Figure 3 Controllable switches S7 and S8 are turned on, while G M3 R out >>1, therefore

[0055] Vout1 = G M1 / G M3 *Vos1+Vos2,

[0056] Because the charges injected into the offset capacitors C1 and C2 may not be completely equal at the moment S7 and S8 are disconnected, an uncorrectable error voltage is generated at the gates of MOSFETs M3 and M4 due to the open feedback loop. Assuming the error voltage is ΔX, its equivalent error voltage at the output is ΔVout1 = G. M3 R out *ΔX,

[0057] At this time, Vout1 = G M1 / G M3 *Vos1+Vos2+G M3 R out *ΔX,

[0058] After the automatic zeroing phase, comparator 1 begins pre-amplification, controllable switches S7 and S8 are opened, and the offset voltage is stored in offset capacitors C1 and C2. For the input terminal, the equivalent input noise is:

[0059] V input,offset=Vos1 / G M3 R out +Vos2 / G M1 R out +G M3 / G M1 *ΔX,

[0060] Therefore, in order to obtain a smaller equivalent input noise V input,offset To better eliminate imbalance, R out G M1 The values ​​of are all relatively large, thus resulting in a smaller G. M3 / G M1 .

[0061] This invention also provides another embodiment of the operational amplifier structure, the circuit diagram of which is shown below. Figure 4 As shown. This embodiment is similar to... Figure 3 The only difference of the integrating amplifier shown is that it can adjust the self-biased load and does not require additional bias voltages such as VBP1 and VBP2. Simply connect the gate of MOSFET M7 to the gate of MOSFET M12 and the gate of MOSFET M8 to the gate of MOSFET M11, and the integrating amplifier will still work normally.

[0062] The present invention also provides a high-precision analog-to-digital converter, which includes the comparator described above, and can achieve offset voltage elimination and improve the speed and accuracy of analog-to-digital conversion.

[0063] This invention employs a two-stage operational amplifier structure to reduce latch offset and noise, thereby improving the comparator's accuracy. To reduce operational amplifier offset, offset voltage cancellation technology is used. Furthermore, a shorting stage is added to each bit of the analog-to-digital converter to maintain the output common-mode voltage at a certain value, thus increasing the comparator's speed and achieving a higher-performance comparator.

[0064] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A comparator for use in an analog-to-digital converter, characterized by The application relates to a comparator of an analog-to-digital converter, comprising: a pre-amplification circuit composed of two cascaded operational amplifiers, used to amplify an input signal; a latch circuit used to determine the output result of the comparator according to the output voltage of the pre-amplification circuit; wherein a short-circuit stage is added in each bit conversion process of the analog-to-digital conversion stage of the analog-to-digital converter, and the output end of the operational amplifier is short-circuited to reset the output end, so as to improve the speed of the comparator; when the analog-to-digital converter works in the sample-hold stage, the comparator enters an automatic zero adjustment stage, and the offset voltage is stored on an offset capacitor coupled with the output end of the operational amplifier in the stage, wherein one end of the offset capacitor receives an input power supply voltage, and the other end is coupled with the output end of the operational amplifier through a controllable switch.

2. The comparator of claim 1, wherein, The input end of each operational amplifier has an input controllable switch used to control whether the input signal is connected to the operational amplifier, an input short-circuit controllable switch used to control whether the input end is short-circuited, and an output short-circuit controllable switch used to control whether the output end is short-circuited.

3. The comparator of claim 2, wherein, During the automatic zero adjustment stage of the comparator, the input end of the operational amplifier is short-circuited through the input short-circuit controllable switch, so as to store the offset voltage on the offset capacitor coupled with the output end of the operational amplifier.

4. The comparator of claim 2, wherein, During the analog-to-digital conversion stage of the analog-to-digital converter, the comparator has a short-circuit stage, in which the output end of the operational amplifier is short-circuited through the output short-circuit controllable switch, so that the output voltage of the operational amplifier can start to change from a predetermined level in each bit conversion, thereby improving the comparison speed of the comparator.

5. The comparator of claim 4, wherein, During the short-circuit stage of the comparator, the input controllable switch is turned on.

6. The comparator of claim 4, wherein, During the analog-to-digital conversion stage of the analog-to-digital converter, and after the short-circuit stage, the comparator has a pre-amplification stage, in which the pre-amplification circuit amplifies the input signal, so as to improve the comparison accuracy of the comparator, and the duration of the pre-amplification stage is a first time.

7. The comparator of claim 6, wherein, During the pre-amplification stage of the comparator, the input controllable switch is turned on, and the input short-circuit controllable switch and the output short-circuit controllable switch are turned off.

8. The comparator of claim 6, wherein, During the pre-amplification stage of the comparator, the latch circuit does not work.

9. The comparator of claim 6, wherein, During the analog-to-digital conversion stage of the analog-to-digital converter, and after the pre-amplification stage, the comparator has a conversion stage, in which the latch circuit determines the output result of the comparator according to the output voltage of the pre-amplification circuit, and the duration of the conversion stage is a second time.

10. The comparator of claim 9, wherein, During the conversion stage of the comparator, the input controllable switch is turned on, and the input short-circuit controllable switch and the output short-circuit controllable switch are turned off.

11. The comparator of claim 9, wherein, When the analog-to-digital converter operates in synchronous timing, the sum of the first time and the second time is fixed; when the analog-to-digital converter operates in asynchronous timing, the sum of the first time and the second time is not fixed.

12. The comparator of claim 1, wherein, The operational amplifier further comprises a common-mode feedback circuit to maintain the common-mode level of the operational amplifier output at a predetermined value or a predetermined range.

13. The comparator of claim 12, wherein, The common-mode feedback circuit is in operation at least at the shorting phase.

14. The comparator of claim 1, wherein, The operational amplifier further has a mismatch controllable switch to couple the mismatch capacitor to the output of the operational amplifier, and the mismatch controllable switch is only turned on when the analog-to-digital converter operates in a sample-and-hold phase.

15. An analog-to-digital converter, comprising: a capacitor array; the comparator of any one of claims 1-14, and successive approximation logic circuitry.

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