Semiconductor integrated circuit for power supply

Abstract

A power supply semiconductor integrated circuit includes a first abnormality detection circuit, a second abnormality detection circuit, a delay circuit that delays an output of the first abnormality detection circuit and an output of the second abnormality detection circuit, and a latch circuit that takes in and holds an output of the delay circuit. The delay circuit includes a constant current source that charges a delay capacitor, a switching unit that discharges the delay capacitor, and a voltage comparison circuit that compares a charged voltage of the delay capacitor with a predetermined voltage. The charging of the delay capacitor is started in accordance with a change in a state indicating an abnormality in the output of the first abnormality detection circuit or an abnormality in the output of the second abnormality detection circuit. When the voltage comparison circuit determines that the charged voltage of the delay capacitor reaches the predetermined voltage, an output is changed, and the delay capacitor is discharged by taking the output into the latch circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to a technology effective in use in a power supply semiconductor integrated circuit (power supply IC) for a voltage regulator such as a series regulator that converts a direct-current voltage or a power supply switch that directly supplies or cuts off a voltage of a power supply device to a load. BACKGROUND

[0002] As a power supply device that outputs a desired potential of a direct-current voltage by controlling a transistor provided between a direct-current voltage input terminal and an output terminal, there is a series regulator (hereinafter, simply referred to as a regulator).

[0003] In a regulator for a vehicle, a car navigation system or the like is connected to the regulator by a connector. Therefore, the connector is sometimes detached due to vibration of a vehicle body, an output terminal of a power supply becomes open, or a short circuit occurs in the inside of an electronic device as a load. Therefore, it is required that the regulator for a vehicle has a function of detecting such abnormal states.

[0004] Therefore, for example, as shown in Figure 6 , an invention related to a regulator semiconductor integrated circuit (regulator IC) is proposed, which is configured to provide a comparator CMP1 for detecting an open state of an output terminal, a comparator CMP2 for detecting a short circuit state, and a delay circuit DLY for delaying outputs of the open abnormality detection circuit and the short circuit abnormality detection circuit, and to generate abnormality detection signals Err_op and Err_sc from the delayed signals and output them from the output terminal (Patent Documents 1 and 2). The delay circuit is provided to avoid erroneous output of the abnormality detection signal from the short circuit abnormality detection circuit due to inflow of an impact current to a capacitor Co connected to the output terminal at the start of operation.

[0005] In the regulator IC with the delay circuit shown in Figure 6 , when a load device of the output terminal OUT shifts from an unconnected state to a connected state, a voltage VCD of an external terminal CD to which a capacitor Cd for delay setting is connected rises to a considerably high voltage, and thus there is a problem that the discharge time is insufficient for a period Td as shown in (A) of Figure 7 , elimination of the open state of the output terminal cannot be detected, and a false detection pulse EP1 appears in the short circuit abnormality detection signal Err_sc. In addition, when the load device shifts from a short circuit state to a state in which the short circuit is eliminated, the discharge time of the capacitor for delay setting is also insufficient and detection of elimination of the short circuit cannot be performed, as shown in (B) of Figure 7As shown in (B) of FIG. 6, it is found that there is a problem that a false detection pulse EP2 occurs in the open-circuit abnormality detection signal Err_op. In addition, the same problem occurs in a power supply switch IC having a similar structure to the above-described regulator IC, which directly supplies or cuts off the voltage of a power supply device (a battery or the like) to a load.

[0006] Patent Literature 1: Japanese Patent Application Publication No. 2017-45096

[0007] Patent Literature 2: Japanese Patent Application Publication No. 2018-55545 SUMMARY

[0008] The present application has been made in view of the above-described problems, and has an object to provide a power supply IC (regulator IC, power supply switch IC) in which a false detection pulse does not occur in an abnormality detection signal when an abnormal state is eliminated, in a power supply IC having a circuit that detects two or more kinds of abnormalities such as a short-circuit abnormality and an open-circuit abnormality of an output terminal and a delay circuit that delays an abnormality detection signal.

[0009] Another object of the present application is to provide a power supply IC (regulator IC, power supply switch IC) that can detect an abnormality such as a fall of a delay setting capacitor from an external terminal and output an abnormality detection signal to the outside.

[0010] To achieve the above object, the present application provides a power supply semiconductor integrated circuit including: an output transistor connected between a voltage input terminal to which a direct-current voltage is input and an output terminal; and a control circuit that controls the output transistor, wherein the power supply semiconductor integrated circuit includes:

[0011] a first abnormality detection circuit that detects a first abnormal state;

[0012] a second abnormality detection circuit that detects a second abnormal state different from the first abnormal state;

[0013] a delay circuit that delays an output of the first abnormality detection circuit and an output of the second abnormality detection circuit; and

[0014] a latch circuit that takes in and holds the output of the delay circuit,

[0015] the delay circuit includes: a constant current source that charges a delay capacitor; a switching unit that discharges the delay capacitor; and a voltage comparison circuit that compares a charged voltage of the delay capacitor with a predetermined voltage.

[0016] According to the semiconductor integrated circuit for power supply having the above-described structure, when the charging voltage of the delay capacitor is determined to reach the predetermined voltage, the output of the voltage comparison circuit changes, and the delay capacitor is discharged by taking the output into the latch circuit, so that the charging voltage of the delay capacitor can not become excessively high, and thus, for example, in a power IC such as a regulator IC or a power switch IC having a circuit that detects two or more kinds of abnormality such as short-circuit abnormality or open-circuit abnormality of the output terminal and a delay abnormality detection signal, when the abnormal state is eliminated, false detection pulses can not be generated in the abnormality detection signal.

[0017] Here, preferably, the first abnormality detection circuit is a circuit that detects a short-circuit state of the output terminal, and the semiconductor integrated circuit for power supply is configured to: start charging of the delay capacitor in accordance with a change to a state indicating abnormality of the output of the first abnormality detection circuit or the output of the second abnormality detection circuit, when the voltage comparison circuit determines that the charging voltage of the delay capacitor reaches the predetermined voltage, the output changes, and the delay capacitor is discharged by taking the output into the latch circuit and turning on the switching unit.

[0018] Further, preferably, the semiconductor integrated circuit for power supply includes a voltage upper limit limiting unit that limits the upper limit of the charging voltage of the delay capacitor.

[0019] According to this structure, the upper limit of the charging voltage of the delay capacitor can be limited by the voltage upper limit limiting unit (clamp circuit), so that the time required for discharging the delay capacitor can be shortened, and thus false detection pulses of the abnormality detection signal can be prevented.

[0020] Further, preferably, the voltage upper limit limiting unit is a transistor connected between the charging side terminal of the delay capacitor and the ground, and a predetermined voltage is applied to the control terminal of the transistor when the internal circuit including the control circuit operates.

[0021] According to this structure, when the power IC is turned off or the like and the operation of the internal circuit stops, the voltage of the control terminal (gate terminal) of the transistor (P-MOS) drops to make the transistor in an on state, so that the charging charge of the delay capacitor can be rapidly discharged, and false operation at the time of turning on of the power IC thereafter can be avoided. In addition, the capacitor can be discharged when the power semiconductor integrated circuit is turned off.

[0022] Further, preferably, the second abnormality detection circuit is a circuit that detects an open-circuit state of the output terminal,

[0023] The power-supply semiconductor integrated circuit has a first transistor and a second transistor that are arranged in parallel with the output transistor and that pass currents that are proportional to and reduced from the current passing through the output transistor,

[0024] The first abnormality detection circuit includes a first voltage comparison circuit that compares a voltage converted from the current passing through the first transistor with a predetermined comparison voltage to determine the magnitude,

[0025] The second abnormality detection circuit includes a second voltage comparison circuit that compares a voltage converted from the current passing through the second transistor with a predetermined comparison voltage to determine the magnitude,

[0026] The first voltage comparison circuit outputs a signal indicating a short-circuit abnormality when a current larger than a predetermined short-circuit abnormality detection current value flows through the first transistor, and the second voltage comparison circuit outputs a signal indicating an open-circuit abnormality when a current smaller than a predetermined open-circuit abnormality detection current value flows through the second transistor.

[0027] According to the above-described configuration, in the power-supply IC that includes a circuit that detects the short-circuit state of the output terminal and a circuit that detects the open-circuit state, when the short-circuit abnormality and the open-circuit abnormality are eliminated, the abnormality detection signal can be prevented from generating a false detection pulse.

[0028] In addition, preferably, the power-supply semiconductor integrated circuit includes a first output terminal that outputs the detection result of the first abnormality detection circuit to the outside,

[0029] a second output terminal that outputs the detection result of the second abnormality detection circuit to the outside, and

[0030] a delay time abnormality detection circuit that detects whether the delay time of the delay circuit is within a predetermined time range that is set in advance,

[0031] In a case where the delay time abnormality detection circuit detects an abnormality in the delay time, a signal indicating that an abnormality is detected is output from the first output terminal and the second output terminal.

[0032] According to this configuration, it is possible to detect that an abnormality such as the detachment of the delay-setting capacitor from the external terminal has occurred and to output an abnormality detection signal to the outside.

[0033] According to the present application, in a power supply IC such as a regulator IC and a power supply switch IC provided with two or more kinds of abnormality such as a short-circuit abnormality and an open-circuit abnormality of a detection output terminal and a delay circuit that delays an abnormality detection signal, when an abnormal state is eliminated, false detection pulses are not generated in the abnormality detection signal. In addition, there is an effect that a power supply IC (regulator IC, power supply switch IC) that can detect an abnormality such as a delay capacitor set for delay falling off from an external terminal and output an abnormality detection signal to the outside can be implemented. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a circuit configuration view that shows an embodiment of a regulator IC to which the present application is applied.

[0035] Figure 2 is a view that shows a voltage change of each part of the regulator IC of Figure 1 , (A) is a timing chart in a case where an open-circuit abnormality is eliminated after the open-circuit abnormality occurs, and (B) is a timing chart in a case where a short-circuit abnormality is eliminated after the short-circuit abnormality occurs.

[0036] Figure 3 is a circuit configuration view that shows a modification example of the regulator IC of Figure 1

[0037] Figure 4 is a view that shows a change in each voltage in a case where a short-circuit state is shifted from an open-circuit state in the IC of the modification example of Figure 3 , (A) is a timing chart in a case where a delay capacitor is connected to an external terminal, and (B) is a timing chart in a case where there is an abnormality in the delay circuit such as the delay capacitor falling off.

[0038] Figure 5 (A) of is a circuit configuration view that shows a structure example of a general power supply switch IC, and (B) is a circuit configuration view that shows a structure example of an IC in a case where the present application is applied to a power supply switch IC provided with an open-circuit abnormality detection circuit and a short-circuit abnormality detection circuit.

[0039] Figure 6 is a circuit configuration view that shows an example of a conventional regulator IC provided with an open-circuit abnormality detection circuit and a short-circuit abnormality detection circuit.

[0040] Figure 7 is a view that shows a voltage change of each part of the conventional regulator IC of Figure 6 , (A) is a timing chart in a case where an open-circuit abnormality is eliminated after the open-circuit abnormality occurs, and (B) is a timing chart in a case where a short-circuit abnormality is eliminated after the short-circuit abnormality occurs.

[0041] LIST OF SYMBOLS

[0042] ​10 regulator IC, 11 error amplifier, 12 reference voltage circuit, 13 bias circuit, 14 current limiting circuit, 15 thermal shutdown circuit, 16 delay circuit, 17 latch circuit, 18 delay time abnormality detection circuit, CMP1 comparator for open-circuit abnormality detection, CMP2 comparator for short-circuit abnormality detection, Q1 transistor for voltage control (output transistor), Q2, Q3 current mirror transistors, Qc clamp transistor, Cd delay capacitor. DETAILED DESCRIPTION

[0043] Hereinafter, a preferred embodiment of the present application will be described based on the drawings.

[0044] Figure 1 An embodiment of a series regulator as a direct current power supply device to which the present application is applied is shown. Further, in Figure 1 the portion enclosed by the dotted line in FIG. 1 is formed as a semiconductor integrated circuit (regulator IC) 10 on a semiconductor chip such as a single crystal silicon, and a capacitor Co is connected to an output terminal OUT of the regulator IC 10, thereby functioning as a direct current power supply device for supplying a stable direct current voltage.

[0045] In the regulator IC 10 of the present embodiment, as shown in Figure 1 a transistor Ql for voltage control composed of a P-channel MOS transistor is connected between a voltage input terminal IN to which a direct current voltage VDD is applied and the output terminal OUT, and bleeder resistors Rl, R2 for dividing an output voltage Vout are connected in series between the output terminal OUT and a ground line to which a ground potential GND is applied.

[0046] The voltage VFB divided by the resistors Rl, R2 for output division is fed back to a non-inverting input terminal of an error amplifier 11 of an error amplifying circuit which is a control gate terminal of the transistor Ql for voltage control. Further, the error amplifier 11 controls the transistor Ql for voltage control in accordance with a potential difference between the feedback voltage VFB and a predetermined reference voltage Vref, and controls the output voltage Vout to be a desired potential.

[0047] Further, in the regulator IC 10 of the present embodiment, a reference voltage circuit 12 for generating a reference voltage Vref applied to the inverting input terminal of the error amplifier 11, a bias circuit 13 for causing an operating current to flow through the error amplifier 11 and the reference voltage circuit 12, a current limiting circuit 14 connected to the gate terminal of the voltage control transistor Ql for limiting the output current, and a thermal shutdown circuit 15 for stopping the operation of the error amplifier 11 to turn off the transistor Ql when the temperature of the chip rises above a predetermined temperature are provided. The CE is an external terminal into which a signal for turning the operation of the IC on / off is input.

[0048] The reference voltage circuit 12 can be configured by a series connection of a resistor and a Zener diode or the like. In the bias circuit 13, a function of supplying or cutting off the bias current to the error amplifier 11 in accordance with a control signal input from an external microcomputer (CPU) or the like to the external terminal CE is provided. The current limiting circuit 14 limits the output current Io by applying a clamp when the output current increases, the output voltage decreases, and the error amplifier 11 wants to lower the gate voltage to cause more current to flow through the transistor Ql due to abnormality of the load or the like, so that the drain current does not increase above a predetermined value.

[0049] Further, in the regulator IC 10 of the present embodiment, transistors Q2 and Q3 configured as a current mirror circuit with the transistor Ql are provided in parallel with the transistor Ql, and the same voltage as that applied to the gate terminal of the transistor Ql is applied to the gate terminals of these transistors Q2 and Q3 as control terminals. Thus, in the Q2 and Q3, a current proportional to the drain current of the Ql (a current of 1 / N) flows in accordance with the size ratio N of the elements. In the case where the transistor Ql is configured by connecting N transistors of the same size in parallel, and the transistors Q2 and Q3 are each configured by one transistor, a current proportional to the number of elements is caused to flow.

[0050] Further, in the regulator IC 10 of the present embodiment, an external terminal Pl for connecting a resistance Rop for current-voltage conversion outside the chip, and an external terminal P2 for connecting a resistance Rsc are provided, the drain terminal of the current mirror transistor Q2 is connected to the external terminal Pl, and the drain terminal of the current mirror transistor Q3 is connected to the external terminal P2. Further, a comparator CMP1 for open-circuit abnormality detection, in which the inverting input terminal is connected to the external terminal Pl and a reference voltage Vrefl is applied to the non-inverting input terminal, and a comparator CMP2 for short-circuit abnormality detection, in which the non-inverting input terminal is connected to the external terminal P2 and the reference voltage Vrefl is applied to the inverting input terminal, are provided.

[0051] The resistance value of the external resistor Rop is set so that, when a relatively small open-circuit abnormality detection current flows in the transistor Ql for voltage control, the voltage across the terminals of the resistor becomes the same value as the reference voltage Vrefl. On the other hand, the resistance value of the external resistor Rsc is set so that, when a relatively large short-circuit abnormality detection current flows in the transistor Ql for voltage control, the voltage across the terminals of the resistor becomes the same value as the reference voltage Vrefl.

[0052] Thus, in the present embodiment, the current values for detecting open-circuit abnormality and short-circuit abnormality are set by the external resistors Rop and Rsc, so that the detection current values (threshold values) can be arbitrarily set according to the system used, and the same voltage value can be used as the reference voltage Vrefl used by the comparators CMPl and CMP2, so that the circuit for generating the reference voltage can be simplified.

[0053] Further, in the regulator IC 10 of the present embodiment, in order to prevent false detection signals caused by an impact current, there are provided: a delay circuit 16 composed of resistors, capacitors, and the like that delay the outputs of the comparators CMPl and CMP2; a latch circuit 17 that takes in and holds the output of the delay circuit 16; an NOR gate Gl that takes the logical OR of the outputs of the comparators CMPl and CMP2; an OR gate G2 that takes the logical OR of the output of the NOR gate Gl and the output of the latch circuit 17 and inputs the result to the delay circuit 16; AND gates G3 and G4 that take the logical AND of the output of the latch circuit 17 and the outputs of the comparators CMPl and CMP2 before delay.

[0054] Further, there are provided an N-channel MOS transistor Q5 that inputs the output of the AND gate G3 to the gate terminal, and an N-MOS transistor Q6 that inputs the output of the AND gate G3 to the gate terminal. Further, there are provided external terminals P3 and P4 for outputting a signal to an external CPU or the like in a drain open-circuit form in the regulator IC, the drain terminal of the transistor Q5 is connected to the external terminal P3, and the drain terminal of the transistor Q6 is connected to the external terminal P4.

[0055] The regulator IC of the present embodiment determines that a short-circuit state has occurred when a relatively large current flows to the output terminal. On the other hand, at the time of startup of the IC, a relatively large impact current flows to the capacitor Co of the output terminal. However, in the comparator CMP2 for short-circuit abnormality detection of the present regulator IC, it is not possible to distinguish between this impact current and the current that flows to the output terminal when a short-circuit abnormality occurs, so that, without the delay circuit 16, it is not possible to avoid the occurrence of a false detection pulse accompanying detection of the impact current in the output of the comparator CMP2. Therefore, by providing the delay circuit 16, it is not possible to generate a false detection signal accompanying detection of the impact current.

[0056] The delay circuit 16 is composed of a constant current source II, a switching transistor Qs connected in series to the constant current source II, and a comparator CMP3 which takes as inputs the potential of the connection node Nl of the constant current source II and the transistor Qs and a predetermined reference voltage Vrefl, and inputs the output voltage of the above or gate G2 to the gate terminal of the transistor Qs. Further, an external terminal CD is provided which is connected to the connection node Nl, and by connecting an external capacitor Cd charged by the above constant current source II to this terminal CD, the delay time can be increased without increasing the chip size.

[0057] Further, a P-MOS transistor Qc is connected between the node Nl and the ground, and the gate terminal of this transistor Qc is applied with a predetermined bias voltage Vb, and if the threshold voltage of the P-MOS is set to Vthp, when the potential of the node Nl rises to (Vb + Vthp) or more, it becomes in the on state and a current flows, thereby functioning as a clamp unit. Therefore, the time required for the discharge of the capacitor Cd when the potential of the node Nl exceeds the threshold value and does not rise, changes from open to short or from short to open, can be lengthened. Further, when the external terminal CE is set to low, the operation of the IC is stopped, and thereby the gate terminal of the transistor Qc for clamping changes to low and Qc becomes on, and thereby the charge of the capacitor Cd can be rapidly discharged. Further, the reference voltages of CMPl and CMP2 can be set to different voltages, respectively.

[0058] On the other hand, in the normal operation state where the outputs of the comparators CMPl and CMP2 are both low, or when the output of the NOR gate Gl becomes high, the gate terminal of the transistor Qs is applied with high by the or gate G2 and is in the on state, and the capacitor Cd becomes in the state of being discharged. Then, when the comparator CMP 1 detects the open state or the comparator CMP2 detects the short state, and the output of either comparator changes to high, or the output of the NOR gate Gl becomes low, and the output of the immediately preceding latch circuit 17 is low, and therefore the output of the or gate G2 changes to low, and the transistor Qs is cut off.

[0059] Then, the capacitor Cd is gradually charged, and the potential of the connection node Nl gradually rises. Then, when the potential of the connection node Nl becomes higher than the reference voltage Vref2 of the comparator CMP3 after a predetermined time has elapsed, the output of the comparator CMP3 changes from low to high. Then, this high is taken in by the latch circuit 17, and the output of the latch circuit 17 changes to high. Thereby, when the open state is detected, the output of the and gate G3 changes to high, the transistor Q5 is on, and the external terminal P3 changes from high to low.

[0060] Furthermore, upon detecting a short-circuit anomaly, the output of AND gate G4 changes to a high level, transistor Q6 turns on, and external terminal P4 changes from a high level to a low level. Additionally, the delay time of delay circuit 16 is set to be slightly longer than the period during which the inrush current flows. By configuring delay circuit 16 and AND gates G3 and G4 as described above, false detection pulses accompanying the detection of the inrush current will not occur.

[0061] When the output of the NOR gate G1 is input to the reset terminal, the open-circuit or short-circuit state of the latch circuit 17 is released, and the outputs of comparators CMP1 and CMP2 both become low. When the output of the NOR gate G1 changes to a high level, it is reset, and its output changes to a low level. Consequently, the outputs of AND gates G3 and G4 change to a high level, transistors Q5 and Q6 are cut off, and external terminals P3 and P4 change to a high level, resulting in a state where no abnormal detection is output.

[0062] Next, use Figure 2 The timing diagram is used to illustrate the operation of the regulator IC10 in this embodiment. Furthermore, Figure 2 (A) indicates the timing when the load device at the output terminal OUT transitions from an unconnected state to a connected state. Figure 2 (B) indicates the timing when the load device transitions from a short-circuit state to a state where the short circuit has been eliminated.

[0063] like Figure 2 As shown in (A), when the load device is disconnected from the output terminal OUT at time t1 and changes from the normal state to the open circuit state, the output current Io stops flowing, thereby the voltage Vp1 of the external terminal P1 drops, and the output of the comparator CMP1 used for open circuit fault detection becomes high. Then, the transistor Qs of the delay circuit 16 is turned off, the external capacitor Cd of the external terminal CD is charged, and its voltage VCD gradually rises.

[0064] Then, when VCD reaches the voltage Vref2, which is the threshold voltage of comparator CMP3, the output of CMP3 goes high and is picked up by latch circuit 17. Its output LATCH_OUT goes high, and the open-circuit fault detection signal Err_op drops (timing t2). At this time, the change of the output LATCH_OUT of latch circuit 17 to a high level causes the output of OR gate G2 to go high, transistor Qs turns on, and therefore the external capacitor Cd of external terminal CD discharges, and its voltage VCD drops.

[0065] Subsequently, at time t3, when the load device is connected to the output terminal and the open circuit state is released, a large output current (inrush current) Io flows for a short time to charge the output capacitor Co. Consequently, a proportional current also flows through the current mirror transistors Q2 and Q3, causing a sharp rise in the voltages Vp1 and Vp2 at external terminals P1 and P2. Therefore, the comparator CMP2 used for short-circuit fault detection detects the rise in Vp2, and its output changes to a high level.

[0066] Therefore, transistor Qs in delay circuit 16 is turned off, external capacitor Cd at external terminal CD is charged, and its voltage VCD gradually rises. However, before VCD reaches the voltage Vref2, which is the threshold voltage of comparator CMP3, transistor Qs turns on, the charge in capacitor Cd is discharged, and the potential of VCD drops. As a result, the output of comparator CMP3 does not change to a high level, preventing the short-circuit fault detection signal Err_sc output from external terminal P4 from erroneously changing to a high level. In addition, the voltage VCD is suppressed by clamping transistor Qc, thus shortening the time required for capacitor Cd to discharge.

[0067] Furthermore, when the inrush current flows through the comparator CMP2 during open-circuit fault detection, the output of CMP2 changes to a low level, and the output of AND gate G3 also changes to a low level. This causes transistor Q5 to turn off, and the open-circuit fault detection signal Err_op changes to a high level. Additionally, when the output of comparator CMP2 changes to a low level, latch circuit 17 is reset, its output becomes low, and the output of AND gate G3 remains low, maintaining the open-circuit fault detection signal Err_op at a high level.

[0068] From Figure 2 When the load device, as shown in (B), transitions from a short-circuit state to a state where the short circuit is eliminated, the output current Io increases sharply when the short-circuit state occurs at time t11, the voltage Vp2 at external terminal P2 rises, and the output of the comparator CMP2 used for short-circuit fault detection changes to a high level. Consequently, transistor Qs in delay circuit 16 is turned off, the external capacitor Cd at external terminal CD is charged, and its voltage VCD gradually increases.

[0069] Then, when the voltage VCD at the external terminal CD reaches the threshold voltage Vref2 of comparator CMP3, the output of CMP3 goes high, which is then latched by latch circuit 17. Its output LATCH_OUT goes high, and the short-circuit fault detection signal Err_sc drops (timing t12). At this time, the change of the output LATCH_OUT of latch circuit 17 to a high level causes the output of OR gate G2 to go high, transistor Qs turns on, and thus the external capacitor Cd at the external terminal CD discharges, causing its voltage VCD to drop.

[0070] After that, at timing t13, if the short-circuit state of the load device connected to the output terminal is eliminated, the output current Io sharply decreases. In this way, the current flowing through the current mirror transistors Q2, Q3 also decreases, and the voltages Vp1, Vp2 of the external terminals P1, P2 drop, so the comparator CMP1 for open-circuit abnormality detection detects the drop of Vp1, and its output changes to the high level.

[0071] Thus, the transistor Qs of the delay circuit 16 is turned off, the external capacitor Cd of the external terminal CD is charged, and its voltage VCD gradually rises, but before VCD reaches the voltage Vref2 as the threshold value of the comparator CMP3, the transistor Qs is turned on, the charge of the capacitor Cd is discharged, and the potential of VCD drops. Therefore, the output of the comparator CMP3 does not change to the high level, and the open-circuit abnormality detection signal Err_op output from the external terminal P3 is prevented from erroneously changing to the high level. In addition, the voltage VCD is suppressed from rising by the transistor Qc for clamping, so the time required for discharging the capacitor Cd can be shortened.

[0072] Further, the comparator CMP2 for short-circuit abnormality detection changes its output to the low level at timing t13 when the output current decreases, and the output of the AND gate G3 changes to the low level, so the transistor Q6 is turned off, and the short-circuit abnormality detection signal Err_sc changes to the high level. In addition, at timing when the output of the comparator CMP2 for short-circuit abnormality detection changes to the low level, the latch circuit 17 is reset, and its output changes to the low level, and the output of the AND gate G3 remains at the low level, so the short-circuit abnormality detection signal Err_sc is maintained at the high level.

[0073] As described above, according to the regulator IC of the above-described embodiment, it is possible to prevent the short-circuit abnormality detection signal Err_sc and the open-circuit abnormality detection signal Err_op from appearing false detection pulses, regardless of whether the load device is shifted from the unconnected state to the connected state or from the short-circuit state to the state where the short circuit is eliminated.

[0074] (Modified Example)

[0075] Next, a modified example of the regulator IC of the above-described embodiment will be described. Figure 3 and Figure 4 A modified example of the regulator IC of the above-described embodiment will be described.

[0076] The structure of the regulator IC of the modified example is shown in Figure 3 Figure 3 ​The modification example shown is configured to output an abnormal state through the abnormality detection signals Err_op, Err_sc in the case where the delay time is abnormally long due to the capacitor Cd of the external terminal CD falling off or the like, by providing the delay time abnormality detection circuit 18, or the gates G5, G6. Further, in the case where the delay time is not abnormal, the abnormality detection signals Err_op, Err_sc are output in the state where the or gates G5, G6 are reset by the output of the NAND gate G1 shared with the delay circuit 16. Figure 3 The symbol Cs of the capacitor not shown in Figure 1

[0077] The delay time abnormality detection circuit 18 includes a constant current source I2, a transistor Q9 connected in series to the constant current source I2 for discharging, a capacitor C3 connected to the connection node N2 of the constant current source I2 and the transistor Q9, a comparator CMP4 comparing the potential of the connection node N2 to which a predetermined offset voltage Voff is added with the potential of the connection node Nl of the delay circuit 16, and a latch circuit LT taking in and holding the output of the comparator CMP4, the output voltage of the above or gate G2 being input to the gate terminal of the transistor Q9. Further, the latch circuit LT is configured to be able to be reset by the output of the NAND gate G1 shared with the delay circuit 16.

[0078] Further, in the rear stage of the NAND gates G3, G4, or gates G5, G6 are respectively provided in the input terminals of one side, which input the output of the latch circuit LT of the above delay time abnormality detection circuit 18.

[0079] The constant current source I2 and the capacitor C3 are circuits generating the delay time Tsd that becomes a reference, the reference delay time Tsd being represented by Tsd = C3 x (Vref2 - Voff) ÷ I2. The comparator CMP4 compares the reference delay time Tsd with the delay time Td of the delay circuit 16 to determine whether or not it is abnormal, and if the time required for the voltage VCD of the terminal CD to reach Vref2 when the capacitor Cd is not connected to the terminal CD is set to Tl, and the time required for the voltage VCD of the terminal CD to reach Vref2 when the capacitor Cd is connected to the terminal CD is set to T2, the values of I2, C3, I2, C3 are set in a manner satisfying the relation T2 > Tsd > Tl.

[0080] In the delay time abnormality detection circuit 18 having the above structure, the output of the comparator CMP4 becomes low (with the capacitor Cd) in the case where the delay time Td of the delay circuit 16 is Td > Tsd, and the output of the comparator CMP4 becomes high (without the capacitor Cd) in the case where Td < Tsd. Then, the output of this comparator CMP4 is taken in and held by the latch circuit LT, and is supplied to the gates G5, G6 of the control transistors Q5, Q6.

[0081] Figure 4 ​(A) indicates the change of each signal in the case where the capacitor Cd is connected to the terminal CD, Figure 4 (B) indicates the change of each signal in the case where the capacitor Cd is not connected to the terminal CD. The changes of each signal in the case where the capacitor Cd is connected to the terminal CD are shown in Table 1. Figure 3 The relationship between the abnormality detection signals Err_op, Err_sc and each state in the regulator IC of (A) is shown in Table 2.

[0082] [Table 1]

[0083] Normal Open circuit Short circuit Delay anomaly Err_op Output H Output L Output H Output L Err_sc Output H Output H Output L Output L

[0084] From Figure 4 Also, in the case where the capacitor Cd is connected, as in the regulator IC of the above embodiment, in the normal state, the transistors Q5, Q6 become the off state, and the abnormality detection signals Err_op, Err_sc both output the high level. Also, when the open-circuit abnormality occurs and the comparator CMP1 detects the open-circuit abnormality, Err_op outputs the low level, and Err_sc outputs the high level.

[0085] Also, in the case where the capacitor is not connected, the output of the delay time abnormality detection circuit 18, or the output of the or gates G5, G6 both become the high level, the transistors Q5, Q6 both become the on state, and the abnormality detection signals Err_op, Err_sc both output the low level. Therefore, the CPU receiving these signals can determine that the capacitor Cd for delay is dropped when the abnormality detection signals Err_op, Err_sc are both the low level.

[0086] Also, in the above embodiment, an example in which the present application is applied to the regulator IC is shown, but the present application can also be applied to an IC 20 for a power switch that directly supplies or cuts off the voltage of a power supply device (a battery or the like) as shown in (A). Figure 5 The IC for a power switch shown in (A) is provided with a gate control circuit 21 instead of the error amplifier in the regulator IC, and the gate control circuit 21 is designed to control the output transistor Ql to be in the full on state or the full off state depending on whether the control terminal CE is the high level or the low level. Figure 5

[0087] Figure 5 (B) indicates an example in which the present application is applied to Figure 5 the IC for a power switch of (A). As in (B) of the above embodiment, the structure of the modified example of the regulator IC shown in (A) can also be applied to the IC for a power switch of (A). In such an IC for a power switch 20, the same effects as those explained in the above embodiment can also be obtained. Figure 5 Figure 3 Figure 5 (B) indicates an example in which the present application is applied to Figure 5 the IC for a power switch of (A). As in (B) of the above embodiment, the structure of the modified example of the regulator IC shown in (A) can also be applied to the IC for a power switch of (A). In such an IC for a power switch 20, the same effects as those explained in the above embodiment can also be obtained. ​

[0088] The above describes the invention accomplished by the present inventors based on the embodiments, but the present invention is not limited to the above-described embodiments. For example, in the above-described embodiments, a case where one MOS transistor Qc is used as a clamping unit that clamps the potential of the external terminal CD is shown, but it can be configured to use a clamping circuit such as a diode or an operational amplifier, for example. Also, in the above-described embodiments, the clamping unit (Qc) and the latch circuit 17 are provided, but it can be a structure where only the clamping unit (Qc) is provided and the latch circuit 17 is omitted.

[0089] Also, in the above-described embodiments, a case where a MOS transistor is used as a transistor that configures the internal circuit of the regulator IC 10 and the power supply switch IC 20 is shown, but a bipolar transistor can be used instead of the MOS transistor. Also, the delay capacitor Cd can be formed on the IC chip instead of being an external element.

[0090] Also, in the above-described embodiments, a case where the short-circuit abnormality detection circuit and the open-circuit abnormality detection circuit are provided as the abnormality detection circuit and configured to be able to delay their detection signals by one common delay circuit is described, but it is not limited to the combination of the short-circuit abnormality detection circuit and the open-circuit abnormality detection circuit, and it can be applied to a regulator IC or a power supply switch IC that has a short-circuit abnormality detection circuit and another abnormality detection circuit such as a circuit that monitors the output voltage, for example.

Claims

1. A power supply semiconductor integrated circuit, comprising: an output transistor connected between a voltage input terminal and an output terminal to which a DC voltage is input; and a control circuit that controls the output transistor, characterized in that, The power supply semiconductor integrated circuit includes: The first anomaly detection circuit detects the first anomaly state; The second anomaly detection circuit detects a second anomaly state that is different from the first anomaly state. A delay circuit that delays the outputs of the first anomaly detection circuit and the second anomaly detection circuit; and A latching circuit that takes in and holds the output of the delay circuit. The delay circuit includes: a constant current source for charging a delay capacitor; a switching unit for discharging the delay capacitor; and a voltage comparison circuit for comparing the charging voltage of the delay capacitor with a predetermined voltage. The power supply semiconductor integrated circuit further includes: a voltage upper limit limiting unit, which limits the upper limit of the charging voltage of the delay capacitor.

2. The power supply semiconductor integrated circuit according to claim 1, characterized in that, The first anomaly detection circuit is a circuit that detects the short-circuit state of the output terminal. The power supply semiconductor integrated circuit is configured such that, based on a change in the state indicating an abnormality in the output of the first abnormality detection circuit or the output of the second abnormality detection circuit, the switching unit is turned off, thereby initiating the charging of the delay capacitor. When the voltage comparison circuit determines that the charging voltage of the delay capacitor has reached the predetermined voltage, the output changes, and by taking this output into the latching circuit, the switching unit is turned on to discharge the delay capacitor.

3. The power supply semiconductor integrated circuit according to claim 1, characterized in that, The voltage upper limit limiting unit is a transistor connected between the charging side terminal of the delay capacitor and the ground point. When the internal circuit containing the control circuit is in operation, a predetermined voltage is applied to the control terminal of the transistor.

4. The power supply semiconductor integrated circuit according to claim 3, characterized in that, The capacitor is discharged when the power supply semiconductor integrated circuit is turned off.

5. The power supply semiconductor integrated circuit according to claim 1 or 2, characterized in that, The second anomaly detection circuit is a circuit that detects the open-circuit state of the output terminal. The power supply semiconductor integrated circuit has a first transistor and a second transistor arranged in parallel with the output transistor, and the current flowing through them is proportionally reduced to the current flowing through the output transistor. The first anomaly detection circuit includes: a first voltage comparison circuit, which compares the voltage obtained by converting the current flowing through the first transistor with a predetermined comparison voltage to determine the magnitude. The second anomaly detection circuit includes a second voltage comparison circuit that compares the voltage obtained by converting the current flowing through the second transistor with a predetermined comparison voltage to determine the magnitude. When a current greater than the preset short-circuit fault detection current value flows through the first transistor, the first voltage comparator circuit outputs a signal indicating a short-circuit fault. When a current less than the preset open-circuit fault detection current value flows through the second transistor, the second voltage comparator circuit outputs a signal indicating an open-circuit fault.

6. The power supply semiconductor integrated circuit according to claim 1 or 2, characterized in that, The power supply semiconductor integrated circuit includes: The first output terminal is used to output the detection result of the first anomaly detection circuit to the outside; The second output terminal is used to output the detection result of the second anomaly detection circuit to the outside. as well as The delay time anomaly detection circuit detects whether the delay time of the delay circuit is within a preset predetermined time range. If the delay time anomaly detection circuit detects an anomaly in the delay time, it outputs a signal indicating that an anomaly has been detected from the first output terminal and the second output terminal.

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