Signal generation circuit, semiconductor device using the same, and signal generation method

Abstract

The present application relates to a signal generation circuit, a semiconductor device using the same, and a signal generation method. The signal generation circuit includes a first delay circuit, a second delay circuit, and a duty cycle control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty cycle control circuit compares phases of the first output signal and the second output signal and changes a value of the second delay control signal, and then reduces times of delaying the first input signal and the second input signal by the same value.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application 10-2020-0121949, filed with the Korean Intellectual Property Office on September 22, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The various embodiments generally relate to integrated circuit technology, and more specifically, to signal generation circuits and semiconductor devices using the signal generation circuits. Background Technology

[0004] Electronic devices may include many electronic components. Among these components, a computer system may include many semiconductor devices composed of semiconductors. These semiconductor devices constituting a computer system can communicate with each other while sending and receiving clock signals and data. Internal clock signals with various phases can be generated by buffering or dividing the system clock signal. However, depending on circuit characteristics, phase skew and / or duty cycle distortion may occur between the buffered or divided clock signals. Typically, semiconductor devices may include duty cycle correction circuitry to correct for such phase skew and / or duty cycle distortion. A universal duty cycle correction circuit can use any one of multiple clock signals as a reference clock signal and can adjust the phase difference between other clock signals and the reference clock signal to compensate for phase skew and / or duty cycle distortion. Summary of the Invention

[0005] In one embodiment, the signal generation circuit may include a first delay circuit, a second delay circuit, and a duty cycle control circuit. The first delay circuit may be configured to generate a first output signal by delaying a first input signal based on a first delay control signal. The second delay circuit may be configured to generate a second output signal by delaying a second input signal based on a second delay control signal. The duty cycle control circuit may be configured to compare the phases of the first and second output signals and change the value of the second delay control signal. The duty cycle control circuit may then reduce the values ​​of the first and second delay control signals by the same value.

[0006] In one embodiment, the signal generation method may include generating a first output signal and a second output signal by delaying a first input signal and a second input signal by a first time, respectively. The signal generation method may include: comparing the phases of the first output signal and the second output signal; and changing the time of the delay of the second input signal to a second time. Alternatively, the signal generation method may include reducing the first time and the second time by the same amount of time.

[0007] In one embodiment, the signal generation circuit may include a first delay circuit, a second delay circuit, and a duty cycle control circuit. The first delay circuit may be configured to generate a first output signal by delaying a first input signal, and the second delay circuit may be configured to generate a second output signal by delaying a second input signal. The duty cycle control circuit may be configured to change the delay time of the second delay circuit until the phase difference between the first and second output signals reaches a target value. Then, the duty cycle control circuit may reduce the delay times of the first and second delay circuits by the same amount of time.

[0008] In one embodiment, the signal generation circuit may include four delay circuits and a duty cycle control circuit. A first delay circuit may be configured to generate a first-phase clock signal by delaying a first input clock signal by a reference delay time. A second delay circuit may be configured to generate a second-phase clock signal by delaying a second input clock signal by a first variable delay time. A third delay circuit may be configured to generate a third-phase clock signal by delaying a third input clock signal by a second variable delay time. A fourth delay circuit may be configured to generate a fourth-phase clock signal by delaying a fourth input clock signal by a third variable delay time. The duty cycle control circuit may be configured to change the first to third variable delay times based on the phase difference between the first and fourth phase clock signals, and then reduce the reference delay time and the first to third variable delay times by the same amount of time.

[0009] In one embodiment, the semiconductor device may include a clock divider, a first duty cycle correction circuit, and a delay-locked loop (DLL) circuit. The clock divider may be configured to generate a first divided clock signal and a second divided clock signal by dividing an input clock signal. The first duty cycle correction circuit may be configured to generate a first reference clock signal and a second reference clock signal by delaying the first and second divided clock signals, compare the phases of the first and second reference clock signals to adjust the delay time of the second divided clock signal, and then reduce the delay time of the first and second divided clock signals by the same amount of time. The DLL circuit may be configured to compare the phases of the first reference clock signal and a feedback clock signal, and generate one or more output clock signals by delaying the first and second reference clock signals. The DLL circuit may then generate a feedback clock signal by delaying the one or more output clock signals.

[0010] In one embodiment, the semiconductor device may include a delay-locked loop (DLL) circuit, a clock divider, and a duty cycle correction circuit. The DLL circuit may be configured to compare the phase of a reference clock signal with the phase of a feedback clock signal generated by delaying a first output clock signal, and to generate a delayed clock signal by variably delaying the reference clock signal. The clock divider may be configured to generate at least a first divided clock signal and a second divided clock signal by dividing the delayed clock signal. The duty cycle correction circuit may be configured to generate a first output clock signal and a second output clock signal by delaying the first and second divided clock signals, and may compare the phases of the first and second output clock signals to adjust the time the second output clock signal is delayed. The duty cycle correction circuit may then reduce the time the first and second output clock signals are delayed by the same amount of time.

[0011] In one embodiment, the semiconductor device may include a delay-locked loop (DLL) circuit, a multiphase clock generation circuit, a clock distribution network, and a duty cycle correction circuit. The DLL circuit may be configured to generate a delayed clock signal by delaying a reference clock signal, and may compare the phase of the reference clock signal with the phase of a feedback clock signal generated by delaying the delayed clock signal. The DLL circuit may also change the time the reference clock signal is delayed. The multiphase clock generation circuit may be configured to generate at least a first output clock signal and a second output clock signal by dividing the frequency of the delayed clock signal. The clock distribution network may be configured to drive the first and second output clock signals and output the first and second distributed clock signals. The duty cycle correction circuit may be configured to generate a first transmission clock signal and a second transmission clock signal by delaying the first and second distributed clock signals, and may compare the phases of the first and second transmission clock signals to adjust the time the second distributed clock signal is delayed. The duty cycle correction circuit may then reduce the time the first and second distributed clock signals are delayed by the same amount of time. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating the configuration of a signal generation circuit according to an embodiment.

[0013] Figure 2 It is shown Figure 1 A diagram showing the configuration of the first and second delay circuits.

[0014] Figure 3 It is shown Figure 1 The block diagram shown illustrates the configuration of the delay control circuit.

[0015] Figure 4This is a block diagram illustrating the operation of the signal generation circuit according to this embodiment.

[0016] Figure 5 This is a block diagram illustrating the configuration of a signal generation circuit according to an embodiment.

[0017] Figure 6 It is shown Figure 5 The block diagram shown illustrates the configuration of the delay control circuit.

[0018] Figure 7 This is a block diagram illustrating the configuration of a semiconductor device according to an embodiment.

[0019] Figure 8 It is shown Figure 7 The diagram shows the configuration of the delay model circuit.

[0020] Figure 9 This is a block diagram illustrating the operation of a semiconductor device according to an embodiment.

[0021] Figure 10 This is a block diagram illustrating the operation of a semiconductor device according to an embodiment.

[0022] Figure 11 This is a block diagram illustrating the operation of a semiconductor device according to an embodiment. Detailed Implementation

[0023] Figure 1 This is a block diagram illustrating the configuration of a signal generation circuit 100 according to an embodiment. The signal generation circuit 100 can receive a first input signal IN1 and a second input signal IN2, and generate a first output signal OUT1 and a second output signal OUT2. The signal generation circuit 100 can generate the first output signal OUT1 by delaying the first input signal IN1, and can generate the second output signal OUT2 by delaying the second input signal IN2. The signal generation circuit 100 can perform phase and / or duty cycle correction operations on the first output signal OUT1 and the second output signal OUT2. The signal generation circuit 100 can change the delay time of the second input signal IN2 based on the phase of the first output signal OUT1 and the second output signal OUT2. The signal generation circuit 100 can change the delay time of the second input signal IN2, and then reduce the delay time of the first input signal IN1 and the second input signal IN2 by the same amount of time. The signal generation circuit 100 can reduce the delay time of the first input signal IN1 and the second input signal IN2 by the shorter of the delay times of the first input signal IN1 and the second input signal IN2. Therefore, the delay time between the first input signal IN1 and the second input signal IN2 can be set to a minimum value by the signal generation circuit 100.

[0024] The signal generation circuit 100 may include a first delay circuit 110, a second delay circuit 120, and a duty cycle control circuit 130. The first delay circuit 110 may receive a first input signal IN1 and generate a first output signal OUT1 by delaying the first input signal IN1. The second delay circuit 120 may receive a second input signal IN2 and generate a second output signal OUT2 by delaying the second input signal IN2. The first and second delay circuits 110 and 120 may be variable delay circuits, wherein the first delay circuit 110 may receive a first delay control signal D1<1:n> and may have a delay time that changes according to the first delay control signal D1<1:n>. Here, n may be an integer equal to or greater than 2. The second delay circuit 120 may receive a second delay control signal D2<1:n> and may have a delay time that changes according to the second delay control signal D2<1:n>. The first and second delay circuits 110 and 120 may be digital delay circuits. The first and second delay control signals D1<1:n> and D2<1:n> may be digital signals, each comprising multiple bits. In one embodiment, the first and second delay circuits 110 and 120 may be analog delay circuits. The first and second delay control signals D1<1:n> and D2<1:n> may be analog signals with various voltage levels. The following description will be based on the assumption that the first and second delay control signals D1<1:n> and D2<1:n> are digital signals, and that the first and second delay circuits 110 and 120 are digital delay lines whose delay amounts are adjusted based on the first and second delay control signals D1<1:n> and D2<1:n>, respectively.

[0025] The duty cycle control circuit 130 can receive a first output signal OUT1 and a second output signal OUT2. The duty cycle control circuit 130 can compare the phases of the first output signal OUT1 and the second output signal OUT2. The duty cycle control circuit 130 can compare the phases of the first and second output signals OUT1 and OUT2, and can change the delay times of the first and second delay circuits 110 and 120. To change the delay times of the first and second delay circuits 110 and 120, the duty cycle control circuit 130 can compare the phases of the first output signal OUT1 and the second output signal OUT2, and can change the logic values ​​of the first delay control signal D1<1:n> and the second delay control signal D2<1:n>. The duty cycle control circuit 130 can change the value of the second delay control signal D2<1:n> until the phase difference between the first output signal OUT1 and the second output signal OUT2 reaches a target value that can be arbitrarily set. For example, when the first input signal IN1 and the second input signal IN2 are clock signals, the target value can correspond to 1 / 4 of the cycle of the first input signal IN1 or the second input signal IN2. After changing the value of the second delay control signal D2<1:n>, the duty cycle control circuit 130 can reduce the values ​​of the first delay control signal D1<1:n> and the second delay control signal D2<1:n> by the same amount. In one embodiment, the duty cycle control circuit 130 can reduce the logic values ​​of the first and second delay control signals D1<1:n> and D2<1:n> by the logic value of the delay control signal that has the smaller value among the first and second delay control signals D1<1:n> and D2<1:n>. That is, the logic values ​​of the first and second delay control signals D1<1:n> and D2<1:n> can be compared, and the smaller logic value of the first and second delay control signals D1<1:n> and D2<1:n> can be used to reduce each logic value of the first and second delay control signals D1<1:n> and D2<1:n>. The duty cycle control circuit 130 can sequentially decrease the logic values ​​of the first and second delay control signals D1<1:n> and D2<1:n> until the logic value of either the first and second delay control signals D1<1:n> and D2<1:n> is minimized.

[0026] In the initial state, the first and second delay control signals D1<1:n> and D2<1:n> can each have default values. Therefore, the first delay circuit 110 and the second delay circuit 120 can delay the first delay control signal D1<1:n> and the second delay control signal D2<1:n> with default values ​​by a reference delay time. When the phase difference between the first output signal OUT1 and the second output signal OUT2 is greater than or less than a target value, the duty cycle control circuit 130 can increase or decrease the logic value of the second delay control signal D2<1:n>. The second delay circuit 120 can change the delay time of the second input signal IN2 based on the second delay control signal D2<1:n> with its increased or decreased logic value. When the phase difference between the first output signal OUT1 and the second output signal OUT2 is equal to the target value, the duty cycle control circuit 130 can decrease the logic values ​​of the first delay control signal D1<1:n> and the second delay control signal D2<1:n> by the same value. The delay time of the first delay circuit 110 and the second delay circuit 120 can be decreased by the same time. The duty cycle control circuit 130 can adjust the duty cycle of the first output signal OUT1 and the second output signal OUT2 by controlling the phase difference between the first output signal OUT1 and the second output signal OUT2 to correspond to the target value. Since the delay time of the first delay circuit 110 and the second delay circuit 120 used to adjust the duty cycle can be set to the minimum value, the operating characteristics and speed of the signal generation circuit 100 can be improved.

[0027] The duty cycle control circuit 130 may include a phase detector 131 and a delay control circuit 132. The phase detector 131 may receive a first output signal OUT1 and a second output signal OUT2. The phase detector 131 may also generate a phase detection signal PD by comparing the phases of the first output signal OUT1 and the second output signal OUT2. The phase detector 131 may employ any known configuration of phase detectors and / or duty cycle detectors, and may generate phase detection signals PD with different logic levels depending on whether the phase difference between the first output signal OUT1 and the second output signal OUT2 is greater than or less than a target value. For example, a phase detection signal PD with a first logic level may increase the logic value of the second delay control signal D2<1:n> generated by the duty cycle control circuit 130, thereby increasing the delay time of the second delay circuit 120. A phase detection signal PD with a second logic level may decrease the logic value of the second delay control signal D2<1:n> generated by the duty cycle control circuit 130, thereby decreasing the delay time of the second delay circuit 120.

[0028] The delay control circuit 132 can generate first and second delay control signals D1<1:n> and D2<1:n> based on the phase detection signal PD. The delay control circuit 132 can output the first and second delay control signals D1<1:n> and D2<1:n> with default values ​​in an initial state. Based on the first delay control signal D1<1:n> and the second delay control signal D2<1:n> with default values, the first delay circuit 110 and the second delay circuit 120 can delay the first input signal IN1 and the second input signal IN2 by a reference delay time, respectively. Based on the phase detection signal PD, the delay control circuit 132 can change the logic value of the second delay control signal D2<1:n> until the phase difference between the first output signal OUT1 and the second output signal OUT2 equals a target value. After the phase difference between the first output signal OUT1 and the second output signal OUT2 equals the target value, the delay control circuit 132 can reduce the logic values ​​of the first delay control signal D1<1:n> and the second delay control signal D2<1:n> by the same value.

[0029] Figure 2 It is shown Figure 1 A diagram showing the configuration of the first delay circuit 110 and the second delay circuit 120. (Refer to...) Figure 2 The first delay circuit 110 may include a first delay unit 211, a first driver group 221, a second driver group 222, and a first output inverter 231. The first delay unit 211 may have a delay amount equal to the maximum delay time that the first delay circuit 110 may have. Based on the first delay control signal D1<1:n>, the first delay circuit 110 may change the weights of the first and second driver groups 221 and 222, and thus change the time by which the first input signal IN1 is delayed.

[0030] Each of the first driver group 221 and the second driver group 222 can receive a first delay control signal D1<1:n>.

[0031] The first driver group 221 can receive a first input signal IN1. Based on the first delay control signal D1<1:n>, the first driver group 221 can invert the first input signal IN1 with variable drivability. The drivability of the first driver group 221 can be changed based on the inverted signal D1B<1:n> of the first delay control signal. The first driver group 221 may include multiple inverters corresponding to each bit of the first delay control signal D1<1:n>. That is, the first driver group 221 may include n inverters, wherein each inverter can receive one bit of the first delay control signal D1<1:n>. For example, as the number of bits with low logic levels in the first delay control signal D1<1:n> increases, the drivability of the first driver group 221 can increase, and the delay time of the first delay time circuit 110 can be shortened.

[0032] The second driver group 222 can receive the output of the first delayer 211. Based on the first delay control signal D1<1:n>, the second driver group 222 can invert the output of the first delayer 211 with variable driveability. The driveability of the second driver group 222 can be changed based on the first delay control signal D1<1:n>. The second driver group 222 may include multiple inverters corresponding to each bit of the first delay control signal D1<1:n>. Each inverter can receive one bit of the first delay control signal D1<1:n>. For example, as the number of bits with high logic levels in the first delay control signal D1<1:n> increases, the driveability of the second driver group 222 can increase. Therefore, the delay time of the first delay circuit 110 can be extended.

[0033] The first output inverter 231 can be commonly coupled to the first and second driver groups 221 and 222, and can receive the outputs of the first and second driver groups 221 and 222. The first output inverter 231 can generate a first output signal OUT1 by inverting the outputs of the first and second driver groups 221 and 222. By mixing the phases of the outputs of the first and second driver groups 221 and 222, which are generated according to weights determined based on the first delay control signal D, the first output inverter 231 can generate a first output signal OUT11<1:n>.

[0034] The second delay circuit 120 may include a second delay unit 212, a third driver group 223, a fourth driver group 224, and a second output inverter 232. The second delay unit 212 may have a delay amount corresponding to the maximum delay time that the second delay circuit 120 may have. The delay amount of the second delay unit 212 may be substantially equal to the delay amount of the first delay unit 211. Based on the second delay control signal D2<1:n>, the second delay circuit 120 may change the weights of the third driver group 223 and the fourth driver group 224, thereby changing the delay time of the second input signal IN2. Each of the third driver group 223 and the fourth driver group 224 may receive the second delay control signal D2<1:n>.

[0035] The third driver group 223 can receive the second input signal IN2. Based on the second delay control signal D2<1:n>, the third driver group 223 can invert the second input signal IN2 with variable driveability. The driveability of the third driver group 223 can be changed based on the inverted signal D2B<1:n> of the second delay control signal. The third driver group 223 may include multiple inverters corresponding to each bit of the second delay control signal D2<1:n>, wherein each inverter can receive one bit of the second delay control signal D2<1:n>. For example, as the number of low logic bits in the second delay control signal D2<1:n> increases, the driveability of the third driver group 223 can increase, thereby shortening the delay time of the second delay circuit 120.

[0036] The fourth driver group 224 can receive the output of the second delayer 212. Based on the second delayer control signal D2<1:n>, the fourth driver group 224 can invert the output of the second delayer 212 with variable driveability. Based on the second delay control signal D2<1:n>, the driveability of the fourth driver group 224 can be changed. The fourth driver group 224 may include multiple inverters corresponding to each bit of the second delay control signal D2<1:n>, wherein each inverter can receive one bit of the second delay control signal D2<1:n>. For example, as the number of bits with high logic levels in the second delay control signal D2<1:n> increases, the driveability of the fourth driver group 224 can increase. Therefore, the delay time of the second delay circuit 120 can be extended.

[0037] The second output inverter 232 can be commonly coupled to the third and fourth driver groups 223 and 224, and can receive the outputs of the third and fourth driver groups 223 and 224. By inverting the outputs of the third and fourth driver groups 223 and 224, the second output inverter 232 can generate a second output signal OUT2. The second output inverter 232 can generate the second output signal OUT2 by mixing the phases of the outputs of the third and fourth driver groups 223 and 224, which are generated according to weights determined based on the logic value of the second delay control signal D2.

[0038] Figure 3 It is shown Figure 1 A block diagram showing the configuration of the delay control circuit 132. (Refer to...) Figure 3 The delay control circuit 132 may include a first phase-locked detector 310, a second phase-locked detector 320, and a delay control signal generation circuit 330. Based on the phase detection signal PD, the first phase-locked detector 310 can generate a first phase-locked signal PL1. The first phase-locked detector 310 can detect changes in the logic level of the phase detection signal PD and enable the first phase-locked signal PL1. When the previously received phase detection signal PD is at a first logic level and the currently received phase detection signal PD is at a second logic level, the first phase-locked detector 310 can enable the first phase-locked signal PL1. For example, the phase detection signal PD with a first logic level can increase the logic value of the second delay control signal D2<1:n> and increase the delay time of the second delay circuit 120. The phase detection signal PD with a second logic level can decrease the logic value of the second delay control signal D2<1:n> and decrease the delay time of the second delay circuit 120.

[0039] The first phase-locked detector 310 may include a first flip-flop 311 and a second flip-flop 312. The first flip-flop 311 may have an input terminal D configured to receive a power supply voltage VDD and a clock terminal configured to receive a phase detection signal PD. The power supply voltage VDD may have a voltage level that can be determined to be a high logic level. The second flip-flop 312 may have an input terminal D coupled to the output terminal Q of the first flip-flop 311 and may be configured to receive a signal output from the first flip-flop 311. The second flip-flop 312 may have a clock terminal configured to receive an inverted signal of the phase detection signal PD and an output terminal Q configured to output a first phase-locked signal PL1. When the previously received phase detection signal PD has a high logic level and the currently received phase detection signal PD has a low logic level, the first flip-flop 311 and the second flip-flop 312 may output the power supply voltage VDD as the first phase-locked signal PL1 to enable the first phase-locked signal PL1 to a high logic level.

[0040] The second phase-locked detector 320 can generate a second phase-locked signal PL2 based on the first delay control signal D1<1:n> and the second delay control signal D2<1:n>. The second phase-locked detector 320 can generate the second phase-locked signal PL2 based on at least some bits of the first and second delay control signals D1<1:n> and D2<1:n>. For example, the second phase-locked detector 320 can receive the least significant bit of the first and second delay control signals D1<1:n> and D2<1:n>, detect the logic level of the least significant bit, and enable the second phase-locked signal PL2. The second phase-locked detector 320 enables the second phase-locked signal PL2 when any of the least significant bits of the first and second delay control signals D1<1:n> and D2<1:n> goes low. As the number of bits with low logic levels in the first delay control signal D1<1:n> increases, the first delay circuit 110 can have a shorter delay time. Therefore, when the least significant bit of the first delay control signal D1<1:n> has a low logic level, the first delay control signal D1<1:n> can have a minimum value, and the second phase-locked detector 320 can detect that the delay time of the first delay circuit 110 is set to the minimum value. Similarly, as the number of bits with low logic levels in the bits of the second delay control signal D2<1:n> increases, the second delay circuit 120 can have a short delay time. Therefore, when the least significant bit of the second delay control signal D2<1:n> has a low logic level, the second delay control signal D2<1:n> can have a minimum value, and the second phase-locked detector 320 can detect that the delay time of the second delay circuit 120 is set to the minimum value. Therefore, when either the first delay circuit 110 or the second delay circuit 120 has a minimum delay time, the second phase-locked detector 320 can enable the second phase-locked signal PL2.

[0041] The second phase-locked detector 320 may include a NAND gate 321, which can receive the least significant bits of the first and second delay control signals D1<1:n> and D2<1:n>, and output a second phase-locked signal PL2. When either the least significant bit of the first delay control signal D1<1:n> or the second delay control signal D2<1:n> transitions to a low logic level, the NAND gate 321 can enable the second phase-locked signal PL2 to a high logic level.

[0042] The delay control signal generation circuit 330 can receive a phase detection signal PD, a first phase-locked signal PL1, and a second phase-locked signal PL2, and can generate a first delay control signal D1<1:n> and a second delay control signal D2<1:n>. The delay control signal generation circuit 330 can output the first and second delay control signals D1<1:n> and D2<1:n> with default values ​​in an initial state. The default values ​​can be stored in the delay control signal generation circuit 330, and the delay control signal generation circuit 330 can change the logic value of the second delay control signal D2<1:n> based on the phase detection signal PD until the first phase-locked signal PL1 is enabled. For example, when the phase detection signal PD is at a high logic level, the delay control signal generation circuit 330 can increase the logic value of the second delay control signal D2<1:n>. When the phase detection signal PD is at a low logic level, the delay control signal generation circuit 330 can decrease the logic value of the second delay control signal D2<1:n>. When the first phase-locked signal PL1 is enabled, the delay control signal generation circuit 330 can change the logic values ​​of the first and second delay control signals D1<1:n> and D2<1:n>. For example, the delay control signal generation circuit 330 can sequentially decrease the logic values ​​of the first and second delay control signals D1<1:n> and D2<1:n>, such that these logic values ​​are increased or decreased like a thermometer code. For example, the delay control signal generation circuit 330 can sequentially change the logic values ​​of the first and second delay control signals D1<1:n> and D2<1:n> from the most significant bit with a high logic level to a low logic level, thereby sequentially decreasing the logic values ​​of the first and second delay control signals D1<1:n> and D2<1:n>. The delay control signal generation circuit 330 can decrease the logic values ​​of the first delay control signal D1<1:n> and the second delay control signal D2<1:n> until the second phase-locked signal PL2 is enabled. When the second phase-locked signal PL2 is enabled, the delay control signal generation circuit 330 can maintain the logic values ​​of the first and second delay control signals D1<1:n> and D2<1:n>. For example, when the first and second delay control signals D1<1:n> and D2<1:n> are 4-bit signals, the logic value of the first delay control signal D1<1:n> is 0011, and the logic value of the second delay control signal D2<1:n> is 0111. The delay control signal generation circuit 330 can first change the third bit of the first delay control signal D1<1:n> and the second bit of the second delay control signal D2<1:n> to a low logic level. Therefore, the first delay control signal D1<1:n> can have a logic value of 0001, and the second delay control signal D2<1:n> can have a logic value of 0011.Then, the delay control signal generation circuit 330 can change the least significant bit of the first delay control signal D1<1:n> and the third bit of the second delay control signal D2<1:n> to a low logic level, so that the logic value of the first delay control signal D1<1:n> can be 0000 and the logic value of the second delay control signal D2<1:n> can be 0001. When the least significant bit of the first delay control signal D1<1:n> is converted to a low logic level, the second phase-locked signal PL2 can be enabled, and the delay control signal generation circuit 330 can no longer decrease the logic values ​​of the first delay control signal D1<1:n> and the second delay control signal D2<1:n>. Therefore, the first delay control signal D1<1:n> can be set to 0000 and the second delay control signal D2<1:n> can be set to 0001. The delay control signal generation circuit 330 may include any logic circuit configured to perform the above operations.

[0043] Figure 4 This is a block diagram illustrating the operation of the signal generation circuit according to this embodiment. Figure 4 In the graph, the bar chart represents the delay time set by the first delay circuit 110 based on the first delay control signal D1<1:n>, and the delay time set by the second delay circuit 120 based on the second delay control signal D2<1:n>. (Refer to...) Figures 1 to 4 The operation of the signal generation circuit 100 according to an embodiment will be described below. In the initial state shown, the delay control signal generation circuit 330 can output first and second delay control signals D1<1:n> and D2<1:n> with default values, and the delay time of the first and second delay circuits 110 and 120 can be set as a reference delay time, which can be a first time T1. The phase detector 131 can detect the phase of the first output signal OUT1 and the second output signal OUT2, and can generate a phase detection signal PD. For example, when the phase difference between the first output signal OUT1 and the second output signal OUT2 is greater than a target value, the phase detector 131 can generate a phase detection signal PD with a low logic level, and the delay control signal generation circuit 330 can reduce the logic value of the second delay control signal D2<1:n> based on the phase detection signal PD. When the delay time of the second delay circuit 120 continuously decreases according to the logic value of the second delay control signal D2<1:n>, the phase difference between the first output signal OUT1 and the second output signal OUT2 can approach the target value. When the phase difference between the first output signal OUT1 and the second output signal OUT2 becomes less than a target value near the target value, the phase detector 131 can generate a phase detection signal PD with a logic high level. The delay control signal generation circuit 330 can increase the logic value of the second delay control signal D2<1:n>, and the phase difference between the first output signal OUT1 and the second output signal OUT2 can become greater than a target value near the target value. The phase detector 131 can generate a phase detection signal PD with a low logic level, and the first phase-locked detector 310 can detect the phase detection signal PD changing from a high logic level to a low logic level and enable the first phase-locked signal PL1. As shown, the delay time of the second delay circuit 120 can be set to a variable delay time shorter than the first time T1, and the variable delay time can be the second time T2. Therefore, the difference between the delay time of the first delay circuit 110 and the delay time of the second delay circuit 120 can be equal to the time T1-T2 obtained by subtracting the second time from the first time. When the first phase-locked signal PL1 is enabled, the delay control signal generation circuit 330 can sequentially decrease the logic values ​​of the first delay control signal D1<1:n> and the second delay control signal D2<1:n>. Since the second time T2 is shorter than the first time T1 and the second time T2, the delay control signal generation circuit 330 can decrease the logic values ​​of the first delay control signal D1<1:n> and the second delay control signal D2<1:n> by the logic value corresponding to the second delay control signal D2<1:n>. That is, the delay control signal generation circuit 330 can change the high logic level bits of the first and second delay control signals D1<1:n> and D2<1:n> to low logic levels by the same number of high logic level bits in the second delay control signal D2<1:n>. When the logic value of the second delay control signal D2<1:n> is minimized, the second phase-locked detector 320 can enable the second phase-locked signal PL2. When the second phase-locked signal PL2 is enabled, the delay time of the first delay circuit 110 can be set to a time T1-T2 obtained by subtracting the second time from the first time, such as... <c>As shown, the delay time of the second delay circuit 120 can be essentially set to 0. Therefore, the signal generation circuit 100 can generate the first output signal OUT1 and the second output signal OUT2 by delaying the first input signal IN1 and the second input signal IN2 by a minimum time. The signal generation circuit 100 can minimize the delay time required to generate the first output signal OUT1 and the second output signal OUT2 while adjusting the duty cycle of the first output signal OUT1 and the second output signal OUT2.

[0044] < / c> Figure 5 This is a block diagram illustrating the configuration of the signal generation circuit 500 according to an embodiment. Figure 1 The signal generation circuit 100 shown is configured to adjust the duty cycle and / or phase of two output signals generated based on two input signals, while Figure 5 The signal generation circuit 500 shown can be configured to adjust the duty cycle and / or phase of four output signals generated based on four input signals. The number of signals input to or output from the signal generation circuit is not limited to 2 or 4, but can be set to 3, 5, or more. (See reference...) Figure 5 The signal generation circuit 500 may include a first delay circuit 510, a second delay circuit 520, a third delay circuit 530, a fourth delay circuit 540, and a duty cycle control circuit 550. The first delay circuit 510 can receive a first input clock signal ICLK1 and generate a first phase clock signal OCLK1 by variably delaying the first input clock signal ICLK1. The first delay circuit 510 can generate the first phase clock signal OCLK1 by variably delaying the first input clock signal ICLK1 based on a first delay control signal D1<1:n>. By delaying the first input clock signal ICLK1 by a first variable delay time, the first delay circuit 510 can generate the first phase clock signal OCLK1. In the initial state, the first delay control signal D1<1:n> may have a default value, and the first variable delay time can be set as a reference delay time based on the first delay control signal D1<1:n> with the default value. The second delay circuit 520 can receive a second input clock signal ICLK2 and generate a second phase clock signal OCLK2 by variably delaying the second input clock signal ICLK2. Based on the second delay control signal D2<1:n>, the second delay circuit 520 can generate the second phase clock signal OCLK2 by variably delaying the second input clock signal ICLK2. The second delay circuit 520 can generate the second phase clock signal OCLK2 by delaying the second input clock signal ICLK2 by a second variable delay time. In the initial state, the second delay control signal D2<1:n> can have a default value, and the second variable delay time can be set as a reference delay time based on the second delay control signal D2<1:n> with the default value. The third delay circuit 530 can receive the third input clock signal ICLK3 and generate the third phase clock signal OCLK3 by variably delaying the third input clock signal ICLK3. Based on the third delay control signal D3<1:n>, the third delay circuit 530 can generate the third phase clock signal OCLK3 by variably delaying the third input clock signal ICLK3. The third delay circuit 530 can generate the third phase clock signal OCLK3 by delaying the third input clock signal ICLK3 by a third variable delay time. In the initial state, the third delay control signal D3<1:n> can have a default value, and based on the third delay control signal D3<1:n> with the default value, the third variable delay time can be set as the reference delay time. The fourth delay circuit 540 can receive the fourth input clock signal ICLK4 and generate the fourth phase clock signal OCLK4 by variably delaying the fourth input clock signal ICLK4. By variably delaying the fourth input clock signal ICLK4 based on the fourth delay control signal D4<1:n>, the fourth delay circuit 540 can generate the fourth phase clock signal OCLK4.By delaying the fourth input clock signal ICLK4 by a fourth variable delay time, the fourth delay circuit 540 can generate a fourth phase clock signal OCLK4. In the initial state, the fourth delay control signal D4<1:n> can have a default value, and the fourth variable delay time can be set as a reference delay time based on the fourth delay control signal D4<1:n> with the default value.

[0045] The first to fourth input clock signals ICLK1 to ICLK4 can sequentially have a 90-degree phase difference between each other. Therefore, the first input clock signal ICLK1 can lead the second input clock signal ICLK2 by 90 degrees, the second input clock signal ICLK2 can lead the third input clock signal ICLK3 by 90 degrees, the third input clock signal ICLK3 can lead the fourth input clock signal ICLK4 by 90 degrees, and the fourth input clock signal ICLK4 can lead the first input clock signal ICLK1 by 90 degrees. Ideally, when the delay times of the first to fourth delay circuits 510, 520, 530, and 540 are equal to the reference delay time, the first to fourth phase clock signals ICLK1 to ICLK4 can sequentially have a 90-degree phase difference. However, the delay times of the first to fourth delay circuits 510, 520, 530, and 540 can be changed by variations in the characteristics and manufacturing processes of the first to fourth delay circuits 510, 520, 530, and 540, or by variations in the characteristics and manufacturing processes of other circuits that generate or transmit the first to fourth input clock signals ICLK1 to ICLK4. Additionally, the phase difference and duty cycle of the first to fourth phase clock signals OCLK1 to OCLK4 output from the first to fourth delay circuits 510, 520, 530, and 540 can be changed. The duty cycle control circuit 550 can detect the phase of the first to fourth phase clock signals OCLK1 to OCLK4 and can compensate for changes in phase and / or duty cycle by individually controlling the first to fourth variable delay times. The first to fourth delay circuits 510, 520, 530, and 540 can have... Figure 2 The first and second delay circuits 110 and 120 shown have the same structure except for the input signal and the output signal.

[0046] The duty cycle control circuit 550 can detect the phases of the first to fourth phase clock signals OCLK1 to OCLK4 and generate the first to fourth delay control signals D1<1:n> to D4<1:n>. The duty cycle control circuit 550 can individually adjust the second to fourth variable delay times based on the results obtained by detecting the phases of the first to fourth phase clock signals OCLK1 to OCLK4. The first variable delay time can be maintained as a reference delay time. After adjusting the second to fourth variable delay times, the duty cycle control circuit 550 can reduce the first to fourth variable delay times by the same amount of time. For example, the duty cycle control circuit 550 can reduce the first to fourth variable delay times by the shortest of the first to fourth variable delay times. The duty cycle control circuit 550 can detect the phases of the first to fourth phase clock signals OCLK1 to OCLK4 and individually change the logic values ​​of the second to fourth delay control signals D2<1:n> to D4<1:n>, while the first delay control signal D1<1:n> can maintain its default value. The duty cycle control circuit 550 can change the logic values ​​of the second to fourth delay control signals D2<1:n> to D4<1:n>. Then, the duty cycle control circuit 550 can decrease the logic values ​​of the first to fourth delay control signals D1<1:n> to D4<1:n> by the same amount. For example, the duty cycle control circuit 550 can decrease the logic value of the delay control signal with the smallest logic value among the first to fourth delay control signals D1<1:n> to D4<1:n>.

[0047] The duty cycle control circuit 550 may include a phase detector 551 and a delay control circuit 552. The phase detector 551 can detect the phases of the first to fourth phase clock signals OCLK1 to OCLK4 and can generate a first phase detection signal PD1, a second phase detection signal PD2, and a third phase detection signal PD3. The phase detector 551 may include any known phase detector or duty cycle detector capable of detecting the phase difference between the four input signals. For example, the phase detector 551 can detect whether the phase difference between the first phase clock signal OCLK1 and the second phase clock signal OCLK2 corresponds to a first target value. Then, the phase detector 551 can generate the first phase detection signal PD1. The first target value may correspond to 1 / 4 of the cycle of the first input clock signal ICKL1. The phase detector 551 can detect whether the phase difference between the first phase clock signal OCLK1 and the third phase clock signal OCLK3 corresponds to a second target value, which may correspond to 1 / 2 of the cycle of the first input clock signal ICKL1, and can generate the second phase detection signal PD2. Phase detector 551 can detect whether the phase difference between the first phase clock signal OCLK1 and the fourth phase clock signal OCLK4 corresponds to a third target value, which may correspond to 3 / 4 of the cycle of the first input clock signal ICKL1, and can generate a third phase detection signal PD3. The function and operation of phase detector 551 have now been described. However, this embodiment is not limited to this, and various phase detectors that function and operate in different ways can be used as phase detector 551.

[0048] The delay control circuit 552 can generate first to fourth delay control signals D1<1:n> to D4<1:n> with default values ​​in the initial state. By changing the logic value of the second delay control signal D2<1:n> based on the first phase detection signal PD1, the delay control circuit 552 can change the second variable delay time. By changing the logic value of the third delay control signal D3<1:n> based on the second phase detection signal PD2, the delay control circuit 552 can change the third variable delay time. By changing the logic value of the fourth delay control signal D4<1:n> based on the third phase detection signal PD3, the delay control circuit 552 can change the fourth variable delay time. After changing the second to fourth variable delay times by changing the logic values ​​of the second to fourth delay control signals D2<1:n> to D4<1:n>, the delay control circuit 552 can decrease the logic values ​​of the first to fourth delay control signals D1<1:n> to D4<1:n> by the same value, thereby reducing the first to fourth variable delay times by the same amount of time.

[0049] Figure 6 It is shown Figure 5 A block diagram showing the configuration of the delay control circuit 552. (Refer to...) Figure 6 The delay control circuit 552 may include a first phase-locked detector 610, a second phase-locked detector 620, and a second delay control signal generation circuit 630. The first phase-locked detector 610 can receive first to third phase detection signals PD1 to PD3, and can generate a first phase-locked signal PL1 based on the first to third phase detection signals PD1 to PD3. Since the first phase-locked detector 610 is configured to receive three phase detection signals, in addition to... Figure 3 In addition to the components shown in the first phase-locked detector 310, the first phase-locked detector 610 may also include other components. The first phase-locked detector 610 may include a first flip-flop 611, a second flip-flop 612, a third flip-flop 613, a fourth flip-flop 614, a fifth flip-flop 615, a sixth flip-flop 616, and a first gate circuit 617. The first flip-flop 611 and the second flip-flop 612 may be a first lock detector used to generate a first lock signal LOCK1 based on a first phase detection signal PD1. The first flip-flop 611 may have an input terminal D configured to receive a power supply voltage VDD and a clock terminal configured to receive the first phase detection signal PD1. The second flip-flop 612 may have an input terminal D coupled to the output terminal Q of the first flip-flop 611 and may be configured to receive a signal output from the first flip-flop 611. The second flip-flop 612 may have a clock terminal configured to receive an inverted signal of the first phase detection signal PD1 and an output terminal Q configured to output the first lock signal LOCK1. When the previously received first phase detection signal PD1 has a high logic level and the currently received first phase detection signal PD1 has a low logic level, the first flip-flop 611 and the second flip-flop 612 can output the power supply voltage VDD as the first lock signal LOCK1, and thus enable the first lock signal LOCK1 to a high logic level.

[0050] The third flip-flop 613 and the fourth flip-flop 614 can be a second lock detector for generating a second lock signal LOCK2 based on the second phase detection signal PD2. The third flip-flop 613 may have an input terminal D configured to receive a power supply voltage VDD and a clock terminal configured to receive the second phase detection signal PD2. The fourth flip-flop 614 may have an input terminal D coupled to the output terminal Q of the third flip-flop 613. Furthermore, the fourth flip-flop 614 may be configured to receive a signal output from the third flip-flop 613. The fourth flip-flop 614 may have a clock terminal configured to receive an inverted signal of the second phase detection signal PD2, and an output terminal Q configured to output the second lock signal LOCK2. When the previously received second phase detection signal PD2 has a high logic level and the currently received second phase detection signal PD2 has a low logic level, the third flip-flop 613 and the fourth flip-flop 614 can output the power supply voltage VDD as the second lock signal LOCK2, thereby enabling the second lock signal LOCK2 to a high logic level.

[0051] The fifth and sixth flip-flops 615 and 616 can be third lock detectors used to generate a third lock signal LOCK3 based on the third phase detection signal PD3. The fifth flip-flop 615 can have an input terminal D configured to receive a power supply voltage VDD and a clock terminal configured to receive the third phase detection signal PD3. The sixth flip-flop 616 can have an input terminal D coupled to the output terminal of the fifth flip-flop 615 and can be configured to receive a signal output from the fifth flip-flop 615. The sixth flip-flop 616 can have a clock terminal configured to receive an inverted signal of the third phase detection signal PD3 and an output terminal configured to output the third lock signal LOCK3. When the previously received third phase detection signal PD3 has a high logic level and the currently received third phase detection signal PD3 has a low logic level, the fifth and sixth flip-flops 615 and 616 can output the power supply voltage VDD as the third lock signal LOCK3, thereby enabling the third lock signal LOCK3 to a high logic level.

[0052] The first gating circuit 617 can receive first to third lock signals LOCK1 to LOCK3 and output a first phase-locked signal PL1. When all three lock signals LOCK1 to LOCK3 are enabled, the first gating circuit 617 can enable the first phase-locked signal PL1. The first gating circuit 617 may include an AND gate. When all three lock signals LOCK1 to LOCK3 are enabled to a high logic level, the first gating circuit 617 can output the first phase-locked signal PL1, which is enabled to a high logic level.

[0053] The second phase-locked detector 620 can generate a second phase-locked signal PL2 based on a first delay control signal D1<1:n>, a second delay control signal D2<1:n>, a third delay control signal D3<1:n>, and a fourth delay control signal D4<1:n>. The second phase-locked detector 620 can generate the second phase-locked signal PL2 based on at least some bits of the first to fourth delay control signals D1<1:n> to D4<1:n>. For example, the second phase-locked detector 620 can receive the least significant bit of the first to fourth delay control signals D1<1:n> to D4<1:n> and detect the logic level of the least significant bit to enable the second phase-locked signal PL2. When any of the least significant bits of the first to fourth delay control signals D1<1:n> to D4<1:n> go low, the second phase-locked detector 620 enables the second phase-locked signal PL2. When any of the first to fourth delay circuits 510, 520, 530, and 540 has a minimum delay time, the second phase-locked detector 620 can enable the second phase-locked signal PL2. The second phase-locked detector 620 may include a NAND gate 631. The NAND gate 631 can receive the least significant bits of the first to fourth delay control signals D1<1:n> to D4<1:n> and output the second phase-locked signal PL2. When any of the least significant bits of the first to fourth delay control signals D1<1:n> to D4<1:n> transition to a logic low level, the NAND gate 631 can enable the second phase-locked signal PL2 to a high logic level.

[0054] The delay control signal generation circuit 630 can receive the first to third phase detection signals PD1 to PD3 and the first and second phase-locking signals PL1 and PL2, and generate the first to fourth delay control signals D1<1:n> to D4<1:n>. In its initial state, the delay control signal generation circuit 630 can output the first to fourth delay control signals D1<1:n> to D4<1:n> with default values. The delay control signal generation circuit 630 can change the logic values ​​of the second to fourth delay control signals D2<1:n> to D4<1:n> based on the first to third phase detection signals PD1 to PD3 until the first phase-locking signal PL1 is enabled. For example, when the first to third phase detection signals PD1 to PD3 are all at a high logic level, the delay control signal generation circuit 630 can increase the logic values ​​of the second to fourth delay control signals D2<1:n> to D4<1:n>. When the first to third phase detection signals PD1 to PD3 are all at a low logic level, the delay control signal generation circuit 630 can decrease the logic values ​​of the second to fourth delay control signals D2<1:n> to D4<1:n>. When the first phase lock signal PL1 is enabled, the delay control signal generation circuit 630 can change the logic values ​​of the first to fourth delay control signals D1<1:n> to D4<1:n>. For example, the delay control signal generation circuit 630 can sequentially decrease the logic values ​​of the first to fourth delay control signals D1<1:n> to D4<1:n>. The delay control signal generation circuit 630 can sequentially change the logic values ​​of the first to fourth delay control signals D1<1:n> to D4<1:n> from the most significant bit with a high logic level to a low logic level. The delay control signal generation circuit 630 can decrease the logic values ​​of the first to fourth delay control signals D1<1:n> to D4<1:n> until the second phase lock signal PL2 is enabled. When the second phase-locked signal PL2 is enabled, the delay control signal generation circuit 630 can maintain the logic values ​​of the first to fourth delay control signals D1<1:n> to D4<1:n>. Therefore, the delay control signal generation circuit 630 can reduce the logic value of the first to fourth delay control signals D1<1:n> to D4<1:n> to the logic value of the delay control signal with the smallest logic value among the first to fourth delay control signals D1<1:n> to D4<1:n>, thereby setting the first to fourth variable delay times to the minimum delay time.

[0055] Figure 7 This is a block diagram illustrating the configuration of a semiconductor device 700 according to an embodiment. (Refer to...) Figure 7 The semiconductor device 700 may include a clock receiver 710, a first clock divider 720, a first duty cycle correction circuit 730, and a delay-locked loop circuit 740. The clock receiver 710 can receive a system clock signal CLK transmitted from outside the semiconductor device 700 and can generate an input clock signal INCLK, wherein the system clock signal CLK can be transmitted as a differential signal or a single-ended signal. When the system clock signal CLK is transmitted as a differential signal, the clock receiver 710 can generate the input clock signal INCLK by differentially amplifying the system clock signal CLK and the complementary signal CLKB. When the system clock signal CLK is transmitted as a single-ended signal, the input clock signal INCLK can be generated by the clock receiver 710 by differentially amplifying the system clock signal CLK and a reference voltage VREF. The reference voltage VREF may have a voltage level corresponding to the middle of the swing range of the system clock signal CLK.

[0056] The first clock divider 720 generates a first divided clock signal CLK1 and a second divided clock signal CLK2 by dividing the input clock signal INCLK. By dividing the frequency of the input clock signal INCLK, the first clock divider 720 can generate first and second divided clock signals CLK1 and CLK2 with frequencies lower than the frequency of the input clock signal INCLK. For example, the first clock divider 720 can divide the frequency of the input clock signal INCLK by 2, and the frequencies of the first and second divided clock signals CLK1 and CLK2 can both correspond to half the frequency of the input clock signal INCLK. The first divided clock signal CLK1 can have a 180-degree phase difference with the second divided clock signal CLK2.

[0057] The first duty cycle correction circuit 730 can receive first and second divided clock signals CLK1 and CLK2, and generate a first reference clock signal RCLK and a second reference clock signal FCLK. By delaying the first and second divided clock signals CLK1 and CLK2, the first duty cycle correction circuit 730 can generate the first and second reference clock signals RCLK and FCLK. The first duty cycle correction circuit 730 can compare the phases of the first reference clock signal RCLK and the second reference clock signal FCLK, and adjust the delay time of the second divided clock signal CLK2. After adjusting the delay time of the second divided clock signal CLK2, the first duty cycle correction circuit 730 can reduce the delay time of the first divided clock signal CLK1 and the second divided clock signal CLK2 by the specified time. Figure 1 The signal generation circuit 100 shown can be used as a first duty cycle correction circuit 730, so that the first and second frequency division clock signals CLK1 and CLK2 can correspond to Figure 1 The first and second input signals IN1 and IN2, the first reference clock signal RCLK and the second reference clock signal FCLK can correspond to Figure 1 The first output signal OUT1 and the second output signal OUT2. The first duty cycle correction circuit 730 can minimize the delay time required to adjust the phase and duty cycle of the first reference clock signal RCLK and the second reference clock signal FCLK.

[0058] The delay-locked loop circuit 740 can receive a first reference clock signal RCLK and a second reference clock signal FCLK, and can generate one or more output clock signals by performing a delay-locking operation on the first reference clock signal RCLK and the second reference clock signal FCLK. For example, the delay-locked loop circuit 740 can generate first to fourth output clock signals ICLK, QCLK, IBCLK, and QBCLK. However, the delay-locked loop circuit 740 can be modified to generate more or fewer than four output clock signals. By comparing the phases of the first reference clock signal RCLK and the feedback clock signal FBCLK and delaying the first reference clock signal RCLK and the second reference clock signal FCLK, the delay-locked loop circuit 740 can generate one or more output clock signals. The delay-locked loop circuit 740 can generate the feedback clock signal FBCLK by delaying one or more output clock signals.

[0059] The delay-locked loop circuit 740 may include a first delay line 741, a second delay line 742, a second clock divider 743, a second duty cycle correction circuit 744, a delay model circuit 745, and a delay line control circuit 746. The first delay line 741 may receive a first reference clock signal RCLK and generate a first delayed clock signal CLKD1 by delaying the first reference clock signal RCLK based on the delay line control signal DLC. The first delay line 741 may have a delay time determined based on the delay line control signal DLC. The second delay line 742 may receive a second reference clock signal FCLK and generate a second delayed clock signal CLKD2 by delaying the second reference clock signal FCLK based on the delay line control signal DLC. The second delay line 742 may have a delay time determined based on the delay line control signal DLC.

[0060] The second clock divider 743 can receive the first and second delayed clock signals CLKD1 and CLKD2, and divide the frequencies of the first and second delayed clock signals CLKD1 and CLKD2. When the second clock divider 743 divides the frequencies of the first and second delayed clock signals CLKD1 and CLKD2, it outputs four divided clock signals. For example, the second clock divider 743 can divide the frequencies of the first delayed clock signal CLKD1 and the second delayed clock signal CLKD2 by 2, and generate four divided clock signals with a 90-degree phase difference in sequence.

[0061] The second duty cycle correction circuit 744 can receive four divided clock signals output from the second clock divider 743 and generate one or more output clock signals, such as a first output clock signal ICLK, a second output clock signal QCLK, a third output clock signal IBCLK, and a fourth output clock signal QBCLK. One or more output clock signals can be, for example, the first output clock signal ICLK. The second duty cycle correction circuit 744 can detect the phases of the first to fourth output clock signals ICLK, QCLK, IBCLK, and QBCLK, and adjust the phases and / or duty cycles of the first to fourth output clock signals ICLK, QCLK, IBCLK, and QBCLK. The second duty cycle correction circuit 744 can be implemented as any known duty cycle correction circuit. In one embodiment, Figure 5 The signal generation circuit 500 shown can be used as a second duty cycle correction circuit 744. The four divided clock signals output from the second clock divider 743 can correspond to... Figure 5 The first to fourth input clock signals ICLK1, ICLK2, ICLK3, and ICLK4, and the first to fourth output clock signals ICLK, QCLK, IBCLK, and QBCLK can correspond to... Figure 5 The first to fourth phase clock signals are OCLK1, OCLK2, OCLK3 and OCLK4.

[0062] The delay model circuit 745 can generate a feedback clock signal FBCLK by delaying one or more output clock signals. The delay model circuit 745 can receive a first output clock signal ICLK and generate the feedback clock signal FBCLK by delaying the first output clock signal ICLK by a modeled delay time. The modeled delay time can correspond to the delay time occurring along the path through which the clock signal propagates in the semiconductor device 700. The delay model circuit 745 can have a fixed delay time and a variable delay time, wherein the fixed delay time can be a constant delay time, and the variable delay time can be a delay time that can be changed in various ways. By modeling the delay time caused by circuits other than the first duty cycle correction circuit 730, a fixed delay time can be obtained among these delay times occurring along the paths through which the clock signal propagates in the semiconductor device 700. The variable delay time can be changed in substantially the same way as the delay time of the first duty cycle correction circuit 730. For example, the delay model circuit 745 can include a delay circuit having a structure similar to that of the delay circuit included in the first duty cycle correction circuit 730. Alternatively, the delay model circuit 745 may have a variable delay time corresponding to half of the delay time of the delay circuit. That is, the maximum value of the variable delay time may be half of the delay time of the delay circuit and may correspond to a reference delay time. Based on the delay control signal used in the first duty cycle correction circuit 730, the delay model circuit 745 may change the variable delay time. When the first delay control signal D1<1:n> is used to adjust... Figure 1 When the delay time of the first delay circuit 110 is adjusted, for example, the delay model circuit 745 can receive the first delay control signal D1<1:n> from the first duty cycle correction circuit 730. The variable delay time of the delay model circuit 745 can be reduced by the amount of delay time reduction in the delay circuit of the first duty cycle correction circuit 730. Therefore, the delay-locked loop circuit 740 can perform the delay-locking operation more accurately and can reduce the total delay time of the path through which the clock signal has propagated.

[0063] The delay line control circuit 746 can receive a first reference clock signal RCLK and a feedback clock signal FBCLK, and generate a delay line control signal DLC by comparing the phases of the first reference clock signal RCLK and the feedback clock signal FBCLK. By changing the logic value of the delay line control signal DLC according to the phase difference between the first reference clock signal RCLK and the feedback clock signal FBCLK, the delay line control circuit 746 can change the delay time of the first delay line 741 and the second delay line 742.

[0064] The semiconductor device 700 may further include a clock distribution network 750 and a clock transmitter 760. The clock distribution network 750 may receive and transmit one or more output clock signals generated by the delay-locked loop circuit 740. The clock distribution network 750 may receive and transmit first to fourth output clock signals ICLK, QCLK, IBCLK, and QBCLK. The clock distribution network 750 may be coupled to multiple data input / output circuits (not shown) and may transmit the first to fourth output clock signals ICLK, QCLK, IBCLK, and QBCLK to multiple data input / output circuits. The clock distribution network 750 may include transmission lines, repeaters, etc., configured to transmit the first to fourth output clock signals ICLK, QCLK, IBCLK, and QBCLK.

[0065] The clock transmitter 760 can receive the output of the clock distribution network 750, generate a data strobe signal DQS, and send the data strobe signal DQS to the outside of the semiconductor device 700, wherein the data strobe signal DQS can be a clock signal synchronized with data output from multiple data input / output circuits. Figure 7 A clock transmitter is shown, but this clock transmitter can be set in each data input / output circuit.

[0066] Figure 8 It is shown Figure 7 A diagram showing the configuration of the delay model circuit 745. (Refer to...) Figure 8 The delay model circuit 745 may include a first delay unit 810, a second delay unit 820, a first driver group 831, a second driver group 832, and an output inverter 840. The first delay unit 810 may receive a first output clock signal ICLK, delay the first output clock signal ICLK, and may have a delay amount corresponding to a fixed delay time of the delay model circuit 745. The second delay unit 820 may receive the output of the first delay unit 810 and delay the output of the first delay unit 810. The maximum value of the delay amount of the second delay unit 820 may be set to the value of the delay circuit constituting the first duty cycle correction circuit 730 (e.g., [missing information]). Figure 1 The delay time of the first delay circuit 110 is half the maximum delay time of the reference delay time, and the delay amount of the second delay circuit 820 can correspond to the reference delay time. Based on the delay control signal D1<1:n> provided from the duty cycle control circuit constituting the first duty cycle correction circuit 730, the delay model circuit 745 can change the weights of the first and second driver groups 831 and 832, and thus can change the delay time of the first output clock signal ICLK. Each of the first driver group 831 and the second driver group 832 can receive the delay control signal D1<1:n>.

[0067] The first driver group 831 can receive signals output from the first delayer 810. Based on the delay control signal D1<1:n>, the first driver group 831 can invert the signal output from the first delayer 810 with variable drivability. The drivability of the first driver group 831 can be changed based on the inverted signal of the delay control signal D1<1:n>. The first driver group 831 may include multiple inverters corresponding to each bit of the delay control signal D1<1:n>. Each inverter can receive one bit of the delay control signal D1<1:n>. For example, as the number of bits with low logic levels in the delay control signal D1<1:n> increases, the drivability of the first driver group 831 can increase, and the delay time of the delay model circuit 745 can be shortened.

[0068] The second driver group 832 can receive signals output from the second delayer 820. Based on the delay control signal D1<1:n>, the second driver group 832 can invert the signal output from the second delayer 820 with variable drivability. The drivability of the second driver group 832 can be changed based on the delay control signal D1<1:n>. The second driver group 832 may include multiple inverters corresponding to individual bits of the delay control signal D1<1:n>, wherein each of these inverters can receive one bit of the delay control signal D1<1:n>. For example, as the number of bits with high logic levels in the delay control signal D1<1:n> increases, the drivability of the second driver group 832 can increase, and the delay time of the delay model circuit 745 can be lengthened.

[0069] Output inverter 840 can be commonly coupled to first and second driver groups 831 and 832, and receives the outputs of first and second driver groups 831 and 832. By inverting the outputs of first and second driver groups 831 and 832, output inverter 840 can generate a feedback clock signal FBCLK. Output inverter 840 can generate the feedback clock signal FBCLK by mixing the phases of the outputs of first and second driver groups 831 and 832, which are generated according to weights determined based on a delay control signal D1<1:n>.

[0070] The delay model circuit 745 may have a minimum delay time set to correspond to the delay amount of the first delayer 810, and a maximum delay time set to correspond to the sum of the delay amounts of the first delayer 810 and the second delayer 820. Changing the delay time in the first duty cycle correction circuit 730 can change the delay time of the delay model circuit 745.

[0071] Figure 9 This is a block diagram illustrating the operation of the semiconductor device 700 according to this embodiment. Figure 9 In the diagram, the bar chart represents the delay time of the delay circuit 910 of the first duty cycle correction circuit 730 that delays the first frequency-divided clock signal CLK1, the delay time of the delay circuit 920 of the first duty cycle correction circuit 730 that delays the second frequency-divided clock signal CLK2, and the delay model circuit 745 that delays the first output clock signal ICLK. (Refer to...) Figures 7 to 9 The operation of the semiconductor device 700 according to this embodiment will be described below. When the clock receiver 710 receives the system clock signal CLK and generates an input clock signal INCLK, the first clock divider 720 can generate first and second divided clock signals CLK1 and CLK2 by dividing the input clock signal INCLK. In the initial state shown, the delay time of the delay circuit 910 used to delay the first divided clock signal CLK1 can be set to a first time T1, and the delay time of the delay circuit 920 used to delay the second divided clock signal CLK2 can also be set to a first time T1. The delay time of the delay model circuit 745 can be set to the sum of a fixed delay time Tf and the first time T1. Ideally, the first and second divided clock signals CLK1 and CLK2 need to have a 180-degree phase difference between them, and each has a 50:50 duty cycle. However, depending on the characteristics of the clock receiver 710 and the first clock divider 720, the first and second divided clock signals CLK1 and CLK2 may have neither a 180-degree phase difference between them nor a 50:50 duty cycle. Therefore, by variably delaying the first and second frequency-divided clock signals CLK1 and CLK2, the first duty cycle correction circuit 730 can generate the first and second reference clock signals RCLK and FCLK, thereby adjusting the phase difference between the first and second reference clock signals RCLK and FCLK to 180° and adjusting the duty cycle of the first and second reference clock signals RCLK and FCLK to 50:50. For example, when the delay time of the delay circuit 920 used to delay the second reference clock signal FCLK is reduced to adjust the phase and / or duty cycle of the second reference clock signal FCLK, such as... As shown, the delay time of the delay circuit 910 used to delay the first reference clock signal RCLK can be maintained at a first time T1, and the delay time of the delay circuit 920 used to delay the second reference clock signal FCLK can be changed to a second time T2. That is, the delay time of the delay circuit 920 can be reduced by the difference T1-T2 between the first time and the second time. The delay time of the delay model circuit 745 can still be maintained as the sum of the fixed delay time Tf and the first time T1.

[0072] Then, the first duty cycle correction circuit 730 can together reduce the delay times of delay circuits 910 and 920 and the delay model circuit 745. The second time T2 can be the minimum delay time among the delay times of delay circuits 910 and 920 used to delay the first reference clock signal RCLK and the second reference clock signal FCLK. The delay times of delay circuits 910 and 920 and the delay model circuit 745 can all be reduced by the second time T2. <c>As shown, the delay time of the delay circuit 910 used to delay the first reference clock signal RCLK can be set to time T1-T2, which is obtained by subtracting the second time from the first time. The delay of the delay circuit 920 used to delay the second reference clock signal FCLK can be essentially zero. The delay time of the delay model circuit 745 can be set to the sum of a fixed delay time Tf and time T1-T2, which is obtained by subtracting the second time from the first time. Therefore, the delay times of delay circuits 910 and 920, as well as the delay model circuit 745, can all be set to the minimum time.

[0073] < / c> Figure 10 This is a block diagram illustrating the configuration of a semiconductor device 1000 according to an embodiment. (Refer to...) Figure 10 The semiconductor device 1000 may include a clock receiver 1010, a delay-locked loop circuit 1020, a clock divider 1030, a duty cycle correction circuit 1040, a clock distribution network 1050, and a clock transmitter 1060. Figure 7 In this circuit, the first duty cycle correction circuit 730 can be positioned between the delay-locked loop circuit 740 and the first clock divider 720 that receives the output of the clock receiver 710. However, as... Figure 10 As shown, the duty cycle correction circuit 1040 can be disposed between the clock distribution network 1050 and the clock divider 1030 that receives the output of the delay-locked loop circuit 1020. The semiconductor device 1000 may include components that... Figure 7 The components of the semiconductor device 700 shown are similar to those of other components; therefore, repeated descriptions of the same functions and operations of the same parts will be omitted here. The clock receiver 1010 can receive the system clock signal CLK and generate a reference clock signal RCLK.

[0074] By performing a delay-locked operation on the reference clock signal RCLK, the delay-locked loop circuit 1020 can generate a delayed clock signal CLKD. The delay-locked loop circuit 1020 can compare the phase of the reference clock signal RCLK with the phase of the feedback clock signal FBCLK generated by delaying the first output clock signal ICLK, and variably delay the reference clock signal RCLK. By variably delaying the reference clock signal RCLK, the delay-locked loop circuit 1020 can generate the delayed clock signal CLKD. The delay-locked loop circuit 1020 may include a delay line 1021, a delay model circuit 1022, and a delay line control circuit 1023. By variably delaying the reference clock signal RCLK based on the delay line control signal DLC, the delay line 1021 can generate the delayed clock signal CLKD. The delay model circuit 1022 can receive the first output clock signal ICLK generated by the duty cycle correction circuit 1040, and generate the feedback clock signal FBCLK by delaying the first output clock signal ICLK. The delay model circuit 1022 can receive the delay control signal D1<1:n>, which will be used in the duty cycle correction circuit 1040 described below, and has a delay time that changes based on the delay control signal D1<1:n>. The delay line control circuit 1023 can generate the delay line control signal DLC by comparing the phases of the reference clock signal RCLK and the feedback clock signal FBCLK.

[0075] Clock divider 1030 can receive a delayed clock signal CLKD from delay-locked loop circuit 1020. Clock divider 1030 can generate at least first and second divided clock signals CLK1 and CLK2 by dividing the delayed clock signal CLKD. Clock divider 1030 can also generate first and second divided clock signals CLK1 and CLK2 by dividing the frequency of the delayed clock signal CLKD by 2, with a 90-degree phase difference between them. By inverting the first and second divided clock signals CLK1 and CLK2, clock divider 1030 can generate four divided clock signals. Clock divider 1030 can generate a third divided clock signal CLK3 with a 180-degree phase difference from the first divided clock signal CLK1 and a fourth divided clock signal CLK4 with a 180-degree phase difference from the second divided clock signal CLK2. Ideally, the first to fourth divided clock signals CLK1 to CLK4 need to have a 90-degree phase difference sequentially, and each has a 50:50 duty cycle. However, the phase difference and duty cycle of the first to fourth divided clock signals CLK1 to CLK4 can be changed according to the characteristics and process variations of the clock divider 1030. A duty cycle correction circuit 1040 can be provided to compensate for the phase and phase variations caused by the clock divider 1030.

[0076] The duty cycle correction circuit 1040 can receive at least the first and second divided clock signals CLK1 and CLK2, and generate a first output clock signal ICLK and a second output clock signal QCLK. The duty cycle correction circuit 1040 can generate the first and second output clock signals ICLK and QCLK by delaying the first and second divided clock signals CLK1 and CLK2, and compare the phases of the first and second output clock signals ICLK and QCLK to adjust the delay time of the second output clock signal QCLK. After adjusting the delay time of the second output clock signal QCLK, the duty cycle correction circuit 1040 can reduce the delay time of the first output clock signal ICLK and the second output clock signal QCLK by the same amount of time. At this time, based on the delay control signal D1<1:n> used to set the delay time of the first output clock signal ICLK, the delay time of the delay model circuit 1022 can be reduced to be as much as the delay time of the first output clock signal ICLK. Figure 1 The signal generation circuit 100 shown can be used as a duty cycle correction circuit 1040. The first and second frequency divider clock signals CLK1 and CLK2 can correspond to... Figure 1 The first and second input signals IN1 and IN2, and the first and second output clock signals ICLK and QCLK can be corresponding to Figure 1 The first and second output signals OUT1 and OUT2. In addition to the first and second divided clock signals CLK1 and CLK2, the duty cycle correction circuit 1040 can also receive the third and fourth divided clock signals CLK3 and CLK4. When the duty cycle correction circuit 1040 receives the first to fourth divided clock signals CLK1 to CLK4 together, in Figure 5 The signal generation circuit 500 shown can be used as the duty cycle correction circuit 1040. The first to fourth frequency division clock signals CLK1 to CLK4 can correspond to... Figure 5 The first to fourth input clock signals ICLK1 to ICLK4, and the first to fourth output clock signals ICLK, QCLK, IBCLK, and QBCLK can correspond to... Figure 5 The first to fourth phase clock signals OCLK1 to OCLK4. The clock distribution network 1050 can transmit the first to fourth output clock signals ICLK, QCLK, IBCLK and QBCLK output from the duty cycle correction circuit 1040, and the clock transmitter 1060 can generate a data strobe signal DQS based on the output of the clock distribution network 1050.

[0077] Figure 11 This is a block diagram illustrating the configuration of a semiconductor device 1100 according to an embodiment. (Refer to...) Figure 11 The semiconductor device 1100 may include a clock receiver 1110, a delay-locked loop circuit 1120, a multiphase clock generation circuit 1130, a clock distribution network 1140, a duty cycle correction circuit 1150, and a clock transmitter 1160. Figure 7 In this circuit, the duty cycle correction circuit 730 is positioned between the delay-locked loop circuit 740 and the first clock divider 720 that receives the output of the clock receiver 710. Figure 10 In this circuit, a duty cycle correction circuit 1040 is positioned between the clock distribution network 1050 and the clock divider 1030 that receives the output of the delay-locked loop circuit 1020. However, in Figure 11 In this configuration, a duty cycle correction circuit 1150 may be disposed between a clock distribution network 1140 and a clock transmitter 1160. A semiconductor device 1100 may include components that... Figure 7 or Figure 10 The semiconductor devices 700 or 1000 shown are similar components, and repeated descriptions of the same functions and operations of the same components will be omitted here. The clock receiver 1110 can receive the system clock signal CLK and generate a reference clock signal RCLK.

[0078] By performing a delay-locked operation on the reference clock signal RCLK, the delay-locked loop circuit 1120 can generate a delayed clock signal CLKD. The delay-locked loop circuit 1120 can compare the phase of the reference clock signal RCLK with the phase of the feedback clock signal FBCLK generated by delaying the delayed clock signal CLKD, and change the delay time of the reference clock signal RCLK. The delay-locked loop circuit 1120 may include a delay line 1121, a delay model circuit 1122, and a delay line control circuit 1123. The delay line 1121 can delay the reference clock signal RCLK based on the delay line control signal DLC and output the delayed clock signal CLKD. By delaying the delayed clock signal CLKD, the delay model circuit 1122 can generate the feedback clock signal FBCLK. The delay model circuit 1122 can receive a delay control signal D1<1:n> to be used in the duty cycle correction circuit 1150 described below, and has a delay time that is changed based on the delay control signal D1<1:n>. By comparing the phases of the reference clock signal RCLK and the feedback clock signal FBCLK, the delay line control circuit 1123 can generate the delay line control signal DLC.

[0079] The multiphase clock generation circuit 1130 can receive a delayed clock signal CLKD output from the delay-locked loop circuit 1120. The multiphase clock generation circuit 1130 can generate at least a first output clock signal ICLK and a second output clock signal QCLK based on the delayed clock signal CLKD. The multiphase clock generation circuit 1130 may include a clock divider (not shown), and generates the first output clock signal ICLK and the second output clock signal having a 90-degree phase difference with each other by dividing the delayed clock signal CLKD via the clock divider. The multiphase clock generation circuit 1130 can further generate third and fourth output clock signals IBCLK and QBCLK, wherein the third output clock signal IBCLK may have a 180-degree phase difference with the first output clock signal ICLK, and the fourth output clock signal QBCLK may have a 180-degree phase difference with the second output clock signal QCLK.

[0080] The clock distribution network 1140 can receive at least a first output clock signal ICLK and a second output clock signal QCLK, and output a first distributed clock signal DCLK1 and a second distributed clock signal DCLK2. The clock distribution network 1140 can drive the first and second output clock signals ICLK and QCLK, and can output the first and second distributed clock signals DCLK1 and DCLK2, wherein the first distributed clock signal DCLK1 can have a phase corresponding to the first output clock signal ICLK, and the second distributed clock signal DCLK2 can have a phase corresponding to the second output clock signal QCLK. The clock distribution network 1140 can further receive a third and a fourth output clock signal IBCLK and QBCLK, and also output a third distributed clock signal DCLK3 and a fourth distributed clock signal DCLK4. The third distributed clock signal DCLK3 can have a phase corresponding to the third output clock signal IBCLK, and the fourth distributed clock signal DCLK4 can have a phase corresponding to the fourth output clock signal QBCLK. Ideally, the first to fourth distributed clock signals DCLK1 to DCLK4 need to have a 90-degree phase difference between each other sequentially, and each distributed clock signal needs to have a 50:50 duty cycle. However, the phase difference and duty cycle of the first to fourth distributed clock signals DCLK1 to DCLK4 can vary depending on the characteristics and manufacturing process of the clock distribution network 1140. Since the clock distribution network 1140 includes long clock transmission lines through which clock signals are transmitted, it is difficult to maintain the phase difference and duty cycle of the first to fourth output clock signals ICLK, QCLK, IBCLK, and QBCLK. A duty cycle correction circuit 1050 can be provided to compensate for the phase and duty cycle variations caused by the clock distribution network 1140.

[0081] The duty cycle correction circuit 1150 can receive at least the first allocated clock signal DCLK1 and the second allocated clock signal DCLK2, and generate the first transmission clock signal TCLK1 and the second transmission clock signal TCLK2. The duty cycle correction circuit 1150 can generate the first transmission clock signal TCLK1 and the second transmission clock signal TCLK2 by delaying the first allocated clock signal DCLK1 and the second allocated clock signal DCLK2, and compare the phases of the first transmission clock signal TCLK1 and the second transmission clock signal TCLK2 to adjust the delay time of the second allocated clock signal DCLK2. After adjusting the delay time of the second allocated clock signal DCLK2, the duty cycle correction circuit 1150 can reduce the delay time of the first and second allocated clock signals DCLK1 and DCLK2 by the same amount. At this time, based on the delay control signal D1<1:n> used to set the delay time of the first allocated clock signal DCLK1, the delay time of the delay model circuit 1122 can be reduced by the same amount as the reduction in the delay time of the first allocated clock signal DCLK1. Figure 1 The signal generation circuit 100 shown can be used as a duty cycle correction circuit 1150. The first and second distribution clock signals DCLK1 and DCLK2 can correspond to... Figure 1 The first and second input signals IN1 and IN2, and the first and second transmission clock signals TCLK1 and TCLK2 can correspond to Figure 1 The first and second output signals OUT1 and OUT2 are provided. The duty cycle correction circuit 1150 can further receive the third allocated clock signal DCLK3 and the fourth allocated clock signal DCLK4, and also generate the third transmission clock signal TCLK3 and the fourth transmission clock signal TCLK4. The duty cycle correction circuit 1150 can generate the first to fourth transmission clock signals TCLK1, TCLK2, TCLK3 and TCLK4 by delaying the first to fourth allocated clock signals DCLK1 to DCLK4, and compare the phases of the first to fourth allocated clock signals DCLK1 to DCLK4 to adjust the delay time of the second to fourth allocated clock signals DCLK2 to DCLK4. After adjusting the delay time of the second to fourth allocated clock signals DCLK2 to DCLK4, the duty cycle correction circuit 1150 can reduce the delay time of the first to fourth allocated clock signals DCLK1 to DCLK4 by the same amount of time. At this time, based on the delay control signal D1<1:n> used to set the delay time of the first allocation clock signal DCLK1, the delay time of the delay model circuit 1122 can be reduced by the same amount as the reduction in the delay time of the first allocation clock signal DCLK1. Figure 5 The signal generation circuit 500 shown can be used as the duty cycle correction circuit 1150. The first to fourth distributed clock signals DCLK1 to DCLK4 can correspond to... Figure 5 The first to fourth input clock signals ICLK1 to ICLK4, and the first to fourth transmission clock signals TCLK1 to TCLK4 can correspond to Figure 5 The first to fourth phase clock signals OCLK1 to OCLK4.

[0082] Although various embodiments have been described above, those skilled in the art will understand that the described embodiments are merely examples. Therefore, the signal generation circuits and methods and semiconductor devices described herein should not be limited based on the described embodiments.

Claims

1. A signal generation circuit, comprising: A first delay circuit is configured to delay a first input signal based on a first delay control signal to generate a first output signal; The second delay circuit is configured to delay the second input signal based on the second delay control signal to generate the second output signal; A phase detector is configured to compare the phases of the first output signal and the second output signal to generate a phase detection signal; and A delay control circuit is configured to change the value of the second delay control signal based on the phase detection signal, and then reduce the values ​​of the first delay control signal and the second delay control signal by the same value.

2. The signal generation circuit according to claim 1, wherein, The delay control circuit decreases the logic values ​​of the first delay control signal and the second delay control signal until either of the first delay control signal or the second delay control signal has a minimum value.

3. The signal generation circuit according to claim 1, wherein, The delay control circuit includes: A first phase-locked detector is configured to generate a first phase-locked signal based on the phase detection signal; A second phase-locked detector is configured to generate a second phase-locked signal when either the first delay control signal or the second delay control signal has a minimum value; and A delay control signal generation circuit is configured to change the logic values ​​of the first delay control signal and the second delay control signal based on the phase detection signal, the first phase lock signal, and the second phase lock signal.

4. The signal generation circuit according to claim 3, wherein, The first phase-locked detector enables the first phase-locked signal when the previously received phase detection signal has a first logic level and the currently received phase detection signal has a second logic level.

5. The signal generation circuit according to claim 3, wherein, The second phase-locked detector enables the second phase-locked signal based on the logic level of the least significant bit of the first delay control signal and the second delay control signal.

6. The signal generation circuit according to claim 3, wherein, The delay control signal generation circuit changes the logic value of the second delay control signal based on the phase detection signal until the first phase lock signal is enabled. When the first phase lock signal is enabled, the logic values ​​of the first delay control signal and the second delay control signal are sequentially decreased until the second phase lock signal is enabled.

7. A signal generation method, comprising: The first output signal and the second output signal are generated by delaying the first input signal and the second input signal by a first time, respectively. Compare the phases of the first output signal and the second output signal, and change only the delay time of the second input signal to the second time; and Reduce the first time and the second time by the same amount of time.

8. The signal generation method according to claim 7, wherein, The same time corresponds to the shorter of the first time and the second time.

9. A signal generation circuit, comprising: A first delay circuit is configured to delay a first input signal to generate a first output signal; A second delay circuit is configured to delay the second input signal to generate a second output signal; and A duty cycle control circuit is configured to: change only the delay time of the second delay circuit until the phase difference between the first output signal and the second output signal reaches a target value, and then reduce the delay times of the first delay circuit and the second delay circuit by the same amount of time.

10. The signal generation circuit according to claim 9, wherein, The duty cycle control circuit reduces the delay time of the first delay circuit and the second delay circuit to the shorter of the two delay times.

11. The signal generation circuit according to claim 9, wherein, The first delay circuit delays the first input signal based on a first delay control signal, and The second delay circuit delays the second input signal based on the second delay control signal.

12. The signal generation circuit according to claim 11, wherein, The duty cycle control circuit compares the phases of the first output signal and the second output signal, changes the value of the second delay control signal, and then reduces the values ​​of the first delay control signal and the second delay control signal by the same value.

13. The signal generation circuit according to claim 11, wherein, The duty cycle control circuit includes: A phase detector configured to compare the phases of the first output signal and the second output signal to generate a phase detection signal; and A delay control circuit is configured to: change the logic value of the second delay control signal based on the phase detection signal, and then reduce the logic values ​​of the first delay control signal and the second delay control signal by the same value.

14. The signal generation circuit according to claim 13, wherein, The delay control circuit includes: A first phase-locked detector is configured to generate a first phase-locked signal based on the phase detection signal; A second phase-locked detector is configured to generate a second phase-locked signal when either the first delay control signal or the second delay control signal has a minimum value; and A delay control signal generation circuit is configured to change the logic values ​​of the first delay control signal and the second delay control signal based on the phase detection signal, the first phase lock signal, and the second phase lock signal.

15. The signal generation circuit according to claim 14, wherein, The first phase-locked detector enables the first phase-locked signal when the previously received phase detection signal has a first logic level and the currently received phase detection signal has a second logic level.

16. The signal generation circuit according to claim 14, wherein, The second phase-locked detector enables the second phase-locked signal based on the logic level of the least significant bit of the first delay control signal and the second delay control signal.

17. The signal generation circuit according to claim 14, wherein, The delay control signal generation circuit changes the logic value of the second delay control signal based on the phase detection signal until the first phase lock signal is enabled. When the first phase lock signal is enabled, the logic values ​​of the first delay control signal and the second delay control signal are sequentially decreased until the second phase lock signal is enabled.

18. A signal generation circuit, comprising: A first delay circuit is configured to delay a first input clock signal by a reference delay time to generate a first phase clock signal; The second delay circuit is configured to delay the second input clock signal by a first variable delay time to generate a second phase clock signal; The third delay circuit is configured to delay the third input clock signal by a second variable delay time to generate a third phase clock signal; A fourth delay circuit is configured to delay the fourth input clock signal by a third variable delay time to generate a fourth phase clock signal; and A duty cycle control circuit is configured to change the first variable delay time to the third variable delay time based on the phase difference between the first phase clock signal and the fourth phase clock signal, and then reduce the reference delay time and the first variable delay time to the third variable delay time by the same amount of time.

19. The signal generation circuit according to claim 18, wherein, The duty cycle control circuit reduces the reference delay time and the first variable delay time to the third variable delay time to the shortest of the reference delay time and the first variable delay time to the third variable delay time.

20. The signal generation circuit according to claim 18, wherein, The first delay circuit delays the first input clock signal based on the first delay control signal. The second delay circuit delays the second input clock signal based on the second delay control signal. The third delay circuit delays the third input clock signal based on the third delay control signal, and The fourth delay circuit delays the fourth input clock signal based on the fourth delay control signal.

21. The signal generation circuit according to claim 20, wherein, The duty cycle control circuit compares the phases of the first phase clock signal to the fourth phase clock signal, changes the values ​​of the second phase clock signal to the fourth delay control signal, and then reduces the values ​​of the first delay control signal to the fourth delay control signal by the same value.

22. The signal generation circuit according to claim 21, wherein, The duty cycle control circuit reduces the value of the first to fourth delay control signals by the value of the delay control signal that has the minimum value among the first to fourth delay control signals.

23. The signal generation circuit according to claim 20, wherein, The duty cycle control circuit includes: A phase detector, configured to detect the phase difference between a first phase clock signal and a fourth phase clock signal, and to generate a first phase detection signal, a second phase detection signal, and a third phase detection signal; and A delay control circuit is configured to change the logic values ​​of the second delay control signal to the fourth delay control signal based on the first phase detection signal to the third phase detection signal, and to change the logic values ​​of the first delay control signal to the fourth delay control signal by the same value.

24. The signal generation circuit according to claim 23, wherein, The delay control circuit includes: A first phase-locked detector is configured to generate a first phase-locked signal based on the first phase detection signal to the third phase detection signal; A second phase-locked detector is configured to generate a second phase-locked signal when any one of the logic values ​​of the first to fourth delay control signals has a minimum value; and A delay control signal generation circuit is configured to change the logic value of the first delay control signal to the fourth delay control signal based on the first phase detection signal, the second phase detection signal, the third phase detection signal, the first phase lock signal, and the second phase lock signal.

25. The signal generation circuit according to claim 24, wherein, The first phase-locked detector includes: A first lock detector is configured to generate a first lock signal based on the logic level of the first phase detection signal; A second lock detector is configured to generate a second lock signal based on the logic level of the second phase detection signal; A third lock detector is configured to generate a third lock signal based on the logic level of the third phase detection signal; and A gating circuit configured to enable the first phase-locking signal when all three locking signals are enabled.

26. The signal generation circuit according to claim 24, wherein, The second phase-locked detector enables the second phase-locked signal based on the logic level of the least significant bit of the first to fourth delay control signals.

27. The signal generation circuit according to claim 24, wherein, The delay control signal generation circuit changes the logic values ​​of the second delay control signal to the fourth delay control signal based on the first phase detection signal to the third phase detection signal until the first phase lock signal is enabled, and when the second phase lock signal is enabled, sequentially decreases the logic values ​​of the first delay control signal to the fourth delay control signal.

28. A semiconductor device, comprising: A clock divider is configured to generate a first divided clock signal and a second divided clock signal by dividing the input clock signal. The first duty cycle correction circuit is configured to: generate a first reference clock signal and a second reference clock signal by delaying the first frequency-divided clock signal and the second frequency-divided clock signal, compare the phases of the first reference clock signal and the second reference clock signal to adjust the time the second frequency-divided clock signal is delayed, and then delay the time the first frequency-divided clock signal and the second frequency-divided clock signal are delayed by the same time. and A delay-locked loop circuit is configured to compare the phases of a first reference clock signal and a feedback clock signal, generate one or more output clock signals by delaying the first reference clock signal and a second reference clock signal, and generate the feedback clock signal by delaying the one or more output clock signals.

29. The semiconductor device according to claim 28, wherein, The delay-locked loop circuit reduces the time by which the one or more output clock signals are delayed by the same amount of time.

30. The semiconductor device according to claim 28, wherein, The first duty cycle correction circuit includes: A first delay circuit is configured to delay the first frequency-divided clock signal based on a first delay control signal to generate the first reference clock signal; A second delay circuit is configured to delay the second frequency-divided clock signal based on a second delay control signal to generate the second reference clock signal; and A duty cycle control circuit is configured to change the value of the second delay control signal by comparing the phases of the first reference clock signal and the second reference clock signal, and then change the values ​​of the first delay control signal and the second delay control signal to the same value.

31. The semiconductor device according to claim 30, wherein, The duty cycle control circuit reduces the values ​​of the first delay control signal and the second delay control signal to the value of the delay control signal that has the smaller value among the first delay control signal and the second delay control signal.

32. The semiconductor device according to claim 30, wherein, The duty cycle control circuit includes: A phase detector configured to generate a duty cycle detection signal by comparing the phases of the first reference clock signal and the second reference clock signal; and A delay control circuit is configured to change the logic value of the second delay control signal based on the duty cycle detection signal, and then change the logic values ​​of the first delay control signal and the second delay control signal to the same value.

33. The semiconductor device according to claim 30, wherein, The delay-locked loop circuit includes: A first delay line is configured to generate a first delayed clock signal by delaying the first reference clock signal based on a delay line control signal, wherein the one or more output clock signals have a phase corresponding to the first delayed clock signal; The second delay line is configured to generate a second delayed clock signal by delaying the second reference clock signal based on the delay line control signal; A delay model circuit, configured to generate the feedback clock signal by delaying the one or more output clock signals; and A delay line control circuit is configured to generate the delay line control signal by detecting the phase of the first reference clock signal and the feedback clock signal.

34. The semiconductor device according to claim 33, wherein, The delay model circuit has a variable delay time that varies based on the first delay control signal.

35. The semiconductor device of claim 33, further comprising: A clock divider is configured to generate a first divided clock signal, a second divided clock signal, a third divided clock signal, and a fourth delayed clock signal by dividing the first delayed clock signal and the second delayed clock signal. and A second duty cycle correction circuit is configured to generate the one or more output clock signals by adjusting the phase of the first divided clock signal to the fourth divided clock signal.

36. The semiconductor device of claim 35, further comprising: A clock distribution network configured to transmit the one or more output clock signals; and A clock transmission circuit is configured to output a data strobe signal based on the output of the clock distribution network.

37. A semiconductor device, comprising: A delay-locked loop circuit is configured to: compare the phase of a reference clock signal with the phase of a feedback clock signal generated by delaying a first output clock signal, and generate a delayed clock signal by variably delaying the reference clock signal; A clock divider configured to generate at least a first divided clock signal and a second divided clock signal by dividing the delayed clock signal. and The duty cycle correction circuit is configured to: generate a first output clock signal and a second output clock signal by delaying the first and second divided clock signals, compare the phases of the first and second output clock signals to adjust the time the second output clock signal is delayed, and then delay the first and second output clock signals by the same time.

38. The semiconductor device according to claim 37, characterized in that, The delay-locked loop circuit reduces the time the first output clock signal is delayed by the same amount of time to generate the feedback clock signal.

39. The semiconductor device according to claim 37, wherein, The delay-locked loop circuit includes: A delay line, configured to delay the reference clock signal based on a delay line control signal, to generate the delayed clock signal; A delay model circuit, configured to delay the first output clock signal to generate the feedback clock signal; and A delay line control circuit is configured to detect the phase of the reference clock signal and the feedback clock signal to generate the delay line control signal.

40. The semiconductor device of claim 39, wherein, The delay model circuit has a variable delay time that is altered by the duty cycle correction circuit.

41. The semiconductor device according to claim 37, wherein, The duty cycle correction circuit includes: A first delay circuit is configured to delay the first frequency-divided clock signal based on a first delay control signal to generate the first output clock signal; A second delay circuit is configured to delay the second frequency-divided clock signal based on a second delay control signal to generate the second output clock signal; and A duty cycle control circuit is configured to change the value of the second delay control signal by comparing the phases of the first output clock signal and the second output clock signal, and then change the values ​​of the first delay control signal and the second delay control signal to the same value.

42. The semiconductor device according to claim 41, wherein, The duty cycle control circuit reduces the values ​​of the first delay control signal and the second delay control signal to the value of the delay control signal that has the smaller value among the first delay control signal and the second delay control signal.

43. The semiconductor device according to claim 41, wherein, The duty cycle control circuit includes: A phase detector configured to generate a phase detection signal by comparing the phases of the first output clock signal and the second output clock signal; and A delay control circuit is configured to change the logic value of the second delay control signal based on the phase detection signal, and then change the logic values ​​of the first delay control signal and the second delay control signal to the same value.

44. The semiconductor device of claim 37, further comprising: A clock distribution network configured to transmit the first output clock signal and the second output clock signal; and A clock transmission circuit is configured to output a data strobe signal based on the output of the clock distribution network.

45. A semiconductor device, comprising: A delay-locked loop circuit is configured to: generate a delayed clock signal by delaying a reference clock signal, compare the phase of the reference clock signal with the phase of a feedback clock signal generated by delaying the delayed clock signal, and change the time by which the reference clock signal is delayed; A multiphase clock generation circuit is configured to generate at least a first output clock signal and a second output clock signal by dividing the frequency of the delayed clock signal. A clock distribution network configured to drive the first output clock signal and the second output clock signal and output a first distributed clock signal and a second distributed clock signal; and A duty cycle correction circuit is configured to generate a first transmission clock signal and a second transmission clock signal by delaying the first allocation clock signal and the second allocation clock signal, compare the phases of the first transmission clock signal and the second transmission clock signal to adjust the time the second allocation clock signal is delayed, and then reduce the time the first allocation clock signal and the second allocation clock signal are delayed by the same amount of time.

46. ​​The semiconductor device according to claim 45, characterized in that, The delay-locked loop circuit reduces the time the delayed clock signal is delayed by the same amount of time to generate the feedback clock signal.

47. The semiconductor device of claim 45, wherein, The delay-locked loop circuit includes: A delay line, configured to delay the reference clock signal based on a delay line control signal, to generate the delayed clock signal; A delay model circuit, configured to delay the delayed clock signal to generate the feedback clock signal; and A delay line control circuit is configured to compare the phases of the reference clock signal and the feedback clock signal to generate the delay line control signal.

48. The semiconductor device according to claim 47, characterized in that, The delay model circuit has a variable delay time that is altered by the duty cycle correction circuit.

49. The semiconductor device according to claim 45, wherein, The duty cycle correction circuit includes: A first delay circuit is configured to delay the first allocated clock signal based on a first delay control signal to generate the first transmission clock signal; A second delay circuit is configured to delay the second allocated clock signal based on a second delay control signal to generate the second transmission clock signal; and A duty cycle control circuit is configured to change the value of the second delay control signal by comparing the phases of the first transmission clock signal and the second transmission clock signal, and then change the values ​​of the first delay control signal and the second delay control signal to the same value.

50. The semiconductor device according to claim 49, wherein, The duty cycle control circuit reduces the values ​​of the first delay control signal and the second delay control signal to the value of the delay control signal that has the smaller value among the first delay control signal and the second delay control signal.

51. The semiconductor device according to claim 49, wherein, The duty cycle control circuit includes: A phase detector configured to compare the phases of the first output clock signal and the second output clock signal to generate a duty cycle detection signal; and A delay control circuit is configured to change the logic value of the second delay control signal based on the duty cycle detection signal, and to change the logic values ​​of the first delay control signal and the second delay control signal by the same value.

52. The semiconductor device of claim 45, further comprising: A clock transmission circuit is configured to output a data strobe signal based on the first transmission clock signal and the second transmission clock signal.

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