Method and apparatus for determining link bifurcation availability

Abstract

A method and apparatus implemented in a computer system for determining link bifurcation availability includes allocating, by a controller, a channel including a link for one or more components connected according to a currently known configuration. The controller transmits an ordered set including the allocations to the one or more components, the ordered set being received by the one or more components. The one or more components respond to the controller with a first link; and based on the link received by the controller not satisfying the currently known configuration, the controller issues an interrupt and is reconfigured.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Non-Provisional Patent Application No. 16 / 521,562, filed on July 24, 2019, the contents of which are hereby incorporated by reference herein. Background Art

[0003] Peripheral Component Interconnect Express (PCIe) controllers may enable a default configuration deployment with fewer than the ideal number of ports. A software program then uses information available after a PCIe link is established on an available port to determine what the ideal PCIe controller configuration is. For example, the configuration may be stored off-chip, and the information communicated only after the link is negotiated and active. A complete reset and reconfiguration of the PCIe controller and other affected devices must then be triggered in order to achieve the correct configuration. This mechanism may take on the order of seconds to determine the ideal configuration, which slows down overall processing power. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] A more detailed understanding may be obtained from the following description given by way of example in conjunction with the accompanying drawings, in which:

[0005] Figure 1 is a block diagram of an exemplary device in which one or more features of the present disclosure may be implemented;

[0006] Figure 2 is a flow chart of an exemplary method of determining link fork availability; and

[0007] Figure 3 The diagram is a schematic diagram determined based on a link bifurcation of an instance. DETAILED DESCRIPTION

[0008] Although the method and apparatus will be further described in detail below, the mechanism for determining link bifurcation availability is briefly described herein. A PCIe controller may be deployed when the desired or ideal port configuration is unknown at chip initialization. In such cases, the number of PCIe devices physically connected to a PCIe controller (controller) may exceed the number of ports (e.g., channels) currently configured for it by the controller (and the rest of the PCIe stack). Multiple add-in cards connected to bifurcated downstream ports and / or multiple components instantiated on the add-in cards are examples of such situations. For example, multiple disk controllers may be instantiated on an insert card, or multiple graphics cards may be connected. In addition, there is the possibility that the controller can be reconfigured to support a complete set of connected devices that cannot be supported in the current configuration, or at least more. That is, the controller is physically able to do so when it is properly programmed / configured to support additional ports. Thus, this document describes a method and apparatus for identifying additional and previously unknown ports that may exist; and defines a mechanism for communicating the discovery to software so that the software can react and take necessary measures to optimize the PCIe controller (e.g., through management features for managing links, such as PCIe link management features).

[0009] The mechanism exploits the receipt of an unexpected valid link number at a specific point in the link training sequence. The receipt of an unexpected but valid link number by a port on a subset of channels indicates that it can be connected to more than one device and that a link fork is possible. When these conditions are met and the feature is enabled, the link controller loads the received link number into a set of per-channel registers and generates an interrupt that directs the software to those registers where the controller can infer what the actual configuration should be. At that point, the software has the option of selecting a more appropriate configuration, and communications on the link can continue, but training will not advance until the new configuration is written. At this point, additional link training state machines (LTSSMs) can be brought online and synchronized to the same point in the ordered set transmission, where the ports transmitting the unexpected link number will be handed over to those LTSSMs, allowing all ports to continue training. A method implemented in a computer system for determining link fork availability includes: allocating channels by a controller, the channels including links for one or more components connected according to a currently known configuration. The controller transmits an ordered set including allocations to one or more components, the ordered set being received by one or more components. The one or more components respond to the controller using the first link; and based on the link received by the controller not satisfying the currently known configuration, the controller issues an interrupt and is reconfigured

[0010] An apparatus implemented in a computer system for determining link bifurcation availability includes: a controller; and one or more components communicatively coupled to the controller via a plurality of physical channels. The controller allocates channels including links for one or more components connected according to a first configuration, and transmits an ordered set including the allocations to the one or more components. The controller receives the ordered set via the one or more components, and based on values ​​received by the controller via the one or more components not satisfying the first configuration, issues an interrupt, calculates a second configuration, configures the controller according to the second configuration, and trains the links as indicated by the second configuration.

[0011] A non-transitory computer-readable medium for providing services for tasks in a computer system has instructions recorded thereon, which when executed by a processor cause the processor to perform operations. The operations include allocating a channel, the channel including links for one or more components connected according to a first configuration. An ordered set including the allocations to the one or more components is transmitted to the one or more components and received by the one or more components. Based on a value received by the one or more components not satisfying the first configuration, the operations include: issuing an interrupt, calculating a second configuration, configuring a controller according to the second configuration, and training the links as indicated by the second configuration.

[0012] Figure 1 1 is a block diagram of an exemplary device 100 in which one or more features of the present disclosure may be implemented. Device 100 may include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, a memory 104, a storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 may also optionally include an input driver 112 and an output driver 114. In addition, device 100 includes a memory controller 115, which communicates with processor 102 and memory 104 and may also communicate with external memory 116. It should be understood that device 100 may include Figure 1 Additional components not shown.

[0013] In various alternatives, the processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU on the same die, or one or more processor cores, where each processor core can be a CPU or a GPU. In various alternatives, the memory 104 is located on the same die as the processor 102, or is located separately from the processor 102. The memory 104 includes volatile or non-volatile memory, such as random access memory (RAM), dynamic RAM, or cache.

[0014] Storage device 106 includes fixed storage device or removable storage device, such as hard disk drive, solid state drive, optical disk or flash drive. Input device 108 includes but is not limited to keyboard, keypad, touch screen, touch pad, detector, microphone, accelerometer, gyroscope, biometric scanner or network connection (for example, wireless LAN card for transmitting and / or receiving wireless IEEE 802 signals). Output device 110 includes but is not limited to display, speaker, printer, tactile feedback device, one or more lights, antenna or network connection (for example, wireless LAN card for transmitting and / or receiving wireless IEEE 802 signals).

[0015] The input driver 112 communicates with the processor 102 and the input device 108 and allows the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110 and allows the processor 102 to send output to the output device 110. It should be noted that the input driver 112 and the output driver 114 are optional components and that the device 100 would operate in the same manner in the absence of the input driver 112 and the output driver 114.

[0016] The external memory 116 may be similar to the memory 104 and may reside in the form of off-chip memory. Alternatively, the external memory may be memory residing in a server, where the memory controller 115 communicates through a network interface to access the memory 116.

[0017] Figure 2 is a flow chart of an exemplary method 200 of determining link bifurcation availability. Figure 3 Based on an example Figure 2 Schematic diagram of link bifurcation determination of method 200. In step 210, the PCIe controller allocates lanes and transmits a TS1 training sequence (TS1) ordered set to the intended PCIe components connected based on an initial configuration known to the PCIe controller. The TS1 ordered set includes information about each lane, including a link number. Figure 3 , step 210 is shown in 300A, where the PCIe controller transmits a TS1 ordered set with a lane number set to PAD and a link number set to 0-15 on physical lanes 0-15 (310) to the downstream component. That is, the PCIe controller transmits TS1 / Lnk0...TS1 / Lnk15 on physical lanes 0...15, respectively. Figure 3As shown, there are three downstream components connected to the upstream channel 320 (e.g., a first component connected to 8 upstream channels corresponding to downstream channels 0-7, a second component connected to 4 upstream channels (0-3) corresponding to downstream channels 8-11, and a third component connected to 4 upstream channels (0-3) corresponding to downstream channels 12-15).

[0018] Each port (e.g., downstream channel or upstream channel) has one valid register set / physical channel associated with the initial link width. Thus, a port with an "n" channel width has valid registers for logical channels "0" to "n-1". In addition, as part of the initial configuration (i.e., the current configuration), the port is assigned to physical channels "m" to "m+n-1". Thus, the channel "0" to channel "n-1" registers for the port represent physical channels "m" to "m+n-1", respectively. For example, if the PCIe controller is programmed to operate as 8 / 4 / 4 (lanes), and the ports are shifted so that, for example, port A (i.e., an 8-lane port) occupies channels 4 to 11, then the channel 0 to channel 7 registers of port A represent physical channels 4 to 11. Therefore, in step 220, the downstream components receive TS1 ordered sets and each downstream component responds to the upstream component PCIe controller with a TS1 ordered set that announces the same link number on all channels associated with each downstream component. The link number advertised by each downstream component must be one of the link numbers received from the upstream component. The PCIe controller then determines whether the response matches the expected configuration (step 230). If the response matches the expected configuration in step 230, the method proceeds to step 260 where the current configuration is accepted and the link is trained according to the expected configuration. For example, in 300A, the expected configuration is a 16-lane device connected on lanes 0-15. If the response does not match the expected configuration (step 230), the PCIe controller issues an interrupt and the software / firmware determines the new configuration (step 240). Referring again to Figure 3, in 300B, the first component responds with link0 on all 8 upstream lanes to which it is connected, the second component responds with link8 on all 4 upstream lanes to which it is connected, and the third component responds with link12 on all 4 upstream lanes. In this case, the PCIe controller has received information that does not correspond to the current configuration information that the controller has. The expectation in this example is that there is a 16 lane device connected to 16 lanes, and the PCIe controller is receiving information that there are 3 connected components (one connected to 8 lanes and 2 each connected to 4 lanes). Therefore, the PCIe controller issues an interrupt (e.g., using the PCIe IP link management feature or an onboard microcontroller (not shown)). In step 250, the PCIe controller implements the new configuration. For example, again referring to Figure 3 , 300C shows that downstream channels 0-7 are allocated link0 according to the response from the first component, while channels 8-15 are not utilized.

[0019] From this point on, after providing an outage, the link trains as usual and it is in the domain of the software to determine if it must participate and take the necessary steps to fork the link. For example, once it is determined to fork the link, the new configuration is determined. Figure 3 In the example shown, channels 0-7 are configured for use as a first component of an 8-channel component, channels 8-11 are configured for use as a second component of a 4-channel component, and channels 12-15 are configured for use as a third component of a 4-channel component.

[0020] Once the new configuration is programmed as described above, link training may continue or the controller may be reset and link training may restart with the new configuration.

[0021] The provided method may be implemented in a general purpose computer, a processor, or a processor core. By way of example, suitable processors include a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), and / or a state machine. Such processors may be manufactured by configuring a manufacturing process using the result of processed hardware description language (HDL) instructions and other intermediate data including a netlist (such instructions can be stored on a computer readable medium). The result of such processing may be a mask work, which is then used in a semiconductor manufacturing process to manufacture a processor that implements the features of the present disclosure. In addition, although the above method and apparatus are described in the context of controlling and configuring PCIe links and ports, the method and apparatus may be utilized in any interconnect protocol that negotiates link width.

[0022] The methods or flow charts provided herein may be implemented in a computer program, software, or firmware that is incorporated into a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs). For example, the above method may be implemented in processor 102 or on any other processor in computer system 100.

Claims

1. A method implemented in a computer system for determining link bifurcation availability, comprising: allocating, by a controller, a channel including links for one or more components connected according to a first configuration; transmitting an ordered set comprising said assignment to said one or more components, wherein said ordered set is a training sequence for said link; receiving, by the one or more components, the ordered set, wherein a first set of values ​​is received from a first component and a second set of values ​​is received from a second component, the first set of values ​​comprising a first link number of the channel associated with the first component, and the second set of values ​​comprising a second link number of the channel associated with the second component; as well as Based on the values ​​received by the controller via the one or more components not satisfying the first configuration: Send an interrupt; calculating a second configuration; configuring the controller according to the second configuration; and The links are trained as indicated by the second configuration, wherein the training of the links comprises training a first set of links for the first component and training a second set of links for the second component.

2. The method of claim 1, wherein the first configuration is an initial configuration based on an expected number of components.

3. The method of claim 1, wherein said transmitting said ordered set comprises transmitting said training sequence on said channel.

4. The method of claim 1, further comprising: The one or more components transmit a first link number to the controller upon receiving the ordered set as the value. 5 . The method of claim 4 , wherein the first link number is a number selected from link numbers received by each of the one or more components.

6. The method of claim 1, wherein upon receiving the value that does not satisfy the first configuration, information for calculating the second configuration is sent by the controller via a link management feature. The method of claim 6 , wherein the second configuration is an optimized configuration for link training.

8. The method of claim 7, wherein the calculating the second configuration comprises allocating a lane comprising the link for a first component of the one or more components.

9. The method of claim 8, wherein the calculating the second configuration comprises allocating a channel, the channel comprising a link for a second component of the one or more components.

10. The method of claim 1, wherein the channel is a Peripheral Component Interconnect Express (PCIe) channel.

11. An apparatus implemented in a computer system for determining link bifurcation availability, comprising: Controller; as well as one or more components communicatively coupled to the controller via a plurality of physical channels; The controller: allocating the channel, the channel comprising links for one or more components connected according to a first configuration; transmitting an ordered set comprising said assignment to said one or more components, wherein said ordered set is a training sequence for said link; receiving, by the one or more components, the ordered set, wherein a first set of values ​​is received from a first component and a second set of values ​​is received from a second component, the first set of values ​​comprising a first link number of the channel associated with the first component and the second set of values ​​comprising a second link number of the channel associated with the second component; and Based on the values ​​received by the controller via the one or more components not satisfying the first configuration: Send an interrupt; calculating a second configuration; configuring the controller according to the second configuration; and The links are trained as indicated by the second configuration, wherein the controller trains a first set of links for the first component and a second set of links for the second component.

12. The apparatus of claim 11, wherein the first configuration is an initial configuration based on an expected number of components.

13. The apparatus of claim 11, wherein said transmitting said ordered set comprises transmitting said training sequence on said channel.

14. The apparatus of claim 11, further comprising: The one or more components, upon receiving the ordered set as the value, transmit a first link number to the controller.

15. The apparatus of claim 14, wherein the first link number is a number selected from link numbers received by each of the one or more components.

16. The apparatus of claim 11, wherein upon receiving the value that does not satisfy the first configuration, the controller sends information for calculating the second configuration via a link management feature.

17. The apparatus of claim 16, wherein the second configuration is an optimized configuration for link training.

18. The apparatus of claim 17, wherein the calculating the second configuration comprises allocating a channel including the link for a first component of the one or more components.

19. The apparatus of claim 18, wherein the calculating the second configuration comprises allocating a channel, the channel comprising a link for a second component of the one or more components.

20. The apparatus of claim 11, wherein the channel is a Peripheral Component Interconnect Express (PCIe) channel.

21. The apparatus of claim 11, the one or more components being Peripheral Component Interconnect Express (PCIe) components.

22. A non-transitory computer-readable medium for providing services for tasks in a computer system, the non-transitory computer-readable medium having instructions recorded thereon, the instructions, when executed by a processor, causing the processor to perform operations comprising: allocating a channel, the channel comprising links for one or more components connected according to a first configuration; transmitting an ordered set comprising said assignment to said one or more components, wherein said ordered set is a training sequence for said link; receiving, by the one or more components, the ordered set, wherein a first set of values ​​is received from a first component and a second set of values ​​is received from a second component, the first set of values ​​comprising a first link number of the channel associated with the first component, and the second set of values ​​comprising a second link number of the channel associated with the second component; as well as Based on the value received by the one or more components not satisfying the first configuration: Send an interrupt; calculating a second configuration; configuring the controller according to the second configuration; and The links are trained as indicated by the second configuration, wherein the training of the links comprises training a first set of links for the first component and training a second set of links for the second component.

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