Data transmission method, device, equipment and computer readable storage medium

Abstract

The present application discloses a data transmission method, including: setting the read / write type of the LPC bus to the IO read / write type; under the IO read / write type, sending first data to the BMC through the LPC bus; receiving second data sent by the BMC through the LPC bus; the first data and the second data include index and level signals. The method adopts the LPC bus to transmit the level signal, which can avoid complex hardware pin wiring while realizing power-on interaction and interrupt functions. The present application also discloses a data transmission device, equipment and computer-readable storage medium, all of which have the above-mentioned technical effects.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a data transmission method; and also to a data transmission device, equipment and a computer-readable storage medium. Background Art

[0002] Reliable, easy-to-use management features and additional service functions of servers are becoming the core competitiveness that major server manufacturers urgently need. The birth of IPMI (Intelligent Platform Management Interface) has solved the problem of reliable server management. IPMI defines the communication protocol between hardware devices on the server motherboard and the communication protocol interface between SMS (System Management Software) and hardware devices on the server motherboard. The core of IPMI is BMC (Baseboard Management Controller). The management of each managed device by the system management software is achieved through communication with BMC. Among them, when the system is started, it is necessary to judge the status of BMC to decide whether it needs to be powered on, so an interactive response is required between the system and BMC. The traditional power-on method is to connect to the external CPLD through the system's hardware pins for power-on, which is very inconvenient. In addition, the interrupt caused by BMC also requires hardware wiring. It is relatively complicated to implement power-on and interrupts through hardware pin wiring.

[0003] Therefore, how to solve the above technical defects has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] The purpose of the present application is to provide a data transmission method that can achieve power-on interaction and interrupt functions while avoiding complex hardware pin connections. Another purpose of the present application is to provide a data transmission device, equipment and computer-readable storage medium, all of which have the above technical effects.

[0005] In order to solve the above technical problems, the present application provides a data transmission method, including:

[0006] Set the read / write type of the LPC bus to IO read / write type;

[0007] In the IO read-write type, first data is sent to the BMC through the LPC bus;

[0008] Receiving second data sent by the BMC through the LPC bus;

[0009] The first data and the second data include an index and a level signal.

[0010] Optionally, the bit width of the first data and the second data is 16 bits, the upper 8 bits are the index, and the lower 8 bits are the level signal.

[0011] Optionally, the upper 4 bits of the level signal serve as a mask for the lower 4 bits of the level signal.

[0012] Optionally, also include:

[0013] An address is sent to the BMC via the LPC bus, and an address sent by the BMC via the LPC bus is received.

[0014] Optionally, the bit width of the address is 16 bits.

[0015] In order to solve the above technical problems, the present application also provides a data transmission device, including:

[0016] A setting module is used to set the read / write type of the LPC bus to the IO read / write type;

[0017] A sending module, used for sending first data to the BMC through the LPC bus under the IO read-write type;

[0018] A receiving module, used for receiving second data sent by the BMC through the LPC bus;

[0019] The first data and the second data include an index and a level signal.

[0020] Optionally, the bit width of the first data and the second data is 16 bits, the upper 8 bits are the index, and the lower 8 bits are the level signal.

[0021] Optionally, the upper 4 bits of the level signal serve as a mask for the lower 4 bits of the level signal.

[0022] In order to solve the above technical problems, the present application also provides a data transmission device, including:

[0023] Memory for storing computer programs;

[0024] A processor is used to implement the steps of the data transmission method as described in any one of the above when executing the computer program.

[0025] In order to solve the above technical problems, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the data transmission method as described in any one of the above items are implemented.

[0026] The data transmission method provided by the present application includes: setting the read / write type of the LPC bus to the IO read / write type; under the IO read / write type, sending first data to the BMC through the LPC bus; receiving second data sent by the BMC through the LPC bus; the first data and the second data include an index and a level signal. It can be seen that compared with the traditional technical solution of transmitting level signals by connecting hardware pins in order to realize power-on interaction and interrupt functions, the data transmission method provided by the present application packages the level signals for transmission through the LPC bus, so that there is no need for complex hardware connection with the BMC, and the power-on interaction and interrupt functions with the BMC can be completed conveniently.

[0027] The data transmission device, equipment and computer-readable storage medium provided in this application all have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the prior art and the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A flowchart of a data transmission method provided in an embodiment of the present application;

[0030] Figure 2 A list of LPC bus signals provided in an embodiment of the present application;

[0031] Figure 3 A timing diagram of an IO read and write mode of an LPC bus provided in an embodiment of the present application;

[0032] Figure 4 A LAD[3:1] definition list provided in an embodiment of the present application;

[0033] Figure 5 A timing diagram of a host sending a signal to a BMC provided in an embodiment of the present application;

[0034] Figure 6 A timing diagram of a BMC sending a signal to a host provided in an embodiment of the present application;

[0035] Figure 7 A schematic diagram of a data transmission device provided in an embodiment of the present application;

[0036] Figure 8 A schematic diagram of a data transmission device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The core of this application is to provide a data transmission method, which can realize power-on interaction and interruption functions while avoiding complex hardware pin wiring. Another core of this application is to provide a data transmission device, equipment and computer-readable storage medium, all of which have the above technical effects.

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] Please refer to Figure 1 , Figure 1 A schematic diagram of a data transmission method provided in an embodiment of the present application, referring to Figure 1 As shown, the method includes:

[0040] S101: Set the read / write type of the LPC bus to IO read / write type;

[0041] Specifically, in the traditional technical solution, the way to transmit the level signal to realize power-on interaction or interruption is to transmit it through the hard wire connected between the hardware pins on the basis of connecting the hardware pins. For example, the level signal to be transmitted is 1, 0, 1, 1. The traditional technical solution needs to connect four hardware pins, transmit the level signal 1 through the hard wire connected to the first hardware pin, transmit the level signal 0 through the hard wire connected to the second hardware pin, transmit the level signal 1 through the hard wire connected to the third hardware pin, and transmit the level signal 1 through the hard wire connected to the fourth hardware pin. Different from the traditional technical solution, the present application adopts the LPC bus to transmit the level signal. The full name of LPC in English is Low PinCount, which is a bus proposed by Intel Corporation and is used to replace the traditional ISA (Industry Standard Architecture) bus in the computer system. The LPC bus includes functions such as IO read and write, memory read and write, and DMA (Direct Memory Access) operation. In this embodiment, the read / write type of the LPC bus is set to the IO read / write type, and the IO read / write operation of the LPC bus is used to transmit the level signal without complicated hardware pin connection.

[0042] The interface signals used in this embodiment are as follows: Figure 2 In addition, refer to Figure 3The timing diagram of the LPC bus IO read and write mode is shown in the figure. An access cycle usually follows Figure 3 When the LFARAM# signal is low, it indicates the start of an access cycle, and the LAD signal is START. In IO read / write mode, LAD[3:0] is 0. Figure 4 In the second clock shown, the definition of LAD[3:1], the read / write type used in this embodiment is IO read / write, so LAD[3:2] is 00. In the first clock phase of TAR, LAD[3:0] is 4'b1111, and in the second clock phase, it is driven to three states.

[0043] S102: sending first data to the BMC through the LPC bus under the IO read / write type;

[0044] S103: receiving second data sent by the BMC through the LPC bus;

[0045] The first data and the second data include an index and a level signal.

[0046] Among them, it also includes:

[0047] An address is sent to the BMC via the LPC bus, and an address sent by the BMC via the LPC bus is received.

[0048] Specifically, on the basis of setting the read / write type of the LPC bus to the IO read / write type, the host can send an address and first data including an index and a level signal to the BMC via the LPC bus. The address represents the level signal transmitted. The index is used to identify the type of function implemented. For example, the power-on function or the interrupt function is implemented.

[0049] Different from the traditional technical solution of transmitting level signals through hard wires connected between hardware pins, this embodiment adopts LPC bus to transmit level signals in the form of data packets. For example, when the level signals to be transmitted are 1, 0, 1, 1, the LPC bus is used to transmit 1, 0, 1, 1 in the form of data packets.

[0050] It should be noted that the above expressions "first" and "second" are only used to distinguish the subject of the sent data, and are not used as a limitation on the order, size, etc. The first data refers to the data sent by the host to the BMC, and the second data refers to the data sent by the BMC to the host.

[0051] Based on the above embodiment, as a specific implementation method, the bit width of the address is 16 bits.

[0052] Specifically, in this embodiment, the bit width of the address is 16 bits. In addition, the value of the address can be 0x0007. It is understood that the bit width of the address and the specific value of the address can also be set to other bit widths and values, and this application does not make a unique limitation on this, and can be set differently.

[0053] Further, based on the above embodiment, as a specific implementation manner, the bit width of the first data and the second data is 16 bits, wherein the upper 8 bits are the index and the lower 8 bits are the level signal.

[0054] Specifically, in this embodiment, the bit widths of the first data and the second data are 16 bits, and the index and the level signal each occupy 8 bits.

[0055] refer to Figure 5 As shown in the timing diagram, for the host, the host sends a 16-bit address, an 8-bit index, and an 8-bit level signal in sequence in the IO read and write mode of the LPC bus.

[0056] refer to Figure 6 As shown, for BMC, after the host initiates a read command and sends a 16-bit address, the BMC returns an 8-bit index and an 8-bit level signal.

[0057] Further, based on the above embodiment, as a specific implementation manner, the upper 4 bits of the level signal are shielded from the lower 4 bits of the level signal.

[0058] Specifically, in this embodiment, the level signal is divided into two parts: a shield and a real level signal. The high 4 bits of the level signal are marks or shields of the corresponding low 4 bits. That is, the 8th bit is a shield of the 4th bit, the 7th bit is a shield of the 3rd bit, the 6th bit is a shield of the 2nd bit, and the 5th bit is a shield of the 1st bit. When one of the high 4 bits is 1, the data of the corresponding one of the low 4 bits is valid; on the contrary, if one of the high 4 bits is 0, the data of the corresponding one of the low 4 bits remains unchanged. For example, if the 8th bit is 1, the corresponding data of the 4th bit is valid. If the 7th bit is 0, the corresponding data of the 3rd bit remains unchanged.

[0059] Each index can represent a group of GPIOs (General-purpose input / output), each group of 4 GPIOs. If the index interval 128 to 255 is defined to represent the interval of GPIOs, then a total of 128*4=512 GPIOs can be included.

[0060] For example, when the index is 128, it indicates the first group of GPIO[3:0], and the level signal is 11000011. The lower four bits 0011 are the data of GPIO[3] to GPIO[0]. Since the upper 4 bits of the level signal are 1100, the data of GPIO[3] and GPIO[2] are valid, while GPIO[1] and GPIO[0] remain unchanged. In other words, the upper two bits in 0011 are valid, and no matter what the data of the lowest two bits is, GPIO[1] and GPIO[0] will remain unchanged, that is, 11 in the lower four bits 0011 has no effect.

[0061] Furthermore, based on the above embodiment, it also includes: after the data transmission is completed, the state of the dotted line mark signal is changed.

[0062] Specifically, compared with the technical solution of using hard wire to transmit level signal, the present application uses LPC bus to transmit level signal. In the traditional technical solution, the level signal transmitted by hard wires 1 to 4 can be correspondingly defined as the data of dotted lines 1 to 4 in the present technical solution. For example, for the level signal 1011, the 1 in the 4th bit can be positioned as the data of dotted line 1; the 0 in the 3rd bit can be defined as the data of dotted line 2; the 1 in the 2nd bit can be defined as the data of dotted line 3; the 1 in the 1st bit can be defined as the data of dotted line 4. For each dotted line, a corresponding dotted line flag signal is preset. At the end of each transmission, the state of the dotted line flag signal is changed.

[0063] As shown in Figure 5, at the end of the transmission, a dotted line mark signal ( Figure 5 ) changes from low to high. Correspondingly, as shown in 6, at the end of the transmission, the host's dotted line flag signal ( Figure 6 vwire) shown in ) changes from low to high.

[0064] It should be noted that Figure 5 as well as Figure 6 Only one dotted line flag signal is indicated in the figure. For each index, a group of GPIOs can be represented. In the case of 4 GPIOs in each group, the number of dotted line flag signals of the host and the number of dotted line flag signals of the BMC are both 4. Therefore, at the end of the transmission, the 4 dotted line flag signals are changed accordingly.

[0065] In summary, the data transmission method provided by the present application includes: setting the read / write type of the LPC bus to IO read / write; under the read / write type, sending first data to the BMC through the LPC bus; receiving second data sent by the BMC through the LPC bus; the first data and the second data include an index and a level signal. It can be seen that compared with the traditional technical solution of transmitting level signals by connecting hardware pins in order to realize power-on interaction and interrupt functions, the data transmission method provided by the present application packages the level signals for transmission through the LPC bus, so that there is no need for complex hardware wiring with the BMC, and the power-on interaction and interrupt functions with the BMC can be completed conveniently.

[0066] The present application also provides a data transmission device, and the device described below can be referred to in correspondence with the method described above. Figure 7 , Figure 7 A schematic diagram of a data transmission device provided in an embodiment of the present application, combined with Figure 7 As shown, the device comprises:

[0067] A setting module 10 is used to set the read / write type of the LPC bus to IO read / write;

[0068] A sending module 20, configured to send first data to the BMC via the LPC bus in the read-write type;

[0069] A receiving module 30, configured to receive second data sent by the BMC via the LPC bus;

[0070] The first data and the second data include an index and a level signal.

[0071] Specifically, different from the conventional technical solution of transmitting the level signal through the hard wire connected between the hardware pins on the basis of connecting the hardware pins, the present embodiment adopts the IO read and write operation of the LPC bus to transmit the level signal. The read and write type of the LPC bus is set to the IO read and write type by the setting module 10. On the basis of the setting module 10 setting the read and write type of the LPC bus to the IO read and write type, the sending module 20 sends the first data including the index and the level signal to the BMC through the LPC bus. In addition, the receiving module 30 receives the second data including the index and the level signal sent by the BMC.

[0072] The sending module 20 also sends an address to the BMC via the LPC bus, and the receiving module 30 receives the address sent by the BMC via the LPC bus. The address represents the level signal transmitted. The index is used to identify the type of function implemented. For example, the power-on function or the interrupt function is implemented.

[0073] Different from the traditional technical solution of transmitting level signals through hard wires connected between hardware pins, this embodiment adopts LPC bus to transmit level signals in the form of data packets. For example, when the level signals to be transmitted are 1, 0, 1, 1, the LPC bus is used to transmit 1, 0, 1, 1 in the form of data packets.

[0074] It should be noted that the above-mentioned expressions "first" and "second" are only used to distinguish the subjects of sending data, and are not used as limitations on the order, size, etc.

[0075] Based on the above embodiment, as a specific implementation manner, the bit width of the first data and the second data is 16 bits, wherein the upper 8 bits are the index and the lower 8 bits are the level signal.

[0076] Specifically, in this embodiment, the bit width of the first data and the second data is 16 bits, and the index and the level signal each occupy 8 bits. In the IO read and write mode of the LPC bus, the sending module 20 sends a 16-bit address, an 8-bit index, and an 8-bit level signal in sequence. The receiving module 30 receives the 8-bit index and the 8-bit level signal returned by the BMC in sequence.

[0077] Based on the above embodiment, as a specific implementation manner, the upper 4 bits of the level signal are shielded from the lower 4 bits of the level signal.

[0078] Specifically, in this embodiment, the level signal is divided into two parts: a shield and a real level signal. The high 4 bits of the level signal are marks or shields of the corresponding low 4 bits. That is, the 8th bit is a shield of the 4th bit, the 7th bit is a shield of the 3rd bit, the 6th bit is a shield of the 2nd bit, and the 5th bit is a shield of the 1st bit. When one of the high 4 bits is 1, the data of the corresponding one of the low 4 bits is valid; on the contrary, if one of the high 4 bits is 0, the data of the corresponding one of the low 4 bits remains unchanged. For example, if the 8th bit is 1, the corresponding data of the 4th bit is valid. If the 7th bit is 0, the corresponding data of the 3rd bit remains unchanged.

[0079] Each index can represent a group of GPIOs (General-purpose input / output), each group of 4 GPIOs. If the index interval 128 to 255 is defined to represent the interval of GPIOs, then a total of 128*4=512 GPIOs can be included.

[0080] For example, when the index is 128, it indicates the first group of GPIO[3:0], and the level signal is 11000011. The lower four bits 0011 are the data of GPIO[3] to GPIO[0]. Since the upper 4 bits of the level signal are 1100, the data of GPIO[3] and GPIO[2] are valid, while GPIO[1] and GPIO[0] remain unchanged. In other words, the upper two bits in 0011 are valid, and no matter what the data of the lowest two bits is, GPIO[1] and GPIO[0] will remain unchanged, that is, 11 in the lower four bits 0011 has no effect.

[0081] Based on the above embodiment, as a specific implementation method, the bit width of the address is 16 bits.

[0082] Specifically, in this embodiment, the bit width of the address is 16 bits. In addition, the value of the address can be 0x0007. It can be understood that the bit width of the address and the specific value of the address can also be set to other bit widths and values.

[0083] Based on the above embodiment, as a specific implementation method, it also includes:

[0084] The adjustment module is used to change the state of the virtual flag signal after the data transmission is completed.

[0085] Specifically, compared with the technical solution of using hard wires to transmit level signals, the present application uses LPC bus to transmit level signals. In the traditional technical solution, the level signal transmitted by hard wires 1 to 4 can be correspondingly defined as being transmitted by dotted lines 1 to 4 in the present technical solution. For example, for the level signal 1011, the 1 in the 4th bit can be positioned as the data of dotted line 1; the 0 in the 3rd bit can be defined as the data of dotted line 2; the 1 in the 2nd bit can be defined as the data of dotted line 3; the 1 in the 1st bit can be defined as the data of dotted line 4. For each dotted line, a corresponding dotted line flag signal is preset. At the end of each transmission, the adjustment module changes the state of the dotted line flag signal.

[0086] As shown in Figure 5, at the end of the transmission, a dotted line mark signal ( Figure 5 ) changes from low to high. Correspondingly, as shown in 6, at the end of the transmission, the host's dotted line flag signal ( Figure 6 vwire) shown in ) changes from low to high.

[0087] Compared with the traditional technical solution of transmitting level signals by connecting hardware pins in order to realize power-on interaction and interrupt functions, the data transmission device provided in the present application packages the level signals for transmission through the LPC bus, which does not require complex hardware connection with the BMC and can conveniently complete the power-on interaction and interrupt functions with the BMC.

[0088] The present application also provides a data transmission device, referring to Figure 8 As shown, the device includes a memory 1 and a processor 2 .

[0089] Memory 1, used for storing computer programs;

[0090] Processor 2 is used to execute the computer program to implement the following steps:

[0091] Set the read / write type of the LPC bus to IO read / write type;

[0092] In the IO read-write type, first data is sent to the BMC through the LPC bus;

[0093] Receiving second data sent by the BMC through the LPC bus;

[0094] The first data and the second data include an index and a level signal.

[0095] For an introduction to the equipment provided in this application, please refer to the above method embodiments, and this application will not go into details here.

[0096] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps can be implemented:

[0097] Set the read / write type of the LPC bus to IO read / write type;

[0098] In the IO read-write type, first data is sent to the BMC through the LPC bus;

[0099] Receiving second data sent by the BMC through the LPC bus;

[0100] The first data and the second data include an index and a level signal.

[0101] The computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0102] For an introduction to the computer-readable storage medium provided in this application, please refer to the above method embodiment, and this application will not go into details here.

[0103] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the devices, equipment, and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0104] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0105] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0106] The data transmission method, device, equipment and computer-readable storage medium provided by the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A data transmission method, characterized in that: include: Set the read / write type of the LPC bus to IO read / write type; In the IO read-write type, first data is sent to the BMC through the LPC bus; Receiving second data sent by the BMC through the LPC bus; The first data and the second data include index and level signals; The index is used to identify the type of function implemented; the function type includes power-on function and interrupt function; each index represents a group of GPIO; the upper 4 bits of the level signal are the mask of the lower 4 bits of the level signal, when one of the upper 4 bits is 1, the data of the corresponding one of the lower 4 bits is valid; when one of the upper 4 bits is 0, the data of the corresponding one of the lower 4 bits remains unchanged.

2. The data transmission method according to claim 1, characterized in that: The bit width of the first data and the second data is 16 bits, wherein the upper 8 bits are the index and the lower 8 bits are the level signal.

3. The data transmission method according to claim 1, characterized in that: Also includes: An address is sent to the BMC via the LPC bus, and an address sent by the BMC via the LPC bus is received.

4. The data transmission method according to claim 3, characterized in that: The bit width of the address is 16 bits.

5. A data transmission device, characterized in that: include: A setting module is used to set the read / write type of the LPC bus to the IO read / write type; A sending module, used for sending first data to the BMC through the LPC bus under the IO read-write type; A receiving module, used for receiving second data sent by the BMC through the LPC bus; The first data and the second data include index and level signals; The index is used to identify the type of function implemented; the function type includes power-on function and interrupt function; each index represents a group of GPIO; the upper 4 bits of the level signal are the mask of the lower 4 bits of the level signal, when one of the upper 4 bits is 1, the data of the corresponding one of the lower 4 bits is valid; when one of the upper 4 bits is 0, the data of the corresponding one of the lower 4 bits remains unchanged.

6. The data transmission device according to claim 5, characterized in that: The bit width of the first data and the second data is 16 bits, wherein the upper 8 bits are the index and the lower 8 bits are the level signal.

7. A data transmission device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data transmission method according to any one of claims 1 to 4 when executing the computer program.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data transmission method according to any one of claims 1 to 4 are implemented.

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