An implementation method, device and equipment of a particle filtering algorithm and a readable medium

Abstract

The application discloses an implementation method of a particle filtering algorithm, and comprises the following steps: decomposing the particle filtering algorithm to obtain a plurality of mathematical calculation steps, designing a plurality of hardware calculation units and a plurality of extensible instructions based on the mathematical calculation steps; embedding the plurality of hardware calculation units into an execution layer in a pipeline manner, and sequentially mapping the plurality of extensible instructions to an instruction buffer memory; obtaining an address value in an instruction counter, and obtaining a corresponding extensible instruction from the instruction buffer memory based on the address value; sending an activation signal to a corresponding hardware calculation unit in the execution layer based on the corresponding extensible instruction, so as to perform a calculation operation of the corresponding hardware calculation unit, and storing a calculation result obtained in a corresponding register; and processing the calculation result in all registers based on a load storage unit to obtain an optimal solution of the particle filtering algorithm. The application further discloses an implementation device of the particle filtering algorithm, a computer device and a readable storage medium.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of particle filtering technology, and in particular to a particle filtering algorithm implementation method, device, equipment and readable medium. BACKGROUND

[0002] Particle filter (PF) refers to: finding a set of random samples propagating in the state space to approximate the identification probability density function, replacing the integral operation with the sample mean, and then obtaining the minimum variance estimation of the system state. These samples are called "particles" and are called particle filtering.

[0003] The superiority of particle filtering technology in nonlinear and non-Gaussian systems determines that its application range is very wide. In addition, the multi-modal processing capability of the particle filter is also one of the reasons for its wide application. Internationally, particle filtering has been applied in various fields. In the field of economics, it is applied in economic data prediction; in the military field, it has been applied to radar tracking of airborne objects, passive tracking of air-to-air and air-to-ground; in the field of traffic control, it is applied to vehicle or human video monitoring; it is also used for global positioning of robots.

[0004] However, as a new method, particle filtering is still in development and there are many problems to be solved. For example, the operation amount required by particle filtering is extremely large, and pure software implementation is difficult to guarantee real-time performance, which is one of the bottlenecks encountered in the development of particle filtering.

[0005] At present, the scheme of particle filtering algorithm hardware acceleration is mostly realized by FPGA. The use of FPGA to realize particle filtering algorithm hardware acceleration can indeed reflect the characteristics of FPGA pipeline parallelism and data parallelism, but the existing scheme only realizes an independent particle filtering algorithm accelerator, and cannot realize other ordinary operations, the function is relatively single, and the universality is low. After the hardware circuit is realized, it is difficult to easily change. If the particle filtering algorithm needs to be slightly adjusted, in the case where the CPU general instruction cannot be used, the hardware circuit must be redesigned. SUMMARY

[0006] Therefore, the purpose of the embodiments of the present application is to provide a particle filtering algorithm implementation method, device, equipment and readable medium,

[0007] In order to achieve the above object, one aspect of the embodiment of the present application provides a method for implementing a particle filter algorithm, comprising the following steps: decomposing the particle filter algorithm to obtain a plurality of mathematical calculation steps, designing a plurality of hardware calculation units and a plurality of extensible instructions based on the mathematical calculation steps; embedding the plurality of hardware calculation units into an execution layer in a pipeline manner, and sequentially mapping the plurality of extensible instructions into an instruction buffer memory; obtaining an address value in an instruction counter, and obtaining a corresponding extensible instruction from the instruction buffer memory based on the address value; sending an activation signal to a corresponding hardware calculation unit in the execution layer based on the corresponding extensible instruction, so as to perform a calculation operation of the corresponding hardware calculation unit, and storing a calculation result obtained in a corresponding register; and processing the calculation result in all registers by a load storage unit to obtain an optimal solution of the particle filter algorithm.

[0008] In some embodiments, the method further comprises: obtaining high-level language code input by an application layer, and inputting the high-level language code into a compiler to obtain assembly instructions; storing the assembly instructions in a memory, and mapping the assembly instructions from the memory to the instruction buffer memory.

[0009] In some embodiments, the plurality of mathematical calculation steps at least comprise particle initialization, weight updating, resampling and state value calculation; the plurality of hardware calculation units at least comprise a particle initialization module, a weight updating module, a resampling module and a state value calculation module; and the plurality of extensible instructions at least comprise a particle initialization instruction, a weight updating instruction, a resampling instruction and a state value calculation instruction.

[0010] In some embodiments, obtaining an address value in an instruction counter and obtaining a corresponding extensible instruction from the instruction buffer memory based on the address value comprises: obtaining the address value in the instruction counter in real time by a fetch unit, and obtaining the corresponding extensible instruction from the instruction buffer memory based on the address value.

[0011] In some embodiments, sending an activation signal to a corresponding hardware calculation unit in the execution layer based on the corresponding extensible instruction comprises: generating a corresponding activation signal by a decoder based on the corresponding extensible instruction, and sending the activation signal to the corresponding hardware calculation unit in the execution layer.

[0012] In some embodiments, the method further comprises: the register performing data interaction with the memory through the load storage unit.

[0013] Another aspect of the embodiments of the present application also provides an implementation device of a particle filtering algorithm, comprising: a first module configured to decompose the particle filtering algorithm to obtain a plurality of mathematical calculation steps, and design a plurality of hardware calculation units and a plurality of extensible instructions based on the mathematical calculation steps; a second module configured to embed the plurality of hardware calculation units into an execution layer in a pipeline manner, and sequentially map the plurality of extensible instructions into an instruction buffer memory; a third module configured to obtain an address value in an instruction counter, and obtain a corresponding extensible instruction from the instruction buffer memory based on the address value; a fourth module configured to send an activation signal to a corresponding hardware calculation unit in the execution layer based on the corresponding extensible instruction, to perform a calculation operation of the corresponding hardware calculation unit, and store a calculation result obtained into a corresponding register; and a fifth module configured to process the calculation results in all registers based on a load storage unit to obtain an optimal solution of the particle filtering algorithm.

[0014] In some embodiments, the method further comprises: obtaining high-level language code input by an application layer, and inputting the high-level language code into a compiler to obtain assembly instructions; and storing the assembly instructions into a memory, and mapping the assembly instructions from the memory into the instruction buffer memory.

[0015] Another aspect of the embodiments of the present application also provides a computer device, comprising: at least one processor; and a memory storing computer instructions executable on the processor, and the instructions, when executed by the processor, implement steps of a method comprising: decomposing a particle filtering algorithm to obtain a plurality of mathematical calculation steps, and designing a plurality of hardware calculation units and a plurality of extensible instructions based on the mathematical calculation steps; embedding the plurality of hardware calculation units into an execution layer in a pipeline manner, and sequentially mapping the plurality of extensible instructions into an instruction buffer memory; obtaining an address value in an instruction counter, and obtaining a corresponding extensible instruction from the instruction buffer memory based on the address value; sending an activation signal to a corresponding hardware calculation unit in the execution layer based on the corresponding extensible instruction, to perform an operation of the corresponding hardware calculation unit, and storing a calculation result obtained into a corresponding register; and processing the calculation results in all registers based on a load storage unit to obtain an optimal solution of the particle filtering algorithm.

[0016] In some embodiments, the method further comprises: obtaining high-level language code input by an application layer, and inputting the high-level language code into a compiler to obtain assembly instructions; and storing the assembly instructions into a memory, and mapping the assembly instructions from the memory into the instruction buffer memory.

[0017] In some embodiments, the plurality of mathematical calculation steps comprise at least particle initialization, weight update, resampling and state value calculation; the plurality of hardware calculation units comprise at least a particle initialization module, a weight update module, a resampling module and a state value calculation module; and the plurality of extensible instructions comprise at least a particle initialization instruction, a weight update instruction, a resampling instruction and a state value calculation instruction.

[0018] In some embodiments, the obtaining of the address value in the instruction counter and the obtaining of the corresponding extensible instruction from the instruction buffer memory based on the address value comprise: real-time obtaining, by the instruction fetch unit, of the address value in the instruction counter and obtaining, based on the address value, of the corresponding extensible instruction from the instruction buffer memory.

[0019] In some embodiments, the sending of the activation signal to the corresponding hardware calculation unit in the execution layer based on the corresponding extensible instruction comprises: generating, by the decoder, a corresponding activation signal based on the corresponding extensible instruction and sending the activation signal to the corresponding hardware calculation unit in the execution layer.

[0020] In some embodiments, the method further comprises: the register interacting with the memory for data by the load store unit.

[0021] In still another aspect of the embodiments of the present application, a computer readable storage medium is provided, which stores a computer program that, when executed by a processor, implements the method steps as described above.

[0022] The present application has at least the following beneficial technical effects: the prior scheme only implements an independent particle filter algorithm accelerator, cannot implement other ordinary operations, has a relatively single function and low versatility. After the hardware circuit is implemented, it is difficult to easily modify. If the particle filter algorithm needs to be slightly adjusted, the hardware circuit needs to be redesigned in the case that the CPU general instruction cannot be used. However, the instruction extension provided by the present application does not need to worry about this point. If the algorithm needs to be adjusted, other general instructions can be used instead. In addition, if the particle filter algorithm accelerator is externally connected to a CPU, the control signal and data interaction between the accelerator and the CPU will occupy a considerable amount of time. However, the instruction extension provided by the present application does not have such a problem. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other embodiments can also be obtained from these drawings without creative labor.

[0024] Figure 1 A schematic diagram of an embodiment of the implementation method of the particle filtering algorithm provided by the present application is shown in the figure.

[0025] Figure 2 A processor schematic diagram of the implementation method of the particle filtering algorithm provided by the present application is shown in the figure.

[0026] Figure 3 A schematic diagram of an embodiment of the implementation device of the particle filtering algorithm provided by the present application is shown in the figure.

[0027] Figure 4 A schematic diagram of an embodiment of the computer device provided by the present application is shown in the figure.

[0028] Figure 5 A schematic diagram of an embodiment of the computer readable storage medium provided by the present application is shown in the figure. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application are further described in detail below with reference to the accompanying drawings.

[0030] It should be noted that all the expressions of "first" and "second" in the embodiments of the present application are used to distinguish two same-named different entities or different parameters, and the "first" and "second" are only used for the convenience of description, and should not be understood as a limitation of the embodiments of the present application. The subsequent embodiments will not be described one by one.

[0031] Based on the above purpose, the first aspect of the embodiments of the present application proposes an embodiment of the implementation method of the particle filtering algorithm. Figure 1 A schematic diagram of an embodiment of the implementation method of the particle filtering algorithm provided by the present application is shown in the figure. As shown in the figure, Figure 1 The implementation method of the particle filtering algorithm in the embodiments of the present application includes the following steps:

[0032] 001, the particle filtering algorithm is disassembled to obtain a plurality of mathematical calculation steps, a plurality of hardware calculation units and a plurality of extensible instructions are designed based on the mathematical calculation steps;

[0033] 002, a plurality of hardware calculation units are embedded in the execution layer in a pipeline manner, and a plurality of extensible instructions are sequentially mapped into the instruction buffer memory;

[0034] 003, the address value in the instruction counter is obtained, and the corresponding extension instruction is obtained from the instruction buffer memory based on the address value;

[0035] 004、sending an activation signal to the corresponding hardware computing unit in the execution layer based on the corresponding extended instruction, to perform the computing operation of the corresponding hardware computing unit, and store the obtained computing result in the corresponding register; and

[0036] 005、processing the computing results in all registers by the load storage unit to obtain the optimal solution of the particle filtering algorithm.

[0037] In the embodiment, the huge computation required by the particle filtering algorithm is completed by the special execution unit of the processor. RISC-V is an open reduced instruction set architecture, which allows users to freely extend on the basis of its standard instruction set; specifically including the following: the particle filtering algorithm is disassembled to obtain different mathematical computing steps; the corresponding hardware computing unit and the corresponding extensible instruction are designed according to the above computing steps; the instruction is embedded in the pipeline execution stage of the RISC-V processor core; the supporting compiler is designed to compile the task obtained from the application layer into assembly instructions.

[0038] In some embodiments of the application, the method further comprises: obtaining the high-level language code input by the application layer, and inputting the high-level language code into the compiler to obtain the assembly instructions; storing the assembly instructions in the memory and mapping them to the instruction buffer memory from the memory.

[0039] In some embodiments of the application, the plurality of mathematical computing steps at least include: particle initialization, weight update, resampling and state value calculation; the plurality of hardware computing units at least include: a particle initialization module, a weight update module, a resampling module and a state value calculation module; and the plurality of extensible instructions at least include: a particle initialization instruction, a weight update instruction, a resampling instruction and a state value calculation instruction.

[0040] In the embodiment, the particle filtering algorithm is generally divided into the following steps:

[0041] (1) particle set initialization: the system prior probability is selected as the importance density function, and the sampling particles are generated, all particles are assigned the same weight;

[0042] (2) update weight: the weight of each particle is calculated by the weight iteration formula, and then normalized;

[0043] (3) resampling: to prevent the phenomenon of particle degradation, high-weight particles are retained and copied, and low-weight particles are discarded;

[0044] (4) calculate state estimation value: constantly repeat steps (2) and (3), and calculate the state estimation value when the optimal solution of the system state is obtained.

[0045] In some embodiments of the present invention, obtaining the address value in the instruction counter and obtaining the corresponding extended instruction from the instruction buffer memory based on the address value includes: the instruction fetch unit obtaining the address value in the instruction counter in real time and obtaining the corresponding extended instruction from the instruction buffer memory based on the address value.

[0046] In some embodiments of the present invention, sending an activation signal to the corresponding hardware computing unit in the execution layer based on the corresponding extended instruction includes: generating a corresponding activation signal by the decoder based on the corresponding extended instruction, and sending the activation signal to the corresponding hardware computing unit in the execution layer.

[0047] In some embodiments of the present invention, the method further includes: the register interacting with memory via a loading storage unit.

[0048] The specific embodiments of the present invention are further described below with reference to specific examples. Figure 2 The diagram shown is a processor schematic of the implementation method of the particle filter algorithm provided by the present invention, as follows: Figure 2 As shown, this processor includes an instruction buffer, a programmable counter (PC), an instruction fetch unit, a decoder, a load balancer (LSU), and a cache (memory), which together form a complete processor. The instruction buffer (I$) stores the actual instructions; the PC stores the address of the next access, and increments as instructions are executed sequentially; the instruction fetch unit retrieves instructions from the instruction buffer and passes them to the decoder; the decoder decodes the received instructions, identifies them, and sends a signal to activate the execution unit; the LSU reads and writes data from memory to registers; and the cache is used to improve the data exchange rate between the CPU and main memory.

[0049] In this embodiment, the programmer writes high-level language code at the application layer, which is then compiled into assembly instructions and stored in DDR (DDR memory). Data in DDR is mapped into the cache and I$ (instruction buffer). I$ stores instructions, arranged sequentially. The PC value changes according to demand, and the instruction fetch unit fetches instructions based on the current PC value. Instructions are retrieved from I$ by the instruction fetch unit and passed to the decoder. The decoder decodes the instructions and then sends corresponding activation signals to each module in the execution layer. The data and calculation results required by the execution module are stored in registers, and the LSU (Large Unit Buffer) is responsible for data exchange between the registers and the cache.

[0050] It should be noted that the steps in each embodiment of the above-mentioned particle filter algorithm implementation method can be interleaved, substituted, added, or deleted. Therefore, these reasonable permutations and combinations of the particle filter algorithm implementation method should also fall within the protection scope of this invention, and the protection scope of this invention should not be limited to the embodiments.

[0051] In order to achieve the above object, the second aspect of the embodiments of the present application provides an implementation device of a particle filter algorithm. Figure 3 Fig. 1 shows a schematic diagram of an embodiment of the implementation device of the particle filter algorithm provided by the present application. As shown in Figure 3 The implementation device of the particle filter algorithm of the embodiments of the present application comprises the following modules: a first module 011 configured to decompose the particle filter algorithm to obtain a plurality of mathematical calculation steps, and to design a plurality of hardware calculation units and a plurality of extensible instructions based on the mathematical calculation steps; a second module 012 configured to embed the plurality of hardware calculation units into an execution layer in a pipeline manner, and to sequentially map the plurality of extensible instructions into an instruction buffer memory; a third module 013 configured to obtain an address value in an instruction counter, and to obtain a corresponding extensible instruction from the instruction buffer memory based on the address value; a fourth module 014 configured to send an activation signal to a corresponding hardware calculation unit in the execution layer based on the corresponding extensible instruction, to perform a calculation operation of the corresponding hardware calculation unit, and to store a calculation result obtained into a corresponding register; and a fifth module 015 configured to process the calculation results in all registers based on a load storage unit to obtain an optimal solution of the particle filter algorithm.

[0052] In some embodiments of the present application, a sixth module is further included, which is configured to obtain a high-level language code input by an application layer, and to input the high-level language code into a compiler to obtain assembly instructions; and to store the assembly instructions into a memory, and to map the assembly instructions from the memory into the instruction buffer memory.

[0053] In order to achieve the above object, the third aspect of the embodiments of the present application provides a computer device. Figure 4 Fig. 2 shows a schematic diagram of an embodiment of the computer device provided by the present application. As shown in Figure 4 The computer device of the embodiments of the present application comprises the following devices: at least one processor 021; and a memory 022, which stores computer instructions 023 executable on the processor, and the instructions executed by the processor implement the steps of the method, including: decomposing a particle filter algorithm to obtain a plurality of mathematical calculation steps, and designing a plurality of hardware calculation units and a plurality of extensible instructions based on the mathematical calculation steps; embedding the plurality of hardware calculation units into an execution layer in a pipeline manner, and sequentially mapping the plurality of extensible instructions into an instruction buffer memory; obtaining an address value in an instruction counter, and obtaining a corresponding extensible instruction from the instruction buffer memory based on the address value; sending an activation signal to a corresponding hardware calculation unit in the execution layer based on the corresponding extensible instruction, to perform a calculation operation of the corresponding hardware calculation unit, and to store a calculation result obtained into a corresponding register; and processing the calculation results in all registers based on a load storage unit to obtain an optimal solution of the particle filter algorithm.

[0054] In some embodiments of the present application, the method further comprises: obtaining the high-level language code input by the application layer, and inputting the high-level language code into a compiler to obtain the assembly instructions; and storing the assembly instructions in the memory and mapping the assembly instructions from the memory to the instruction buffer memory.

[0055] In some embodiments of the present application, the plurality of mathematical calculation steps at least comprise: particle initialization, weight update, resampling and state value calculation; the plurality of hardware calculation units at least comprise: a particle initialization module, a weight update module, a resampling module and a state value calculation module; and the plurality of extensible instructions at least comprise: a particle initialization instruction, a weight update instruction, a resampling instruction and a state value calculation instruction.

[0056] In some embodiments of the present application, the obtaining of the address value in the instruction counter and the obtaining of the corresponding extensible instruction from the instruction buffer memory based on the address value comprise: the obtaining of the address value in the instruction counter in real time by the instruction fetch unit, and the obtaining of the corresponding extensible instruction from the instruction buffer memory based on the address value.

[0057] In some embodiments of the present application, the sending of the activation signal to the corresponding hardware calculation unit in the execution layer based on the corresponding extensible instruction comprises: the generation of the corresponding activation signal by the decoder based on the corresponding extensible instruction, and the sending of the activation signal to the corresponding hardware calculation unit in the execution layer.

[0058] In some embodiments of the present application, the method further comprises: the data interaction of the register with the memory through the load store unit.

[0059] The present application further provides a computer readable storage medium. Figure 5 Shown is a schematic diagram of an embodiment of the computer readable storage medium provided by the present application. Figure 5 As shown, the computer readable storage medium 031 stores a computer program 032 which, when executed by a processor, executes the above method.

[0060] Finally, it needs to be noted that those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by a computer program to instruct related hardware to complete, and the program of the particle filtering algorithm implementation method can be stored in a computer readable storage medium. When the program is executed, it can include the processes of the above-mentioned embodiments of each method. Among them, the storage medium of the program can be a disc, an optical disc, a read-only memory (ROM) or a random access memory (RAM) and the like. The above-mentioned computer program embodiments can achieve the same or similar effects as the corresponding any method embodiments.

[0061] Moreover, the method disclosed by the embodiments of the present application can also be implemented as a computer program executed by a processor, and the computer program can be stored in a computer readable storage medium. When the computer program is executed by the processor, the above-mentioned functions defined in the method disclosed by the embodiments of the present application are performed.

[0062] In addition, the above-mentioned method steps and system units can also be implemented by using a controller and a computer readable storage medium for storing a computer program enabling the controller to implement the above-mentioned steps or unit functions.

[0063] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

[0064] In one or more exemplary designs, the functions described can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media can be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or other wire-based, fiber-based, or wireless technologies, then the coaxial cable, fiber optic cable, twisted pair, DSL, or other wire-based, fiber-based, or wireless technologies are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0065] The foregoing is considered as illustrative of the principles of the application. However, further modifications and changes can occur to those skilled in the art without departing from the scope of the application as defined in the following claims. The singular number of an element in the claims has its "usual" meaning in patent law for that element (i.e., one of one or more of the element). The plural number of an element in the claims has its "usual" meaning in patent law for that element (i.e., two or more of the element). The use of "or" in the claims is used to mean "and / or" unless explicitly indicated to the contrary in the claims or description. The use of "comprise", "comprises" or "comprising" in the claims or description will not exclude the presence of elements or steps other than those listed in the claims or description. The word "comprising" and "comprises", and the like, does not necessarily exclude the presence of

[0066] It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. It is to be understood that the term "and / or" as used herein encompasses all possible combinations of particular items listed apart from a disjunctive phrase, such as "and / or," e.g., the phrase "at least one of A and / or B" is understood to encompass all possible combinations of A alone, B alone, A and B together, and the like.

[0067] The above-mentioned exemplary embodiment numbers of the present application are only for description and do not represent advantages or disadvantages of the embodiments.

[0068] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by program instructing relevant hardware to complete, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0069] Those skilled in the art shall understand that the above discussion of any embodiment is only exemplary, and is not intended to imply that the scope (including claims) of the embodiments of the present application is limited to these examples; the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes of different aspects of the embodiments of the present application as above. In order to be brief, they are not provided in details. Therefore, any omission, modification, equivalent replacement, improvement, etc. made in the spirit and principle of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A method of implementing a particle filter algorithm, characterized by, The method comprises the following steps: The particle filter algorithm is disassembled to obtain a plurality of mathematical calculation steps, a plurality of hardware calculation units and a plurality of extensible instructions are designed based on the mathematical calculation steps; The plurality of hardware calculation units are embedded into the execution layer in a pipeline manner, and the plurality of extensible instructions are sequentially mapped into the instruction buffer memory; An address value in an instruction counter is obtained, and a corresponding extensible instruction is obtained from the instruction buffer memory based on the address value, which comprises that the address value in the instruction counter is obtained by a fetch unit in real time, and the corresponding extensible instruction is obtained from the instruction buffer memory based on the address value; An activation signal is sent to a corresponding hardware calculation unit in the execution layer based on the corresponding extensible instruction, so as to execute the calculation operation of the corresponding hardware calculation unit, and the obtained calculation result is stored in a corresponding register; and The calculation results in all registers are processed based on a load storage unit to obtain the optimal solution of the particle filter algorithm; The plurality of mathematical calculation steps at least comprise particle initialization, weight update, resampling and state value calculation; The plurality of hardware calculation units at least comprise a particle initialization module, a weight update module, a resampling module and a state value calculation module; The plurality of extensible instructions at least comprise a particle initialization instruction, a weight update instruction, a resampling instruction and a state value calculation instruction.

2. The method of claim 1, wherein, Further comprising: High-level language codes input by an application layer are obtained, and the high-level language codes are input into a compiler to obtain assembly instructions; The assembly instructions are stored in a memory, and are mapped from the memory to the instruction buffer memory.

3. The method of claim 1, wherein, The activation signal is sent to the corresponding hardware calculation unit in the execution layer based on the corresponding extensible instruction, which comprises: The corresponding activation signal is generated by a decoder based on the corresponding extensible instruction, and the activation signal is sent to the corresponding hardware calculation unit in the execution layer.

4. The method of claim 1, wherein, Further comprising: The registers interact with the memory for data through the load storage unit.

5. An apparatus for implementing a particle filter algorithm, characterized in that Comprise: A first module configured to disassemble the particle filter algorithm to obtain a plurality of mathematical calculation steps, and design a plurality of hardware calculation units and a plurality of extensible instructions based on the mathematical calculation steps; A second module configured to embed the plurality of hardware calculation units into the execution layer in a pipeline manner, and sequentially map the plurality of extensible instructions into the instruction buffer memory; A third module configured to obtain an address value in an instruction counter, and obtain a corresponding extensible instruction from the instruction buffer memory based on the address value; A fourth module configured to send an activation signal to a corresponding hardware calculation unit in the execution layer based on the corresponding extensible instruction, so as to execute the calculation operation of the corresponding hardware calculation unit, and store the obtained calculation result in a corresponding register; And A fifth module configured to process the calculation results in all registers based on a load storage unit to obtain the optimal solution of the particle filter algorithm; The third module is further used for obtaining the address value in the instruction counter by the fetch unit in real time, and obtaining the corresponding extensible instruction from the instruction buffer memory based on the address value. The multiple mathematical calculation steps include at least: particle initialization, weight update, resampling, and state value calculation; The plurality of hardware computing units include at least: a particle initialization module, a weight update module, a resampling module, and a state value calculation module; The plurality of extensible instructions include at least: particle initialization instructions, weight update instructions, resampling instructions, and state value calculation instructions.

6. The apparatus of claim 5, wherein, It also includes a sixth module, configured for: Obtain the high-level language code input from the application layer, and input the high-level language code into the compiler to obtain assembly instructions; The assembly instructions are stored in memory and then mapped from memory to the instruction buffer.

7. A computer device, characterized by include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method according to any one of claims 1-4.

8. A computer-readable storage medium storing a computer program, the computer-readable storage medium comprising: When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-4.

Images