A chip simulation verification method, system, device and readable storage medium

Abstract

The present invention discloses a chip simulation verification method, system, device, and computer-readable storage medium. The method pre-plans simulation processes adapted to different EDA tools for a chip and compiles simulation files required for each simulation process. After receiving simulation requirement information containing EDA tool selection parameters for the chip, the method determines the target simulation process for the chip based on the simulation requirement information. The method calls the corresponding simulation file according to the target simulation process to simulate the chip, and verifies whether the chip's performance meets the design requirements based on the simulation results of the chip. This method can simultaneously support chip simulation processes using different EDA tools, eliminating the need to re-change the chip simulation process each time an EDA tool is changed, saving time and effort.

Description

Technical Field

[0001] This invention relates to the field of chip simulation and verification, and in particular to a chip simulation and verification method, system, apparatus, and computer-readable storage medium. Background Technology

[0002] Currently, after a chip is designed, it needs to be simulated to verify whether its performance meets the design requirements. Chip simulation requires EDA (Electronic Design Automation) tools for verification. However, EDA tools are expensive, and users typically only purchase the EDA tool suitable for simulating their current chip and design a suitable simulation flow based on that tool. However, if the purchased EDA tool expires and is replaced with another, a new simulation flow must be designed based on the new tool, which is time-consuming and labor-intensive.

[0003] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that those skilled in the art need to solve at present. Summary of the Invention

[0004] The purpose of this invention is to provide a chip simulation verification method, system, device, and computer-readable storage medium that can simultaneously support chip simulation processes when using different EDA tools, eliminating the need to modify the chip simulation process every time an EDA tool is changed, thus saving time and effort.

[0005] To address the aforementioned technical problems, this invention provides a chip simulation and verification method, comprising:

[0006] Pre-plan the simulation flow for the chip to adapt to different EDA tools, and write the required simulation files for each of the different simulation flows;

[0007] After receiving simulation requirement information containing EDA tool selection parameters for the chip, the target simulation process for the chip is determined based on the simulation requirement information.

[0008] The corresponding simulation file is called according to the target simulation process to simulate the chip, and the performance of the chip is verified based on the simulation results to determine whether the chip meets the design requirements.

[0009] Optionally, after planning a simulation flow adapted to different EDA tools for the chip, the chip simulation verification method further includes:

[0010] Each path in the different simulation processes is numbered; wherein the simulation path parameters composed of the path numbers in the different simulation processes are different from each other.

[0011] Upon receiving simulation requirement information containing EDA tool selection parameters for the chip, the target simulation process for the chip is determined based on the simulation requirement information, including:

[0012] After receiving simulation requirement information containing EDA tool selection parameters for the chip, the target simulation path parameters applicable to the chip simulation are determined based on the simulation requirement information, and the target simulation process for the chip is determined based on the target simulation path parameters.

[0013] Optionally, a simulation flow adapted to different EDA tools can be pre-planned for the chip, including:

[0014] A first simulation stage is planned for the chip, comprising a pre-simulation module and a post-simulation module; wherein, the pre-simulation module is used to determine the simulation mode of the chip as the pre-simulation mode; and the post-simulation module is used to determine the simulation mode of the chip as the post-simulation mode.

[0015] A second simulation stage is planned for the chip, which includes different EDA tool modules; wherein, the EDA tool module corresponding to the target EDA tool is used to determine the EDA tool used for chip simulation as the target EDA tool, and to use the target EDA tool to simulate the chip;

[0016] A third simulation stage is planned for the chip, which includes different EDA file modules; wherein, the EDA file module corresponding to the target EDA file is used to call the target EDA file when using the target EDA tool, so as to provide the chip with the simulation environment it needs;

[0017] A fourth simulation stage is planned for the chip, which includes different waveform viewing tool modules; wherein, the waveform viewing tool module corresponding to the target waveform viewing tool is used to determine the tool for viewing the simulation waveform obtained after the chip simulation as the target waveform viewing tool, and to use the target waveform viewing tool to view the simulation waveform;

[0018] A fifth simulation stage is planned for the chip, including a waveform dump module and a waveform no-dump module; wherein, the waveform dump module is used to store the simulation waveform; and the waveform no-dump module is used not to store the simulation waveform.

[0019] Connect the modules in the Nth simulation stage to each other in the (N+1)th simulation stage to obtain a simulation flow adapted to different EDA tools based on the module connection path between each simulation stage; where 1≤N<5 and N is an integer.

[0020] Optionally, a second simulation stage is planned for the chip, including different EDA tool modules, comprising:

[0021] A second simulation stage is planned for the chip, which includes the ncsim simulation tool module and the vcs simulation tool module.

[0022] Optionally, a third simulation stage is planned for the chip, comprising different EDA file modules, including:

[0023] A third simulation stage is planned for the chip, including the ncsim.f file module and the vcs.f file module.

[0024] Optionally, a fourth simulation stage is planned for the chip, including different waveform viewing tool modules, comprising:

[0025] The fourth simulation stage for the chip includes the ncsim waveform viewing tool module, the verdi waveform viewing tool module, and the dve waveform viewing tool module.

[0026] Optionally, the chip simulation verification method further includes:

[0027] After the chip verification project changes to a new EDA tool, it is determined whether the original simulation process of the chip, which is designed to be compatible with different EDA tools, is compatible with the new EDA tool.

[0028] If not, then plan a new simulation process for the chip to adapt to the new EDA tool, and add the new simulation process to the original simulation process.

[0029] To address the aforementioned technical problems, the present invention also provides a chip simulation and verification system, comprising:

[0030] The process planning module is used to pre-plan simulation processes for chips that are adapted to different EDA tools, and to write the required simulation files for each of the different simulation processes.

[0031] The process determination module is used to determine the target simulation process of the chip based on the simulation requirement information after receiving simulation requirement information containing EDA tool selection parameters of the chip.

[0032] The simulation verification module is used to call the corresponding simulation file according to the target simulation process to simulate the chip, and to verify whether the performance of the chip meets the design requirements based on the simulation results.

[0033] To address the aforementioned technical problems, the present invention also provides a chip simulation and verification device, comprising:

[0034] Memory, used to store computer programs;

[0035] A processor is used to implement the steps of any of the above-described chip simulation and verification methods when executing the computer program.

[0036] To address the aforementioned technical problems, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above-described chip simulation and verification methods.

[0037] This invention provides a chip simulation verification method. It pre-plans simulation flows adapted to different EDA tools for the chip and writes the necessary simulation files for each flow. Upon receiving simulation requirement information containing the chip's EDA tool selection parameters, it determines the target simulation flow for the chip based on this information. The method then calls the corresponding simulation files according to the target simulation flow to simulate the chip and verifies whether the chip's performance meets design requirements based on the simulation results. Therefore, this application can simultaneously support chip simulation flows using different EDA tools, eliminating the need to modify the chip simulation flow every time an EDA tool is changed, saving time and effort.

[0038] The present invention also provides a chip simulation verification system, apparatus and computer-readable storage medium, which have the same beneficial effects as the chip simulation verification method described above. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A flowchart of a chip simulation verification method provided in an embodiment of the present invention;

[0041] Figure 2 A system diagram of a chip simulation process provided in an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of a chip simulation and verification system provided in an embodiment of the present invention. Detailed Implementation

[0043] The core of this invention is to provide a chip simulation verification method, system, device, and computer-readable storage medium that can simultaneously support chip simulation processes using different EDA tools, eliminating the need to modify the chip simulation process every time an EDA tool is changed, thus saving time and effort.

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] Please refer to Figure 1 , Figure 1 This is a flowchart of a chip simulation verification method provided in an embodiment of the present invention.

[0046] The chip simulation verification method includes:

[0047] Step S1: Plan simulation processes for the chip in advance to adapt to different EDA tools, and write the required simulation files for each simulation process.

[0048] Specifically, this application plans simulation processes for the chip in advance to adapt to different EDA tools. That is, it equips each of the multiple EDA tools with a simulation process adapted to this EDA tool, and writes the required simulation files for the different planned simulation processes. That is, it writes a set of simulation files adapted to this simulation process for each of the multiple simulation processes for subsequent simulation use.

[0049] Step S2: After receiving the simulation requirement information containing the EDA tool selection parameters for the chip, determine the target simulation process for the chip based on the simulation requirement information.

[0050] Specifically, during chip pre-simulation verification, users can select the EDA tool for chip simulation based on actual conditions, and generate simulation requirement information including the EDA tool selection parameters for the chip based on the selected EDA tool. After receiving the simulation requirement information including the EDA tool selection parameters for the chip, this application can determine the target simulation flow for the chip based on the simulation requirement information (the target simulation flow is the simulation flow adapted to the simulation requirement information).

[0051] Step S3: Call the corresponding simulation file according to the target simulation process to simulate the chip, and verify whether the chip's performance meets the design requirements based on the simulation results.

[0052] Specifically, after determining the target simulation process of the chip based on the simulation requirements information, this application calls the corresponding simulation file (the called simulation file is a simulation file adapted to the target simulation process) according to the determined target simulation process to simulate the chip, obtain the simulation results of the chip, and then verify whether the performance of the chip meets the design requirements based on the simulation results of the chip.

[0053] As can be seen, this application can simultaneously support chip simulation processes when using different EDA tools, eliminating the need to change the chip simulation process every time the EDA tool is changed, thus saving time and effort.

[0054] Based on the above embodiments:

[0055] As an optional embodiment, after planning a simulation flow adapted to different EDA tools for the chip, the chip simulation verification method further includes:

[0056] Each path in different simulation processes is numbered; the simulation path parameters formed by the path numbers in different simulation processes are different.

[0057] Upon receiving simulation requirement information containing the EDA tool selection parameters for the chip, the target simulation process for the chip is determined based on this information, including:

[0058] After receiving simulation requirement information including EDA tool selection parameters for the chip, the target simulation path parameters applicable to the chip simulation are determined based on the simulation requirement information, and the target simulation process for the chip is determined based on the target simulation path parameters.

[0059] Furthermore, after planning simulation flows for chips to adapt to different EDA tools, this application can also number each path of different simulation flows. It should be noted that the simulation path parameters composed of each path number of different simulation flows are different, so as to distinguish the paths of different simulation flows.

[0060] Based on this, the process of determining the target simulation flow of the chip in this application includes: after receiving simulation requirement information containing the EDA tool selection parameters of the chip, the target simulation path parameters applicable to the chip simulation can be determined according to the simulation requirement information (the target simulation path parameters are the simulation path parameters composed of the path numbers of a simulation flow that adapts to this simulation requirement information), thereby determining the target simulation flow of the chip according to the target simulation path parameters.

[0061] As an optional implementation, a simulation flow adapted to different EDA tools is pre-planned for the chip, including:

[0062] The first simulation stage for chip planning includes a pre-simulation module and a post-simulation module; the pre-simulation module is used to determine the chip's simulation method as the pre-simulation method; the post-simulation module is used to determine the chip's simulation method as the post-simulation method.

[0063] The second simulation stage for chip planning includes different EDA tool modules; wherein, the EDA tool module corresponding to the target EDA tool is used to determine the EDA tool used for chip simulation as the target EDA tool, and to use the target EDA tool to simulate the chip;

[0064] The third simulation stage for chip design includes different EDA file modules; among them, the EDA file module corresponding to the target EDA file is used to call the target EDA file when using the target EDA tool, so as to provide the simulation environment required by the chip.

[0065] The fourth simulation stage for chip planning includes different waveform viewing tool modules; wherein, the waveform viewing tool module corresponding to the target waveform viewing tool is used to determine the tool for viewing the simulation waveform obtained after chip simulation as the target waveform viewing tool, and to use the target waveform viewing tool to view the simulation waveform;

[0066] The chip design includes a fifth simulation stage comprising a waveform dump module and a waveform no-dump module; the waveform dump module is used to store the simulation waveforms; the waveform no-dump module is used to prevent the storage of simulation waveforms.

[0067] Connect the modules in the Nth simulation stage to each other in the (N+1)th simulation stage to obtain a simulation flow adapted to different EDA tools based on the module connection path between each simulation stage; where 1≤N<5 and N is an integer.

[0068] Specifically, the simulation process for chip planning adapted to different EDA tools in this application includes: 1) A first simulation stage for chip planning, comprising a pre-simulation module (functional simulation, no delay, relatively fast) and a post-simulation module (timing simulation, delay, closer to the actual working condition of the chip). The pre-simulation module determines the chip's simulation method as pre-simulation; the post-simulation module determines the chip's simulation method as post-simulation. It should be noted that pre-simulation is generally performed first, followed by post-simulation. 2) A second simulation stage for chip planning, comprising different EDA tool modules. Any target EDA tool module (corresponding to the target EDA tool) is used to determine the EDA tool used for chip simulation as the target EDA tool, and the target EDA tool is used to simulate the chip. 3) A third simulation stage for chip planning, comprising different EDA file modules. The simulation process includes: 1) A target EDA file module (corresponding to the target EDA file, which is compatible with the target EDA tool) is used to call the target EDA file when using the target EDA tool, providing the necessary simulation environment for the chip. 2) A fourth simulation stage is planned for the chip, including different waveform viewing tool modules. A target waveform viewing tool module (corresponding to the target waveform viewing tool) is used to identify the tool used to view the simulation waveform obtained after chip simulation as the target waveform viewing tool, and then use the target waveform viewing tool to view the simulation waveform obtained after chip simulation. 3) A fifth simulation stage is planned for the chip, including a dump (storage) waveform module and a no-dump (do not store) waveform module. The dump waveform module is used to store the simulation waveform obtained after chip simulation to assist in debugging; the no-dump waveform module does not store the simulation waveform obtained after chip simulation and is faster. 6) Connect modules in adjacent simulation stages in pairs. Specifically, connect modules in the first simulation stage to modules in the second simulation stage, connect modules in the second simulation stage to modules in the third simulation stage, connect modules in the third simulation stage to modules in the fourth simulation stage, and connect modules in the fourth simulation stage to modules in the fifth simulation stage. It should be noted that the connection path between the target EDA tool module in the second simulation stage and the target EDA file module in the third simulation stage is valid, while the connection path between the target EDA tool module in the second simulation stage and other EDA file modules in the third simulation stage is invalid. Invalid connection paths are not needed when obtaining simulation flows adapted to different EDA tools, so they can be removed. 7) Obtain simulation flows adapted to different EDA tools based on the module connection paths between each simulation stage.

[0069] As an optional embodiment, the second simulation stage for chip planning includes different EDA tool modules, including:

[0070] The second simulation stage for chip design includes the ncsim simulation tool module and the vcs simulation tool module.

[0071] Specifically, the different EDA tool modules in the second simulation stage of chip planning in this application include the ncsim simulation tool (an EDA software for simulation verification) module and the vcs simulation tool (an EDA software for simulation verification) module, and may also include other simulation tool modules. This application does not make any special limitations here.

[0072] As an optional embodiment, a third simulation stage for chip planning, comprising different EDA file modules, includes:

[0073] The third simulation stage for chip planning includes the ncsim.f file module and the vcs.f file module.

[0074] Specifically, the different EDA file modules in the third simulation stage of chip planning in this application include the ncsim.f file module (adapted to the ncsim simulation tool module) and the vcs.f file module (adapted to the vcs simulation tool module), and may also include other file modules. This application does not make any special limitations here.

[0075] As an optional embodiment, the fourth simulation stage for chip planning includes different waveform viewing tool modules, including:

[0076] The fourth simulation stage for chip planning includes the ncsim waveform viewing tool module, the verdi waveform viewing tool module, and the dve waveform viewing tool module.

[0077] Specifically, the different waveform viewing tool modules in the fourth simulation stage of chip planning in this application include the ncsim waveform viewing tool (a waveform analysis software) module, the verdi waveform viewing tool (a waveform analysis software) module, and the dve waveform viewing tool (a waveform analysis software) module. Other waveform viewing tool modules may also be included, and this application does not make any special limitations here.

[0078] In summary, we can obtain the following: Figure 2 The system diagram of the chip simulation process shown (all system information is stored in the case information module) will then... Figure 2 The entire chip simulation system path is numbered as shown in Table 1 below:

[0079] Table 1

[0080]

[0081] For example, if the current simulation requirements for this chip simulation project are: pre-simulation, using VCS as the EDA tool, and Verdi as the waveform viewing tool with waveform dumping, then the target simulation path parameter applicable to the current simulation requirements is 01110. Based on the target simulation path parameter "01110", the target simulation process for the chip is determined as follows: 1) Execute the pre-simulation module to determine the chip simulation method as pre-simulation; 2) Execute the VCS simulation tool module to determine the EDA tool used for chip simulation as VCS, and use VCS to simulate the chip; simultaneously, execute the vcs.f file module to call the vcs.f file when using the VCS simulation tool, providing the chip with the necessary simulation environment; 4) Execute the Verdi waveform viewing tool module to determine the tool for viewing the simulation waveforms obtained after chip simulation as Verdi, and use Verdi to view the simulation waveforms obtained after chip simulation; 5) Execute the waveform dump module to store the simulation waveforms obtained after chip simulation, finally obtaining the simulation result.

[0082] As an optional embodiment, the chip simulation verification method further includes:

[0083] After a chip verification project switches to a new EDA tool, it is determined whether the original simulation process for the chip, which was designed to be compatible with different EDA tools, is compatible with the new EDA tool.

[0084] If not, then a new simulation process will be designed to adapt the chip to the new EDA tool, and the new simulation process will be added to the original simulation process.

[0085] Furthermore, after the chip verification project replaces with a new EDA tool, this application determines whether the original simulation flow planned for the chip to adapt to different EDA tools is compatible with the new EDA tool. If it is compatible with the new EDA tool, the original simulation flow is not processed. If it is not compatible with the new EDA tool, a new simulation flow adapted to the new EDA tool is planned for the chip, and the new simulation flow is added to the original simulation flow to ensure that there is a simulation flow adapted to the new EDA tool in each simulation flow planned for the chip.

[0086] Please refer to Figure 3 , Figure 3 This is a schematic diagram of a chip simulation and verification system provided in an embodiment of the present invention.

[0087] The chip simulation and verification system includes:

[0088] Process planning module 1 is used to pre-plan simulation processes for chips that are adapted to different EDA tools, and to write the simulation files required for each simulation process.

[0089] The process determination module 2 is used to determine the target simulation process of the chip based on the simulation requirement information after receiving the simulation requirement information containing the EDA tool selection parameters of the chip.

[0090] The simulation verification module 3 is used to call the corresponding simulation file according to the target simulation process to simulate the chip, and to verify whether the chip's performance meets the design requirements based on the simulation results.

[0091] For a description of the chip simulation verification system provided in this application, please refer to the embodiments of the chip simulation verification method described above; further details will not be repeated here.

[0092] This application also provides a chip simulation and verification device, including:

[0093] Memory, used to store computer programs;

[0094] A processor is used to implement the steps of any of the above-described chip simulation and verification methods when executing a computer program.

[0095] For a description of the chip simulation verification device provided in this application, please refer to the embodiments of the chip simulation verification method described above; further details will not be repeated here.

[0096] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above-described chip simulation and verification methods.

[0097] For a description of the computer-readable storage medium provided in this application, please refer to the embodiments of the chip simulation verification method described above; further details will not be repeated here.

[0098] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0099] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip simulation and verification method, characterized in that, include: Pre-plan the simulation flow for the chip to adapt to different EDA tools, and write the required simulation files for each of the different simulation flows; After receiving simulation requirement information containing EDA tool selection parameters for the chip, the target simulation process for the chip is determined based on the simulation requirement information. The corresponding simulation file is called according to the target simulation process to simulate the chip, and the performance of the chip is verified based on the simulation results to see if it meets the design requirements. This includes pre-planning simulation workflows for the chip to adapt to different EDA tools, including: A first simulation stage is planned for the chip, comprising a pre-simulation module and a post-simulation module; wherein, the pre-simulation module is used to determine the simulation mode of the chip as the pre-simulation mode; and the post-simulation module is used to determine the simulation mode of the chip as the post-simulation mode. A second simulation stage is planned for the chip, which includes different EDA tool modules; wherein, the EDA tool module corresponding to the target EDA tool is used to determine the EDA tool used for chip simulation as the target EDA tool, and to use the target EDA tool to simulate the chip; A third simulation stage is planned for the chip, which includes different EDA file modules; wherein, the EDA file module corresponding to the target EDA file is used to call the target EDA file when using the target EDA tool, so as to provide the chip with the simulation environment it needs; A fourth simulation stage is planned for the chip, which includes different waveform viewing tool modules; wherein, the waveform viewing tool module corresponding to the target waveform viewing tool is used to determine the tool for viewing the simulation waveform obtained after the chip simulation as the target waveform viewing tool, and to use the target waveform viewing tool to view the simulation waveform; A fifth simulation stage is planned for the chip, including a waveform dump module and a waveform no-dump module; wherein, the waveform dump module is used to store the simulation waveform; and the waveform no-dump module is used not to store the simulation waveform. Connect the modules in the Nth simulation stage to each other in the (N+1)th simulation stage to obtain a simulation flow adapted to different EDA tools based on the module connection path between each simulation stage; where 1≤N<5 and N is an integer.

2. The chip simulation verification method as described in claim 1, characterized in that, After planning the simulation flow to adapt to different EDA tools for the chip, the chip simulation verification method further includes: Each path in the different simulation processes is numbered; wherein the simulation path parameters composed of the path numbers in the different simulation processes are different from each other. Upon receiving simulation requirement information containing EDA tool selection parameters for the chip, the target simulation process for the chip is determined based on the simulation requirement information, including: After receiving simulation requirement information containing EDA tool selection parameters for the chip, the target simulation path parameters applicable to the chip simulation are determined based on the simulation requirement information, and the target simulation process for the chip is determined based on the target simulation path parameters.

3. The chip simulation verification method as described in claim 1, characterized in that, The second simulation stage for the chip includes different EDA tool modules, including: A second simulation stage is planned for the chip, which includes the ncsim simulation tool module and the vcs simulation tool module.

4. The chip simulation verification method as described in claim 3, characterized in that, The third simulation stage for the chip includes different EDA file modules, including: A third simulation stage is planned for the chip, including the ncsim.f file module and the vcs.f file module.

5. The chip simulation verification method as described in claim 1, characterized in that, The fourth simulation stage for the chip includes different waveform viewing tool modules, including: The fourth simulation stage for the chip includes the ncsim waveform viewing tool module, the verdi waveform viewing tool module, and the dve waveform viewing tool module.

6. The chip simulation verification method according to any one of claims 1-5, characterized in that, The chip simulation verification method further includes: After the chip verification project changes to a new EDA tool, it is determined whether the original simulation process of the chip, which is designed to be compatible with different EDA tools, is compatible with the new EDA tool. If not, then plan a new simulation process for the chip to adapt to the new EDA tool, and add the new simulation process to the original simulation process.

7. A chip simulation and verification system, characterized in that, include: The process planning module is used to pre-plan simulation processes for chips that are adapted to different EDA tools, and to write the required simulation files for each of the different simulation processes. The process determination module is used to determine the target simulation process of the chip based on the simulation requirement information after receiving simulation requirement information containing EDA tool selection parameters of the chip. The simulation verification module is used to call the corresponding simulation file according to the target simulation process to simulate the chip, and to verify whether the performance of the chip meets the design requirements based on the simulation results of the chip. This includes pre-planning simulation workflows for the chip to adapt to different EDA tools, including: A first simulation stage is planned for the chip, comprising a pre-simulation module and a post-simulation module; wherein, the pre-simulation module is used to determine the simulation mode of the chip as the pre-simulation mode; and the post-simulation module is used to determine the simulation mode of the chip as the post-simulation mode. A second simulation stage is planned for the chip, which includes different EDA tool modules; wherein, the EDA tool module corresponding to the target EDA tool is used to determine the EDA tool used for chip simulation as the target EDA tool, and to use the target EDA tool to simulate the chip; A third simulation stage is planned for the chip, which includes different EDA file modules; wherein, the EDA file module corresponding to the target EDA file is used to call the target EDA file when using the target EDA tool, so as to provide the chip with the simulation environment it needs; A fourth simulation stage is planned for the chip, which includes different waveform viewing tool modules; wherein, the waveform viewing tool module corresponding to the target waveform viewing tool is used to determine the tool for viewing the simulation waveform obtained after the chip simulation as the target waveform viewing tool, and to use the target waveform viewing tool to view the simulation waveform; A fifth simulation stage is planned for the chip, including a waveform dump module and a waveform no-dump module; wherein, the waveform dump module is used to store the simulation waveform; and the waveform no-dump module is used not to store the simulation waveform. Connect the modules in the Nth simulation stage to each other in the (N+1)th simulation stage to obtain a simulation flow adapted to different EDA tools based on the module connection path between each simulation stage; where 1≤N<5 and N is an integer.

8. A chip simulation and verification device, characterized in that, include: memory for storing computer programs; A processor for implementing the steps of the chip simulation verification method as described in any one of claims 1-6 when executing the computer program.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the chip simulation verification method as described in any one of claims 1-6.

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