Method of forming a semiconductor device

Abstract

The application provides a semiconductor device forming method, comprising the following steps: providing a semiconductor substrate; forming a layer to be etched on the semiconductor substrate; forming a patterned core layer on the layer to be etched; forming a protective layer on the side of the core layer or forming the protective layer on the side and top of the core layer; processing the layer to be etched; forming a pattern on the semiconductor substrate after removing the layer to be etched; wherein the protective layer of the core layer is removed together in the process of removing the layer to be etched. The above scheme can improve the performance of the formed semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuits, and in particular, to a forming method of a semiconductor device. BACKGROUND

[0002] Semiconductor technology continues to move towards smaller process nodes driven by Moore's law. With the continuous progress of semiconductor technology, the function of the device is becoming more powerful, but the difficulty of semiconductor manufacturing is also increasing. Photolithography technology is the most critical production technology in the semiconductor manufacturing process. With the continuous reduction of semiconductor process nodes, the existing light source photolithography technology has been unable to meet the needs of semiconductor manufacturing. Extreme ultraviolet lithography technology (EUV), multi-beam maskless technology and nano-imprint technology have become the research focus of the next generation of lithography candidate technologies. However, the above-mentioned next-generation lithography candidate technologies still have inconveniences and defects, and need to be further improved.

[0003] When the step of Moore's law continues to move forward is irreversible, multiple patterning technology is undoubtedly one of the best choices in the industry. Multiple patterning technology only needs to make small changes to the existing photolithography infrastructure, which can effectively fill the gap of smaller node photolithography technology and improve the minimum pitch between adjacent semiconductor patterns. Since the self-aligned double patterning (SADP) process is simpler and has lower cost, it is more commonly used in the forming process of semiconductor devices.

[0004] However, even if the self-aligned double patterning process is introduced, the quality of the target pattern formed after etching is still poor, which affects the performance of the formed semiconductor structure. SUMMARY

[0005] The problem solved by the present application is to provide a forming method of a semiconductor device to improve the performance of the formed semiconductor structure.

[0006] To solve the above problems, the present application provides a forming method of a semiconductor device, comprising:

[0007] providing a to-be-etched layer;

[0008] forming a patterned core layer on the to-be-etched layer;

[0009] performing inclined ion implantation on the side portions of the core layer on both sides in the first direction;

[0010] After performing the inclined ion implantation, etching the to-be-etched layer with the core layer as a mask.

[0011] Optionally, the layer to be etched includes an etching stop material layer and a hard mask material layer on the etching stop material layer.

[0012] The method of etching the layer to be etched with the core layer as a mask includes:

[0013] Etching the hard mask material layer with the core layer as a mask until the top surface of the etching stop material layer is exposed to form a patterned hard mask layer.

[0014] After forming the patterned hard mask layer, performing a material modification treatment on the etching stop material layer with the core layer and the hard mask layer as masks.

[0015] After performing the material modification treatment, etching and removing the material-modified region in the etching stop material layer with the core layer and the hard mask layer as masks to form a patterned etching stop layer.

[0016] Optionally, during the material modification treatment on the etching stop material layer with the core layer and the hard mask layer as masks, the material modification treatment process is also performed on the core layer.

[0017] During the etching and removing of the material-modified region in the etching stop material layer, the core layer is also etched and removed.

[0018] Optionally, the layer to be etched also includes a substrate or gate material layer; the etching stop layer is on the substrate or gate material layer.

[0019] After forming the patterned etching stop layer, the method further includes:

[0020] Etching the substrate or gate material layer with the patterned hard mask layer and etching stop layer as masks to form discrete fin or gate structures.

[0021] Optionally, the material modification treatment process is a plasma treatment process.

[0022] Optionally, the process parameters of the plasma treatment process include: the treatment gas is at least one of H2 and He, the gas flow is 100-500 sccm, the chamber pressure is 5-200 mTorr, the power supply power is 100-1000 W, the bias voltage is 10-300 V, and the treatment time is 30-600 s.

[0023] Optionally, the process of etching the hard mask material layer is an atomic layer etching process.

[0024] Optionally, the process of etching and removing the material-modified region in the etching stop material layer is a wet etching process.

[0025] Optionally, the process parameters of the wet etching process include: the etching solution is a hydrofluoric acid solution, the volume percentage of the hydrofluoric acid solution is 0.05%-2%, and the etching time is 30s-600s.

[0026] Optionally, the process parameters of the tilted ion implantation process include: the implanted ion is a phosphorus ion, and the ion implantation angle is 7°.

[0027] This invention also provides a method for forming a semiconductor device, the method comprising:

[0028] Provide the layer to be etched;

[0029] A patterned mask layer is formed on the layer to be etched;

[0030] Form a conformal sidewall layer covering the layer to be etched and the mask layer;

[0031] The layer to be etched is etched using the sidewall layer and the mask layer as a mask.

[0032] Optionally, the sidewall layer is a silicon dioxide layer.

[0033] Optionally, the step of forming the silicon dioxide layer includes:

[0034] A conformally conformally coated silicon film is formed covering the layer to be etched and the mask layer;

[0035] The silicon film is subjected to an oxidation process to form the silicon dioxide layer.

[0036] Optionally, the patterned mask layer includes a hard mask layer and a core layer located on the hard mask layer;

[0037] Methods for forming patterned mask layers include:

[0038] A hard mask material layer is formed on the layer to be etched;

[0039] A patterned core layer is formed on the hard mask material layer;

[0040] The mask material layer is etched using the core layer as a mask to form a patterned hard mask layer.

[0041] Optionally, the process of etching the mask material layer using the core layer as a mask is an asynchronous pulse etching process.

[0042] Optionally, the process parameters of the asynchronous pulse etching process include: the etching gas includes at least one of C4F6, O2 and Ar; the flow rate of C4F6 is 5-200 sccm; the flow rate of O2 is 1-200 sccm; the flow rate of Ar is 50-500 sccm; the provided source power is 50-1000 W; the provided bias power is 0-500 W; the duty cycle of the source power is 10%-90%; the duty cycle of the bias power is 10%-90%; the etching chamber pressure is 2-100 mTorr; and the etching time is 5-600 s.

[0043] Optionally, the side wall layer and the mask layer are etched and removed together after the etching of the to-be-etched layer.

[0044] Optionally, the to-be-etched layer includes an etching stop material layer.

[0045] The etching stop material layer is etched to form a patterned etching stop layer.

[0046] Optionally, the to-be-etched layer further includes a substrate or gate material layer; and the etching stop layer is located on the substrate or gate material layer.

[0047] After the etching of the etching stop material layer with the side wall layer as a mask, the method further includes:

[0048] The substrate or gate material layer is etched with the patterned hard mask layer and the etching stop layer as masks to form discrete fin structures or gate structures.

[0049] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0050] The method for forming a semiconductor device provided in the embodiment of the present application includes: providing a semiconductor substrate; forming a to-be-etched layer on the semiconductor substrate; forming a patterned core layer on the to-be-etched layer; forming a protective layer on the side surface of the core layer or forming a protective layer on the side surface and top surface of the core layer; processing the to-be-etched layer; and forming a pattern on the semiconductor substrate after removing the to-be-etched layer, wherein the protective layer of the core layer is removed together during the removal of the to-be-etched layer. By forming a protective layer on the side surface of the core layer or forming a protective layer on the side surface and top surface of the core layer, the etching loss of the core layer in the subsequent etching process can be reduced, and thus the quality of the topography of the subsequently formed target pattern can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1 is a flowchart of a method for forming a semiconductor device in the embodiment of the present application;

[0052] Figures 2 to 8is a schematic diagram of an intermediate structure formed by each step of the method for forming a semiconductor device in an embodiment of the present application;

[0053] Figure 9 is a flowchart of another method for forming a semiconductor device in an embodiment of the present application;

[0054] Figures 10 to 13 is a schematic diagram of an intermediate structure formed by each step of the method for forming another semiconductor device in an embodiment of the present application. DETAILED DESCRIPTION

[0055] As known from the background art, even if a self-aligned double patterning process is introduced, the quality of the target pattern formed after etching is still poor, which affects the performance of the semiconductor structure formed.

[0056] The technical solution in the embodiment of the present application can reduce etching loss of the core layer in the subsequent etching process by forming a protective layer on the side surface of the core layer or forming a protective layer on the side surface and top surface of the core layer, thereby improving the morphology quality of the target pattern formed subsequently.

[0057] Figure 1 A flowchart of a method for forming a semiconductor device in an embodiment of the present application is shown. The method for forming a patterned semiconductor device includes:

[0058] Step S101: providing a semiconductor substrate;

[0059] Step S102: forming a layer to be etched on the semiconductor substrate;

[0060] Step S103: forming a patterned core layer on the layer to be etched;

[0061] Step S104: forming a protective layer on the side surface of the core layer or forming a protective layer on the side surface and top surface of the core layer;

[0062] Step S105: processing the layer to be etched;

[0063] Step S106: forming a pattern on the semiconductor substrate after removing the layer to be etched; wherein the protective layer of the core layer is removed together during the process of removing the layer to be etched.

[0064] To make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0065] The method for forming a semiconductor device shown in the drawings will be described in further detail below with reference to the drawings, taking the layer to be etched as the etching stop material layer and the hard mask material layer as an example. Figure 1 The method for forming a semiconductor device shown in the drawings will be described in further detail below with reference to the drawings, taking the layer to be etched as the etching stop material layer and the hard mask material layer as an example.

[0066] Referring to Figure 2 A semiconductor substrate 100 is provided, which has an etching stop material layer 110 and a hard mask material layer 120 on the etching stop material layer 110.

[0067] In this embodiment, the semiconductor substrate 100 is a silicon substrate, which is used to form a fin in subsequent etching.

[0068] The etching stop material layer 110 is used to stop the etching in subsequent etching of the hard mask material layer 120, so as to reduce the etching loss of the semiconductor substrate 100.

[0069] In this embodiment, the material of the etching stop material layer 110 is silicon nitride.

[0070] The hard mask material layer 120 is used to form an etching mask for etching the semiconductor substrate 100 in subsequent etching.

[0071] In this embodiment, the material of the hard mask material layer 120 is silicon oxide.

[0072] Referring to Figure 3 A patterned core layer 130 is formed on the hard mask material layer 120.

[0073] The core layer 120 provides a process basis for subsequent patterning of the hard mask material layer 120.

[0074] In this embodiment, the material of the core layer 130 is silicon nitride.

[0075] The step of forming the core layer includes: forming a core material layer on the hard mask material layer; forming a patterned mask layer on the core material layer; etching the core material layer with the patterned mask layer as a mask to form the core layer; and removing the patterned mask layer after forming the core layer.

[0076] In other embodiments, the step of forming the patterned mask layer on the core material layer can further include a step of forming a top anti-reflective coating (not shown) on the core material layer, so as to improve the topography quality of the mask layer.

[0077] In this embodiment, the core material layer is etched by using a dry etching process. Specifically, the core material layer is removed by using a plasma dry etching process.

[0078] After forming the core layer, the mask layer and the top anti-reflective coating are removed by using an ashing process or a wet adhesive removal process.

[0079] Referring to Figure 4A protective layer 135 is formed on the side of the core layer 130.

[0080] In this embodiment, the process of forming the protective layer 135 on the side of the core layer 130 is an ion implantation process.

[0081] By performing ion implantation on the two sides of the core layer 130 in the first direction (the fin width direction), the etching loss of the side of the core layer 130 during the etching of the hard mask material layer 120 can be reduced in the subsequent process of etching the hard mask material layer with the core layer 130 as a mask. The morphology of the core layer 130 can be maintained during the etching of the hard mask material layer 120, thereby improving the morphology quality of the formed hard mask layer, and further improving the morphology quality of the subsequently formed target pattern.

[0082] In this embodiment, the process parameters of the ion implantation process include: the implanted ions are phosphorus ions, and the ion implantation angle is 7°.

[0083] Referring to Figure 5 After the protective layer 135 is formed on the side of the core layer 130, the hard mask material layer 120 is etched with the core layer 130 and the protective layer 135 as masks until the top surface of the etching stop material layer 110 is exposed, forming a patterned hard mask layer 125.

[0084] In this embodiment, the process of etching the hard mask material layer 120 with the core layer 130 and the protective layer 135 as masks is an atomic layer etching process.

[0085] Referring to Figure 6 After the patterned hard mask layer 125 is formed, a material modification treatment process is performed on the etching stop material layer 110 with the core layer 130, the protective layer 135, and the hard mask layer 125 as masks.

[0086] By performing the material modification treatment process on the etching stop material layer 110, the etching selectivity of the region of the etching stop material layer 110 that has undergone material modification treatment is greater than that of the region that has not undergone material modification treatment, thereby facilitating the rapid removal of the region of the etching stop material layer 110 that has undergone material modification treatment, shortening the time required for etching to remove the region of the etching stop material layer 110 that has undergone material modification treatment, and thus reducing the etching loss of the hard mask material layer, and further improving the morphology quality of the subsequently formed fin.

[0087] In this embodiment, the material modification treatment process is a plasma treatment process. Specifically, the process parameters of the plasma treatment process include: the treatment gas is at least one of H2and He, the gas flow is 100-500sccm, the chamber pressure is 5-200mTorr, the power of the power supply is 100-1000W, the bias voltage is 10-300v, and the treatment time is 30s-600s.

[0088] In this embodiment, the material modification treatment process is performed on the core layer 130 as well as the etching stop material layer 110 in the process of taking the core layer 130 and the hard mask layer 125 as masks.

[0089] By performing the plasma treatment on the core layer 130 and the exposed etching stop material layer 110, H atoms and / or He atoms are implanted into the core layer 130 and the exposed etching stop material layer 110, which weakens the bond energy of the core layer 130 and the exposed etching stop material layer 110, so that the etching selectivity of the core layer 130 and the exposed etching stop material layer 110 in the subsequent etching process can be improved.

[0090] It should be noted that the process parameters of the plasma treatment process can be determined according to the thicknesses of the core layer 130, the protection layer 135 and the exposed etching stop material layer 110, so that the core layer 130 and the exposed etching stop material layer 110 can be completely affected by the plasma treatment process.

[0091] Referring to Figure 7 After the material modification treatment process is performed, the core layer 130, the protection layer 135 and the hard mask layer 125 are taken as masks to etch and remove the material modification treated region of the etching stop material layer 110, so as to form a patterned etching stop layer 115.

[0092] In the process of taking the core layer 130, the protection layer 135 and the hard mask layer 125 as masks to etch and remove the material modification treated region of the etching stop material layer 110, the etching removal rate of the material modification treated region of the etching stop material layer 110 is increased, and the time is shortened, so that the etching loss of the hard mask layer 125 and the etching stop material layer 110 located below the hard mask layer 125 can be reduced, and the morphology quality of the subsequently formed fin can be improved.

[0093] In the embodiment, the core layer 130, the protection layer 135 and the exposed etching stop material layer 110 are removed by using a wet etching process. Specifically, the etching solution used in the wet etching process is hydrofluoric acid (HF) solution, the volume percentage of the hydrofluoric acid solution is 0.05%-2%, and the etching time is 30s-600s.

[0094] In the embodiment, the core layer 130 and the protection layer 135 are removed together in the process of removing the region of the etching stop material layer 110 subjected to the material modification treatment by using the wet etching process.

[0095] Since the material bond energy of the core layer 130, the protection layer 135 and the exposed etching stop material layer 110 is reduced after the plasma treatment, the core layer 130 and the exposed etching stop material layer 110 can be stripped by using the hydrofluoric acid solution. Compared with the etching method using phosphoric acid, the etching method using the hydrofluoric acid solution can improve the etching stability and avoid the problem of too fast etching rate, so as to improve the morphology quality of the formed hard mask layer and the remaining etching stop material layer. In addition, the etching method using the hydrofluoric acid solution can also reduce the etching loss of the semiconductor substrate 100.

[0096] The parameters of the wet etching process are determined according to the thickness of the film layer subjected to the plasma treatment. In the embodiment, the parameters of the wet etching process are determined according to the thickness of the core layer 130, the protection layer 135 and the exposed etching stop material layer 110.

[0097] Referring to Figure 8 The semiconductor substrate 100 is etched by taking the hard mask layer 125 and the etching stop layer 115 as a mask to form discrete fin portions 105.

[0098] In the embodiment, the process of forming the discrete fin portions 105 is a dry etching process.

[0099] After the discrete fin portions 105 are formed, a step of removing the hard mask layer 125 and the etching stop layer 115 is further included.

[0100] The above describes the method for forming the semiconductor device in the embodiment of the present application by taking the etching of the substrate and the fin portion as an example. In other embodiments, the layer to be etched can also be a gate material layer, and the discrete gate structure is formed by etching.

[0101] The present application also provides another method for forming a semiconductor device.

[0102] Referring to Figure 9A semiconductor substrate 200 is provided, which has an etching stop material layer 210, a patterned hard mask layer 220 on the etching stop material layer 210, and a core layer 230.

[0103] In this embodiment, the semiconductor substrate 200 is a silicon substrate, which is used to form a fin in subsequent etching.

[0104] The etching stop material layer 210 is used to stop the etching of the semiconductor substrate 200 in subsequent etching of the hard mask material layer thereon, so as to reduce the etching loss of the semiconductor substrate 200.

[0105] In this embodiment, the material of the etching stop material layer 210 is silicon nitride.

[0106] The hard mask layer 220 is used as an etching mask in subsequent etching of the semiconductor substrate 200.

[0107] In this embodiment, the material of the hard mask layer 220 is silicon oxide.

[0108] The core layer 230 provides a process basis for forming the hard mask layer 230 from a patterned hard mask material layer.

[0109] In this embodiment, the material of the core layer 230 is silicon nitride.

[0110] The steps of forming the core layer 230 and the hard mask layer 220 include: forming a hard mask material layer on the etching stop material layer; forming a core material layer on the hard mask material layer; forming a patterned mask layer on the core material layer; etching the core material layer with the patterned mask layer as a mask to form the core layer; after forming the core layer, removing the patterned mask layer; and etching the hard mask material layer with the core layer as a mask to form the hard mask layer.

[0111] In other embodiments, before forming the patterned mask layer on the core material layer, a step of forming a top anti-reflective coating (not shown) on the core material layer can be further included to improve the topography quality of the mask layer.

[0112] In this embodiment, a dry etching process is used to etch and remove part of the core material layer on the layer to be etched. Specifically, a plasma dry etching process is used to etch and remove part of the core material layer on the layer to be etched.

[0113] After forming the core layer, a gray ash process or a wet adhesive removal process is used to remove the mask layer and the top anti-reflective coating.

[0114] In the embodiment, the patterned hard mask layer is formed by using an asynchronous pulse etching process. The process parameters of the asynchronous pulse etching process include: the etching gas includes at least one of C4F6, O2 and Ar; the flow rate of C4F6 is 5-200 sccm; the flow rate of O2 is 1-200 sccm; the flow rate of Ar is 50-500 sccm; the provided source power is 50-1000 W; the provided bias power is 0-500 W; the duty cycle of the source power is 10%-90%; the duty cycle of the bias power is 10%-90%; the etching chamber pressure is 2-100 mTorr; and the etching time is 5-600 s.

[0115] The patterned hard mask layer is formed by using the asynchronous pulse etching process, which can reduce the etching loss of the core layer and the hard mask layer during etching, is conducive to maintaining the topography of the core layer, improves the topography quality of the formed hard mask layer, and further improves the topography quality of the subsequently formed fin.

[0116] Referring to Figure 10 A protective material layer 240 is formed to conformally cover the etching stop material layer 210, the hard mask layer 220 and the core layer 230.

[0117] The protective material layer 240 is used to protect the hard mask layer 220 during subsequent etching of the etching stop material layer 210, so as to reduce the etching loss of the hard mask layer 220 and be conducive to maintaining the topography of the hard mask layer 220.

[0118] In the embodiment, the protective material layer 240 is a silicon dioxide layer.

[0119] The step of forming the silicon dioxide layer includes: forming a silicon film conformally covering the etching stop material layer 110, the hard mask layer 220 and the core layer 230; and performing oxidation treatment on the silicon film to form the silicon dioxide layer.

[0120] The formation method of the silicon dioxide layer makes the silicon dioxide layer and the steps of the aforementioned semiconductor device formation method be completed in the same reaction chamber, so as to reduce the cost.

[0121] The process of forming the silicon film can be a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In the embodiment, the atomic layer deposition (ALD) process is used to form the silicon film, so that the step coverage of the formed silicon film is better, and the coverage of the silicon film at the corner of the hard mask layer 220 and the core layer 230 is better.

[0122] Referring to Figure 11The protective layer 245 is formed by removing the protective layer on the etching stop material layer 210, leaving only the protective layer 240 on the sidewall of the core layer 230 and the sidewall and top of the hard mask layer 220.

[0123] In this embodiment, the process of removing the protective layer on the etching stop material layer 210 is a maskless etching process.

[0124] Referring to Figure 12 The etching stop material layer 210 is etched to form a patterned etching stop layer 215, using the protective layer 245, the core layer 230 and the hard mask layer 220 as masks.

[0125] Since the sidewall and top of the core layer 230 and the sidewall of the hard mask layer 220 are conformally covered with the protective layer 245, the hard mask layer 220 can be protected during the etching of the etching stop material layer 210, reducing the etching loss of the hard mask layer 220 and helping to maintain the topography of the hard mask layer 220.

[0126] In this embodiment, the etching stop layer 215 is formed by atomic layer etching.

[0127] In this embodiment, the protective layer 245 and the core layer 230 are etched together during the etching to form the patterned etching stop layer 215.

[0128] Referring to Figure 13 The semiconductor substrate 200 is etched to form a plurality of discrete fin structures 202, using the hard mask layer 220 and the etching stop layer 215 as masks.

[0129] In this embodiment, the process of forming the discrete fin structures 202 is a dry etching process.

[0130] The above describes the formation of a semiconductor device using an etching substrate to form a substrate and a fin structure. In other embodiments, the layer to be etched can also be a gate material layer, and the etching can form discrete gate structures.

[0131] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present application, and the scope of protection of the present application should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, comprising: providing a semiconductor substrate; forming a layer to be etched on the semiconductor substrate, the layer to be etched comprising a layer of etch stop material and a layer of hard mask material on the layer of etch stop material; forming a patterned core layer on the layer to be etched; forming a protective layer on a side of the core layer or on a side and a top of the core layer; processing the layer to be etched, comprising: etching the layer of hard mask material with the core layer as a mask until a top surface of the layer of etch stop material is exposed, forming a patterned layer of hard mask; after forming the patterned layer of hard mask, performing a material modification process on the layer of etch stop material with the core layer and the patterned layer of hard mask as a mask, the material modification process being a plasma process; after performing the material modification process, removing the material modification processed region of the layer of etch stop material with the core layer and the patterned layer of hard mask as a mask, forming a patterned layer of etch stop; during the material modification process on the layer of etch stop material with the core layer and the patterned layer of hard mask as a mask, the core layer is also subjected to the material modification process; during the removing of the material modification processed region of the layer of etch stop material with the core layer and the patterned layer of hard mask as a mask, the core layer is also etched; after removing the layer to be etched, forming a target pattern on the semiconductor substrate; wherein the protective layer of the core layer is also removed during the removing of the layer to be etched. 2.The method of claim 1, wherein the process of forming a protective layer on a side of the core layer is an ion implantation process. 3.The method of claim 2, wherein the ion implantation process has process parameters including: the implanted ions are phosphorus ions, and the ion implantation angle is 7°. 4.The method of claim 1, wherein after forming the patterned layer of etch stop, the method further comprises: etching the semiconductor substrate with the patterned layer of hard mask and the patterned layer of etch stop as a mask, forming a plurality of discrete fin structures. 5.The method of claim 1, wherein the layer to be etched further comprises a gate material layer, and the layer of etch stop material is on the gate material layer; after forming the patterned layer of etch stop, the method further comprises: etching the gate material layer with the patterned layer of hard mask and the patterned layer of etch stop as a mask, forming a plurality of discrete gate structures. 6.The method of claim 1, wherein the plasma process has process parameters including: the process gas is at least one of H 2 and He, the gas flow rate is 100-500sccm, the chamber pressure is 5-200mTorr, the power is 100-1000W, the bias voltage is 10-300V, and the processing time is 30s-600s. 7.The method of claim 1, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The process of etching the hard mask material layer is an atomic layer etching process.

8. The method of claim 1, wherein, The process of etching and removing the material-modified region of the etching stop material layer is a wet etching process.

9. The method of claim 8, wherein, The process parameters of the wet etching process include: the etching solution is a hydrofluoric acid solution, the volume percentage of the hydrofluoric acid solution is 0.05%-2%, and the etching time is 30s-600s.

10. The method of claim 1, wherein, The step of forming a protective layer on the side surface and top surface of the core layer includes: forming a protective material layer conformally covering the to-be-etched layer and the core layer; removing the protective material layer on the to-be-etched layer, and only retaining the protective material layer covering the top surface and side surface of the core layer as the protective layer.

11. The method of claim 10, wherein, The process of forming the protective material layer is an atomic layer deposition process.

12. The method of claim 10, wherein, The protective material layer is a silicon dioxide layer.

13. The method of claim 12, wherein, The step of forming the silicon dioxide layer includes: forming a silicon film conformally covering the to-be-etched layer and the core layer; performing an oxidation treatment on the silicon film to form the silicon dioxide layer.

14. The method of claim 8, wherein, The to-be-etched layer includes an etching stop material layer and a hard mask material layer located on the etching stop material layer; The step of treating the to-be-etched layer includes: etching the hard mask material layer with the core layer and the protective layer as masks until the top surface of the etching stop material layer is exposed to form a patterned hard mask layer; during the process of forming the patterned hard mask layer, the protective layer is etched and removed together; forming a patterned etching stop layer on the etching stop material layer with the core layer and the hard mask layer as masks.

15. The method of claim 14, wherein, The process of etching the hard mask material layer is an asynchronous pulse etching process.

16. The method of claim 15, wherein, The process parameters of the asynchronous pulse etching process include: the etching gas includes at least one of C4F6, O2, and Ar; the flow rate of C4F6 is 5-200sccm; the flow rate of O2 is 1-200sccm; the flow rate of Ar is 50-500sccm; the provided source power is 50-1000W; the provided bias power is 0-500W; the duty cycle of the source power is 10%-90%; the duty cycle of the bias power is 10%-90%; the etching chamber pressure is 2-100mTorr; and the etching time is 5-600s.

17. The method of claim 14, wherein, After forming the patterned etch stop layer, the method further comprises: Etching the semiconductor substrate using the patterned hard mask layer and etch stop layer as a mask to form a plurality of discrete fin portions.

18. The method of claim 14, wherein: The layer to be etched further comprises a gate material layer; and the etch stop material layer is on the gate material layer. After forming the patterned etch stop layer, the method further comprises: Etching the gate material layer using the patterned hard mask layer and etch stop layer as a mask to form a plurality of discrete gate structures.

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