Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the method comprising: providing a substrate, a first semiconductor layer and a second semiconductor layer being formed on a surface of the substrate and located at different regions of the substrate, the first semiconductor layer and the second semiconductor layer being different in material; patterning the first semiconductor layer and the second semiconductor layer to remain a first fin portion on the substrate as the first semiconductor layer and a second fin portion on the substrate as the second semiconductor layer, a wall thickness of the first fin portion being greater than a wall thickness of the second fin portion; forming a protection layer covering the second fin portion; after forming the protection layer covering the second fin portion, removing part of a sidewall of the first fin portion, so that a difference between the wall thickness of the first fin portion after the removal and the wall thickness of the second fin portion is less than or equal to a first preset value. The method improves the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of transistors is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes the subthreshold leakage phenomenon, also known as the short-channel effect (SCE), more likely to occur.

[0003] Therefore, in order to reduce the impact of short-channel effects, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field-Effect Transistors (FinFETs). In FinFETs, the gate structure can control the ultrathin body (fin) from at least two sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel, can effectively suppress short-channel effects, and has better compatibility with existing integrated circuit manufacturing.

[0004] However, devices manufactured using existing semiconductor processes do not perform well. Summary of the Invention

[0005] The problem addressed by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the electrical performance of the device.

[0006] To address the above problems, the present invention provides a method for forming a semiconductor structure, comprising:

[0007] A substrate is provided, on the surface of which a first semiconductor layer and a second semiconductor layer are formed in different regions of the substrate, the first semiconductor layer and the second semiconductor layer being made of different materials;

[0008] The first semiconductor layer and the second semiconductor layer are graphically represented, with the first semiconductor layer remaining on the substrate as the first fin and the second semiconductor layer remaining on the substrate as the second fin, wherein the wall thickness of the first fin is greater than the wall thickness of the second fin.

[0009] A protective layer is formed covering the second fin.

[0010] After forming a protective layer covering the second fin, a portion of the sidewall of the first fin is removed, such that the difference between the wall thickness of the first fin after removing the portion of the sidewall and the wall thickness of the second fin is less than or equal to a first preset value.

[0011] Accordingly, embodiments of the present invention further provide a semiconductor structure, including:

[0012] Substrate;

[0013] A first fin and a second fin are located on a substrate, and the first fin and the second fin are made of different materials;

[0014] A protective layer used to cover the second fin;

[0015] The difference between the wall thickness of the first fin and the wall thickness of the second fin is less than or equal to a first preset value.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0017] In this embodiment of the invention, after the first fin and the second fin are patterned, a protective layer is formed covering the second fin with a smaller wall thickness. Furthermore, while the second fin is protected by the protective layer, a portion of the sidewall of the first fin is removed, so that the difference between the wall thickness of the first fin and the wall thickness of the second fin after the removal of the partial sidewall is less than or equal to a first preset value, thereby improving the uniformity of the device size and enhancing the performance of the device. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a semiconductor structure.

[0019] Figures 2 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0020] The devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0021] refer to Figure 1 The diagram illustrates a semiconductor structure, including a first fin 1 and a second fin 2, wherein the first fin 1 and the second fin 2 are made of different materials. Typically, in semiconductor fabrication processes, the first fin 1 and the second fin 2 are formed simultaneously, that is, using the same patterning process and dry etching to form both the first fin and the second fin.

[0022] Traditionally, it is assumed that the dimensions of the first and second fins formed by the same patterning process are the same, thus rarely paying attention to the potential issue of dimensional uniformity in this process.

[0023] However, the inventors of this invention have discovered that during the formation of the first fin and the second fin, since the first fin and the second fin are made of different materials, the corresponding etching rates are substantially different, resulting in different sizes of the formed first fin and the second fin, which in turn leads to poor device performance.

[0024] To address the aforementioned technical problem, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a first semiconductor layer and a second semiconductor layer are formed on the surface of the substrate in different regions of the substrate, the first semiconductor layer and the second semiconductor layer being made of different materials; patterning the first semiconductor layer and the second semiconductor layer, wherein the remaining first semiconductor layer on the substrate is designated as a first fin, and the remaining second semiconductor layer on the substrate is designated as a second fin, wherein the wall thickness of the first fin is greater than the wall thickness of the second fin; forming a protective layer covering the second fin; and removing a portion of the sidewalls of the first fin, such that the difference between the wall thickness of the first fin after removing the portion of the sidewalls and the wall thickness of the second fin is less than or equal to a first preset value.

[0025] As can be seen, in the embodiments of the present invention, after the first fin and the second fin are patterned, a protective layer is formed covering the second fin with a smaller wall thickness. Furthermore, under the premise that the protective layer protects the second fin, part of the sidewall of the first fin is removed, so that the difference between the wall thickness of the first fin and the wall thickness of the second fin after removing part of the sidewall is less than or equal to a first preset value, thereby improving the uniformity of the device size and enhancing the performance of the device.

[0026] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Figures 2 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0028] refer to Figure 2 A substrate 100 is provided, on the surface of which a first semiconductor layer 110 and a second semiconductor layer 120 are formed in different regions of the substrate 100.

[0029] The substrate 100 is used as a base for the device to provide support for the device formation. The first semiconductor layer 110 and the second semiconductor layer 120 are used to form fins. The first semiconductor layer 110 and the second semiconductor layer 120 are made of different materials, so that first fins and second fins with different materials can be formed.

[0030] In this embodiment, the substrate 100 can be made of silicon. In other embodiments, the substrate can also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, or other materials. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material can be suitable for process requirements or easy to integrate.

[0031] The material of the first semiconductor layer 110 formed on the surface of the substrate can be silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ide, etc. The material of the second semiconductor layer 120 formed on the surface of the substrate can also be silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ide, etc. When selecting the materials of the first semiconductor layer 110 and the second semiconductor layer 120, it is only necessary to ensure that the materials of the first semiconductor layer 110 and the second semiconductor layer 120 are different. In this embodiment, the material of the first semiconductor layer 110 formed on the surface of the substrate can be silicon, and the material of the second semiconductor layer 120 formed on the surface of the substrate can be silicon germanide.

[0032] In the specific formation process, an epitaxial growth process can be used to form a first semiconductor layer 110 and a second semiconductor layer 120 in different regions of the substrate. For example, after shielding the region II for forming the second semiconductor layer, the first semiconductor layer can be formed in the region I for forming the first semiconductor layer. Then, the region II for forming the second semiconductor layer is exposed, and the second semiconductor layer is formed in the region II for forming the second semiconductor layer.

[0033] refer to Figures 3 to 4 ,in, Figure 3 This is a sectional view. Figure 4 This is a top view. Figure 3 It can be understood as Figure 4 A cross-sectional view along the straight line AA1, graphically representing the first semiconductor layer and the second semiconductor layer, with the first semiconductor layer remaining on the substrate as the first fin 111 and the second semiconductor layer remaining on the substrate as the second fin 121, wherein the wall thickness D1 of the first fin 111 is greater than the wall thickness D2 of the second fin 121.

[0034] It is understandable that the first fin 111 and the second fin 121 are made of different materials and are used to form different types of devices on the same wafer, for example, to form devices with different functions, or to form devices with the same function but different conductivity types (e.g., N-type and P-type).

[0035] In conventional understanding, the wall thickness D1 of the first fin and the wall thickness D2 of the second fin are usually considered to be equal or nearly equal. However, the inventors of this invention have discovered that due to the difference in materials between the first and second fins, the wall thickness D1 of the first fin and the wall thickness D2 of the second fin are not equal, and the difference between them affects the dimensional uniformity of the device. It is understood that due to the different materials of the first and second semiconductor layers, the dimensions of the first and second fins formed in the same patterning step are substantially different. Therefore, embodiments of this invention provide corresponding solutions to reduce this difference and improve the dimensional uniformity of the device.

[0036] On the substrate surface (reference) Figure 4 The first direction is the extension direction of the fin (X direction in the figure), and the second direction is the direction perpendicular to the extension direction of the fin (Y direction in the figure). The wall thickness of the fin refers to the size of the fin along the second direction (Y direction in the figure).

[0037] In this embodiment of the invention, a fin with a larger wall thickness can be predefined as a first fin, and the corresponding semiconductor layer used to form the first fin is a first semiconductor layer. A fin with a smaller wall thickness is a second fin, and the corresponding semiconductor layer used to form the second fin is a second semiconductor layer.

[0038] In this embodiment of the invention, the step of patterning the first semiconductor layer and the second semiconductor layer may include: forming a patterned first mask layer 130 on the first semiconductor layer and the second semiconductor layer; using the first mask layer 130 as a mask, etching away a portion of the first semiconductor layer and a portion of the second semiconductor layer to form a first fin and a second fin.

[0039] The first mask layer 130 can be formed by self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP), or other processes in the art.

[0040] During the etching process to remove a portion of the first semiconductor layer and a portion of the second semiconductor layer, a dry etching process, a wet etching process, or a combination of dry and wet etching processes can be used. In this embodiment, a dry etching process can be used to etch and remove a portion of the first semiconductor layer and a portion of the second semiconductor layer. The etching gases used include Cl2 and HBr. The flow rate of Cl2 is 50 sccm to 1000 sccm, the flow rate of HBr is 50 sccm to 500 sccm, the pressure can be 2 mτ to 100 mτ, and the power can be 100 W to 2000 W.

[0041] It should be noted that this step can employ other processes well-known in the art to pattern the first semiconductor layer and the second semiconductor layer. Further details are omitted here.

[0042] In addition, the first mask layer 130 formed during the patterning process can be retained or removed. In a preferred embodiment of the present invention, the first mask layer 130 is retained in order to protect the top of the fin in subsequent steps.

[0043] refer to Figures 5 to 6 This forms a protective layer covering the second fin.

[0044] The protective layer is used to protect the second fin during the subsequent step of removing part of the sidewall of the first fin, so that the wall thickness of the first fin is similar to that of the second fin, thereby improving the uniformity of device size.

[0045] The protective layer can be a layer structure that completely covers the top and sidewalls of the second fin, thereby protecting the second fin.

[0046] In an optional example, the protective layer may be a layer structure covering the top and sidewalls of the second fin and exposing the first fin. Correspondingly, forming the protective layer covering the second fin may include: forming a protective material layer that completely covers the sidewalls and top of both the first and second fins; and patterning the protective material layer to form a protective layer that exposes the first fin and covers the second fin. The protective material layer may be formed by a deposition process or by spin-coating a curable material and then further curing it. The protective material layer may conformally cover the second fin or completely cover it.

[0047] In this embodiment of the invention, a patterned first mask layer 130 is retained on the second fin 121, thereby protecting the top of the second fin 121. This step is preferably carried out by forming an inner sidewall 141 on the sidewall of the second fin to further protect the sidewall of the second fin, thereby using the inner sidewall 141 and the first mask layer 130 as the protective layer.

[0048] To further reduce the feature size of the fin, in this embodiment of the invention, when forming the inner sidewall 141, the inner sidewall 141 is formed in the first recessed space 140 by removing part of the sidewall of the second fin 121.

[0049] Specifically, when a patterned first mask layer 130 is formed on the second fin 121, the step of forming a protective layer 141 covering the second fin 121 may include: removing a portion of the sidewall of the second fin to form a first recessed space 140, the first recessed space 140 being surrounded by the first mask layer 130, the substrate 100, and the remaining sidewall of the second fin 121 (see reference). Figure 5 (The part shown in the dashed box); An inner wall 141 is formed within the first recessed space 140 (see reference). Figure 6 The inner wall 141 and the first mask layer 130 serve as the protective layer.

[0050] To reduce process complexity, a selective etching process can be used to remove part of the sidewall of the second fin 121, thereby avoiding the need to form a mask on the first fin 111 and simplifying the process flow. In the selective etching process, the selective etching ratio of the second fin 121 to the first fin 111 can be greater than or equal to 10:1.

[0051] Specifically, a dry etching process, a wet etching process, or a combination of dry and wet etching processes can be used to remove part of the sidewall of the second fin. In this embodiment of the invention, a dry etching process is used to remove part of the sidewall of the second fin. The etching gas used includes NF3 and H2. The flow rate of NF3 can be 50 sccm to 300 sccm, and the flow rate of H2 can be 50 sccm to 2000 sccm.

[0052] After removing part of the sidewall of the second fin 121, a first recessed space 140 can be formed, which is surrounded by the first mask layer 130, the substrate 100 and the remaining sidewall of the second fin 121, thereby forming an inner sidewall 141 in the first recessed space 140.

[0053] The forming process of the inner sidewall 141 may specifically include: forming a conformal sidewall material layer covering the substrate, the first mask layer and the first recessed space on the side of the substrate having the second fin; etching away the sidewall material layer on top of the substrate and the first mask layer; and retaining the sidewall material layer in the first recessed space as the inner sidewall.

[0054] The material of the inner sidewall 141 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. When multiple materials are included, the inner sidewall can be a layered structure.

[0055] It is understood that, in the embodiments of the present invention, removing part of the sidewall of the second fin 141 will further thin the wall thickness D2 of the second fin, thereby further reducing the feature size of the second fin. Therefore, in the step of patterning the first semiconductor layer and the second semiconductor layer in the embodiments of the present invention, a larger first fin 111 (the wall thickness of the first fin will be thinned in subsequent steps) and a second fin 121 can be formed first, so that the patterning accuracy requirement of this step is reduced accordingly, thereby reducing the difficulty of the patterning step.

[0056] refer to Figure 7 After forming a protective layer covering the second fin, a portion of the sidewall of the first fin 111 is removed, such that the difference between the wall thickness D1 of the first fin 111 after removing the portion of the sidewall and the wall thickness D2 of the second fin 121 is less than or equal to a first preset value.

[0057] The first preset value can be the error range of the feature dimensions of the first fin and the second fin. The smaller the first preset value, the better the uniformity of the first fin and the second fin. In this embodiment, the first preset value is 0 to 20% of the wall thickness D2 of the second fin in this step, that is, 0 to 20% of the wall thickness of the second fin after etching.

[0058] In this embodiment of the invention, the corresponding etching parameters can be determined based on the difference in wall thickness between the first fin and the second fin, thereby making the wall thicknesses of the first fin and the second fin approximately the same. Specifically, the step of removing a portion of the sidewall of the first fin includes: determining the difference between the wall thickness of the first fin and the wall thickness of the second fin after removing the portion of the sidewall, using the difference between the wall thickness of the first fin and the wall thickness of the second fin as a second preset value; and removing a sidewall of a preset thickness from the first fin, wherein the preset thickness is equal to the second preset value.

[0059] The difference between the wall thickness of the first fin and the wall thickness of the second fin after removing part of the sidewall can be determined by spectral measurement. For example, an optical critical dimension (OCD) system can be used to measure the wall thickness of the first fin and the wall thickness of the second fin, and then obtain the difference between the two.

[0060] In the step of removing the sidewall of the first fin to a predetermined thickness, a wet etching process, a dry etching process, or a combination of wet and dry etching processes can be used. In this embodiment, a wet etching process can be used to remove the sidewall of the first fin to a predetermined thickness, wherein the etching solution is tetramethylammonium hydroxide (TMAH).

[0061] It should be noted that, based on this embodiment, the first fin 111 and the substrate 100 are made of the same material. The etching process may simultaneously remove a portion of the substrate material (not shown in the figure). It is understood that, since the effective structural part of the device is in the fin portion, the substrate will be covered by an isolation layer in subsequent steps to achieve isolation between the substrate and the device. Thus, even if a portion of the substrate material is removed in this step, it will not affect the device formation process.

[0062] In this embodiment of the invention, after the step of removing part of the sidewall of the first fin, the method may further include:

[0063] refer to Figure 8 Remove the inner wall 141 to expose the first recessed space 140;

[0064] After obtaining the first fin and the second fin with a wall thickness difference less than or equal to a first preset value, the first recessed space is exposed by removing the inner wall, so as to remove the first mask layer exposed by the first recessed space.

[0065] Specifically, the inner wall can be removed by wet etching, dry etching, or a combination of wet and dry etching processes to expose the first recessed space.

[0066] refer to Figure 9 Etch the sidewalls of the first mask layer until the first mask layer exposed at the top of the first recessed space is removed.

[0067] Specifically, a dry etching process is preferred to remove the sidewalls of the first mask layer. In other embodiments, a wet etching process or a combination of dry and wet etching processes can also be used.

[0068] refer to Figure 10 An isolation layer 150 is formed between the first fin portion 111 and the second fin portion 121.

[0069] An isolation layer is formed between the first fin and the second fin to achieve isolation between the subsequent device structure and the substrate.

[0070] In this embodiment, the step of forming an isolation layer between the first fin and the second fin may include: forming an isolation material layer that completely covers the first mask layer; planarizing the isolation material layer to expose the first mask layer; removing the first mask layer; and etching back to remove a portion of the isolation material layer until a portion of the sidewalls of the first fin and the second fin are exposed.

[0071] A deposition process can be used to form an isolation material layer that completely covers the first mask layer. The isolation material layer can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. The isolation material layer can be planarized using a chemical mechanical polishing (CMP) process. Afterwards, the first mask layer can be removed using etching processes such as wet etching or dry etching. After removing the first mask layer, a portion of the isolation material layer is etched back until part of the sidewalls of the first and second fins are exposed, and the remaining isolation material layer serves as the isolation layer.

[0072] In this embodiment of the invention, after the first fin and the second fin are patterned, a protective layer is formed covering the second fin with a smaller wall thickness. Furthermore, while the second fin is protected by the protective layer, a portion of the sidewall of the first fin is removed. This results in the difference between the wall thickness of the first fin and the wall thickness of the second fin after the removal of the partial sidewall being less than or equal to a first preset value, thereby improving the uniformity of the device size and enhancing the device performance.

[0073] In another embodiment of the present invention, a semiconductor structure is further provided, with reference to... Figure 7 The semiconductor structure may include:

[0074] Substrate 100; a first fin 111 and a second fin 121 located on the substrate, the first fin 111 and the second fin 121 being made of different materials; a protective layer for covering the second fin 121; the difference between the wall thickness D1 of the first fin 111 and the wall thickness D2 of the second fin 121 being less than or equal to a first preset value.

[0075] The substrate 100 serves as the base for the device, providing support for device formation. In this embodiment, the substrate 100 can be made of silicon. In other embodiments, the substrate can also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium phosphate, or other materials. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material can be suitable for process requirements or easy to integrate.

[0076] The material of the first fin 111 can be silicon, germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium, etc., and the material of the second fin 121 can be silicon, germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium, etc. When selecting the materials of the first fin 111 and the second fin 121, it is only necessary to make the materials of the first fin 111 and the second fin 121 different.

[0077] In this embodiment, the material of the first fin 111 can be silicon, and the material of the second fin 121 can be silicon germanide.

[0078] The protective layer can be a layer structure that completely covers the top and sidewalls of the second fin, thereby protecting the second fin. In this embodiment of the invention, a patterned first mask layer 130 is provided on the top of the second fin 121, thereby protecting the top of the second fin 121. In this embodiment, it is preferable to provide an inner sidewall 141 on the sidewall of the second fin, with the inner sidewall 141 and the first mask layer 130 serving as the protective layer.

[0079] The material of the inner sidewall 141 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. When multiple materials are included, the inner sidewall can be a layered structure.

[0080] The first preset value can be the error range of the feature dimensions of the first fin and the second fin. The smaller the first preset value, the better the uniformity of the first fin and the second fin. In this embodiment, the first preset value is 0 to 20% of the wall thickness D2 of the second fin.

[0081] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; they will not be repeated here.

[0082] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0083] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, a first semiconductor layer and a second semiconductor layer being formed on a surface of the substrate and located in different regions of the substrate, the first semiconductor layer and the second semiconductor layer being made of different materials; patterning the first semiconductor layer and the second semiconductor layer to form a first fin portion and a second fin portion, the first fin portion being formed by the first semiconductor layer remaining on the substrate, and the second fin portion being formed by the second semiconductor layer remaining on the substrate, a wall thickness of the first fin portion being greater than a wall thickness of the second fin portion; forming a protective layer covering the second fin portion; after forming the protective layer covering the second fin portion, removing part of the sidewall of the first fin portion, so that a difference between the wall thickness of the first fin portion after the sidewall is removed and the wall thickness of the second fin portion is less than or equal to a first preset value, the first preset value being an error range of characteristic dimensions of the first fin portion and the second fin portion.

2. The method of forming a semiconductor structure of claim 1, wherein, In the step of removing part of the sidewall of the first fin portion, the first preset value is 0-20% of the wall thickness of the second fin portion.

3. The method of forming a semiconductor structure of claim 1, wherein, The patterning of the first semiconductor layer and the second semiconductor layer comprises the following steps: forming a first mask layer on the first semiconductor layer and the second semiconductor layer; using the first mask layer as a mask, etching to remove part of the first semiconductor layer and part of the second semiconductor layer, to form the first fin portion and the second fin portion.

4. The method of forming a semiconductor structure of claim 3, wherein, When the first mask layer is formed on the second fin portion, the forming of the protective layer covering the second fin portion comprises the following steps: removing part of the sidewall of the second fin portion to form a first inner recess space, the first inner recess space being surrounded by the first mask layer, the substrate and the sidewall of the remaining second fin portion; forming an inner sidewall in the first inner recess space, using the inner sidewall and the first mask layer as the protective layer.

5. The method of forming a semiconductor structure of claim 4, wherein, The removing of part of the sidewall of the first fin portion comprises the following steps: determining a difference between the wall thickness of the first fin portion and the wall thickness of the second fin portion after part of the sidewall is removed, using the difference between the wall thickness of the first fin portion and the wall thickness of the second fin portion as a second preset value; removing a preset thickness of the sidewall of the first fin portion, the preset thickness being equal to the second preset value.

6. The method of forming a semiconductor structure of claim 3, wherein, The etching to remove part of the first semiconductor layer and part of the second semiconductor layer is performed by using a dry etching process, wherein the etching gas used comprises Cl2 and HBr, the flow rate of Cl2 is 50-1000 sccm, and the flow rate of HBr is 50-500 sccm.

7. The method of forming a semiconductor structure of claim 4, wherein, The removing of part of the sidewall of the second fin portion is performed by using a selective etching process, wherein the selective etching ratio of the second fin portion to the first fin portion is greater than or equal to 10:

1.

8. The method of forming a semiconductor structure of claim 7, wherein, The removing of part of the sidewall of the second fin portion is performed by using a dry etching process, wherein the etching gas used comprises NF3 and H2, the flow rate of NF3 is 50-300 sccm, and the flow rate of H2 is 50-2000 sccm.

9. The method of forming a semiconductor structure of claim 4, wherein, The material of the inner sidewall is one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitrogen oxide, boron nitride and boron carbon nitride.

10. The method of forming a semiconductor structure of claim 5, wherein, Determine a difference between a wall thickness of the first fin and a wall thickness of the second fin after removing the sidewall of the first fin.

11. The method of forming a semiconductor structure of claim 5, wherein, Remove a preset thickness of the sidewall of the first fin by using a wet etching process, wherein an etching solution used in the wet etching process is tetramethylammonium hydroxide.

12. The method of forming a semiconductor structure of claim 5, wherein, After the step of removing the part of the sidewall of the first fin, further comprising: Remove the inner sidewall to expose the first recessed space; Etch the sidewall of the first mask layer until the first mask layer exposed at the top of the first recessed space is removed; Form an isolation layer between the first fin and the second fin.

13. The method of forming a semiconductor structure of claim 12, wherein, The step of forming the isolation layer between the first fin and the second fin, comprising: Form an isolation material layer covering the first mask layer completely; Planarize the isolation material layer so that the isolation material layer exposes the first mask layer; Remove the first mask layer; Etch back to remove part of the isolation material layer until part of the sidewall of the first fin and the second fin is exposed.

14. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the protection layer covering the second fin, comprising: Form a protection material layer covering the sidewall and the top of the first fin and the second fin; Pattern the protection material layer to form a protection layer exposing the first fin and covering the second fin.

15. A semiconductor structure, characterized by Comprising: A substrate; A first fin and a second fin on the substrate, the first fin and the second fin being made of different materials, the first fin and the second fin being obtained by patterning a first semiconductor layer on the substrate and a second semiconductor layer on the substrate, the first semiconductor layer and the second semiconductor layer being located on different regions of the substrate, the wall thickness of the first fin being greater than the wall thickness of the second fin; A protection layer covering the second fin; The difference between the wall thickness of the first fin and the wall thickness of the second fin is less than or equal to a first preset value, the first preset value being an error range of characteristic dimensions of the first fin and the second fin.

16. The semiconductor structure of claim 15, wherein, The first preset value is 0-20% of the wall thickness of the second fin.

17. The semiconductor structure of claim 15, wherein, The protection layer comprises a first mask layer arranged on the top of the second fin and an inner sidewall arranged on the sidewall of the second fin.

18. The semiconductor structure of claim 17, wherein, The material of the inner sidewall is one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon oxynitride, boron nitride, and boron carbon nitride.

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