Stacked packages including passive components
By adopting a stacked packaging structure in semiconductor packaging, utilizing zigzag and stepped die layout and adhesive layer optimization, the problem of adding passive components in a limited space is solved, and the electrical and signal characteristics of the package are improved.
Patent Information
- Application Number
- CN202110489764.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-09-08
- Filing Date
- 2021-05-06
- Publication Date
- 2025-09-09
- Estimated Expiration
- 2041-05-06
AI Technical Summary
In a semiconductor package of limited size, how to effectively increase the number of passive components to improve electrical characteristics while avoiding an increase in package size.
A stacked packaging structure is adopted, in which the passive components are arranged on the packaging substrate and separated from the tube core, the lower stack and the upper stack are vertically stacked in a zigzag or stepped shape, and the adhesive layer and bonding wire are used to optimize the spatial layout to ensure the effective connection between the passive components and the tube core.
Without increasing the package size, the number of passive components is increased, the electrical and signal characteristics of the package are improved, and interference and damage between components are effectively prevented.
Smart Images

Figure CN114156257B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates generally to semiconductor packaging technology, and more particularly to a stacked package arrangement including passive components. Background Art
[0002] Semiconductor packages are used in various electronic applications. Semiconductor packages can be used in personal computers, mobile phones, cameras, and the like. As electronic products and semiconductor packages require high-speed operation and large-capacity data processing, there is an increasing demand for packaging multiple semiconductor dies within a single semiconductor package. With multiple semiconductor dies embedded in a semiconductor package, attempts have been made to construct structures in which the semiconductor dies are three-dimensionally stacked on top of one another. To improve the electrical characteristics of semiconductor packages, attempts have been made to arrange passive components within the semiconductor package. Attempts are underway to increase the number of passive components within a semiconductor package of limited size. Summary of the Invention
[0003] According to one aspect of the present disclosure, a stacked package may include: a packaging substrate; a lower stack, the lower stack including a lower tube core stacked on the packaging substrate to form a zigzag shape in a vertical direction; an upper stack, the upper tube core including an upper tube core, the upper tube core being stacked sequentially offset in an offset direction while providing a first upper side of a downward step shape, the first end of the uppermost tube core of the upper tube core protruding farther in the horizontal direction than the first lower side of the lower stack; and a first passive component, the first passive component is arranged on the packaging substrate and spaced apart from the first lower side, and is arranged between the first part of the packaging substrate and the first upper side.
[0004] According to one aspect of the present disclosure, a stacked package may include: a packaging substrate; a first passive component and a second passive component, the first passive component and the second passive component being arranged on the packaging substrate to be spaced apart from each other; a lower stack, the lower stack being arranged between the first passive component and the second passive component and including a lower die vertically stacked and providing a first lower side and a second lower side; and an upper stack, the upper stack including a lowermost die, an intermediate die, and an uppermost die, the lowermost die having a second end partially overlapping with the second passive component, the uppermost die having a first end partially overlapping with the first passive component, the lowermost die, the intermediate die, and the uppermost die being stacked sequentially in a stepped shape. BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Figure 1 and Figure 2 is a schematic cross-sectional view showing a stacked package according to one embodiment.
[0006] Figure 3 It shows Figure 1Schematic cross-sectional view of the shape of the lower stack of the stack package.
[0007] Figure 4 It shows Figure 2 Schematic cross-sectional view of the shape of the first sub-stack of the stack package.
[0008] Figure 5 It shows Figure 2 Schematic cross-sectional view of the shape of the lower stack of the stack package.
[0009] Figure 6 It shows Figure 1 Schematic cross-sectional view of the shapes of the lower and upper stack layers of a stack package.
[0010] Figure 7 It is shown that Figure 1 Schematic cross-sectional view of an enlarged portion of a first passive component of a stacked package.
[0011] Figure 8 It is shown that Figure 1 Schematic cross-sectional view of an enlarged portion of a second passive component of the stacked package.
[0012] Figure 9 It shows Figure 1 Schematic plan view of the arrangement shape of the first passive component and the second passive component of the stacked package.
[0013] Figure 10 and Figure 11 is a schematic cross-sectional view showing a stacked package according to one embodiment.
[0014] Figure 12 is a block diagram illustrating an electronic system employing a memory card including a package according to one embodiment.
[0015] Figure 13 is a block diagram illustrating an electronic system including a package according to one embodiment. DETAILED DESCRIPTION
[0016] The terms used herein may correspond to words selected with consideration of their function in the embodiments presented, and the meanings of the terms may be interpreted differently according to the ordinary skill in the art to which the embodiments belong. If defined in detail, the terms may be interpreted according to the definitions. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those of ordinary skill in the art to which the embodiments belong.
[0017] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various devices, these devices should be limited by these terms. These terms are only used to distinguish one device from another, and are not used to indicate a specific order or quantity of the devices.
[0018] The semiconductor device may include a semiconductor substrate or a structure stacked with multiple semiconductor substrates. The semiconductor device may represent a semiconductor package structure in which a structure stacked with a semiconductor substrate is encapsulated. The semiconductor substrate may represent a semiconductor wafer, a semiconductor die or a semiconductor chip integrated with electronic components. The semiconductor chip may represent a memory chip integrated with a memory integrated circuit (e.g., a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a NAND flash memory circuit, a NOR flash memory circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit or a phase change random access memory (PcRAM)) circuit, a logic die or an ASIC chip in which a logic circuit is integrated in a semiconductor substrate, or a processor (e.g., an application processor (Ap), a graphics processing unit (GPU), a central processing unit (CPU) or a system on a chip (SoC)). The semiconductor device may be used in an information communication system (e.g., a mobile phone, an electronic system associated with biotechnology or healthcare, or a wearable electronic system). The semiconductor package may be applied to the Internet of Things (IoT).
[0019] Throughout the specification, the same reference numerals denote the same devices. Even if a reference numeral may not be mentioned or described with reference to a drawing, it may be mentioned or described with reference to another drawing. Also, even if a reference numeral may not be shown in a drawing, it may be shown in another drawing.
[0020] Figure 1 and Figure 2 is a schematic cross-sectional view showing a stacked package 10 according to one embodiment. Figure 1 A schematic cross-sectional shape along a cutting line X1 - X1 ′ passing through the first passive component 610 and the second passive component 620 of the stacked package 10 is shown. Figure 2 A schematic cross-sectional shape along a cutting line X2 - X2 ′ passing through the first bonding line 810 and the second bonding line 820 of the stacked package 10 is shown.
[0021] Reference Figure 1 The stacked package 10 may include a package substrate 200, a lower stack 300, an upper stack 400, a package layer 500, and a first passive component 610. Figure 2The stacked package 10 may further include connecting members, such as first bonding wires 810 and second bonding wires 820. The stacked package 10 may further include a controller die 710 disposed between the lower stack 300 and the package substrate 200. The encapsulation layer 500 may be formed as a protective layer that covers and encapsulates the lower stack 300 and the upper stack 400 while covering the package substrate 200. The encapsulation layer 500 may be formed of epoxy molding compound (EMC).
[0022] The lower stack 300 may include a lower die 301, and the upper stack 400 may include an upper die 401. The controller die 710 may be an integrated semiconductor die having integrated logic circuits for controlling the lower die 301 and the upper die 401. To ensure space for placing the controller die 710, a support member 730 may be introduced. The support member 730 may be provided around the controller die 710 to support the lower stack 300 while elevating the lower stack 300. The support member 730 may be introduced in the form of a dummy die or a dielectric block.
[0023] The support member 730 may be bonded to the package substrate 200 via a third adhesive layer 731. The controller die 710 may be connected to the package substrate 200 via a conductive internal connector 711. The conductive internal connector 711 may include a conductive member such as a bump. The lower laminate 300 may be bonded to the controller die 710 and the support member 730 via a fourth adhesive layer 735.
[0024] The stacked package 10 may further include a second passive component 620. The second passive component 620 may be a different type of component than the first passive component 610. Each of the passive components 610 and 620 may include a capacitor, a resistor, or an inductor. The passive components 610 and 620 may be incorporated into the stacked package 10 as components that provide functions such as decoupling, filtering, resonance attenuation, or voltage regulation. The first passive component 610 may include a capacitor, and the second passive component 620 may include a resistor. The passive components 610 and 620 may help improve the electrical characteristics of the stacked package 10 and improve the reliability of signal characteristics.
[0025] The lower stack 300 may have a structure in which a plurality of lower tube cores 301 are substantially stacked vertically with respect to each other. The upper stack 400 may have a structure in which a plurality of upper tube cores 401 are substantially stacked vertically with respect to each other. The number of stacked lower tube cores 301 may be the same as the number of stacked upper tube cores 401. In one embodiment, the number of stacked lower tube cores 301 may be different from the number of stacked upper tube cores 401. The structure in which the lower tube cores 301 are stacked may be different from the structure in which the upper tube cores 401 are stacked.
[0026] The lower die 301 and the upper die 401 may be semiconductor dies having the same shape and function as each other. The lower die 301 and the upper die 401 may be memory semiconductor dies. In one embodiment, the lower die 301 and the upper die 401 may be semiconductor dies of different types.
[0027] The lower laminate 300 may include a first sub-laminate 311 and a second sub-laminate 331. The second sub-laminate 331 may be vertically stacked on the first sub-laminate 311. A first adhesive layer 350 may be introduced into the interface between the second sub-laminate 331 and the first sub-laminate 311, while bonding the second sub-laminate 331 to the first sub-laminate 311. The first sub-laminate 311 and the second sub-laminate 331 may have substantially the same shape. The first sub-laminate 311 and the second sub-laminate 331 may be stacked to align with each other in the vertical direction. The second sub-laminate 331 may be stacked to completely overlap with the first sub-laminate 311.
[0028] Additional sub-stacks may be further stacked on the first sub-stack 311 and the second sub-stack 331 .
[0029] Figure 3 It shows Figure 1 Schematic cross-sectional view of the shape of the lower stack 300.
[0030] Reference Figure 3 , a plurality of lower tube cores 301 can be stacked substantially perpendicularly to each other to configure the lower stack 300. The lower tube cores 301 can be stacked on each other while forming a zigzag pattern in the vertical direction. The lower tube cores 301 can be stacked so as to be alternately stacked in the vertical direction. The lower stack 300 provides a first lower side 308 and a second lower side 309 opposite to each other. The first lower side 308 and the second lower side 309 can be formed as concave and convex sides, serrated sides, or staggered sides.
[0031] Figure 4 It shows Figure 2 Schematic cross-sectional view of the shape of the first sub-stack 311.
[0032] Reference Figure 4 and Figure 2 , the first sub-stack 311 constituting the lower stack 300 may include a first lower die 310 and a second lower die 320. In one embodiment, an additional lower die may be further provided on the second lower die 320. Each of the lower dies 301 may include a lower bonding pad 303 at an edge portion. The lower bonding pad 303 may be Figure 2 The connecting member connected by the second connecting line 820.
[0033] The second lower die 320 may be disposed at a position shifted a predetermined distance in the second offset direction D2 relative to the first lower die 310. In one embodiment, the second lower die 320 may be disposed at a position horizontally shifted a predetermined distance in the second offset direction D2 relative to the first lower die 310. The second lower die 320 may be offsetly stacked on the first lower die 310. The second lower die 320 may be offsetly stacked on the first lower die 310 while exposing the first lower bonding pads 313 of the first lower die 310.
[0034] Figure 5 It shows Figure 2 Schematic cross-sectional view of the shape of the lower stack 300.
[0035] Reference Figure 5 , the second sub-laminate 331 may be stacked on the first sub-laminate 311. The second sub-laminate 331 may be stacked to be substantially completely aligned with the first sub-laminate 311 in the vertical direction. The second edge E2 of the second sub-laminate 331 may be aligned with the first edge E1 of the first sub-laminate 311 in the vertical direction. The second sub-laminate 331 may have the same shape as the first sub-laminate 311. The third lower die 330 may be disposed on the first sub-laminate 311 to substantially completely overlap with the first lower die 310. The fourth lower die 340 may be disposed to substantially completely overlap with the second lower die 320. The fourth lower die 340 may be stacked on the third lower die 330 offset from a position offset from the third lower die 330 in the second offset direction D2.
[0036] The structure of the lower laminate 300 in which the second sub-laminate 331 is stacked on the first sub-laminate 311 may include a structure in which the lower dies 301 are alternately stacked while forming a zigzag shape in a substantially vertical direction. This zigzag stacking structure can be used to connect the second bonding wire 820 to each of the lower dies 301.
[0037] The second bonding wire 820 may be formed to electrically connect the lower bonding pad 303 of the lower die 301 to the package substrate 200. The package substrate 200 may include a first bonding finger 211 and a second bonding finger 212. The second bonding wire 820 may electrically connect the lower bonding pad 303 to the second bonding finger 212. The second bonding wire 820 may extend to connect the second lower bonding pad 323 to the first lower bonding pad 313, and further to the second bonding finger 212.
[0038] In the zigzag stacking structure of the lower stack 300, the second lower die 320 is stacked on the first lower die 310. The second lower die 320 is stacked offset in the second offset direction D2 to expose the first lower bonding pads 313 of the first lower die 310. The first lower bonding pads 313 are exposed without being covered by the second lower die 320, so that the second lower die 320 does not interfere with the bonding of the second bonding wires 820 to the first lower bonding pads 313.
[0039] The third lower die 330 of the second sub-stack 331 can substantially completely overlap the first lower die 310. The third lower die 330 can be positioned so that a portion of the third lower die 330 overlaps the portion 820B of the second bonding wire 820 bonded to the second lower bonding pad 323. Therefore, the portion 820B of the second bonding wire 820 bonded to the second lower bonding pad 323 may be deformed or damaged due to being squeezed by the third lower die 330. To prevent such damage, a first adhesive layer 350 is introduced between the second lower die 320 and the third lower die 330. The first adhesive layer 350 ensures a gap between the second lower die 320 and the third lower die 330, thereby preventing the portion 820B of the second bonding wire 820 from being damaged by the third lower die 330. To this end, the first adhesive layer 350 can be formed to have a thickness T1 that is thicker than the loop height formed by the portion 820B of the second bonding wire 820 bonded to the second lower bonding pad 323.
[0040] The first adhesive layer 350 may be formed thicker than the second adhesive layer 355 for bonding the lower dies 301 other than the second lower die 320. The first adhesive layer 350 may be formed to have a thickness T1 thicker than the thickness T2 of the second adhesive layer 355. The second adhesive layer 355 may be introduced as a layer for bonding the first lower die 310 and the second lower die 320 to each other. It is not necessary to ensure a gap for the second bonding wire 820 between the first lower die 310 and the second lower die 320. Therefore, the second adhesive layer 355 may be introduced with a thickness T2 thinner than the first adhesive layer 350.
[0041] The second lower die 320 is offsetly stacked on the first lower die 310 to expose the first lower bonding pads 313, allowing the thinner second adhesive layer 355 to be introduced between the second lower die 320 and the first lower die 310 without introducing a thicker adhesive layer (e.g., the first adhesive layer 350). The fourth lower die 340 is also offsetly stacked on the third lower die 330 to expose the third lower bonding pads 333, allowing the thinner second adhesive layer 355 to be introduced between the fourth lower die 340 and the third lower die 330 without introducing a thicker adhesive layer (e.g., the first adhesive layer 350). As described above, because the thicker first adhesive layer 350 can be limitedly introduced only between the first sub-laminate 311 and the second sub-laminate 331, the thickness T3 of the lower laminate 300 can be prevented from excessively increasing.
[0042] A portion 820B of the second bonding wire 820 is bonded to the second lower bonding pad 323 while penetrating into the first adhesive layer 350. The portion 820B of the second bonding wire 820 may be dipped into the first adhesive layer 350.
[0043] Figure 6 It shows Figure 1 FIG. 1 is a schematic cross-sectional view of a stacked shape of a lower stack 300 and an upper stack 400 of a stacked package 10 . Figure 6 Is shown omitted Figure 1 The first passive device and the second passive device ( Figure 1 610 and 620) of the shape of the view.
[0044] Reference Figure 6 , the upper stack 400 is disposed on the lower stack 300. The plurality of upper tube cores 401 can be sequentially moved in a first offset direction D1 and stacked in an offset manner. The first offset direction D1 can be a direction opposite to the second offset direction D2 in which the lower tube core 301 is offset. In one embodiment, the first offset direction D1 can be a horizontal direction opposite to the second offset direction D2 in which the lower tube core 301 is offset. The distance by which each of the upper tube cores 401 is offset and moved in the first offset direction D1 can be substantially the same as the distance by which each of the lower tube cores 301 is moved in the second offset direction D2. The distance by which each of the upper tube cores 401 is offset in the first offset direction D1 can be substantially the same as the distance by which each of the second tube cores 320 is offset relative to the first lower tube core 310 in the second offset direction D2.
[0045] As the upper dies 401 are sequentially stacked in the first offset direction D1, an upper stack 400 having a stepped shape may be formed. The upper stack 400 may have a first upper side 408 having a descending stepped shape descending toward the package substrate 200. The upper stack 400 may have a second upper side 409 having an ascending stepped shape on the opposite side of the first upper side 408. The second upper side 409 may have a shape opposite or inverted to the first upper side 408.
[0046] The first end 440E of the uppermost upper die 440 in the upper dies 401 may protrude beyond the first lower side 308 of the lower laminate 300. In one embodiment, the first end 440E of the uppermost upper die 440 in the upper dies 401 may protrude further in the horizontal direction than the first lower side 308 of the lower laminate 300. The second end 410E of the lowermost upper die 410 in the upper dies 401 may also protrude beyond the second lower side 309 of the lower laminate 300. The first and second intermediate upper dies 420 and 430 may be stacked between the lowermost upper die 410 and the uppermost upper die 440. In one embodiment, three or more upper dies may be stacked between the lowermost upper die 410 and the uppermost upper die 440.
[0047] Together Figure 2 Reference Figure 6 , the upper stack 400 has a first upper side 408 and a second upper side 409. The second upper side 409 may have an upward stepped shape, and the upward stepped shape may expose the upper bonding pad 403 of each of the upper dies 401. First bonding wires 810 may be formed to electrically connect the upper bonding pads 403 to the first bonding fingers 211 of the package substrate 200. Each of the first bonding wires 810 may connect the exposed upper bonding pads 403 to each other through a stepped structure.
[0048] The fifth adhesive layer 455 may be introduced between the upper dies 401 to bond the upper dies 401 to each other. The fifth adhesive layer 455 may be introduced as an adhesive layer having substantially the same thickness as the second adhesive layer 355. The upper dies 401 of the upper stack 400 are stacked in a sequential stepped shape to expose the upper dies 401. Figure 2 The upper bonding pad 403 is shown, so that a thicker adhesive layer (eg, first adhesive layer 350 ) may not be introduced. The thickness T4 of the upper stack 400 can be minimized because each of the upper dies 401 is bonded using a thinner fifth adhesive layer 455 .
[0049] Figure 7 It is shown that Figure 1 FIG. 1 is a schematic cross-sectional view of an enlarged portion of a first passive component 610 of the stacked package 10 .
[0050] Reference Figure 7, the first passive device 610 may be disposed on the first portion 201 of the package substrate 200. The first portion 201 of the package substrate 200 may refer to one edge portion of the edge portions of the package substrate 200 facing each other. The third bond finger 213 to which the first passive device 610 is connected may be disposed on the first portion 201 of the package substrate 200. The first passive device 610 may be bonded to the third bond finger 213 via a first conductive adhesive layer 651. The first conductive adhesive layer 651 may include a solder material. The first passive device 610 may be electrically connected to the package substrate 200 via the first conductive adhesive layer 651.
[0051] The encapsulation layer 500 may have a first outer side 501. The first outer side 501 may be a side facing the first lower side 308 of the lower laminate 300 and the first upper side 408 of the upper laminate 400. A first space 618 may be ensured between the first outer side 501 of the encapsulation layer 500 and the first lower side 308 of the lower laminate 300, and between the first upper side 408 of the upper laminate 400 and the first portion 201 of the encapsulation substrate 200. A first passive component 610 may be disposed in the first space 618. In one embodiment, the first passive component 610 may be disposed in the first space 618 and spaced apart horizontally from the first lower side 308 of the lower laminate 300.
[0052] The first passive component 610 can be disposed on the first portion 201 of the package substrate 200 such that the upper end 610T of the first passive component 610 is lower than the first end 440E of the top-up die 440. The first passive component 610 can be disposed on the first portion 201 of the package substrate 200 such that some portion of the first passive component 610 overlaps with the first end 440E of the top-up die 440. Thus, the first passive component 610 can be disposed on the package substrate 200 while suppressing an increase in the width W or size of the stacked package 10. If the first passive component does not overlap with the first end 440E of the top-up die 440 and is located outside the first end 440E of the top-up die 440, the width of the stacked package may be increased to further ensure an area or space for the first passive component to be disposed. However, because the first passive component 610 is disposed in the stacked package 10 such that some portion of the first passive component 610 overlaps the first end 440E of the topmost die 440, the increase in the width W of the stacked package 10 can be significantly minimized. The overlapping space below the first end 440E of the topmost die 440 can serve as space for disposing the first passive component 610, thereby significantly minimizing the increase in the width W of the stacked package 10.
[0053] The upper end 610T of the first passive component 610 can be spaced apart from, and not in contact with, the first end 440E of the uppermost-upper die 440. The first end 440E of the uppermost-upper die 440 can be located at a higher position than the first passive component 610, so that the first end 440E of the uppermost-upper die 440 can be spaced apart from the upper end 610T of the first passive component 610. Therefore, the upper end 610T of the first passive component 610 can be prevented from contacting the first end 440E of the uppermost-upper die 440. Furthermore, the defect of the upper end 610T of the first passive component 610 contacting the first end 440E of the uppermost-upper die 440 and being damaged can be effectively prevented.
[0054] Figure 8 It is shown that Figure 1 FIG. 1 is a schematic cross-sectional view of an enlarged portion of a second passive component 620 of the stacked package 10 .
[0055] Reference Figure 8 , the second passive device 620 may be disposed on the second portion 202 of the package substrate 200. The fourth bond finger 214 to which the second passive device 620 is connected may be disposed on the second portion 202 of the package substrate 200. The second passive device 620 may be bonded to the fourth bond finger 214 via a second conductive adhesive layer 652. The second passive device 620 may be electrically connected to the package substrate 200 via the second conductive adhesive layer 652.
[0056] The second outer side 502 of the encapsulation layer 500 may be a side facing the second lower side 309 of the lower stack 300 and the second upper side 409 of the upper stack 400. The second outer side 502 of the encapsulation layer 500 is opposite to the first outer side ( Figure 7 501). A second space 619 can be ensured between the second outer side 502 of the encapsulation layer 500 and the second lower side 309 of the lower laminate 300, and between the second upper side 409 of the upper laminate 400 and the second portion 202 of the encapsulation substrate 200. A second passive component 620 can be disposed in the second space 619. In one embodiment, the second passive component 620 can be disposed in the second space 619 and spaced apart horizontally from the second lower side 309 of the lower laminate 300.
[0057] The second passive component 620 may be disposed on the second portion 202 of the package substrate 200 such that the upper end 620T is lower than the second end 410E of the lowermost upper die 410. The second passive component 620 may be disposed on the second portion 201 of the package substrate 200 such that a portion of the second passive component 620 overlaps with the second end 410E of the lowermost upper die 410, and the upper end 620T of the second passive component 620 may be spaced apart from, and not in contact with, the second end 410E of the lowermost upper die 410. The second end 410E of the lowermost upper die 410 may be located at a higher position than the second passive component 620. Therefore, the upper end 620T of the second passive component 620 may be effectively prevented from contacting the second end 410E of the lowermost upper die 410, thereby preventing damage defects caused by the contact.
[0058] The second passive component 620 is disposed within the stacked package 10 such that a portion of the second passive component 620 overlaps the second end 410E of the lowermost upper die 410. Therefore, the arrangement of the second passive component 620 effectively suppresses or substantially minimizes any increase in the width W, or size, of the stacked package 10. If the second passive component were not overlapped with the second end 410E of the lowermost upper die 410 and were located outside of the lowermost upper die 410, the width of the stacked package 10 would likely increase to further secure the area or space for the second passive component. However, because the second passive component 620 is disposed within the stacked package 10 such that a portion of the second passive component 620 overlaps the second end 410E of the lowermost upper die 410, the increase in the width W, or size, of the stacked package 10 can be significantly minimized. The overlapping space below the second end 410E of the lowermost upper die 410 can serve as space for the second passive component 620, significantly minimizing any increase in the width W of the stacked package 10.
[0059] Common Reference Figure 8 and Figure 7 Because the second end 410E of the lowermost upper die 410 is located lower than the first end 440E of the uppermost upper die 440, the height of the second space 619 is lower than the height of the first space 618. To accommodate the second passive component 620 in the second space 619, the thickness T6 of the second passive component 620 is preferably smaller than the thickness T5 of the first passive component 610. In one embodiment, a capacitor component may be included as the first passive component 610, and a resistor component may be included as the second passive component 620.
[0060] Figure 9 It shows that Figure 1 FIG. 1 is a schematic plan view of a planar shape of a first passive component 610 and a second passive component 620 disposed on a package substrate 200 .
[0061] Reference Figure 9 and Figure 1 , the first bond fingers 211 can be arranged in a row on one side of the package substrate 200, and the second bond fingers 212 can be arranged in a row on the opposite side. The second passive device 620 can be arranged between the first bond fingers 211, and the first passive device 610 can be arranged between the second bond fingers 212. Because the passive devices 610 and 620 are arranged between the rows formed by the bond fingers 211 and 212, the area in which the passive devices 610 and 620 are arranged on the package substrate 200 can be effectively ensured. Therefore, the number of passive devices 610 and 620 that can be arranged in the stacked package 10 can be increased. Therefore, the electrical characteristics of the stacked package 10 can be improved.
[0062] At the same time, the controller die 710 may be disposed at the center portion of the package substrate 200, and the support members 730 may be disposed on both sides of the controller die 710. Therefore, the lower laminate 300 is supported in a balanced manner by the support members 730 on both sides, so that the lower laminate 300 and the upper laminate 400 can be stably supported by the support members 730.
[0063] Figure 10 and Figure 11 is a schematic cross-sectional view showing a stacked package 15 according to one embodiment. Figure 10 A schematic cross-sectional shape along a cutting line X3 - X3 ′ passing through the first passive component 1610 and the second passive component 1620 of the stacked package 15 is shown. Figure 11 A schematic cross-sectional shape along a cutting line X4 - X4 ′ passing through the first bonding line 1810 and the second bonding line 1820 of the stacked package 15 is shown.
[0064] and Figure 1 and Figure 2 The stacked package 10 of another embodiment shown is different. Figure 10 and Figure 11 The stacked package 15 of the illustrated embodiment may have a package structure without introducing the controller die 710 and the support member 730 . Figure 10 and Figure 11 Shown with Figure 1 and Figure 2 Elements that are identical or similar to the elements in the description may be understood as substantially identical elements.
[0065] Reference Figure 10 and Figure 11The stacked package 15 may include a package substrate 1200, a package layer 1500, a first passive component 1610 and a second passive component 1620, a lower stack 1300, and an upper stack 1400. The first passive component 1610 and the second passive component 1620 may be disposed on the package substrate 1200 while being spaced apart from each other. The lower stack 1300 may be disposed between the first passive component 1610 and the second passive component 1620 and may be stacked in a vertical direction such that the lower die 1301 provides a first lower side 1308 and a second lower side 1309. The second bonding wire 1820 may be connected to the lower bonding pad 1303 exposed to the first lower side 1308 of the lower stack 1300.
[0066] The lowermost upper die 1410, the intermediate upper dies 1420 and 1430, and the uppermost upper die 1440 may be sequentially stacked in a stepped shape to configure the upper stack 1400. The upper stack 1400 may have a first upper side 1408 in a descending stepped shape and a second upper side 1409 in an ascending stepped shape. The second end 1410E of the lowermost upper die 1410 may partially overlap with the second passive component 1620, and the first end 1440E of the uppermost upper die 1440 may partially overlap with the first passive component 1610. The first bonding wire 1810 may be connected to the upper bonding pad 1403 exposed to the second upper side 1409 of the upper stack 1400.
[0067] According to the above-described embodiments of the present disclosure, a stacked package structure including passive components can be provided. A stacked structure of semiconductor dies can be provided in which space is ensured for the passive components to be disposed within the stacked package. The stacked package can contain multiple passive components while maintaining a limited size and thickness.
[0068] Figure 12 7 is a block diagram illustrating an electronic system including a memory card 7800 that employs at least one of the semiconductor packages according to embodiments. Memory card 7800 includes a memory 7810, such as a nonvolatile memory device, and a memory controller 7820. Memory 7810 and memory controller 7820 can store data or read stored data. At least one of memory 7810 and memory controller 7820 may include at least one of the semiconductor packages according to embodiments.
[0069] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 to read stored data or store data in response to a read / write request from the host 7830 .
[0070] Figure 1387 is a block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to an embodiment. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be coupled to each other via a bus 8715, which provides a path for data movement.
[0071] In one embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include at least one semiconductor package from among the semiconductor packages according to the embodiments of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands to be executed by the controller 8711, etc.
[0072] The memory 8713 may include a volatile memory device such as a DRAM, and / or a non-volatile memory device such as a flash memory device. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid-state drive (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.
[0073] The electronic system 8710 may further include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be a wired type or a wireless type. For example, the interface 8714 may include an antenna or a wired transceiver or a wireless transceiver.
[0074] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smartphone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.
[0075] If the electronic system 8710 is a device capable of performing wireless communications, the electronic system 8710 can be used in a communication system using code division multiple access (CDMA), global system for mobile communications (GSM), North American digital cellular (NADC), enhanced time division multiple access (E-TDMA), wideband code division multiple access (WCDMA), CDMA2000, long term evolution (LTE) or wireless broadband Internet (Wibro) technology.
[0076] The concept has been disclosed in conjunction with some of the embodiments described above. Those skilled in the art will appreciate that various modifications, additions, and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered restrictive, but rather illustrative. The scope of the concept is not limited to the foregoing description, but is defined by the appended claims, and all distinguishing features within the scope of equivalents should be interpreted as included in the concept.
[0077] CROSS-REFERENCE TO RELATED APPLICATIONS
[0078] This application claims priority from Korean Patent Application No. 10-2020-0114965, filed on September 8, 2020, which is hereby incorporated by reference in its entirety.
Claims
1. A stacked package, comprising: Package substrate; a lower stack, the lower stack comprising a lower die stacked on the package substrate to form a zigzag shape in a vertical direction; an upper stack including upper tube cores, the upper tube cores being sequentially offset in a first offset direction while providing a first upper side in a descending step shape; as well as a first passive component disposed on the package substrate and spaced apart from the first lower side of the lower stack, and disposed between a first portion of the package substrate and the first upper side, The first end of the uppermost tube core among the upper tube cores protrudes outward from the first lower side of the lower stack to vertically overlap with the first passive component.
2. The stacked package according to claim 1, wherein: The first end of the uppermost die among the upper dies protrudes farther than the first lower side of the lower stack in a horizontal direction.
3. The stacked package according to claim 1, further comprising an encapsulation layer, the encapsulation layer covering the package substrate and encapsulating the lower stacked layer and the upper stacked layer, wherein: The first passive component is disposed in a first space between a first outer side of the packaging layer and the first lower side and between the first upper side and a first portion of the packaging substrate.
4. The stacked package according to claim 1, wherein: The first passive device is disposed on the first portion of the package substrate to be spaced apart from the first end of the uppermost die.
5. The stacked package according to claim 1 further comprises a second passive component, wherein the second passive component is arranged on the package substrate and is spaced apart from the second lower side of the lower stack, the second lower side of the lower stack is opposite to the first lower side, and the second passive component is arranged between the second portion of the package substrate and the upper stack.
6. The stacked package according to claim 3 further comprises a second passive component, which is arranged in a second space between a second outer side of the packaging layer opposite to the first outer side and a second lower side of the lower stack and between a second portion of the packaging substrate and the upper stack.
7. The stacked package according to claim 6, in, The lowermost upper die of the upper die has a second end that protrudes farther in a horizontal direction than a second lower side of the lower stack opposite to the first lower side, and The second passive component is disposed on the second portion of the package substrate, such that an upper end of the second passive component is lower than the second end of the lowermost upper die.
8. The stacked package according to claim 7, wherein: The second passive component is disposed on the second portion of the package substrate such that a portion of the second passive component overlaps the second end of the lowermost upper die.
9. The stacked package according to claim 5, wherein: The second passive component has a thickness thinner than that of the first passive component.
10. The stacked package according to claim 5, wherein: The first passive component includes a capacitor component, and the second passive component includes a resistor component.
11. The stacked package according to claim 1, wherein: The upper stack further includes a second upper side in an ascending stepped shape located on an opposite side of the first upper side, and The upward stepped shape exposes the upper bonding pad of the upper die. 12 . The stacked package of claim 11 , further comprising a first bonding wire electrically connecting the upper bonding pad to a first bonding finger of the package substrate.
13. The stacked package according to claim 1, wherein: The lower stack comprises: a first sub-stack; a second sub-stack, the second sub-stack being vertically stacked on the first sub-stack; and A first adhesive layer bonds the second sub-laminate to the first sub-laminate.
14. The stacked package according to claim 13, wherein: The first sub-stack and the second sub-stack have the same shape and are stacked while being aligned with each other in the vertical direction.
15. The stacked package according to claim 14, wherein: The first sub-stack comprises: a first lower die comprising a first lower bond pad; and A second lower die is stacked on the first lower die with an offset in a second offset direction opposite to the first offset direction while exposing the first lower bonding pad, and includes a second lower bonding pad.
16. The stacked package according to claim 15, wherein: Each of the upper dies is offset in the first offset direction by the same distance as the second lower die is offset relative to the first lower die in the second offset direction. 17 . The stacked package of claim 15 , further comprising a second bonding wire electrically connecting the second lower bonding pad to the first lower bonding pad and to a second bonding finger of the package substrate.
18. The stacked package according to claim 17, wherein: A portion of each of the second bonding wires is bonded to the second lower bonding pad when dipped by the first adhesive layer.
19. The stacked package according to claim 18, wherein: The second sub-stack includes a third lower die positioned such that a portion of the third lower die overlaps the portion of the second bonding wire impregnated by the first adhesive layer.
20. The stacked package according to claim 17, wherein: The first passive component is disposed between the second bonding fingers of the package substrate.
21. The stacked package according to claim 16, wherein: The first sub-laminate includes a second adhesive layer that bonds the second lower die to the first lower die and has a thickness thinner than the first adhesive layer.
22. The stacked package according to claim 1, further comprising: a controller die, the controller die being disposed between the lower stack and the package substrate; as well as A support member is disposed around the controller die and supports the lower laminate.
23. A stacked package, comprising: Package substrate; a first passive component and a second passive component, wherein the first passive component and the second passive component are disposed on the package substrate to be spaced apart from each other; a lower stack disposed between the first passive component and the second passive component and comprising a lower die vertically stacked and providing a first lower side and a second lower side; as well as an upper stack, the upper stack comprising a lowermost die, an intermediate die, and an uppermost die, the lowermost die having a second end partially overlapping with the second passive component, the uppermost die having a first end partially overlapping with the first passive component, the lowermost die, the intermediate die, and the uppermost die being sequentially stacked in a stepped shape, The first end of the uppermost tube core protrudes outward from the first lower side of the lower stack to vertically overlap with the first passive component.
24. The stacked package according to claim 23, wherein: The second passive component has a thickness thinner than that of the first passive component.
25. The stacked package according to claim 23, wherein: The lower tube cores are formed in a zigzag shape in a vertical direction and are alternately stacked, so that the first lower side and the second lower side have at least one of a zigzag side and a staggered side.
Citation Information
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