Display device and manufacturing method thereof

Abstract

The application provides a display device and a manufacturing method thereof. In the display device, a first chip and a light emitting unit are located on two sides of a wiring layer, and the light emitting unit is encapsulated by a first encapsulation layer, and the first chip is encapsulated by a second encapsulation layer. The heat dissipation of the first chip and the heat dissipation of the light emitting unit do not conflict, the influence of the heat emitted by the first chip during operation on the working state of the light emitting unit is reduced, the working life of the light emitting unit is improved, and the display performance and service life of the display device are improved. Moreover, since the first chip and the light emitting unit are located on the two sides of the wiring layer, the first chip does not occupy the area of the film layer where the light emitting unit is located, that is, the pixel area of the display device is not affected, and the display performance of the display device is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display device and a method for manufacturing the same. Background Technology

[0002] Micro-LED, also known as Micro Light Emitting Diode, is a self-emissive device that has the potential to be applied to next-generation display device technology, following Liquid Crystal Display (LCD) and Active-Matrix Organic Light-Emitting Diode (AMOLED).

[0003] The core technology of Micro-LED display devices is to combine and arrange millions to tens of millions of LED chips, each tens of micrometers in size, to form the individual pixels required for the display device.

[0004] However, at present, there is no suitable TFT AM (Thin Film Transistor Active Matrix) driving circuit and driving method for Mini / Micro-LED, and the stability of TFT also seriously affects the display quality of Micro-LED display devices, and the PM (Passive Matrix) driving method cannot achieve high resolution. Summary of the Invention

[0005] In view of this, in order to solve the above problems, the present invention provides a display device and a method for manufacturing the same, the technical solution of which is as follows:

[0006] A display device, the display device comprising:

[0007] Transparent substrate;

[0008] Multiple light-emitting units located on one side of the transparent substrate;

[0009] Wiring layer located on the side of the light-emitting unit away from the transparent substrate;

[0010] At least one first chip located on the side of the wiring layer opposite to the transparent substrate;

[0011] A first encapsulation layer is located on the side of the transparent substrate near the light-emitting unit. The first encapsulation layer covers the light-emitting unit in a first direction and is used to encapsulate the light-emitting unit; the first direction is perpendicular to the plane of the transparent substrate.

[0012] A second encapsulation layer is located on the side of the wiring layer opposite to the transparent substrate. The second encapsulation layer covers the first chip in the first direction and is used to encapsulate the first chip.

[0013] The first chip is electrically connected to the light-emitting unit through the wiring layer and is used to control the working state of the light-emitting unit.

[0014] A method for manufacturing a display device, the method comprising:

[0015] Provide a transparent substrate;

[0016] A plurality of light-emitting units and a first encapsulation layer are disposed on one side of the transparent substrate. The first encapsulation layer is located on the side of the transparent substrate closer to the light-emitting units. The first encapsulation layer covers the light-emitting units in a first direction and is used to encapsulate the light-emitting units. The first direction is perpendicular to the plane of the transparent substrate.

[0017] A wiring layer is formed on the side of the light-emitting unit that is away from the transparent substrate;

[0018] At least one first chip is disposed on the side of the wiring layer opposite to the transparent substrate;

[0019] A second encapsulation layer is formed on the side of the wiring layer opposite to the transparent substrate. The second encapsulation layer covers the first chip in the first direction and is used to encapsulate the first chip.

[0020] The first chip is electrically connected to the light-emitting unit through the wiring layer and is used to control the working state of the light-emitting unit.

[0021] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0022] In the display device provided by the present invention, the first chip and the light-emitting unit are located on both sides of the wiring layer, and the light-emitting unit is encapsulated by the first encapsulation layer and the first chip is encapsulated by the second encapsulation layer. The heat dissipation of the first chip and the heat dissipation of the light-emitting unit will not conflict, thereby reducing the impact of the heat emitted by the first chip during operation on the working state of the light-emitting unit, thereby improving the working life of the light-emitting unit, and thus improving the display performance and service life of the display device.

[0023] Furthermore, since the first chip and the light-emitting unit are located on opposite sides of the wiring layer, the first chip will obviously not occupy the area of ​​the film layer where the light-emitting unit is located, which means it will not affect the pixel area of ​​the display device, thereby improving the display performance of the display device. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0025] Figure 1 A cross-sectional schematic diagram of a display device provided in an embodiment of the present invention;

[0026] Figure 2 This is a top view schematic diagram of a display device provided in an embodiment of the present invention;

[0027] Figure 3 A cross-sectional schematic diagram of another display device provided in an embodiment of the present invention;

[0028] Figure 4 A cross-sectional schematic diagram of another display device provided in an embodiment of the present invention;

[0029] Figure 5 This is a top view schematic diagram of another display device provided in an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of the structure of a light-emitting unit provided in an embodiment of the present invention;

[0031] Figure 7 A cross-sectional schematic diagram of another display device provided in an embodiment of the present invention;

[0032] Figure 8 A comparative schematic diagram of two light-emitting units provided in an embodiment of the present invention;

[0033] Figure 9 A cross-sectional schematic diagram of another display device provided in an embodiment of the present invention;

[0034] Figure 10 A cross-sectional schematic diagram of another display device provided in an embodiment of the present invention;

[0035] Figure 11 A cross-sectional schematic diagram of another display device provided in an embodiment of the present invention;

[0036] Figure 12 This is a top view schematic diagram of another display device provided in an embodiment of the present invention;

[0037] Figure 13 This is a schematic diagram illustrating the connection between a first chip and a light-emitting unit according to an embodiment of the present invention;

[0038] Figure 14This is a schematic diagram illustrating another connection between the first chip and the light-emitting unit provided in an embodiment of the present invention;

[0039] Figure 15 This is a schematic diagram illustrating another connection between the first chip and the light-emitting unit provided in an embodiment of the present invention;

[0040] Figure 16 A schematic flowchart illustrating a method for manufacturing a display device according to an embodiment of the present invention;

[0041] Figures 17-28 for Figure 16 The flowchart corresponding to the manufacturing method shown is illustrated. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] Based on the content described in the background art, during the invention process of this application, the inventors discovered that current Micro-LED display devices all use Micro-IC to drive one or several pixel units, so the micron-scale Micro-IC must be distributed between the pixel units.

[0044] If Micro-ICs are distributed between pixel units, they will occupy a portion of the pixel area, which will affect the display performance of the display device. Furthermore, the high heat dissipation temperature of Micro-ICs during operation will also affect the working status of adjacent Micro-LEDs, ultimately affecting the display performance and lifespan of the display device.

[0045] Based on this, this application provides a display device in which a first chip and a light-emitting unit are located on opposite sides of a wiring layer. The light-emitting unit is encapsulated by a first encapsulation layer, and the first chip is encapsulated by a second encapsulation layer. The heat dissipation of the first chip and the light-emitting unit does not conflict, reducing the impact of heat emitted by the first chip during operation on the working state of the light-emitting unit, thereby improving the lifespan of the light-emitting unit and consequently improving the display performance and lifespan of the display device. Furthermore, since the first chip and the light-emitting unit are located on opposite sides of the wiring layer, the first chip obviously does not occupy the area of ​​the film layer where the light-emitting unit is located, meaning it does not affect the pixel area of ​​the display device, thus improving the display performance of the display device.

[0046] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] refer to Figure 1 , Figure 1 This is a cross-sectional schematic diagram of a display device provided in an embodiment of the present invention.

[0048] The display device includes:

[0049] Transparent substrate 11; a plurality of light-emitting units 12 located on one side of the transparent substrate 11.

[0050] Wiring layer 13 located on the side of the light-emitting unit 12 away from the transparent substrate 11.

[0051] At least one first chip 14 is located on the side of the wiring layer 13 opposite to the transparent substrate 11.

[0052] A first encapsulation layer 15 is located on the side of the transparent substrate 11 near the light-emitting unit 12. The first encapsulation layer 15 covers the light-emitting unit 12 in a first direction X and is used to encapsulate the light-emitting unit 12. The first direction X is perpendicular to the plane of the transparent substrate 11.

[0053] A second encapsulation layer 16 is located on the side of the wiring layer 13 opposite to the transparent substrate 11. The second encapsulation layer 16 covers the first chip 14 in the first direction X and is used to encapsulate the first chip 14.

[0054] The first chip 14 is electrically connected to the light-emitting unit 12 through the wiring layer 13, and is used to control the working state of the light-emitting unit 12.

[0055] In this embodiment, one side of the transparent substrate 11 is the light-emitting side of the display device, that is, the transparent substrate 11 can also be understood as the cover plate of the display device, such as the glass cover plate of the display device.

[0056] For details, please refer to Figure 2 , Figure 2 This is a top view schematic diagram of a display device provided in an embodiment of the present invention, as shown below. Figure 2 As shown, multiple light-emitting units 12 are located on one side of the transparent substrate 11. The light-emitting units 12 are combined and arranged to form the pixels required by the display device based on the actual application of the display panel.

[0057] Optionally, multiple light-emitting units 12 are arranged in an array, with the spacing between two adjacent light-emitting units 12 being equal in the row direction of the array arrangement, and / or the spacing between two adjacent light-emitting units 12 being equal in the column direction of the array arrangement, thereby improving the uniformity of the arrangement of the light-emitting units 12 and indirectly improving the display uniformity of each display area of ​​the display device.

[0058] Furthermore, such as Figure 1 As shown, in the display device, the first chip 14 and the light-emitting unit 12 are located on both sides of the wiring layer 13, and the light-emitting unit 12 is encapsulated by the first encapsulation layer 15 and the first chip 14 is encapsulated by the second encapsulation layer 16. The heat emitted by the first chip 14 during operation has a very low impact on the working state of the light-emitting unit 12. That is, the heat dissipation of the first chip 14 and the heat dissipation of the light-emitting unit 12 will not conflict, thereby improving the working life of the light-emitting unit 12, and thus improving the display performance and service life of the display device.

[0059] Furthermore, since the first chip 14 and the light-emitting unit 12 are located on opposite sides of the wiring layer 13, the first chip 14 will obviously not occupy the area of ​​the film layer where the light-emitting unit 12 is located, and the combination and arrangement of the light-emitting units 12 will not be restricted. In other words, it will not affect the pixel area of ​​the display device, thereby improving the display performance of the display device.

[0060] It should be noted that, since the heat emitted by the first chip 14 during operation is different from the heat emitted by the light-emitting unit 12 during operation, the materials of the first encapsulation layer 15 and the second encapsulation layer 16 can also be different to meet different heat dissipation requirements.

[0061] Optionally, the coefficient of thermal expansion of the first encapsulation layer 15 material is in the range of 150-250 ppm / K;

[0062] Optionally, the coefficient of thermal expansion of the second encapsulation layer 16 is greater than that of the first encapsulation layer 15; or the coefficient of thermal expansion of the second encapsulation layer 16 is less than that of the first encapsulation layer 15.

[0063] Specifically, the first chip 14 and the light-emitting unit 12 are electrically connected through the wiring in the wiring layer 13, so that the first chip 14 can control the working state of the light-emitting unit 12.

[0064] It should be noted that, Figure 1 The routing structure in the wiring layer is not shown in the figure. Examples will be provided step by step in the following embodiments of this application.

[0065] Furthermore, the various cases of the first encapsulation layer 15 will be explained separately below:

[0066] The first distribution form of the first encapsulation layer 15:

[0067] refer to Figure 3 , Figure 3 A cross-sectional schematic diagram of another display device provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the first encapsulation layer 15 is located on the side of the transparent substrate 11 close to the light-emitting unit 12, but no encapsulation film layer is provided between the light-emitting surface of the light-emitting unit 12 and the transparent substrate 11.

[0068] The second distribution form of the first encapsulation layer 15:

[0069] refer to Figure 4 , Figure 4 A cross-sectional schematic diagram of another display device provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the first encapsulation layer 15 includes a first sub-encapsulation layer 151 and a second sub-encapsulation layer 152. The first sub-encapsulation layer 151 covers the light-emitting unit 12 and fills the gap between the light-emitting units 12. The second sub-encapsulation layer 152 is located between the light-emitting surface of the light-emitting unit 12 and the transparent substrate 11.

[0070] The materials of the first sub-encapsulation layer 151 and the second sub-encapsulation layer 152 can be different; when the materials of the first sub-encapsulation layer 151 and the second sub-encapsulation layer 152 are the same, that is... Figure 1 The first encapsulation layer 15 is shown.

[0071] It should be noted that the light-emitting surface of the light-emitting unit 12 refers to the surface of the light-emitting unit 12 facing the transparent substrate 11.

[0072] It should be noted that the presence of the first encapsulation layer 15 can also improve the positional stability of the light-emitting unit 12, preventing the light-emitting unit 12 from tilting or shifting, thereby improving the display performance of the display panel.

[0073] Optionally, in another embodiment of this application, reference is made to... Figure 5 , Figure 5 This is a top view schematic diagram of another display device provided in an embodiment of the present invention.

[0074] The plurality of light-emitting units 12 constitute at least one light-emitting unit array.

[0075] The number of light-emitting units 12 in the row direction of the light-emitting unit array is M, where M≥2.

[0076] The number of light-emitting units 12 in the column direction of the light-emitting unit array is N, where N≥2.

[0077] One of the first chips 14 controls the operating state of all the light-emitting units 12 in one of the light-emitting unit arrays.

[0078] It should be noted that, Figure 5 The following example illustrates the use of an array of light-emitting units with M=3 and N=3.

[0079] In this embodiment, the first chip 14 differs from conventional Micro-ICs, which are micrometer-scale Micro-ICs that must be distributed between pixel units and can only drive one or a few light-emitting units.

[0080] In this application, the first chip 14 has a minimum size of 1mm × 1mm, which is a millimeter-scale chip structure capable of driving an M*N array of light-emitting units. The first chip 14 and the light-emitting units 12 are located on opposite sides of the wiring layer 13. Since the first chip 14 and the light-emitting units 12 are located on opposite sides of the wiring layer 13, the first chip 14 obviously does not occupy the area of ​​the film layer where the light-emitting units 12 are located, meaning it does not affect the pixel area of ​​the display device, thereby improving the display performance of the display device.

[0081] For example, a display device with a resolution of 480*320 can be implemented by using 6*4 PMLED driver chips that support 80*80 resolution, where M=80 and N=80.

[0082] Optionally, in another embodiment of this application, reference is made to... Figure 6 , Figure 6 This is a schematic diagram of the structure of a light-emitting unit provided in an embodiment of the present invention. The light-emitting unit 12 includes: a first electrode 121 and a second electrode 122.

[0083] Specifically, such as Figure 6 As shown, the light-emitting unit 12 further includes: a substrate 123; an N-type semiconductor layer 124, an MQW (Multiple Quantum Well) layer 125, and a P-type semiconductor layer 126 sequentially located on the substrate 123.

[0084] The first electrode 121 is located on the N-type semiconductor layer 124, and the second electrode 122 is located on the P-type semiconductor layer 126. That is, in this embodiment, the first electrode 121 is the N-electrode of the light-emitting unit 12, and the second electrode 122 is the P-electrode of the light-emitting unit 12.

[0085] It should be noted that the light-emitting unit is a Micro-LED light-emitting unit or a Mini-LED light-emitting unit.

[0086] It should be noted that the material of the substrate 123 includes, but is not limited to, sapphire, aluminum nitride, silicon nitride, gallium nitride single crystal, etc.

[0087] The N-type semiconductor layer 124 includes, but is not limited to, an N-type gallium nitride semiconductor layer, and the P-type semiconductor layer 126 includes, but is not limited to, a P-type gallium nitride semiconductor layer.

[0088] refer to Figure 7 , Figure 7 This is a cross-sectional schematic diagram of another display device provided in an embodiment of the present invention.

[0089] The first encapsulation layer 15 covers the light-emitting unit 12.

[0090] The first encapsulation layer 15 includes multiple sets of first grooves 153 and second grooves 154. The first grooves 153 and the second grooves 154 are located on the surface of the first encapsulation layer 15 away from the transparent substrate 11. Each set of the first grooves 153 and the second grooves 154 corresponds to one light-emitting unit 12.

[0091] The first groove 153 exposes the first electrode 121.

[0092] The second groove 154 exposes the second electrode 122.

[0093] In this embodiment, multiple sets of first grooves 153 and second grooves 154 are formed by improving the first encapsulation layer 15 to expose the first electrode 121 and the second electrode 122 in the light-emitting unit 12, so that the first electrode 121 and the second electrode 122 in the light-emitting unit 12 are electrically connected to the first chip 14 through the wiring in the wiring layer 13.

[0094] Optionally, in another embodiment of this application, reference is made to... Figure 8 , Figure 8 This is a comparative schematic diagram of two light-emitting units provided in an embodiment of the present invention.

[0095] The light-emitting unit 12 includes a first light-emitting unit 12A and a second light-emitting unit 12B.

[0096] In the first direction X, the maximum height H1 of the first light-emitting unit 12A is greater than the maximum height H2 of the second light-emitting unit 12B.

[0097] refer to Figure 9 , Figure 9 This is a cross-sectional schematic diagram of another display device provided in an embodiment of the present invention.

[0098] In the first direction X, the depth H3 of the second groove 154 corresponding to the first light-emitting unit 12A is less than the depth H4 of the second groove 154 corresponding to the second light-emitting unit 12B.

[0099] And / or, in the first direction X, the depth H5 of the first groove 153 corresponding to the first light-emitting unit 12A is less than the depth H6 of the first groove 153 corresponding to the second light-emitting unit 12B.

[0100] In this embodiment, the maximum height H1 of the first light-emitting unit 12A refers to the distance between the surface of the second electrode 122 in the first light-emitting unit 12A away from the substrate 123 and the surface of the substrate 123 away from the second electrode 122, and the maximum height H2 of the second light-emitting unit 12B refers to the distance between the surface of the second electrode 122 in the second light-emitting unit 12B away from the substrate 123 and the surface of the substrate 123 away from the second electrode 122.

[0101] Since the surface of the first encapsulation layer 15 facing away from the transparent substrate 11 is a planarized surface, and the substrates 123 of the first light-emitting unit 12A and the second light-emitting unit 12B are both on the same plane, when the maximum height H1 of the first light-emitting unit 12A is greater than the maximum height H2 of the second light-emitting unit 12B, the depth H3 of the second groove 154 corresponding to the first light-emitting unit 12A in the first encapsulation layer 15 must be less than the depth H4 of the second groove 153 corresponding to the second light-emitting unit 12B.

[0102] Furthermore, when the maximum height H1 of the first light-emitting unit 12A is greater than the maximum height H2 of the second light-emitting unit 12B, the distance between the first electrode 121 and the substrate 123 in the first light-emitting unit 12A will normally be greater than the distance between the first electrode 121 and the substrate 123 in the second light-emitting unit 12B. Therefore, the depth H5 of the first groove 153 of the first light-emitting unit 12A will be less than the depth H6 of the first groove 153 of the second light-emitting unit 12B.

[0103] During the fabrication process of the light-emitting unit 12, the thickness of the first electrode 121 is not a fixed value, but a range of thickness values. Therefore, there may be cases where the maximum height H1 of the first light-emitting unit 12A is greater than the maximum height H2 of the second light-emitting unit 12B. In this case, the distance between the first electrode 121 and the substrate 123 in the first light-emitting unit 12A is less than the distance between the first electrode 121 and the substrate 123 in the second light-emitting unit 12B. Consequently, the depth of the first groove 153 in the first light-emitting unit 12A will be greater than the depth of the first groove 153 in the second light-emitting unit 12B.

[0104] Optionally, the first light-emitting unit 12A emits light of a first color, the wavelength of which is λ1.

[0105] The second light-emitting unit 12B emits a second color light with a wavelength of λ2.

[0106] Where λ1>λ2.

[0107] Specifically, the first light-emitting unit 12A can be a light-emitting unit for emitting red light, and the second light-emitting unit 12B can be a light-emitting unit for emitting green light.

[0108] Optionally, the light-emitting unit 12 may also include a third light-emitting unit.

[0109] In the first direction, the maximum height H1 of the first light-emitting unit 12A is greater than the maximum height H2 of the second light-emitting unit 12B, which is greater than the maximum height of the third light-emitting unit.

[0110] In the first direction, the depth H5 of the first groove 153 corresponding to the first light-emitting unit 12A is less than the depth H6 of the first groove 153 corresponding to the second light-emitting unit 12B, which is less than the depth of the first groove corresponding to the third light-emitting unit.

[0111] Optionally, the first light-emitting unit 12A emits light of a first color, the wavelength of which is λ1.

[0112] The second light-emitting unit 12B emits a second color light with a wavelength of λ2.

[0113] The third light-emitting unit emits a third color light with a wavelength of λ3.

[0114] Among them, λ1>λ2>λ3.

[0115] Specifically, the first light-emitting unit 12A can be a light-emitting unit for emitting red light, the second light-emitting unit 12B can be a light-emitting unit for emitting green light, and the third light-emitting unit can be a light-emitting unit for emitting blue light.

[0116] Specifically, in the display device, each full-color pixel unit can be composed of multiple light-emitting units 12. Taking the most basic pixel unit as an example, in order to achieve full-color display of the display device, it can include at least one light-emitting unit that can emit red light, at least one light-emitting unit that can emit green light, and at least one light-emitting unit that can emit blue light.

[0117] Optional, such as Figure 6 As shown, regardless of whether it is the first light-emitting unit 12A, the second light-emitting unit 12B, or the third light-emitting unit, the distance between the corresponding first electrode 121 and the substrate 123 is smaller than the distance between the second electrode 122 and the substrate 123.

[0118] Therefore, in a set of the first groove 153 and the second groove 154,

[0119] In the first direction, the depth of the first groove 153 is greater than the depth of the second groove 154.

[0120] In other words, in a set of first grooves 153 and second grooves 154 corresponding to any light-emitting unit 12, the depth of the first groove 153 is always greater than the depth of the second groove 154.

[0121] Optionally, in another embodiment of this application, reference is made to... Figure 10 , Figure 10 This is a cross-sectional schematic diagram of another display device provided in an embodiment of the present invention.

[0122] The display device includes:

[0123] The first external electrode 17 is electrically connected to the first electrode 121 through the first groove 153;

[0124] The second external electrode 18 is electrically connected to the second electrode 122 through the second groove 154.

[0125] In this embodiment, if the first electrode 121 and the second electrode 122 in the light-emitting unit 12 are directly electrically connected to the wiring in the wiring layer 13, the electrical connection may be unstable due to the small size of the first electrode 121 and the second electrode 122 in the light-emitting unit 12.

[0126] Therefore, in order to improve the electrical connection stability between the light-emitting unit 12 and the wiring layer 13, the first electrode 121 and the second electrode 122, which are smaller in size, need to be led out to the first external electrode 17 and the second external electrode 18, which are larger in size, so as to improve the display stability of the display device.

[0127] Optionally, in another embodiment of this application, reference is made to... Figure 11 , Figure 11 This is a cross-sectional schematic diagram of another display device provided in an embodiment of the present invention.

[0128] The display device includes:

[0129] Multiple sets of first pads 19 and second pads 20 are located between the wiring layer 13 and the first chip 14.

[0130] The wiring layer 13 has a first via group 131 and a second via group 132. The first via group 131 includes a plurality of first vias, and the second via group 132 includes a plurality of second vias.

[0131] The first pad 19 is electrically connected to the first external electrode 17 through the first through-hole group 131.

[0132] The second pad 20 is electrically connected to the second external electrode 18 through the second through-hole group 132.

[0133] In this embodiment, since the minimum size of the first chip 14 in this application is 1mm×1mm, which is a chip structure on the millimeter scale, it can drive an M*N light-emitting unit array. Its pin size is relatively large. If the pins of the first chip 14 are directly electrically connected to the traces in the wiring layer 13, it may cause the electrical connection to be unstable.

[0134] Therefore, in this application, multiple sets of first pads 19 and second pads 20 are provided on the side of the wiring layer 13 away from the transparent substrate 11, so that the first pads 19 and second pads 20 are connected to the corresponding traces in the wiring layer 13, and then the first pads 19 and second pads 20 are connected to the corresponding first chip 14, thereby improving the electrical connection stability between the first chip 14 and the wiring layer 13.

[0135] Furthermore, in order to achieve electrical connection between the first chip 14 and the light-emitting unit 12, a first via group 131 and a second via group 132 are provided in the wiring layer. Both the first via group 131 and the second via group 132 are provided with traces so that the first pad 19 is electrically connected to the first external electrode 17 through the traces in the first via group 131, and the second pad 20 is electrically connected to the second external electrode 18 through the traces in the second via group 132.

[0136] It should be noted that in the first through-hole group 131, two through-holes that penetrate two adjacent film layers and whose orthogonal projections on the transparent substrate 11 overlap constitute a first through-hole.

[0137] In the second via group 132, two vias that penetrate two adjacent film layers and whose orthogonal projections on the transparent substrate 11 overlap constitute a second via.

[0138] Optionally, in another embodiment of this application, such as Figure 11 As shown, the orthographic projections of the plurality of first through holes in the first through hole group 131 onto the transparent substrate 11 do not overlap.

[0139] And / or, the orthographic projections of the plurality of second through holes in the second through hole group 132 onto the transparent substrate 11 do not overlap.

[0140] In this embodiment, if two through holes are made by a sleeve design during the fabrication of the through hole, the formation of the second through hole will affect the completed first through hole. For example, it may cause the opening area of ​​the first through hole to be uneven, affecting the stability of the wiring. For example, the wiring at the opening area of ​​the first through hole may be broken. In addition, the organic layer at the sleeve position is thicker, which will increase the difficulty of drilling.

[0141] Therefore, in this application, the orthographic projections of the plurality of first through holes in the first through hole group 131 on the transparent substrate 11 do not overlap, and / or the orthographic projections of the plurality of second through holes in the second through hole group 132 on the transparent substrate 11 do not overlap, thereby avoiding the use of through hole design, thereby improving the electrical connection between the first chip 14 and the light-emitting unit 12 and improving the display performance of the display device.

[0142] It should be noted that, in the first through-hole group 131 of this application embodiment, the arrangement of the multiple first through holes can also be such that the orthographic projections of two adjacent first through holes on the transparent substrate 11 do not overlap. Taking three first through holes as an example, the orthographic projections of the first and second first through holes on the transparent substrate 11 do not overlap, the orthographic projections of the second and third first through holes on the transparent substrate 11 do not overlap, while the orthographic projections of the first and third first through holes on the transparent substrate 11 overlap or completely overlap.

[0143] It should be noted that, in the second through-hole group 132 of this application embodiment, the arrangement of multiple second through holes can also be such that the orthographic projections of two adjacent second through holes on the transparent substrate 11 do not overlap. Taking three second through holes as an example, the orthographic projections of the first second through hole and the second second through hole on the transparent substrate 11 do not overlap, the orthographic projections of the second second through hole and the third second through hole on the transparent substrate 11 do not overlap, while the orthographic projections of the first second through hole and the third second through hole on the transparent substrate 11 overlap or completely overlap.

[0144] Optionally, in another embodiment of this application, the orthographic projections of a plurality of the first through holes in the first through hole group 131 onto the transparent substrate 11 are arranged along a second direction.

[0145] And / or, the orthogonal projections of a plurality of the second through holes in the second through hole group 132 onto the transparent substrate 11 are arranged along the second direction.

[0146] The second direction is parallel to the plane where the transparent substrate 11 is located.

[0147] In this embodiment, when the multiple first through holes in the first through hole group 131 are not designed with through holes, the orthogonal projections of the multiple first through holes on the transparent substrate 11 are arranged along a certain direction to form an inclined wiring pattern, so as to reduce the space occupied by the wiring in the wiring layer 13, and at least provide wiring area for other wiring, so that the display device can achieve more functions with effective wiring space.

[0148] Similarly, in the case of multiple second through holes in the second through hole group 132 without a hole sleeve design, the orthogonal projection of multiple second through holes on the transparent substrate 11 is arranged along a certain direction to form an inclined routing method, so as to reduce the space occupied by the routing in the wiring layer 13.

[0149] It should be noted that, in the embodiments of this application, the arrangement direction of the orthographic projection of the plurality of first through holes in the first through hole group 131 onto the transparent substrate 11 may be different from the arrangement direction of the orthographic projection of the plurality of second through holes in the second through hole group 132 onto the transparent substrate 11.

[0150] Optionally, in another embodiment of this application, as shown below... Figure 11 As shown, the wiring layer 13 includes:

[0151] A first wiring layer 13A is located on the side of the first encapsulation layer 15 away from the transparent substrate 11. The first wiring layer 13A has a plurality of third through holes A1, and one third through hole A1 corresponds to one first external electrode 17.

[0152] The display device further includes:

[0153] The third trace B1 is located on the side of the first wiring layer 13A opposite to the transparent substrate 11, and the third trace B1 is electrically connected to the first external electrode 17 through the third through hole A1.

[0154] Among them, the third through hole A1 belongs to the first through hole group 131.

[0155] like Figure 11 As shown, the wiring layer 13 includes:

[0156] The second wiring layer 13B is located on the side of the first wiring layer 13A that is opposite to the transparent substrate 11.

[0157] The first wiring layer 13A has a plurality of fourth vias A2, and one of the fourth vias A2 corresponds to one of the second external electrodes 18.

[0158] The second wiring layer 13B has a plurality of fifth vias A3.

[0159] The display device further includes:

[0160] The fourth trace B2 is located on the side of the second wiring layer 13B opposite to the transparent substrate 11. The fourth trace B2 is electrically connected to the second external electrode 18 through the fifth through hole A3 and the fourth through hole A2.

[0161] Among them, the fourth through hole A2 and the fifth through hole A3 belong to the second through hole group 132, and the orthographic projections of the fourth through hole A2 and the fifth through hole A3 on the transparent substrate 11 do not overlap.

[0162] like Figure 11 As shown, the wiring layer 13 includes:

[0163] The third wiring layer 13C is located on the side of the second wiring layer 13B that is opposite to the transparent substrate 11.

[0164] The second wiring layer 13B has a plurality of sixth through holes A4, and the third wiring layer 13C has a plurality of seventh through holes A5 and a plurality of eighth through holes A6;

[0165] The display device further includes:

[0166] Multiple sets of first oblique wirings B3 and second oblique wirings B4 are located on the side of the third wiring layer 13C opposite to the transparent substrate 11.

[0167] The first oblique wiring B3 is electrically connected to the third wiring B1 through the seventh through hole A5 and the sixth through hole A4.

[0168] The second oblique wiring B4 is electrically connected to the fourth wiring B2 through the eighth through hole A6.

[0169] Among them, the third through hole A1, the sixth through hole A4 and the seventh through hole A5 belong to the first through hole group 131, and the fourth through hole A2, the fifth through hole A3 and the eighth through hole A6 belong to the second through hole group 132. The orthographic projections of the third through hole A1, the sixth through hole A4 and the seventh through hole A5 on the transparent substrate 11 do not overlap and are arranged along a certain direction; the orthographic projections of the fourth through hole A2, the fifth through hole A3 and the eighth through hole A6 on the transparent substrate 11 do not overlap and are arranged along a certain direction.

[0170] like Figure 12 As shown, the wiring layer 13 includes:

[0171] The fourth wiring layer 13D is located on the side of the third wiring layer 13C that is opposite to the transparent substrate 11.

[0172] The fourth wiring layer 13D has multiple ninth vias A7 and multiple tenth vias A8.

[0173] The first pad 19 is electrically connected to the first oblique wiring B3 through the ninth through hole A7; the second pad 20 is electrically connected to the second oblique wiring B4 through the tenth through hole A8.

[0174] Among them, the third through hole A1, the sixth through hole A4, the seventh through hole A5 and the ninth through hole A7 belong to the first through hole group 131, and the fourth through hole A2, the fifth through hole A3, the eighth through hole A6 and the tenth through hole A8 belong to the second through hole group 132. The orthographic projections of the third through hole A1, the sixth through hole A4, the seventh through hole A5 and the ninth through hole A7 on the transparent substrate 11 do not overlap and are arranged along a certain direction; the orthographic projections of the fourth through hole A2, the fifth through hole A3, the eighth through hole A6 and the tenth through hole A8 on the transparent substrate 11 do not overlap and are arranged along a certain direction.

[0175] Therefore, it can be seen that the first pad 19 and the first external electrode 17 are electrically connected through the first via group 131 in the wiring layer 13, that is, the first pad 20 is electrically connected to the first electrode 121 of the light-emitting unit 12; the second pad 20 and the second external electrode 18 are electrically connected through the second via group 132 in the wiring layer 13, that is, the second pad 20 is electrically connected to the second electrode 122 of the light-emitting unit 12.

[0176] The first chip 14 and the light-emitting unit 12 are electrically connected through the first pad 19 and the second pad 20, so that the first chip 14 can control the working state of the light-emitting unit 12.

[0177] Optionally, in another embodiment of this application, reference is made to... Figure 12 , Figure 12 This is a top view schematic diagram of another display device provided in an embodiment of the present invention.

[0178] The display device further includes: a plurality of functional chips 20, wherein the plurality of functional chips 20 are located on the side of the wiring layer 13 opposite to the transparent substrate 11;

[0179] The multiple functional chips 20 are interconnected and all are interconnected with the first chip 14.

[0180] In other words, multiple functional chips 20 are located on the same side as the first chip 14. The minimum size of the functional chip 20 is 1mm×1mm. This means that the multiple functional chips 20 and the first chip 14 are all chip structures on the millimeter scale. The functional chip 20 can be a main control chip, power chip, touch chip, and data communication chip for the display device.

[0181] It should be noted that, Figure 12 The illustration uses only one functional chip 20 as an example, and the layout of the functional chip 20 and the first chip 14 is not limited in this embodiment.

[0182] It should be noted that the intersection of the third trace B1 and the fourth trace B2 is the location of the light-emitting unit 12. The third trace B1 is electrically connected to the first electrode 121 of the light-emitting unit 12, and the fourth trace B2 is electrically connected to the second electrode 122 of the light-emitting unit 12.

[0183] The display device in this application does not have an array substrate, i.e., it does not have a TFT (Thin Film Transistor) design. When cutting small sheets, only the corrosion prevention of the metal wire needs to be considered. However, in ordinary array substrate-based display devices, the high temperature and humidity environment during TFT substrate cutting can easily cause TFT circuit failure, especially the surrounding VSR circuit. Therefore, the display device of this application has higher reliability when manufacturing frameless splicing display devices.

[0184] And, as Figure 12 The display device shown can be used as one of the video wall blocks in a large video wall system. If different screen sizes are needed, simply... Figure 13 The display devices shown can be assembled together.

[0185] Optionally, in another embodiment of this application, reference is made to... Figure 13 , Figure 14 This is a schematic diagram illustrating the connection between a first chip and a light-emitting unit according to an embodiment of the present invention; see reference. Figure 14 , Figure 13 This is a schematic diagram showing another connection between the first chip and the light-emitting unit provided in an embodiment of the present invention.

[0186] Specifically, the first chip 20 includes a first pad group 201 and a second pad group 202. The first pad group 201 includes a plurality of third pads 2011 arranged along a third direction, and the second pad group 202 includes a plurality of fourth pads 2021 arranged along a fourth direction. The third and fourth directions are parallel to the plane where the first chip is located, and the third and fourth directions intersect.

[0187] The third pad 2011 is electrically connected to the first electrode of the light-emitting unit in the light-emitting unit array.

[0188] The fourth pad 2021 is electrically connected to the second electrode of the light-emitting unit in the light-emitting unit array.

[0189] In this embodiment, an example is given with the third and fourth directions perpendicular to each other.

[0190] It should be noted that, as Figure 14As shown, the first pad group 201 in the first row includes the first pad in the first row, which is electrically connected to the first electrode 121 of the light-emitting unit as the third pad 2011; the second pad group 202 in the first column does not include the first pad in the first column.

[0191] It should be noted that, as Figure 13 As shown, the first pad group 201 in the first row does not include the first pad in the first row; the second pad group 202 in the first column includes the first pad in the first column, and is electrically connected to the second electrode 122 of the light-emitting unit as the fourth pad 2021.

[0192] Specifically, such as Figure 15 As shown, the multiple third pads 2011 in the first row are electrically connected to the first electrode 121 of the light-emitting unit, and the multiple fourth pads 2021 in the first column are electrically connected to the second electrode 122 of the light-emitting unit.

[0193] In this embodiment, the pad that overlaps with the first row and the first column is used as the third pad 2011 or as the fourth pad 2021. The overlapping pad is used as the third pad 2011 as an example in this application.

[0194] The other pads of the first chip 20 communicate with other functional chips.

[0195] Optionally, a plurality of third pads 2011 in the m-th row of the first chip 20 are electrically connected to the first electrode 121 of the light-emitting unit 12, and a plurality of fourth pads 2021 in the n-th column are electrically connected to the second electrode 122 of the light-emitting unit 12, wherein n≠1 and m≠1.

[0196] Optional, see reference Figure 15 , Figure 16 This is a schematic diagram showing another connection between the first chip and the light-emitting unit provided in an embodiment of the present invention.

[0197] In the light-emitting unit array, the first electrodes 121 of a row of light-emitting units 12 are connected in sequence, and the second electrodes 122 of a column of light-emitting units 12 are connected in sequence.

[0198] The display panel also includes:

[0199] Multiple first routing lines M1 extend in the column direction and are arranged sequentially along the row direction.

[0200] Multiple second routing lines M2 extend in the row direction and are arranged sequentially along the column direction.

[0201] One of the first traces M1 is connected to the first electrode 121 of the row of light-emitting units 12.

[0202] One of the second traces M2 is connected to the second electrode 122 of one of the light-emitting units 12.

[0203] Multiple first traces M1 are sequentially connected to multiple third pads 2011 in a row of third pads 2011.

[0204] Multiple second traces M2 are sequentially connected to multiple fourth pads 2021 in a column of fourth pads 2021.

[0205] That is, the first trace M1 is connected to the first third pad 2011 in the third pad group 201 in a row, and the first second trace M2 is connected to the first fourth pad 2021 in the fourth pad group 202 in a column.

[0206] In other words, this application simplifies the wiring difficulty of the display device by reasonably optimizing the wiring connection between the first chip 20 and the light-emitting unit 12.

[0207] Optionally, based on all the embodiments described above, another embodiment of this application also provides a method for manufacturing a display device, see reference. Figure 16 , Figure 17 This is a schematic flowchart illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0208] The manufacturing method includes:

[0209] S101: Provide a transparent substrate.

[0210] S102: A plurality of light-emitting units and a first encapsulation layer are disposed on one side of the transparent substrate. The first encapsulation layer is located on the side of the transparent substrate close to the light-emitting units. The first encapsulation layer covers the light-emitting units in a first direction and is used to encapsulate the light-emitting units. The first direction is perpendicular to the plane of the transparent substrate.

[0211] S103: A wiring layer is formed on the side of the light-emitting unit away from the transparent substrate.

[0212] S104: At least one first chip is disposed on the side of the wiring layer opposite to the transparent substrate.

[0213] S105: A second encapsulation layer is formed on the side of the wiring layer opposite to the transparent substrate. The second encapsulation layer covers the first chip in the first direction and is used to encapsulate the first chip. The first chip is electrically connected to the light-emitting unit through the wiring layer and is used to control the working state of the light-emitting unit.

[0214] Specifically, step S102, which involves setting multiple light-emitting units and a first encapsulation layer on one side of the transparent substrate, includes:

[0215] like Figure 18 As shown, a first carrier substrate 21 is provided, on which a plurality of light-emitting units 12 are disposed. Each light-emitting unit 12 includes a first electrode 121 and a second electrode 122. The light-emitting unit 12 includes at least a light-emitting unit for emitting red light, a light-emitting unit for emitting green light, and a light-emitting unit for emitting blue light, to achieve full-color display of the display device.

[0216] like Figure 19 As shown, an adhesive layer is provided, the adhesive layer includes a plurality of independent adhesive units 22, the first electrode 121 and the second electrode 122 respectively correspond to one adhesive unit 22; the surfaces of the plurality of adhesive units 22 facing away from the first carrier substrate 21 are located on the same horizontal plane.

[0217] like Figure 20 As shown, a second carrier substrate 23 is provided; the light-emitting unit 12 is transferred to the second carrier substrate 23 and the first carrier substrate 21 is removed, wherein the bonding unit 22 is in contact with the second carrier substrate 23.

[0218] The adhesive layer can be an adhesive layer of photoresist material. In addition to bonding and fixing with the second carrier substrate 23, it is also used to achieve the planarization of the first electrode 121 and the second electrode 122 in the light-emitting unit 12, and to achieve the overall planarization of light-emitting units 12 at different heights, so as to ensure that the substrates 123 of each light-emitting unit 12 are on the same horizontal plane after the light-emitting unit 12 is transferred to the second carrier substrate 23.

[0219] Furthermore, such as Figure 21 As shown, the first encapsulation layer 15 is formed on the second carrier substrate 23.

[0220] like Figure 22 As shown, a transparent substrate 11 is provided, which is disposed on the side of the first encapsulation layer 15 away from the second carrier substrate 23.

[0221] like Figure 23As shown, after removing the second carrier substrate 23 and the adhesive layer, the first encapsulation layer 15 includes: multiple sets of first grooves 153 and second grooves 154. The first grooves 153 and the second grooves 154 are located on the surface of the first encapsulation layer 15 near the wiring layer 13. Each set of first grooves 153 and second grooves 154 corresponds to one light-emitting unit 12. The first groove 153 exposes the first electrode 121, and the second groove 154 exposes the second electrode 122.

[0222] In this process, after the individual adhesive units 22 in the adhesive layer are removed, the first encapsulation layer 15 can directly have multiple sets of first grooves 153 and second grooves 154, and the first grooves 153 are self-aligned with the first electrode 121, and the second grooves 154 are self-aligned with the second electrode 122.

[0223] In other words, the adhesive layer plays at least three roles in this application:

[0224] Firstly, during the transfer of the light-emitting unit 12, it plays a role in bonding and fixing it to the second carrier substrate 23, preventing the light-emitting unit 12 from tilting or shifting after transfer, thereby improving the positional stability of the light-emitting unit 12.

[0225] Secondly, it plays a role in planarization, ensuring that after the light-emitting unit 12 is transferred, its substrate 123, that is, the light-emitting surface, is on the same horizontal plane.

[0226] Third, the self-alignment of the first electrode 121 with the first groove 153 and the self-alignment of the second electrode 122 with the second groove 154 do not require additional etching of the first encapsulation layer 15 to form the first groove 153 and the second groove 154.

[0227] Furthermore, such as Figure 24 As shown, the first external electrode 17 is led out through the first groove 153, and the second external electrode 18 is led out through the second groove 154.

[0228] Furthermore, a wiring layer 13 is formed on the side of the light-emitting unit 12 facing away from the transparent substrate 11, specifically:

[0229] like Figure 25 As shown, a first wiring layer 13A is formed on the side of the first encapsulation layer 15 away from the transparent substrate 11. The first wiring layer 13A is etched to form a plurality of third through holes A1 and a plurality of fourth through holes A2, wherein one of the third through holes A1 corresponds to a first external electrode 17.

[0230] Furthermore, a third trace B1 is formed on the side of the first wiring layer 13A away from the transparent substrate 11, and the third trace B1 is electrically connected to the first external electrode 17 through the third through hole A1; a transition trace Q1 is formed on the side of the first wiring layer 13A away from the transparent substrate 11, and the transition trace Q1 is electrically connected to the second external electrode 18 through the fourth through hole A2.

[0231] like Figure 26 As shown, a second wiring layer 13B is formed on the side of the first wiring layer 13A away from the transparent substrate 11, and the second wiring layer 13B is etched to form a plurality of fifth through holes A3 and a plurality of sixth through holes A4.

[0232] Furthermore, a fourth trace B2 is formed on the side of the second wiring layer 13B away from the transparent substrate 11. The fourth trace B2 is electrically connected to the second external electrode 18 through the fifth through hole A2 and the fourth through hole A2. A transition trace Q2 is formed on the side of the second wiring layer 13B away from the transparent substrate 11. The transition trace Q2 is electrically connected to the first trace B1 through the sixth through hole A4.

[0233] like Figure 27 As shown, a third wiring layer 13C is formed on the side of the second wiring layer 13B away from the transparent substrate 11, and the third wiring layer 13C is etched to form a plurality of seventh through holes A5 and eighth through holes A6.

[0234] Furthermore, multiple sets of first oblique wirings B3 and second oblique wirings B4 are formed on the side of the third wiring layer 13C opposite to the transparent substrate 11. The first oblique wirings B3 are electrically connected to the third trace B1 through the seventh through hole A5 and the sixth through hole A4; the second oblique wirings B4 are electrically connected to the fourth trace B2 through the eighth through hole A6.

[0235] like Figure 28 As shown, a fourth wiring layer 13D is formed on the side of the third wiring layer 13C away from the transparent substrate 11, and the fourth wiring layer 13D is etched to form a plurality of ninth through holes A7 and tenth through holes A8.

[0236] Furthermore, multiple sets of first pads 19 and second pads 20 are formed on the side of the fourth wiring layer 13D opposite to the transparent substrate 11. The first pads 19 are electrically connected to the first oblique wiring B3 through the ninth through hole A7; the second pads 20 are electrically connected to the second oblique wiring B4 through the tenth through hole A8.

[0237] like Figure 11 As shown, at least one first chip 14 is disposed on the side of the fourth wiring layer 13D opposite to the transparent substrate 11.

[0238] Among them, the third through hole A1, the sixth through hole A4, the seventh through hole A5 and the ninth through hole A7 belong to the first through hole group 131, and the fourth through hole A2, the fifth through hole A3, the eighth through hole A6 and the tenth through hole A8 belong to the second through hole group 132. The orthographic projections of the third through hole A1, the sixth through hole A4, the seventh through hole A5 and the ninth through hole A7 on the transparent substrate 11 do not overlap and are arranged along a certain direction; the orthographic projections of the fourth through hole A2, the fifth through hole A3, the eighth through hole A6 and the tenth through hole A8 on the transparent substrate 11 do not overlap and are arranged along a certain direction.

[0239] Therefore, it can be seen that the first pad 19 and the first external electrode 17 are electrically connected through the first via group 131 in the wiring layer 13, that is, the first pad 19 is electrically connected to the first electrode 121 of the light-emitting unit 12; the second pad 20 and the second external electrode 18 are electrically connected through the second via group 132 in the wiring layer 13, that is, the second pad 20 is electrically connected to the second electrode 122 of the light-emitting unit 12.

[0240] The first chip 14 and the light-emitting unit 20 are electrically connected through the first pad 19 and the second pad 20, so that the first chip 14 can control the working state of the light-emitting unit 20.

[0241] It should be noted that other functional chips can be formed on the side of the fourth wiring layer 13D facing away from the transparent substrate 11 in this process, that is, completed in the same process as the first chip 14.

[0242] like ​ As shown, a second encapsulation layer 16 is formed on the side of the fourth wiring layer 13D opposite to the transparent substrate 11. The second encapsulation layer 16 covers the first chip 14 in the first direction and is used to encapsulate the first chip 14, thereby forming the display device required in the embodiments of this application.

[0243] The above provides a detailed description of a display device and its manufacturing method provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0244] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0245] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0246] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display device, characterized by comprising: The display device comprises: a transparent substrate; a plurality of light-emitting units located on one side of the transparent substrate; a wiring layer located on a side of the light-emitting units away from the transparent substrate; at least one first chip located on a side of the wiring layer away from the transparent substrate; a first encapsulation layer located on a side of the transparent substrate close to the light-emitting units, the first encapsulation layer covering the light-emitting units in a first direction and used for encapsulating the light-emitting units; the first direction being perpendicular to a plane in which the transparent substrate is located; a second encapsulation layer located on a side of the wiring layer away from the transparent substrate, the second encapsulation layer covering the first chip in the first direction and used for encapsulating the first chip; wherein the first chip is electrically connected to the light-emitting units through the wiring layer, and used for controlling the working state of the light-emitting units; the minimum size of the first chip is 1 mm x 1 mm; a plurality of the light-emitting units constitute at least one light-emitting unit array; the number of the light-emitting units in a row direction in the light-emitting unit array is M, wherein M is greater than or equal to 2; the number of the light-emitting units in a column direction in the light-emitting unit array is N, wherein N is greater than or equal to 2; one first chip controls the working state of all the light-emitting units in one light-emitting unit array.

2. The display device according to claim 1, wherein The light-emitting unit comprises a first electrode and a second electrode; the first encapsulation layer covers the light-emitting unit; the first encapsulation layer comprises a plurality of groups of first grooves and second grooves, the first grooves and the second grooves are located on a surface of the first encapsulation layer close to the wiring layer, and one group of the first grooves and the second grooves corresponds to one light-emitting unit; wherein the first grooves expose the first electrode; the second grooves expose the second electrode.

3. The display device according to claim 2, wherein the light-emitting unit comprises a first light-emitting unit and a second light-emitting unit; in the first direction, the maximum height of the first light-emitting unit is greater than the maximum height of the second light-emitting unit; in the first direction, the depth of the second groove corresponding to the first light-emitting unit is less than the depth of the second groove corresponding to the second light-emitting unit; and / or, in the first direction, the depth of the first groove corresponding to the first light-emitting unit is less than the depth of the first groove corresponding to the second light-emitting unit.

4. The display device according to claim 3, wherein the first light-emitting unit emits first color light, and the wavelength of the first color light is λ1; the second light-emitting unit emits second color light, and the wavelength of the second color light is λ2; wherein λ1>λ2.

5. The display device according to claim 2, wherein in one group of the first grooves and the second grooves, in the first direction, the depth of the first groove is greater than the depth of the second groove.

6. The display device according to claim 2, wherein The display device comprises: a first external electrode, the first external electrode being electrically connected to the first electrode through the first groove; a second external electrode, the second external electrode being electrically connected to the second electrode through the second groove.

7. The display device according to claim 6, wherein The display device comprises: a plurality of first pads and a plurality of second pads between the wiring layer and the first chip; the wiring layer has a first via group and a second via group, the first via group includes a plurality of first vias, and the second via group includes a plurality of second vias; the first pad is electrically connected with the first external electrode through the first via group; the second pad is electrically connected with the second external electrode through the second via group.

8. The display device according to claim 7, wherein the orthogonal projections of the plurality of first vias in the first via group on the transparent substrate do not overlap with each other; and / or, the orthogonal projections of the plurality of second vias in the second via group on the transparent substrate do not overlap with each other.

9. The display device according to claim 7, wherein the orthogonal projections of the plurality of first vias in the first via group on the transparent substrate are arranged along a second direction; and / or, the orthogonal projections of the plurality of second vias in the second via group on the transparent substrate are arranged along the second direction; wherein the second direction is parallel to the plane where the transparent substrate is located.

10. The display device according to claim 1, wherein the display device further comprises a plurality of functional chips, and the plurality of functional chips are located on the side of the wiring layer away from the transparent substrate; wherein the plurality of functional chips are in communication connection with each other and with the first chip.

11. The display device according to claim 10, wherein the minimum size of the functional chip is 1mm*1mm.

12. The display device according to claim 2, wherein the first chip includes a first pad group and a second pad group, the first pad group includes a plurality of third pads arranged along a third direction, and the second pad group includes a plurality of fourth pads arranged along a fourth direction, the third direction and the fourth direction are parallel to the plane where the first chip is located, and the third direction and the fourth direction intersect; the third pad is electrically connected with the first electrode of the light emitting unit in the light emitting unit array; the fourth pad is electrically connected with the second electrode of the light emitting unit in the light emitting unit array.

13. The display device of claim 12, wherein, in the light emitting unit array, the first electrodes of a row of light emitting units are sequentially electrically connected, and the second electrodes of a column of light emitting units are sequentially electrically connected; the display device further comprises: a plurality of first wires, the first wires extend in the column direction and are arranged in the row direction in sequence; a plurality of second wires, the second wires extend in the row direction and are arranged in the column direction in sequence; one of the first wires corresponds to connect the first electrodes of a row of light emitting units; one of the second wires corresponds to connect the second electrodes of a column of light emitting units.

14. The display device of claim 13, wherein, a plurality of the first wires are sequentially connected with a plurality of third pads in a row of the third pads in sequence; a plurality of the second wires are sequentially connected with a plurality of fourth pads in a column of the fourth pads in sequence.

15. A method for manufacturing a display device, comprising: the manufacturing method comprises: providing a transparent substrate; providing a plurality of light emitting units and a first packaging layer on one side of the transparent substrate, the first packaging layer is located on the side of the transparent substrate close to the light emitting units; the first packaging layer covers the light emitting units in the first direction and is used for packaging the light emitting units; the first direction is perpendicular to the plane where the transparent substrate is located; forming a wiring layer on the side of the light emitting units away from the transparent substrate; providing at least one first chip on the side of the wiring layer away from the transparent substrate; A second encapsulation layer is formed on the side of the wiring layer away from the transparent substrate, and the second encapsulation layer covers the first chip in the first direction and is used for encapsulating the first chip; The first chip is electrically connected to the light emitting units through the wiring layer, and is used for controlling the working state of the light emitting units; the minimum size of the first chip is 1mm*1mm; a plurality of the light emitting units form at least one light emitting unit array; the number of the light emitting units in the row direction of the light emitting unit array is M, where M≥2; the number of the light emitting units in the column direction of the light emitting unit array is N, where N≥2; one first chip controls the working state of all the light emitting units in one light emitting unit array.

16. The method of manufacturing according to claim 15, wherein, The step of arranging a plurality of light emitting units and a first encapsulation layer on one side of the transparent substrate comprises: A first bearing substrate is provided, and a plurality of the light emitting units are arranged on the first bearing substrate, wherein each of the light emitting units comprises a first electrode and a second electrode; A bonding layer is arranged, wherein the bonding layer comprises a plurality of independent bonding units, and each of the first electrodes and the second electrodes corresponds to one of the bonding units; the surfaces of the plurality of the bonding units on the side away from the first bearing substrate are located on the same horizontal plane; A second bearing substrate is provided; The light emitting units are transferred to the second bearing substrate, and the first bearing substrate is removed, wherein the bonding units are in contact with the second bearing substrate.

17. The method of manufacturing according to claim 16, wherein, The step of arranging a plurality of light emitting units and a first encapsulation layer on one side of the transparent substrate further comprises: The first encapsulation layer is formed on the second bearing substrate; The transparent substrate is provided, and the transparent substrate is arranged on the side of the first encapsulation layer away from the second bearing substrate; The second bearing substrate and the bonding layer are removed, and the first encapsulation layer comprises a plurality of groups of first grooves and second grooves, wherein the first grooves and the second grooves are located on the surface of the first encapsulation layer close to the wiring layer, one group of the first grooves and the second grooves corresponds to one of the light emitting units; the first grooves expose the first electrodes; and the second grooves expose the second electrodes.

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