Three-dimensional semiconductor memory device and method of manufacturing the same

Abstract

Methods of fabricating a three-dimensional (3D) semiconductor memory device are provided. The method can include forming a thin layer structure on a substrate including a cell array region and a connection region; forming a first mask pattern; performing a first etching process to etch the thin layer structure using the first mask pattern as an etching mask; performing a first trimming process to reduce an area of the first mask pattern; alternately and repeatedly performing the first etching process and the first trimming process to form an upper structure on the connection region; forming a second mask pattern; performing a second etching process to etch the thin layer structure and the upper structure using the second mask pattern as an etching mask; performing a second trimming process to reduce an area of the second mask pattern; and alternately and repeatedly performing the second etching process and the second trimming process to form a plurality of intermediate structures under the upper structure.

Description

[0001] This application is a divisional application of patent application No. 201710011121.X, filed on January 6, 2017, entitled "Three-dimensional semiconductor memory device and manufacturing method thereof". Technical Field

[0002] This disclosure relates to three-dimensional (3D) semiconductor devices and methods for manufacturing such 3D semiconductor devices. Background Technology

[0003] Semiconductor devices have been highly integrated to provide excellent performance and low manufacturing costs. The integration level of a semiconductor device affects its manufacturing cost, and therefore, highly integrated semiconductor devices can be advantageous in terms of manufacturing cost. The integration level of traditional two-dimensional (2D) semiconductor devices, or planar semiconductor devices, can be determined by the area occupied by a unit memory cell. Therefore, the integration level of traditional 2D semiconductor devices can be affected by the technology used to form intricate patterns. However, because expensive equipment is used to form intricate patterns, the integration level of 2D semiconductor devices is limited. Consequently, three-dimensional (3D) semiconductor memory devices have been developed to further increase the integration level of semiconductor devices. 3D semiconductor memory devices can include memory cells arranged in three dimensions. Summary of the Invention

[0004] Embodiments of the present invention provide a highly integrated three-dimensional (3D) semiconductor memory device and a method for manufacturing the semiconductor memory device.

[0005] A 3D semiconductor memory device may include: a substrate including a cell array region and a connection region; a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stepped structure extending over the connection region in a first direction and a second stepped structure extending over the connection region in a second direction substantially perpendicular to the first direction; and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each intermediate stack structure may include a plurality of intermediate electrodes vertically stacked and may have a third stepped structure extending over the connection region in the second direction. Each intermediate stack structure may expose the third stepped structure of the intermediate stack structure disposed thereunder.

[0006] A 3D semiconductor memory device may include: a substrate including a cell array region and a connection region; and an electrode structure extending from the cell array region to the connection region in a first direction. The electrode structure may include a lower stack structure comprising a lower electrode vertically stacked on the substrate and a plurality of intermediate stack structures vertically stacked on the lower stack structure to form a stepped structure in the first direction. Each intermediate stack structure may include a vertically stacked intermediate electrode, and each lower electrode may have a lower pad region exposed on the connection region by a lower electrode immediately disposed thereon. Each intermediate electrode may have an intermediate pad region exposed on the connection region by an intermediate electrode immediately disposed thereon. The intermediate pad regions may have substantially equal lengths in the first direction and substantially equal widths in a second direction substantially perpendicular to the first direction. The lower pad regions may have length in the first direction and width in the second direction, the length and width of the lower pad regions decreasing with increasing vertical distance from the substrate.

[0007] A method of manufacturing a 3D semiconductor memory device may include: forming a thin layer structure comprising vertically and alternately stacked insulating and horizontal layers on a substrate including a cell array region and a connection region; forming an upper structure comprising a plurality of vertically stacked upper horizontal patterns on the thin layer structure, the upper structure having a first stepped structure extending in a first direction and a second stepped structure extending in a second direction substantially perpendicular to the first direction on the connection region; forming a mask pattern exposing portions of the first and second stepped structures of the upper structure and portions of the thin layer structure on the connection region; and performing a pad etching process using the mask pattern as an etching mask to etch the upper structure and the thin layer structure.

[0008] A method of manufacturing a 3D semiconductor memory device may include: forming a thin-layer structure comprising vertically and alternately stacked insulating and horizontal layers on a substrate including cell array regions and connection regions; repeatedly performing a first patterning process on an upper portion of the thin-layer structure to form an upper structure comprising a plurality of vertically stacked upper horizontal patterns, the upper structure having a first stepped structure extending in a first direction and a second stepped structure extending in a second direction substantially perpendicular to the first direction on the connection regions; and repeatedly performing a second patterning process on a portion of the upper structure and a lower portion of the thin-layer structure to form a plurality of intermediate structures below the upper structure. The intermediate structures may form a stepped structure in the first direction. Each intermediate structure may include at least two of the horizontal layers and may have a third stepped structure extending in the second direction.

[0009] An integrated circuit device may include an electrode structure on a substrate. The electrode structure may include a plurality of electrodes vertically stacked on the substrate. The plurality of electrodes may include a plurality of intermediate electrodes vertically stacked on the substrate. Each of the plurality of intermediate electrodes may extend longitudinally in a first horizontal direction and may include first and second long sidewalls extending in the first horizontal direction and a short sidewall extending from the first long sidewall toward the second long sidewall in a second horizontal direction substantially perpendicular to the first horizontal direction. The short sidewalls of the plurality of intermediate electrodes may be substantially vertically aligned with each other. A first of the plurality of intermediate electrodes may include a first intermediate pad region exposed by a second of the plurality of intermediate electrodes immediately adjacent to the first of the plurality of intermediate electrodes, and in a plan view, the first intermediate pad region may protrude in the second horizontal direction beyond the second long sidewall of the second of the plurality of intermediate electrodes. The plurality of electrodes may also include a plurality of lower electrodes vertically stacked on the substrate. The plurality of lower electrodes may be located between the substrate and the plurality of intermediate electrodes. Each of the plurality of lower electrodes may extend longitudinally in the first horizontal direction and may include third and fourth long sidewalls extending in the first horizontal direction and a short sidewall extending from the third long sidewall toward the fourth long sidewall in the second horizontal direction. The first of the plurality of lower electrodes may include a first lower pad region exposed by a second of the plurality of lower electrodes immediately adjacent to the first of the plurality of lower electrodes, and in a plan view, the first lower pad region may protrude in a first horizontal direction beyond the short sidewall of the second of the plurality of lower electrodes and may protrude in a second horizontal direction beyond the fourth long sidewall of the second of the plurality of lower electrodes. Attached Figure Description

[0010] The inventive concept will become more apparent from the accompanying drawings and detailed description.

[0011] Figure 1 This is a schematic block diagram illustrating some embodiments of a 3D semiconductor memory device according to the present invention.

[0012] Figure 2 This is a schematic block diagram illustrating some embodiments of a 3D semiconductor memory device according to the present invention.

[0013] Figure 3 This is a schematic circuit diagram illustrating some embodiments of a 3D semiconductor memory device according to the present invention.

[0014] Figure 4 and 5 This is a view illustrating the electrode structure of a 3D semiconductor memory device according to some embodiments of the concept of the present invention.

[0015] Figure 6 and Figures 7A to 7DThis is a view showing the lower stacked structure of an electrode structure according to some embodiments of the concept of the present invention.

[0016] Figure 8 and Figures 9A to 9D This is a view illustrating the intermediate stacked structure of an electrode structure according to some embodiments of the present invention.

[0017] Figure 10 This is a perspective view showing the intermediate stacked structure of an electrode structure according to some embodiments of the present invention.

[0018] Figure 11 and Figures 12A to 12C This is a view showing the upper stacked structure of an electrode structure according to some embodiments of the present invention.

[0019] Figure 13 This is a perspective view illustrating an electrode structure according to some embodiments of the concept of the present invention.

[0020] Figure 14 It is shown in Figure 13 The diagram shows a view of the intermediate stacked structure of the electrode structure.

[0021] Figure 15 , 16 17 and 18 are perspective views illustrating electrode structures according to some embodiments of the concept of the present invention.

[0022] Figure 18 This is a plan view showing a contact plug connected to an electrode structure of a 3D semiconductor memory device according to some embodiments of the present invention.

[0023] Figure 19 It is along Figure 18 The cross-sectional view taken by line I-I' is used to illustrate 3D semiconductor memory devices according to some embodiments of the concept of the present invention.

[0024] Figure 20 This is a plan view illustrating a cell array region of a 3D semiconductor memory device according to some embodiments of the concept of the present invention.

[0025] Figure 21 and 22 They are along Figure 20 The cross-sectional views taken by lines I-I' and II-II' are used to illustrate 3D semiconductor memory devices according to some embodiments of the concept of the present invention.

[0026] Figure 23 yes Figure 21 A magnified view of part 'A'.

[0027] Figure 24This is a cross-sectional view showing a cell array region of a 3D semiconductor memory device according to some embodiments of the present invention.

[0028] Figure 25 yes Figure 24 A magnified view of part 'A'.

[0029] Figure 26 This is a cross-sectional view showing a cell array region of a 3D semiconductor memory device according to some embodiments of the present invention.

[0030] Figures 27 to 35 This is a perspective view illustrating a method for manufacturing an electrode structure of a 3D semiconductor memory device according to some embodiments of the concept of the present invention.

[0031] Figures 36 to 41 This is a perspective view illustrating a method for manufacturing an electrode structure of a 3D semiconductor memory device according to some embodiments of the concept of the present invention.

[0032] Figure 42 , 43 Views 4 and 44 are views illustrating interconnects electrically connected to electrode structures of 3D semiconductor memory devices according to some embodiments of the present invention.

[0033] Figure 45 , 46 Views 4 and 47 are views illustrating the electrode structure of a 3D semiconductor memory device according to some embodiments of the concept of the present invention. Detailed Implementation

[0034] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 This is a schematic block diagram illustrating some embodiments of a 3D semiconductor memory device according to the present invention.

[0036] refer to Figure 1 A 3D semiconductor memory device may include a cell array region (CAR) and a peripheral circuit region. The peripheral circuit region may include a row decoder region (ROW DCR), a page buffer (PBR), a column decoder region (COL DCR), and a control circuit region (not shown). In some embodiments, a connection region (CNR) may be located between the cell array region (CAR) and the row decoder region (ROW DCR).

[0037] A memory cell array comprising multiple memory cells can be arranged in a cell array region (CAR). In some embodiments, the memory cell array may include three-dimensionally arranged memory cells, word lines, and bit lines. The word lines and bit lines may be electrically connected to the memory cells.

[0038] The row decoder for selecting word lines of the memory cell array can be located in the ROW DCR area, and the interconnect structure can be located in the CNR area. The interconnect structure may include contact plugs and interconnects that electrically connect the memory cell array to the row decoder. The row decoder can select one of the word lines of the memory cell array in response to an address signal. In response to a control signal from the control circuitry, the row decoder can provide a first word line voltage and a second word line voltage to the selected word line and the unselected word line, respectively.

[0039] A page buffer used to sense data stored in a memory cell can be set in the page buffer (PBR). Depending on the operating mode, the page buffer can temporarily store data to be stored in the memory cell, or it can sense data already stored in the memory cell. The page buffer can operate as a write driver circuit in programming operation mode and as a sense amplifier circuit in read operation mode.

[0040] The column decoder connected to the bit lines of the memory cell array can be located in the column decoder area (COL DCR). The column decoder can provide a data transfer path between the page buffer and external devices, such as the memory controller.

[0041] Figure 2 This is a schematic block diagram illustrating a cell array of a 3D semiconductor memory device according to some embodiments of the concept of the present invention.

[0042] refer to Figure 2 The cell array may include multiple cell array blocks BLK1 to BLKn. Each cell array block BLK1 to BLKn may include an electrode structure comprising electrodes stacked along a third direction D3 on a plane defined by intersecting first and second directions D1 and D2. The electrode structure may be coupled to multiple vertical structures (e.g., semiconductor pillars) to form a three-dimensionally arranged memory cell. Furthermore, each cell array block BLK1 to BLKn may also include bit lines electrically connected to the memory cell.

[0043] Figure 3 This is a schematic circuit diagram illustrating some embodiments of a 3D semiconductor memory device according to the present invention.

[0044] refer to Figure 3 According to some embodiments, the cell array of a 3D semiconductor memory device may include a common source line CSL, multiple bit lines BL0 to BL2, and multiple cell strings CSTR disposed between the common source line CSL and the bit lines BL0 to BL2.

[0045] Bit lines BL0 to BL2 can be arranged in a two-dimensional manner, and multiple unit strings CSTRs can be connected in parallel to each bit line BL0 to BL2. The unit strings CSTRs can be connected together to a common source line CSL. In other words, multiple unit strings CSTRs can be positioned between a common source line CSL and the multiple bit lines BL0 to BL2. The common source line CSL can include multiple common source lines CSL, and these multiple common source lines CSL can be arranged in a two-dimensional manner. In some embodiments, the same voltage can be applied to the multiple common source lines CSL. In some embodiments, the common source lines CSL can be electrically controlled independently of each other.

[0046] In some implementations, each cell string CSTR may include string select transistors SST1 and SST2 connected in series with each other, memory cells MCT connected in series with each other, and ground select transistor GST. Each memory cell MCT may include a data storage element.

[0047] In some implementations, each cell string CSTR may include first and second string select transistors SST1 and SST2 connected in series with each other. The second string select transistor SST2 may be connected to one of the bit lines BL0 to BL2, and the ground select transistor GST may be connected to the common source line CSL. The memory cell MCT may be connected in series between the first string select transistor SST1 and the ground select transistor GST.

[0048] In addition, each cell string CSTR may also include a dummy cell DMC connected between the first string select transistor SST1 and the memory cell MCT. Although not shown in the figure, an additional dummy cell may be connected between the ground select transistor GST and the memory cell MCT adjacent to the ground select transistor GST.

[0049] In some implementations, in each cell string CSTR, similar to the first and second string select transistors SST1 and SST2, the ground select transistor GST may include a plurality of MOS transistors connected in series with each other. In some implementations, each cell string CSTR may include a single string select transistor.

[0050] In some implementations, the first string select transistor SST1 can be controlled by the first string select line SSL1, and the second string select transistor SST2 can be controlled by the second string select line SSL2. The memory cell MCT can be controlled by multiple word lines WL0 to WLn, and the dummy cell DMC can be controlled by the dummy word line DWL. The ground select transistor GST can be controlled by the ground select line GSL. The common source line CSL can be connected to the source of the ground select transistor GST.

[0051] A cell string CSTR may include the plurality of memory cells MCTs respectively located at different distances / heights from the common source line CSL. Word lines WL0 to WLn and DWL may be located between the common source line CSL and bit lines BL0 to BL2.

[0052] The gate electrodes of memory cells MCT (or dummy cells DWC) located at substantially the same height from the common source line CSL can be commonly connected to one of the word lines WL0 to WLn and DWL, thus being in an equipotential state. Alternatively, even if the gate electrodes of memory cells MCT are located at substantially the same height (e.g., distance / height) from the common source line CSL, the gate electrodes forming a row (or column) can be controlled independently of the gate electrodes forming another row (or column).

[0053] Figure 4 and 5 This is a view illustrating the electrode structure of a 3D semiconductor memory device according to some embodiments of the concept of the present invention. Figure 6 and Figures 7A to 7D This is a view showing the lower stacked structure of an electrode structure according to some embodiments of the concept of the present invention. Figure 8 , Figures 9A to 9D as well as Figure 10 This is a view illustrating the intermediate stacked structure of an electrode structure according to some embodiments of the present invention. Figure 11 and Figures 12A to 12C This is a view showing the upper stacked structure of an electrode structure according to some embodiments of the present invention.

[0054] refer to Figure 4 and 5 The substrate 1 may include a cell array region (CAR) and a connection region (CNR). For example, the substrate 1 may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), and aluminum gallium arsenide (AlGaAs), or any combination thereof. The substrate 1 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate having an epitaxial thin layer obtained by performing a selective epitaxial growth (SEG) process. In some embodiments, the substrate 1 may be formed of an insulating material and may include a single layer or multiple thin layers. For example, the substrate 1 may include at least one of a silicon oxide layer, a silicon nitride layer, or a low-k dielectric layer.

[0055] In some embodiments, multiple electrode structures ST1 and ST2 may be disposed on substrate 1. Electrode structures ST1 and ST2 may extend from the cell array region CAR to the connection region CNR in a first direction D1, and may be spaced apart from each other in a second direction D2 substantially perpendicular to the first direction D1. Here, the first direction D1 and the second direction D2 may be substantially parallel to the top surface of substrate 1.

[0056] In some embodiments, the first and second electrode structures ST1 and ST2 may be spaced apart from each other on the substrate 1 in a second direction D2. The first and second electrode structures ST1 and ST2 may have a stepped structure on the connection region CNR. Each of the first and second electrode structures ST1 and ST2 may include an insulating layer (not shown) and electrodes 10a to 10d, 20a to 20d, and 30a to 30d alternately stacked on the substrate 1. In other words, the insulating layer and electrodes 10a to 10d, 20a to 20d, and 30a to 30d may be alternately stacked in a third direction D3 substantially perpendicular to the top surface of the substrate 1. Electrodes 10a to 10d, 20a to 20d, and 30a to 30d may include a conductive material. For example, electrodes 10a to 10d, 20a to 20d, and 30a to 30d may comprise at least one of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a transition metal (e.g., titanium or tantalum). The insulating layer may comprise an insulating material, such as silicon oxide.

[0057] In detail, such as Figure 5 As shown, each of the first and second electrode structures ST1 and ST2 may include a lower stacked structure 10, an upper stacked structure 30, and a plurality of intermediate stacked structures 20 stacked between the lower stacked structure 10 and the upper stacked structure 30.

[0058] In some embodiments, the lower stack structure 10 may include a plurality (i.e., two or more) of vertically stacked lower electrodes 10a to 10d, with an insulating layer (not shown) interposed therebetween. At the connection region CNR, the end portions of the lower stack structure 10 may be exposed through the intermediate stack structure 20. In other words, at the connection region CNR, portions of the lower electrodes 10a to 10d may be exposed through the intermediate stack structure 20.

[0059] In detail, each of the lower electrodes 10a to 10d may have a lower pad region LP exposed by a lower electrode immediately disposed thereon. It will be understood that the second lower electrode 10b is immediately adjacent to the lower electrode 10a and in the third direction D3, since there is no lower electrode between the second lower electrode 10b and the lower electrode 10a. It will also be understood that the second lower electrode 10b immediately adjacent to the lower electrode 10a is spaced apart from and does not contact (e.g., directly contact) the lower electrode 10a in the third direction D3. In some embodiments, the area (e.g., surface area) of the lower pad region LP may decrease (e.g., monotonically decrease) as the distance / height of the lower electrodes 10a to 10d from the substrate 1 increases. In other words, the longest length of the lower electrodes 10a to 10d in the first direction D1 and the longest width of the lower electrodes 10a to 10d in the second direction D2 can decrease (e.g., decrease monotonically) as the distance / height of the lower electrodes 10a to 10d from the substrate 1 increases. Furthermore, the horizontal distance between the first sidewalls of the vertically adjacent lower electrodes in the first direction D1 can be substantially equal to the horizontal distance between the second sidewalls of the vertically adjacent lower electrodes in the second direction D2.

[0060] The first portion of the lower electrodes 10a to 10d can form a first stepped structure in the first direction D1, and the second portion of the lower electrodes 10a to 10d can form a second stepped structure in the second direction D2. That is, the lower stacked structure 10 can have a first stepped structure formed along the first direction D1 and a second stepped structure formed along the second direction D2. In other words, the lower stacked structure 10 can have a pyramid-shaped stepped structure in the connection region CNR. The angle between the slope of the first stepped structure and the top surface of the substrate 1 can be substantially equal to the angle between the slope of the second stepped structure and the top surface of the substrate 1. In other words, each slope of the first and second stepped structures can form a first tilt angle θ1 relative to the top surface of the substrate 1, as shown in... Figure 5 As shown in the image.

[0061] In some embodiments, intermediate stack structures 20 may be vertically stacked on top of lower stack structures 10. Each intermediate stack structure 20 may include a plurality of vertically stacked intermediate electrodes 20a to 20d. The number of intermediate stack structures 20 may vary depending on the sum of the number of lower electrodes 10a to 10d, intermediate electrodes 20a to 20d, and upper electrodes 30a to 30d, and may also vary depending on the number of intermediate electrodes 20a to 20d included in each intermediate stack structure 20. For example, the number of intermediate electrodes 20a to 20d included in each intermediate stack structure 20 may be n, where "n" represents a natural number equal to or greater than 2. In some embodiments, each intermediate stack structure 20 may include four intermediate electrodes 20a to 20d.

[0062] The plurality of intermediate stacked structures 20 may be stacked on the connection region CNR to have a stepped structure in the first direction D1. In other words, each intermediate stacked structure 20 may expose the end portion of the intermediate stacked structure 20 disposed thereunder.

[0063] Since each intermediate stack structure 20 may include the plurality of intermediate electrodes 20a to 20d, the ramp of the stepped structure formed by the intermediate stack structure 20 in the first direction D1 can form a second tilt angle θ2 relative to the top surface of the substrate 1 that is greater than the first tilt angle θ1.

[0064] In each intermediate stack-up structure 20, the end portions of intermediate electrodes 20a to 20d may be exposed on the connection region CNR. Each intermediate electrode 20a to 20d may have an intermediate pad region MP exposed by one of the intermediate electrodes immediately disposed thereon. It will be understood that the second intermediate electrode 20b is immediately adjacent to the first intermediate electrode 20a and in the third direction D3, since there is no intermediate electrode between the second intermediate electrode 20b and the first intermediate electrode 20a. It will also be understood that the second intermediate electrode 20b, which is immediately adjacent to the first intermediate electrode 20a, is spaced apart from and does not contact (e.g., directly contact) the first intermediate electrode 20a in the third direction D3. In some embodiments, the areas (e.g., surface areas) of the intermediate pad regions MP of the intermediate electrodes 20a to 20d may be substantially equal to each other, and the area of ​​the intermediate pad region MP may be smaller than the area of ​​the lower pad region LP. In other words, the intermediate pad regions MP of the intermediate electrodes 20a to 20d can have a length L in the first direction D1 and a width W in the second direction D2. The lengths L of the intermediate pad regions MP can be substantially equal to each other, and the widths W of the intermediate pad regions MP can be substantially equal to each other. In some embodiments, in each intermediate pad region MP, the length L can be substantially equal to the width W. In some embodiments, such as Figure 10As shown, each intermediate pad area MP can have a different length L and width W than each other. For example, the length L can be greater than the width W.

[0065] In each intermediate stacked structure 20, portions of the intermediate electrodes 20a to 20d can form a third stepped structure in the second direction D2. The ramp of the third stepped structure can form a first tilt angle θ1 relative to the top surface of the substrate 1, just like the first and second stepped structures.

[0066] Furthermore, in a direction parallel to the second direction D2, each intermediate electrode 20a to 20d may have a sidewall that is substantially vertically aligned with the sidewall of the other intermediate electrode disposed thereon. In other words, the sidewalls of the intermediate electrodes 20a to 20d parallel to the second direction D2 may be substantially coplanar with each other. That is, the maximum length of the intermediate electrodes 20a to 20d in the first direction D1 may be substantially equal to each other in each intermediate stacked structure 20.

[0067] In some embodiments, the upper stack structure 30 may include a plurality of upper electrodes 30a to 30d vertically stacked on the topmost of the intermediate stack structure 20. The upper stack structure 30 may expose the end portions of the intermediate stack structure 20 and the lower stack structure 10 on the connection region CNR. Furthermore, the end portions of the upper electrodes 30a to 30d may be exposed on the connection region CNR. In other words, each upper electrode 30a to 30d may have an upper pad region UP exposed by one of the upper electrodes 30a to 30d immediately disposed thereon. It will be understood that the second upper electrode 30b is immediately adjacent to the first upper electrode 30a and in the third direction D3, because there is no upper electrode between the second upper electrode 30b and the first upper electrode 30a. It will also be understood that the second upper electrode 30b, which is immediately adjacent to the first upper electrode 30a, is spaced apart from and does not contact (e.g., directly contact) the first upper electrode 30a in the third direction D3. In the plan view, the upper pad area UP can be arranged in the first direction D1. The area (e.g., surface area) of the upper pad area UP can be larger than the area of ​​the middle pad area MP.

[0068] The portions of the upper electrodes 30a to 30d can form a fourth stepped structure in the first direction D1. In some embodiments, the ramp of the fourth stepped structure can form a first tilt angle θ1 relative to the top surface of the substrate 1, like the first and second stepped structures.

[0069] Furthermore, the lowermost upper electrode 30a in the upper stacked structure 30 may have a sidewall that is substantially vertically aligned with the sidewall of the intermediate electrode 20d disposed below it. The two upper electrodes 30d disposed in the upper region of the upper stacked structure 30 may have, for example... Figure 5The line shape shown.

[0070] Furthermore, the upper dummy stack structure 40 can be disposed on the lowermost upper electrode 30a. The upper dummy stack structure 40 can include vertically stacked upper dummy electrodes 40a to 40c. One sidewall of the upper dummy stack structure 40 can be substantially vertically aligned with one sidewall of the intermediate stack structure 20 disposed below the upper dummy stack structure 40. The upper dummy electrodes 40a to 40c can be laterally spaced from some upper electrodes 30b to 30d in a first direction D1. A first portion of the upper dummy electrodes 40a to 40c can be exposed along the first direction D1, and a second portion of the upper dummy electrodes 40a to 40c can be exposed along the second direction D2. Thus, the upper dummy stack structure 40 can have a first stepped structure formed along the first direction D1 and a second stepped structure formed along the second direction D2. Furthermore, the first stepped structure of the upper dummy stack structure 40 can be opposite to the fourth stepped structure of the upper stack structure 30. In some embodiments, the first step structure of the upper dummy stacked structure 40 can face the fourth step structure of the upper stacked structure 30, such as... Figure 5 As shown.

[0071] In some embodiments, the first and second electrode structures ST1 and ST2 may be symmetrical with respect to an imaginary line extending along a first direction D1 between the first and second electrode structures ST1 and ST2.

[0072] For more details, see the reference. Figure 6 as well as Figures 7A to 7D The lower stack structure 10 may include first to fourth lower electrodes 10a to 10d sequentially stacked on the substrate 1. Each of the first to fourth lower electrodes 10a to 10d may include multiple electrode portions EP, electrode connection portions ECP, and one or more extension portions EXP1 and EXP2. In some embodiments, each of the first to fourth lower electrodes 10a to 10d may include first and second extension portions EXP1 and EXP2.

[0073] Electrode portions EP can extend on the substrate 1 of the cell array region CAR in a first direction D1 and can be spaced apart from each other in a second direction D2 that is substantially perpendicular to the first direction D1. In other words, electrode portions EP can be spaced apart from each other laterally. Each electrode portion EP can have a first width w1 in the second direction D2. In the lower stack structure 10, the electrode portions EP of the first to fourth lower electrodes 10a to 10d can overlap each other in a planar view.

[0074] The electrode connection portion ECP can extend horizontally along the connection region CNR of the adjacent cell array region CAR in the second direction D2, thus enabling the electrode portions EP to be horizontally connected to each other. In other words, in each electrode structure ST1 and ST2, the electrode portions EP located at the same distance / height (or horizontal) from the substrate 1 can be in an equipotential state through the electrode connection portion ECP. In the lower stack structure 10, the electrode connection portions ECP of the first to fourth lower electrodes 10a to 10d can overlap each other in a planar view.

[0075] The first and second extension portions EXP1 and EXP2 can extend from the electrode connection portion ECP to the connection region CNR in a first direction D1 and can be spaced apart from each other. Each of the first and second extension portions EXP1 and EXP2 can have a first width w1 in a second direction D2. In other words, the width w1 of the first and second extension portions EXP1 and EXP2 in the second direction D2 can be substantially equal to the width w1 of the electrode portion EP in the second direction D2. Furthermore, the distance between the first extension portion EXP1 and the second extension portion EXP2 in the second direction D2 can be substantially equal to the distance between the electrode portions EP in the second direction D2.

[0076] In some embodiments, the first and second extension portions EXP1 and EXP2 of the first lower electrode 10a may extend a first length d11a from the electrode connection portion ECP in a first direction D1, such as... Figure 7A As shown. Both the first extension portion EXP1 and the second extension portion EXP2 of the first lower electrode 10a can have a first length d11a. In addition, the first lower electrode 10a can have a lower pad area LP corresponding to the end portions of its first and second extension portions EXP1 and EXP2.

[0077] refer to Figure 6 and 7B The first and second extension portions EXP1 and EXP2 of the second lower electrode 10b can extend from the electrode connection portion ECP in the first direction D1 and can have different lengths from each other. For example, the second length d12 of the first extension portion EXP1 of the second lower electrode 10b can be less than the third length d11b of the second extension portion EXP2 of the second lower electrode 10b. Furthermore, the second lower electrode 10b can include a protruding portion PP that protrudes from the first extension portion EXP1 in the first direction D1. Here, the protruding portion PP can have a second width w2 that is less than the first width w1 of the first extension portion EXP1. The second lower electrode 10b can have a lower pad area LP corresponding to the end portions of the protruding portion PP and the second extension portion EXP2.

[0078] refer to Figure 6 and 7C The second length d12 of the first extension portion EXP1 of the third lower electrode 10c may be less than the fourth length d11c of the second extension portion EXP2 of the third lower electrode 10c. The first extension portion EXP1 of the third lower electrode 10c may expose the protruding portion PP of the second lower electrode 10b. The third lower electrode 10c may have a lower pad area LP corresponding to a portion of its second extension portion EXP2.

[0079] refer to Figure 6 and 7D The first extension portion EXP1 of the fourth lower electrode 10d can expose the protruding portion PP of the second lower electrode 10b. The fourth lower electrode 10d may include a protruding portion PP protruding from the second extension portion EXP2 in the first direction D1. Here, the protruding portion PP of the fourth lower electrode 10d may have a width w2 smaller than the width w1 of the second extension portion EXP2 of the fourth lower electrode 10d. The fourth lower electrode 10d may have a lower pad area LP corresponding to its protruding portion PP.

[0080] A lower stacked structure 10 comprising four lower electrodes 10a to 10d is described as an example. However, the inventive concept is not limited thereto. In some embodiments, the number of lower electrodes 10a to 10d in the lower stacked structure 10 may be greater than four. Furthermore, the number of electrode portions EP and the number of extension portions EXP1 and EXP2 in each lower electrode 10a to 10d may vary. Additionally, in some embodiments, the number of electrode portions EP in each lower electrode 10a to 10d may differ from the number of extension portions EXP1 and EXP2.

[0081] refer to Figure 8 and Figures 9A to 9D The intermediate stack structure 20 may include first to fourth intermediate electrodes 20a to 20d stacked sequentially. Each of the first to fourth intermediate electrodes 20a to 20d may include multiple electrode portions EP, electrode connection portions ECP, and one or more extension portions EXP1 and EXP2.

[0082] In some embodiments, the first to fourth intermediate electrodes 20a to 20d may have sidewalls that are substantially vertically aligned with each other on the connection region CNR, in a direction parallel to the second direction D2. Here, the substantially vertically aligned sidewalls may be defined or formed by an etching process. In other words, the substantially vertically aligned sidewalls of the first to fourth intermediate electrodes 20a to 20d may be substantially coplanar with each other.

[0083] In some embodiments, each of the first to fourth intermediate electrodes 20a to 20d may include first and second extension portions EXP1 and EXP2. In some embodiments, the electrode portion EP and electrode connection portion ECP of the first to fourth intermediate electrodes 20a to 20d may have the same shape as the electrode portion EP and electrode connection portion ECP of the first to fourth lower electrodes 10a to 10d. Thus, in a plan view, the electrode portion EP and electrode connection portion ECP of the first to fourth intermediate electrodes 20a to 20d may overlap with the electrode portion EP and electrode connection portion ECP of the first to fourth lower electrodes 10a to 10d.

[0084] refer to Figure 8 and 9A The first intermediate electrode 20a may have a structure substantially the same as that of the first lower electrode 10a. However, the fifth length d21 of the first and second extension portions EXP1 and EXP2 of the first intermediate electrode 20a in the first direction D1 may be smaller than the first length d11a of the first and second extension portions EXP1 and EXP2 of the first lower electrode 10a in the first direction D1. The first intermediate electrode 20a may have an intermediate pad area MP disposed at the end portion of its first extension portion EXP1.

[0085] refer to Figure 8 and 9B The second intermediate electrode 20b may include first and second extensions EXP1 and EXP2 having a fifth length d21 and a sixth length d22 that are different from each other. The second intermediate electrode 20b may include a protruding portion PP that projects from the first extension EXP1 in a first direction D1. In other words, the second intermediate electrode 20b may have a structure substantially the same as the second lower electrode 10b. However, the length of the protruding portion PP of the second intermediate electrode 20b in the first direction D1 may be less than the length of the protruding portion PP of the second lower electrode 10b in the first direction D1. The second intermediate electrode 20b may have an intermediate pad region MP corresponding to its protruding portion PP.

[0086] refer to Figure 8 and 9C The third intermediate electrode 20c may have a structure substantially the same as that of the third lower electrode 10c. However, the fifth and sixth lengths d21 and d22 of the first and second extensions EXP1 and EXP2 of the third intermediate electrode 20c in the first direction D1 may be smaller than the fourth and second lengths d11c and d12 of the first and second extensions EXP1 and EXP2 of the third lower electrode 10c in the first direction D1, respectively. The first extension EXP1 of the third intermediate electrode 20c may expose the protruding portion PP of the second intermediate electrode 20b. The third intermediate electrode 20c may have an intermediate pad area MP disposed at the end portion of its second extension EXP2.

[0087] refer to Figure 8 and 9D The fourth intermediate electrode 20d may include first and second extension portions EXP1 and EXP2 having substantially equal lengths. Furthermore, the fourth intermediate electrode 20d may also include a protrusion PP projecting from the second extension portion EXP2 in a first direction D1. The fourth intermediate electrode 20d may have substantially the same length as... Figure 7D The fourth lower electrode 10d has the same structure. However, the length of the protruding portion PP of the fourth intermediate electrode 20d in the first direction D1 can be less than that of the first intermediate electrode 20d. Figure 7D The length of the protruding portion PP of the fourth lower electrode 10d in the first direction D1. The fourth intermediate electrode 20d may have an intermediate pad area MP corresponding to its protruding portion PP.

[0088] In some implementations, the intermediate stack-up structure 20 may include, as referenced Figure 8 and Figures 9A to 9D The four intermediate electrodes 20a to 20d are described. However, the inventive concept is not limited thereto. The number of intermediate electrodes 20a to 20d in the intermediate stacked structure 20 can be varied. Furthermore, in each of the intermediate electrodes 20a to 20d, the number of electrode portions EP and the number of extension portions EXP1 and EXP2 can be varied.

[0089] refer to Figure 11 and Figures 12A to 12C The upper stacked structure 30 may include sequentially stacked first to fourth upper electrodes 30a to 30d. In a plan view, the sidewalls of the first to fourth upper electrodes 30a to 30d, substantially parallel to, for example, a second direction D2, may be horizontally spaced apart from each other in a first direction D1. Furthermore, the horizontal distance in the first direction D1 between the sidewalls of the first upper electrode 30a and the sidewalls of the second upper electrode 30b may be greater than the horizontal distance in the first direction D1 between the sidewalls of the second upper electrode 30b and the sidewalls of the third upper electrode 30c. Figure 11 As shown.

[0090] refer to Figure 11 and 12A The first upper electrode 30a may include multiple electrode portions EP, an electrode connection portion ECP, and first and second extension portions EXP1 and EXP2, similar to the first lower electrode 10a and the first intermediate electrode 20a described above. Furthermore, the seventh length d31 of the first and second extension portions EXP1 and EXP2 of the first upper electrode 30a may be substantially equal to each other.

[0091] In some implementations... Figure 5The upper dummy electrodes 40a to 40c can be disposed on the first and second extension portions EXP1 and EXP2 of the first upper electrode 30a, as shown in the reference. Figure 5 Described. Figure 5 The upper dummy electrodes 40a to 40c may have sidewalls that are substantially vertically aligned with the sidewall of the first upper electrode 30a. Figure 5 The dummy electrodes 40a to 40c can expose portions of the first and second extensions EXP1 and EXP2 of the first upper electrode 30a. In other words, the first upper electrode 30a can have an upper pad area UP corresponding to portions of the first and second extensions EXP1 and EXP2. In a plan view, the upper pad area UP of the first upper electrode 30a can be disposed between the second upper electrode 30b and... Figure 5 The upper dummy electrode is between 40a and 40c.

[0092] refer to Figure 11 and 12B The second upper electrode 30b may include multiple first and second sub-electrode portions SEP1 and SEP2, an electrode connection portion ECP, and extension portions EXP1 and EXP2.

[0093] The first and second sub-electrode portions SEP1 and SEP2 of the second upper electrode 30b may extend on the cell array region CAR in the first direction D1 and may overlap the electrode portion EP of the first upper electrode 30a in the plan view. The width of each of the first and second sub-electrode portions SEP1 and SEP2 may be equal to or less than approximately half the width w1 of each electrode portion EP of the first upper electrode 30a.

[0094] The electrode connection portion ECP of the second upper electrode 30b can extend in the connection area CNR in the second direction D2 so that the first sub-electrode portion SEP1 and the second sub-electrode portion SEP2 are horizontally connected to each other. The second upper electrode 30b can have an upper pad area UP disposed at the first and second extension portions EXP1 and EXP2.

[0095] The first and second extension portions EXP1 and EXP2 of the second upper electrode 30b can extend in the connection region CNR in the first direction D1.

[0096] In some embodiments, the second upper electrode 30b may include an electrode portion EP whose width is substantially equal to the width of the first and second extensions EXP1 and EXP2, such as Figure 12C As shown in the image.

[0097] like Figure 11As shown, the two uppermost upper electrodes 30d may have a linear shape extending in the first direction D1, and the width of each of the two uppermost upper electrodes 30d may be less than approximately half the width of the electrode portion EP of the first upper electrode 30a. In the plan view, the third upper electrode 30c may overlap the first and second sub-electrode portions SEP1 and SEP2 of the second upper electrode 30b, respectively. The fourth upper electrode 30d may have a structure substantially the same as the third upper electrode 30c. However, the fourth upper electrode 30d may expose the end portion of the third upper electrode 30c on the connection region CNR.

[0098] Figure 13 This is a perspective view illustrating the electrode structure of a 3D semiconductor memory device according to some embodiments of the concept of the present invention. Figure 14 It is shown in Figure 13 The image shows a view of the intermediate stacked structure of the electrode structure. In the following text, [the image is] compared to... Figures 4 to 12C The same elements described in the embodiments will be indicated by the same reference numerals or the same reference symbols, and for ease of explanation, descriptions of them will be omitted or briefly mentioned.

[0099] according to Figure 13 and 14 In the embodiments shown, each electrode 10a to 10d, 20a to 20d, and 30a to 30d may include multiple electrode portions EP, multiple extension portions EXP1 and EXP2, and an electrode connection portion ECP, as described above. According to this embodiment, the extension portions EXP1 and EXP2 may have a uniform width in the second direction D2 and may extend in the first direction D1. In some embodiments, in each electrode 10a to 10d, 20a to 20d, and 30a to 30d, the number of electrode portions EP may be equal to the number of extension portions EXP1 and EXP2.

[0100] like Figure 14 As shown, at least one of the intermediate electrodes 20b to 20d may include a first extension EXP1 having a first length in the first direction D1 and a second extension EXP2 having a second length in the first direction D1. Here, the second length may be greater than the first length. In each intermediate stack structure 20, the number of second extensions EXP2 of the intermediate electrodes 20a to 20d may sequentially decrease as the distance / height of the intermediate electrodes 20a to 20d from the substrate 1 sequentially increases. The extensions of the lowermost intermediate electrode 20a in each intermediate stack structure 20 may have substantially equal lengths in the first direction D1, such as... Figure 13 As shown.

[0101] Figure 15 , 1617 and 18 are perspective views illustrating the electrode structure of a 3D semiconductor memory device according to some embodiments of the present invention. In the following, with reference to... Figures 4 to 12C The same elements described in the embodiments will be indicated by the same reference numerals or the same reference symbols, and for ease of explanation, descriptions of them will be omitted or briefly mentioned.

[0102] refer to Figure 15 , 16 17. Each of the first and second electrode structures ST1 and ST2 may include a lower stacked structure 10, an upper stacked structure 30, and a plurality of intermediate stacked structures 20 stacked between the lower stacked structure 10 and the upper stacked structure 30, as described above.

[0103] according to Figure 15 In this embodiment, the intermediate stacked structures 20 can be vertically stacked on the lower stacked structure 10 and can form a stepped structure along the first direction D1. In other words, each intermediate stacked structure 20 can expose the end portion of the intermediate stacked structure 20 disposed below it. Each intermediate stacked structure 20 can have a third stepped structure formed along the second direction D2 through intermediate electrodes 20a to 20d. Here, each intermediate stacked structure 20 can be spaced apart from a sidewall of the intermediate stacked structure 20 disposed below it by a first horizontal distance L1 or a second horizontal distance L2 greater than the first horizontal distance L1, such as... Figure 15 As shown. Each intermediate electrode 20a to 20d included in each intermediate stack-up structure 20 may have an intermediate pad area MP exposed by an intermediate electrode immediately disposed thereon, as shown in the reference. Figure 4 Described. In some embodiments, the length L2 of the intermediate pad region MP of one intermediate stack-up structure 20 may be greater than the length L1 of the intermediate pad region MP of the other intermediate stack-up structure 20.

[0104] According to some implementations, the number of electrodes in each lower stack 10, middle stack 20 and upper stack 30 can vary.

[0105] according to Figure 16 In this implementation, each lower stack structure 10, intermediate stack structure 20, and upper stack structure 30 may include six electrodes stacked sequentially. The number of pad regions LP, MP, or UP arranged along the second direction D2 in each stack structure 10, 20, and 30 may increase as the number of electrodes in each stack structure 10, 20, and 30 increases. For example, each intermediate stack structure 20 may include six intermediate pad regions MP.

[0106] according to Figure 17In this embodiment, each lower stack structure 10, intermediate stack structure 20, and upper stack structure 30 may include eight electrodes stacked sequentially. In this embodiment, each intermediate stack structure 20 may include eight intermediate pad regions MP arranged in a second direction D2 in a plan view.

[0107] Figure 18 This is a plan view showing a contact plug connected to an electrode structure of a 3D semiconductor memory device according to some embodiments of the present invention. Figure 19 It is along Figure 18 The cross-sectional view taken by line I-I' is used to illustrate 3D semiconductor memory devices according to some embodiments of the concept of the present invention.

[0108] refer to Figure 18 and 19 The substrate 1 may include a cell array region (CAR) and a connection region (CNR). First and second electrode structures ST1 and ST2 may be disposed on the substrate 1. Each of the first and second electrode structures ST1 and ST2 may include a lower stacked structure 10, a plurality of intermediate stacked structures 20, and an upper stacked structure 30, as shown in the reference. Figures 4 to 12C The lower stack-up structure 10 may include a plurality of lower electrodes 10a to 10d, and may have a first stepped structure formed along a first direction D1 and a second stepped structure formed along a second direction D2 on the connection region CNR. Each lower electrode 10a to 10d may have a lower pad region LP on the connection region CNR, as described in reference. Figure 4 Described.

[0109] The intermediate stack structure 20 may expose the end portion of the lower stack structure 10 and may be stacked as having a stepped structure formed along a first direction D1. Each intermediate stack structure 20 may include a plurality of intermediate electrodes 20a to 20d and may have a third stepped structure formed along a second direction D2 on the connection region CNR. In each intermediate stack structure 20, each intermediate electrode 20a to 20d may have an intermediate pad region MP on the connection region CNR, as referenced. Figure 4 Described.

[0110] The upper stack structure 30 can expose the end portions of the intermediate stack structure 20 and the end portions of the lower stack structure 10. The upper stack structure 30 may include a plurality of upper electrodes 30a to 30d and may have a fourth step structure formed along a first direction D1 on the connection region CNR. Each upper electrode 30a to 30d may have an upper pad region UP on the connection region CNR, as shown in the reference. Figure 4Described. Furthermore, the upper dummy stack structure 40, including multiple upper dummy electrodes 40a to 40c, can be laterally spaced from the upper stack structure 30 and can be disposed on the connection region CNR. In some embodiments, the upper dummy electrodes 40a to 40c can be electrically floated (e.g., electrically isolated from other components).

[0111] The technical features of the first and second electrode structures ST1 and ST2 can be compared with those in the reference. Figures 4 to 12C The technical features of the first and second electrode structures ST1 and ST2 described are essentially the same. Therefore, in this embodiment, the technical features are similar to those in… Figures 4 to 12C In the embodiments, the same elements will be indicated by the same reference numerals or the same reference symbols, and for ease of explanation and convenience, descriptions of them will be omitted or briefly mentioned.

[0112] In some embodiments, the lowest lower electrode among the lower electrodes 10a to 10d of the lower stacked structure 10 may correspond to a reference electrode. Figure 3 The described ground select line GSL is connected to the ground select transistor GST. In the upper stack structure 30, the higher of the upper electrodes 30a to 30d with the line shape can correspond to the reference. Figure 3 The described series select lines SSL1 and SSL2 are connected to series select transistors SST1 and SST2. In some embodiments, the two uppermost upper electrodes 30d can be used as series select lines SSL1 and SSL2. In the upper stack structure 30, the upper electrode (e.g., the second upper electrode 30c) disposed below the upper electrode (e.g., 30d) having a line shape can correspond to the reference. Figure 3 The described virtual word line DWL is connected to the virtual unit DMC. The lower electrodes 10b to 10d, intermediate electrodes 20a to 20d, and at least one upper electrode 30a, disposed between the second upper electrode 30b and the lowest lower electrode 10a, can correspond to a reference. Figure 3 The word lines WL0 to WLn are described as being connected to the memory cell MCT.

[0113] In some embodiments, the insulating pattern 50 may be disposed between the uppermost upper electrodes 30d that are horizontally spaced apart from each other. Furthermore, the insulating pattern 50 may extend downwards to be disposed between the third upper electrodes 30c and penetrate the second upper electrode 30b. The insulating pattern 50 may extend from the cell array region CAR to the connection region CNR in the first direction D1. The length of the insulating pattern 50 in the first direction D1 may be greater than the length of the upper electrodes with a linear shape (e.g., the uppermost upper electrode 30d or the third and fourth upper electrodes 30c and 30d) in the first direction D1.

[0114] Multiple interlayer insulating layers 60, 70 and 80 can cover the first and second electrode structures ST1 and ST2 on the substrate 1 of the cell array region CAR and the connection region CNR.

[0115] The lower contact plug LCP, the middle contact plug MCP, and the upper contact plug UCP can penetrate some of the interlayer insulation layers 60 and 70 on the connection area CNR to connect to the first and second electrode structures ST1 and ST2. In some embodiments, the contact plugs LCP, MCP, and UCP can be connected one-to-one to the vertically stacked electrodes 10a to 10d, 20a to 20d, and 30a to 30d in each of the first and second electrode structures ST1 and ST2.

[0116] refer to Figure 18 More specifically, the lower contact plug LCP can be connected to the reference respectively. Figure 4 The lower pad areas LP of the lower electrodes 10a to 10d are described. In each of the first and second electrode structures ST1 and ST2, the lower contact plug LCP can be disposed on the first and second stepped structures of the lower stack structure 10. In other words, the lower contact plug LCP can be arranged along the first direction D1 and the second direction D2 in a plan view. Because the lower contact plug LCP is disposed on the first and second stepped structures, the bottom surface of the lower contact plug LCP can be disposed at different distances / heights (or horizontally) from the substrate 1. The top surfaces of the lower contact plug LCP can be substantially coplanar with each other, such as... Figure 19 As shown.

[0117] Interconnects can be individually connected to lower contact plugs (LCPs), which are connected to lower electrodes 10a to 10d located at different levels. In some embodiments, multiple lower contact plugs (LCPs) can be connected to one of the lower electrodes 10a to 10d on the connection region CNR. In this case, the multiple lower contact plugs (LCPs) can be connected together to a single interconnect.

[0118] The intermediate contact plug MCP can be connected to the reference respectively. Figure 4 The intermediate pad regions MP of the intermediate electrodes 20a to 20d are described. In each of the first and second electrode structures ST1 and ST2, intermediate contact plugs MCP can be disposed on the third step structure of each intermediate stack structure 20. The third step structure can be formed along the second direction D2, so that the intermediate contact plugs MCP connected to each intermediate stack structure 20 can be arranged in the second direction D2 in plan view. Because the sidewalls of the intermediate stack structure 20 are horizontally spaced apart from each other in the first direction D1, the intermediate contact plugs MCP of the intermediate stack structure 20 can also be arranged in the first direction D1.

[0119] Because the intermediate contact plugs (MCPs) are respectively connected to intermediate electrodes 20a to 20d located at different levels (e.g., distance / height), the vertical lengths (i.e., lengths in the third direction D3) of the intermediate contact plugs (MCPs) can be different from each other. For example, the bottom surfaces of the intermediate contact plugs (MCPs) can be located at different levels (e.g., distance / height) from the substrate 1, and the top surfaces of the intermediate contact plugs (MCPs) can be as follows: Figure 19 The surfaces shown are essentially coplanar. Interconnects can be connected to the intermediate contact plugs (MCPs) individually.

[0120] The upper contact plug UCP can be connected to the reference respectively. Figure 4 The upper pad regions UP of the upper electrodes 30a to 30d are described. In some embodiments, a pair of upper contact plugs UCP can be connected to each upper pad region UP. The upper contact plugs UCP can be disposed on the fourth step structure of the upper stack structure 30. Because the fourth step structure is formed along the first direction D1, upper contact plugs UCP having different vertical lengths from each other can be arranged as follows: Figure 19 The upper contact plugs (UCPs) are arranged as shown in the first direction D1. The bottom surfaces of the upper contact plugs (UCPs) can be located at different levels (e.g., distance / height) from the substrate 1, and the top surfaces of the upper contact plugs (UCPs) can be substantially coplanar with each other. Interconnects can be connected to the upper contact plugs (UCPs) respectively.

[0121] In addition, the dummy contact plug DCP can be connected to the reference respectively. Figure 5 The upper dummy electrodes 40a to 40c are described. Meanwhile, the positions of the lower contact plug LCP, the intermediate contact plug MCP, and the upper contact plug UCP are not limited to... Figure 18 The implementation method is not fixed, but can vary in different ways.

[0122] In some embodiments, the vertical channel VS and the dummy vertical channel DVS can be configured as first and second electrode structures ST1 and ST2 penetrating the substrate 1 of the cell array region CAR. The vertical channel VS and the dummy vertical channel DVS can extend in a third direction D3 substantially perpendicular to the top surface of the substrate 1. A bit line BL extending in a second direction D2 can be disposed on the cell array region CAR. The bit line BL can be electrically connected to the vertical channel VS. The structure of the cell array region CAR of a 3D semiconductor memory device according to some embodiments will be referred to... Figures 20 to 26 It was described in more detail.

[0123] Figure 20 This is a plan view illustrating a cell array region of a 3D semiconductor memory device according to some embodiments of the concept of the present invention. Figure 21 and 22 They are along Figure 20The cross-sectional views taken by lines I-I' and II-II' are used to illustrate 3D semiconductor memory devices according to some embodiments of the concept of the present invention. Figure 23 yes Figure 21 A magnified view of part 'A'.

[0124] refer to Figure 20 , 21 22, vertical channels VS1 to VS4 and dummy vertical channels DVS can be disposed on substrate 1 of cell array region CAR and can extend in the third direction D3. Vertical channels VS1 to VS4 and dummy vertical channels DVS can penetrate each of the first and second electrode structures ST1 and ST2 described above.

[0125] Specifically, the first to fourth vertical channels VS1 to VS4 can penetrate each of the uppermost upper electrodes 30d. In some embodiments, in a plan view, the first to fourth vertical channels VS1 to VS4 can be arranged in a zigzag pattern along the first direction D1. A dummy vertical channel DVS can penetrate each of the first and second electrode structures ST1 and ST2 between the uppermost upper electrodes 30d. In other words, the dummy vertical channel DVS can be arranged along the first direction D1 in a plan view.

[0126] In some implementations, the first to fourth vertical channels VS1 to VS4 and the dummy vertical channel DVS can penetrate the reference. Figures 7A to 7D and Figures 9A to 9D Each electrode portion EP of the lower electrodes 10a to 10d and the intermediate electrodes 20a to 20d is described. Furthermore, a dummy vertical channel (DVS) can penetrate the isolation insulation pattern 50 on the cell array region CAR.

[0127] In some embodiments, the first to fourth vertical channels VS1 to VS4 and the dummy vertical channel DVS may comprise substantially the same material and may have substantially the same structure. For example, the first to fourth vertical channels VS1 to VS4 and the dummy vertical channel DVS may have a hollow tube shape or a hollow macaroni shape. In some embodiments, the first to fourth vertical channels VS1 to VS4 and the dummy vertical channel DVS may have a cylindrical shape.

[0128] The first to fourth vertical channels VS1 to VS4 and the dummy vertical channel DVS may comprise semiconductor or conductive materials. In some embodiments, the bottom surface of the first to fourth vertical channels VS1 to VS4 may be disposed at a horizontal position between the top and bottom surfaces of the substrate 1. Contact pads may be disposed at the top of each of the first to fourth vertical channels VS1 to VS4 and may be electrically connected to the bit line contact plug BPLG.

[0129] In some implementations, each of the first to fourth vertical channels VS1 to VS4 and the dummy vertical channel DVS may include, for example: Figure 23 The lower semiconductor pattern LSP and upper semiconductor pattern USP are shown. In some embodiments, the lower semiconductor pattern LSP and upper semiconductor pattern USP may comprise silicon (Si), germanium (Ge), or mixtures thereof, and may have crystal structures different from each other. Each lower semiconductor pattern LSP and upper semiconductor pattern USP may have a crystal structure including at least one of a single-crystal structure, an amorphous structure, or a polycrystalline structure. The lower semiconductor pattern LSP and upper semiconductor pattern USP may be undoped, or may be doped with a dopant having the same conductivity type as the dopant of substrate 1.

[0130] refer to Figure 23 More specifically, the lower semiconductor pattern LSP can be in direct contact with the substrate 1 and can penetrate the lowest electrode 10a. The upper semiconductor pattern USP can include a first semiconductor pattern SP1 and a second semiconductor pattern SP2. The first semiconductor pattern SP1 can be connected to the lower semiconductor pattern LSP and can have a tube or macaroni shape with a closed bottom end. The interior of the first semiconductor pattern SP1 can be filled with an insulating pattern VI. The first semiconductor pattern SP1 can be in contact with the inner sidewall of the second semiconductor pattern SP2 and the top surface of the lower semiconductor pattern LSP. In other words, the first semiconductor pattern SP1 can be electrically connected to the second semiconductor pattern SP2 to the lower semiconductor pattern LSP. The second semiconductor pattern SP2 can have a tube or macaroni shape with its top and bottom ends open. The second semiconductor pattern SP2 can not be in contact with the lower semiconductor pattern LSP, but can be spaced apart from the lower semiconductor pattern LSP.

[0131] In some embodiments, a data storage layer DS may be disposed between each electrode structure ST1 and ST2 and each vertical channel VS1 to VS4. The data storage layer DS may include a vertical insulating layer VL penetrating each electrode structure ST1 and ST2, and horizontal insulating layers HL extending from between the vertical insulating layer VL and each electrode 10a and 10b to the top and bottom surfaces of each electrode 10a and 10b, such as... Figure 23 As shown. The thermal oxide layer 13 can be disposed between the bottommost electrode 10a and the lower semiconductor pattern LSP.

[0132] In some embodiments, the 3D semiconductor memory device according to some embodiments of the present invention may be a NAND flash memory device. In this case, the data storage layer DS may include a tunnel insulating layer, a charge storage layer, and a barrier insulating layer. The data stored in the data storage layer DS can be changed using Fowler-Nordheim tunneling caused by the voltage difference between each vertical channel VS1 to VS4 and each electrode of each electrode structure ST1 and ST2.

[0133] Refer again Figure 20 , 21 In the plan view, a common source region CSR can be provided in a substrate 1 disposed between the electrode portions of the electrodes. The common source region CSR can extend parallel to the first and second electrode structures ST1 and ST2 in a first direction D1. The common source region CSR can be formed by doping a portion of the substrate 1 with a dopant. The conductivity type of the common source region CSR can be different from the conductivity type of the substrate 1. For example, the common source region CSR can include an N-type dopant (e.g., arsenic (As) or phosphorus (P)).

[0134] A common source plug CSP can be connected to each common source region CSR, and a sidewall insulating spacer SP can be disposed between the common source plug CSP and each electrode structure ST1 and ST2. In some embodiments, the common source plug CSP can have a substantially uniform upper width and can extend in a first direction D1.

[0135] The first interlayer insulating layer 60 and the second interlayer insulating layer 70 can cover electrode structures ST1 and ST2, and auxiliary interconnects SBL can be disposed on the second interlayer insulating layer 70. Some auxiliary interconnects SBL can cross the isolation insulating pattern 50, and other auxiliary interconnects SBL can cross the common source plug CSP. Each auxiliary interconnect SBL can be electrically connected to adjacent vertical channels VS1, VS2, VS3, or VS4 in the second direction D2. The auxiliary interconnects SBL can extend longitudinally in the second direction D2. The length of some auxiliary interconnects SBL can be different from the length of other auxiliary interconnects SBL.

[0136] The third interlayer insulation layer 80 can be disposed on the second interlayer insulation layer 70 to cover the auxiliary interconnect line SBL, and the bit line BL can be disposed on the third interlayer insulation layer 80. The bit line BL can extend in the second direction D2 and can be electrically connected to the auxiliary interconnect line SBL through the bit line contact plug BPLG.

[0137] Figure 24 This is a cross-sectional view illustrating a cell array region of a 3D semiconductor memory device according to some embodiments of the present invention. Figure 25 yes Figure 24An enlarged view of part 'A'. In this embodiment, compared with the reference... Figures 20 to 22 The same elements described will be indicated by the same reference numerals or reference symbols, and for ease of explanation, descriptions of them will be omitted or briefly mentioned.

[0138] refer to Figure 24 and 25 The vertical channel VS can penetrate the first and second electrode structures ST1 and ST2 on the cell array region CAR. The vertical channel VS can penetrate the electrode structures ST1 and ST2 to be electrically connected to the substrate 1.

[0139] In some embodiments, each vertical channel VS may include a first semiconductor pattern SP1 that penetrates the electrode structure to contact the substrate 1 and a second semiconductor pattern SP2 disposed between the electrode structure and the first semiconductor pattern SP1.

[0140] Specifically, the first semiconductor pattern SP1 can have a hollow tube shape or a hollow macaron shape. The bottom end of the first semiconductor pattern SP1 can be closed, and the internal space of the first semiconductor pattern SP1 can be filled with an insulating pattern VI. In some embodiments, the first semiconductor pattern SP1 can have a column shape with a circular horizontal cross-section. The first semiconductor pattern SP1 can contact the inner sidewall of the second semiconductor pattern SP2 and the substrate 1. In other words, the first semiconductor pattern SP1 can electrically connect the second semiconductor pattern SP2 to the substrate 1. The bottom surface of the first semiconductor pattern SP1 can be positioned at a level lower than the top surface of the substrate 1.

[0141] The second semiconductor pattern SP2 may have a tube or macaroni shape with its top and bottom ends open. The bottom surface of the second semiconductor pattern SP2 may be higher than the bottom surface of the first semiconductor pattern SP1 and may be spaced apart from the substrate 1. In some embodiments, the second semiconductor pattern SP2 may be in direct contact with the substrate 1.

[0142] The first and second semiconductor patterns SP1 and SP2 can be undoped or doped with dopants having the same conductivity type as the substrate 1. The first and second semiconductor patterns SP1 and SP2 can be in a polycrystalline or monocrystalline state.

[0143] Figure 26 This is a cross-sectional view illustrating a cell array region of a 3D semiconductor memory device according to some embodiments of the present invention. In this embodiment, compared with reference... Figures 20 to 22 The same elements described will be indicated by the same reference numerals or reference symbols, and for ease of explanation, descriptions of them will be omitted or briefly mentioned.

[0144] refer to Figure 26 The channel structure CHS can penetrate the first and second electrode structures ST1 and ST2 on the cell array region CAR.

[0145] In some embodiments, each channel structure CHS may include first and second vertical channels VSa and VSb penetrating the electrode structure ST1, and a horizontal channel HS disposed below the electrode structure ST1 to connect the first and second vertical channels VSa and VSb to each other. The first and second vertical channels VSa and VSb may be provided in vertical holes penetrating the electrode structure ST1. The horizontal channel HS may be provided in a recessed region formed in the upper portion of the substrate 1. The horizontal channel HS may be disposed between the substrate 1 and the electrode structure ST1 to electrically connect the first and second vertical channels VSa and VSb to each other.

[0146] In some embodiments, the horizontal channel HS can have a hollow tube or macaroni shape continuously connected to the vertical channels VSa and VSb. In other words, the vertical channels VSa and VSb and the horizontal channel HS can form a single tube shape. That is, the vertical channels VSa and VSb and the horizontal channel HS can form a continuous semiconductor layer without interfaces. Here, the semiconductor layer can be formed of a semiconductor material having a crystal structure including at least one of a single crystal structure, an amorphous structure, or a polycrystalline structure. Furthermore, a data storage layer DS can be disposed between each channel structure CHS and the electrode, as described above.

[0147] According to some implementations, in each channel structure CHS, a first vertical channel VSa can be connected to the bit line BL and a second vertical channel VSb can be connected to the common source line CSL. The channel structures CHS can be electrically isolated from each other, and the potential of the channel structures CHS comprising semiconductor material can be controlled by electrode structures ST1 and ST2. Therefore, a current path can be formed between the bit line BL and the common source line CSL through each channel structure CHS.

[0148] Figures 27 to 35 This is a perspective view illustrating a method for manufacturing an electrode structure of a 3D semiconductor memory device according to some embodiments of the concept of the present invention. According to some embodiments, reference is made to... Figures 1 to 26 The described electrode structure can be fabricated using the patterning method described below. In other words, refer to... Figures 1 to 26 The lower electrodes 10a to 10d, the intermediate electrodes 20a to 20d, and the upper electrodes 30a to 30d described herein can be structures formed using the patterning method described below.

[0149] refer to Figure 27The thin-layer structure 100 can be formed on a substrate 1 including a cell array region CAR and a connection region CNR. The thin-layer structure 100 can include a horizontal layer HL and an insulating layer ILD that are vertically and alternately stacked on the substrate 1. In other words, the horizontal layer HL and the insulating layer ILD can be alternately stacked on a third direction D3.

[0150] The horizontal layers HL can be formed of a material that is etch-selective relative to the insulating layers ILD. For example, each insulating layer ILD can be a silicon oxide layer, and each horizontal layer HL can include at least one of a silicon nitride layer, a silicon oxide nitride layer, a polysilicon layer, or a metal layer. In some embodiments, the horizontal layers HL can be formed of the same material.

[0151] refer to Figures 27 to 29 The upper structure UST and multiple upper dummy structures DST can be formed on the thin layer structure 100.

[0152] In some embodiments, forming the upper structure UST and the upper dummy structure DST may include: forming an upper thin-layer structure including an upper horizontal layer UHL vertically stacked on the thin-layer structure 100; forming a first mask pattern MP1 on the upper thin-layer structure; performing a first etching process using the first mask pattern MP1 as an etching mask to etch a portion of the upper thin-layer structure; and performing a first trimming process to reduce the area (e.g., surface area) of the first mask pattern MP1. Here, the first etching process and the first trimming process may be repeated alternately once or multiple times.

[0153] For details, please refer to Figure 27 The upper thin-layer structure may include an insulating layer ILD and an upper horizontal layer UHL alternately stacked on the thin-layer structure 100. The upper horizontal layer UHL may be formed of the same material as the horizontal layer HL and may be stacked with the same vertical pitch as the horizontal layer HL. Here, the vertical pitch of the horizontal layer HL may refer to the vertical distance between the top surfaces of the horizontal layers HL that are vertically adjacent to each other. In other words, the vertical pitch of the horizontal layer HL may refer to the distance between the top surfaces of the horizontal layers HL that are vertically adjacent to each other in the third direction D3. It will be understood that there is no horizontal layer HL between the horizontal layers HL that are vertically adjacent to each other. In some embodiments, when Figure 5 When the number of electrodes included in each of the intermediate stacked structures 20 is n and "n" is a natural number equal to or greater than 2, the number of upper horizontal UHL layers can be n-1.

[0154] The first mask pattern MP1 may expose a portion of the upper thin-layer structure on the connection region CNR. In some embodiments, the first mask pattern MP1 may include a first portion MP1a and a second portion MP1b. The first portion MP1a may cover the cell array region CAR and a portion of the connection region CNR. The second portion MP1b may be spaced apart from the first portion MP1a and may cover other portions of the connection region CNR. The second portions MP1b may have an island shape on the upper thin-layer structure and may be spaced apart from each other in the second direction D2. According to some embodiments, the width and spacing of the second portions MP1b may depend on a reference. Figure 4 and 5 The vertical pitch and horizontal pitch of the pad areas of the described electrode structure are determined. The vertical pitch of the pad areas can refer to the vertical distance between adjacent pad areas, and the horizontal pitch of the pad areas can refer to the horizontal distance between adjacent pad areas. For example, forming the first mask pattern MP1 may include coating the entire top surface of the thin-layer structure with a first photoresist layer and performing an exposure process and a development process on the first photoresist layer.

[0155] refer to Figure 28 The first etching process can use a first mask pattern MP1 as an etching mask to etch a portion of the upper thin layer structure. For example, the first etching process can etch the upper thin layer structure to a first etching depth corresponding to the vertical pitch of the upper horizontal layer UHL. Here, the vertical pitch of the upper horizontal layer UHL can refer to the vertical distance between the top surfaces of upper horizontal layer UHLs that are vertically adjacent to each other. In other words, the vertical pitch of the upper horizontal layer UHL can refer to the distance between the top surfaces of upper horizontal layer UHLs that are vertically adjacent to each other in the third direction D3.

[0156] For example, an upper horizontal layer UHL can be etched using a first etching process, thus forming an upper horizontal pattern UHP and an upper dummy pattern DHP. The upper horizontal pattern UHP can cover the cell array region CAR and a portion of the connection region CNR. The upper dummy pattern DHP can be spaced apart from the upper horizontal pattern UHP and can be disposed on the connection region CNR. Furthermore, the upper dummy patterns DHP can be spaced apart from each other on the connection region CNR.

[0157] refer to Figure 28 A first trimming process can be performed to reduce the area of ​​the first mask pattern MP1. The first trimming process can expand the area exposed by the first mask pattern MP1, so that portions of the upper horizontal pattern UHP and the upper dummy pattern DHP formed in the above process can be exposed.

[0158] The first trimming process can laterally move the sidewalls of the first and second portions MP1a and MP1b of the first mask pattern MP1 by a predetermined distance in the first direction D1 and the second direction D2. Here, the lateral movement distance of the sidewalls of the first mask pattern MP1 can correspond to the above reference. Figure 5 The width of the intermediate pad region MP of the intermediate electrodes 20a to 20d in the second direction D2 is described. For example, the first trimming process can be performed using an isotropic dry etching method or a wet etching method. Furthermore, because the entire surface of the first mask pattern MP1 is etched during the first trimming process, the top surface of the first mask pattern MP1 can be recessed. In other words, the area and thickness of the first mask pattern MP1 can be reduced by the first trimming process.

[0159] Subsequently, the first etching process and the first trimming process can be performed alternately and repeatedly. The number of repetitions of the first etching process and the first trimming process can vary depending on the number of horizontal layers HL stacked on the substrate 1. For example, the number of repetitions of the first etching process and the first trimming process can be based on the composition of the above reference. Figure 5 The number of intermediate electrodes 20a to 20d in the described intermediate stack structure 20 varies. For example, when the number of intermediate electrodes 20a to 20d in each intermediate stack structure 20 is n, where "n" is a natural number equal to or greater than 2, the number of repetitions can be n-1.

[0160] Because the first etching process and the first trimming process are repeated alternately, the upper horizontal layer UHL can be as follows: Figure 29 The layers are sequentially etched as shown. Thus, the upper structure UST and the plurality of upper dummy structures DST can be formed on the thin layer structure 100. In some embodiments, the upper structure UST may include vertically stacked upper horizontal patterns UHP. Each upper dummy structure DST may include vertically stacked upper dummy patterns DHP. The trimmed first mask pattern MP1t may be removed after the upper structure UST and upper dummy structures DST are formed.

[0161] In detail, the upper horizontal pattern UHP can cover the cell array region CAR and can have a stepped structure formed along the first direction D1 on the thin layer structure 100 of the connection region CNR. The length of the upper horizontal pattern UHP in the first direction D1 can sequentially decrease with increasing vertical distance from the substrate 1. The end portions of the upper horizontal pattern UHP can be exposed on the connection region CNR. The horizontal distances, each corresponding to the horizontal distance between the sidewalls of the upper horizontal pattern UHP that are vertically adjacent to each other, can be substantially equal to each other. Therefore, the upper structure UST can have a stepped structure formed along the first direction D1, and the height of the step of the stepped structure of the upper structure UST can correspond to the vertical pitch of the horizontal layer HL.

[0162] The upper dummy pattern DHP may have a length in a first direction D1 and a width in a second direction D2. In each upper dummy structure DST, the length and width of the upper dummy pattern DHP may decrease sequentially with increasing vertical distance from the substrate 1. In some embodiments, the horizontal distance between the first sidewalls of the upper dummy pattern DHP in the first direction D1 may be substantially equal to the horizontal distance between the second sidewalls of the upper dummy pattern DHP in the second direction D2. The length of each upper dummy pattern DHP in the first direction D1 may be greater than the width of each upper dummy pattern DHP in the second direction D2.

[0163] The upper dummy structure DST can have a substantially pyramidal shape. Therefore, each upper dummy structure DST can have a first stepped structure S1 formed in a first direction D1 and a second stepped structure S2 formed in a second direction D2 on the connecting region CNR. The height of the steps of the first and second stepped structures S1 and S2 can correspond to the vertical pitch of the horizontal layer HL.

[0164] refer to Figure 30 The second mask pattern MP2 can be formed to expose portions of the upper dummy structure DST and a portion of the thin layer structure 100. The second mask pattern MP2 can expose portions of the upper dummy structure DST in the first direction D1 and the second direction D2. In other words, a portion of the first stepped structure formed in the upper dummy structure DST in the first direction D1 and a portion of the second stepped structure formed in the second direction D2 can be exposed by the second mask pattern MP2. In some embodiments, forming the second mask pattern MP2 may include forming a second photoresist layer covering the entire surface of the structure formed on the substrate 1, and performing exposure and development processes on the second photoresist layer.

[0165] Subsequently, a second etching process can be performed using the second mask pattern MP2 as an etching mask to etch the upper dummy structure DST and the thin layer structure 100 to a second etching depth. The second etching depth of the second etching process can be equal to or greater than twice the vertical pitch of the horizontal layers HL. In other words, at least two portions of the upper dummy pattern DHP and at least two portions of the horizontal layers HL can be etched by the second etching process. For example, when the number of intermediate electrodes 20a to 20d in each intermediate stack structure 20 is n, where "n" is a natural number equal to or greater than 2, n horizontal layers HL can be etched by the second etching process. For example, four horizontal layers HL can be etched by the second etching process.

[0166] like Figure 31As shown, the end portions of the upper dummy structure DST can be etched by a second etching process, thus reducing the length of the upper dummy structure DST in the first direction D1. Consequently, in each upper dummy structure DST, the upper dummy pattern DHP can have sidewalls that are substantially vertically aligned with each other. In other words, during the second etching process, the first stepped structure of the upper dummy structure DST in the first direction D1 can be etched and transferred to a portion of the thin layer structure 100. Therefore, a lower structure LST having stepped structures in the first direction D1 and the second direction D2 can be formed below the upper dummy structure DST. The lower structure LST can include multiple lower horizontal patterns LHP, the end portions of which can form stepped structures in the first direction D1 and the second direction D2.

[0167] Following the second etching process, a second trimming process can be performed on the second mask pattern MP2. This second trimming process expands the area exposed by the second mask pattern MP2, thus exposing portions of the lower structure LST and the upper dummy structure DST formed in the aforementioned process. In other words, the trimmed second mask pattern MP2 can expose portions of the second stepped structure of the upper dummy structure DST, such as... Figure 31 As shown.

[0168] The second trimming process can laterally move the sidewalls of the second mask pattern MP2 by a predetermined distance in the first direction D1, thereby reducing the area (e.g., surface area) of the second mask pattern MP2. Here, the lateral movement distance of the sidewalls of the second mask pattern MP2 can correspond to the length of the intermediate pad region MP of the intermediate electrodes 20a to 20d described above in the first direction D1. For example, the second trimming process can be performed using an isotropic dry etching method or a wet etching method. Furthermore, because the entire surface of the second mask pattern MP2 is etched during the second trimming process, the top surface of the second mask pattern MP2 can be recessed. In other words, the area and thickness of the second mask pattern MP2 can be reduced by the second trimming process.

[0169] The second etching process can use the modified second mask pattern MP2t as the etching mask to etch part of the lower structure LST and part of the upper dummy structure DST. Therefore, as Figure 32As shown, a portion of the second stepped structure of the upper dummy structure DST can be transferred to the preceding lower structure LST to form the intermediate structure MST, and the lower structure LST can be formed below the intermediate structure MST. The intermediate structure MST may include multiple intermediate horizontal patterns MHP. The end portions of the intermediate horizontal patterns MHP can be arranged in the second direction D2 in the plan view and can be exposed. Furthermore, the sidewalls of the intermediate horizontal patterns MHP of the intermediate structure MST, which are substantially parallel to the second direction D2, can be aligned substantially vertically with each other by a second etching process. In other words, the intermediate structure MST may have a second stepped structure formed in the second direction D2. The end portions of the lower horizontal patterns LHP of the lower structure LST formed below the intermediate structure MST can form a stepped structure in the first direction D1 and the second direction D2.

[0170] Subsequently, a second trimming process can be performed. Then, the second etching process and the second trimming process can be performed alternately and repeatedly. The number of repetitions of the second etching process and the second trimming process can vary depending on the number of horizontal layers HL stacked on the substrate 1. For example, the number of repetitions of the second etching process and the second trimming process can correspond to the number of intermediate stacked structures 20 included in each electrode structure ST1 and ST2.

[0171] Because the second etching process and the second trimming process are repeated alternately, the length of the upper dummy structure DST in the first direction D1 can be reduced, such as... Figure 33 As shown. Multiple intermediate structures MST can be formed below the upper dummy structure DST, and the lower structure LST can be formed below the lowest intermediate structure among the intermediate structures MST. In other words, the stacked structure 200 can be formed with a stepped structure on the connection region CNR. The stacked structure 200 may include the lower structure LST, the multiple intermediate structures MST, and the upper structure UST. After forming the stacked structure 200, the trimmed second mask pattern MP2t can be removed to expose the upper structure UST.

[0172] In some embodiments, the end portions of the lower horizontal pattern LHP of the lower structure LST can form a first stepped structure in a first direction and a second stepped structure in a second direction on the connecting region CNR. In each intermediate structure MST, the end portions of the intermediate horizontal pattern MHP can form a third stepped structure in the second direction D2. The end portions of the upper horizontal pattern UHP of the upper structure UST can form a fourth stepped structure in the first direction D1. Furthermore, the stacked structure 200 may include an upper dummy pattern DHP spaced apart from the upper structure UST and formed on the uppermost intermediate structure in the intermediate structure MST.

[0173] refer to Figure 34The third mask pattern MP3 can be formed on the stacked structure 200 having first to fourth step structures. Each third mask pattern MP3 can include a line portion MP3a and a connecting portion MP3b. The line portions MP3a can extend in a first direction D1 in a planar view and can be spaced apart from each other in a second direction D2. The connecting portions MP3b can extend in the second direction D2 to connect the line portions MP3a to each other. In some embodiments, the connecting portions MP3b of the third mask pattern MP3 can be located on the upper structure UST.

[0174] The stacked structure 200 can be etched using a third mask pattern MP3 as an etching mask to form a first trench T1, a second trench T2, and a third trench T3. The first trench T1 divides the stacked structure 200 into multiple electrode structures ST1 and ST2. The second trench T2 can extend in the first direction D1 on the cell array region CAR and can be shorter than the first trench T1. The third trench T3 can be spaced apart from the second trench T2 and can extend in the first direction D1 on the connection region CNR. Therefore, the electrode structures ST1 and ST2 can be... Figure 35 The electrode structures ST1 and ST2 are formed as shown. They can extend in a first direction D1 and can be spaced apart from each other in a second direction D2. When the horizontal patterns UHP, MHP, and LHP are formed of a conductive material, the horizontal patterns UHP, MHP, and LHP can correspond to electrodes. In some embodiments, when the horizontal patterns UHP, MHP, and LHP are formed of an insulating material, a replacement process can be performed to replace the horizontal patterns UHP, MHP, and LHP with electrodes formed of a conductive material. In this case, the upper dummy pattern DHP can be replaced with a conductive pattern. Each electrode of the electrode structures ST1 and ST2 can have an H-shape in the planar view.

[0175] Figures 36 to 41 This is a perspective view illustrating a method for manufacturing an electrode structure according to some embodiments of the concept of the present invention.

[0176] refer to Figure 36 and 37 The thin-layer structure 100 can be formed on a substrate 1 including a cell array region CAR and a connection region CNR, and the upper structure can be formed to expose a portion of the thin-layer structure 100 on the connection region CNR. The thin-layer structure 100 may include an insulating layer ILD and a horizontal layer HL alternately stacked on a third direction D3, as described above.

[0177] In some embodiments, forming the upper structure may include: forming an upper thin-layer structure including an upper horizontal layer UHL vertically stacked on the thin-layer structure 100; forming a first mask pattern MP1 on the upper thin-layer structure; performing a first etching process using the first mask pattern MP1 as an etching mask to etch a portion of the upper thin-layer structure; and performing a first trimming process to reduce the area (e.g., surface area) of the first mask pattern MP1. Here, the first etching process and the first trimming process may be repeated alternately once or more.

[0178] In some embodiments, the first mask pattern MP1 may have an opening OP that exposes a portion of the upper horizontal layer UHL on the connection region CNR. The width and length of the opening OP of the first mask pattern MP1 can be determined according to a reference. Figure 4 and 5 The vertical and horizontal pitches of the pad areas of the described electrode structure were determined.

[0179] Subsequently, a first etching process can be performed using the first mask pattern MP1 as an etching mask to etch a portion of the upper thin-layer structure to a first etching depth, as described above. For example, the first etching depth can be substantially equal to the vertical pitch of the horizontal layer HL. The upper horizontal pattern UHP with an opening on the connection region CNR can be formed by performing the first etching process.

[0180] The first trimming process can be performed on the first mask pattern MP1 after the first etching process, thus increasing the area (e.g., surface area) of the upper horizontal layer UHL exposed through the first mask pattern MP1. That is, the width and length of the opening OP can be increased by the first trimming process. In other words, the sidewalls of the opening OP can be moved horizontally in the first direction D1 and the second direction D2 by the first trimming process. As a result, a portion of the upper horizontal pattern UHP can be exposed through the opening OP of the trimmed first mask pattern MP1t.

[0181] Next, the first etching process and the first trimming process can be performed alternately and repeatedly on the upper thin-layer structure. Therefore, an upper structure UST including multiple upper horizontal patterns UHP can be formed on the thin-layer structure 100, such as... Figure 37 As shown. The upper horizontal pattern UHP can have an opening 101 on the connection area CNR. As described above, the number of repetitions of the first etching process and the first trimming process can vary depending on the number of horizontal layers HL stacked on the substrate 1. For example, the number of repetitions of the first etching process and the first trimming process can be based on the composition of the above reference. Figure 4 and 5The number of intermediate electrodes 20a to 20d in the described intermediate stack structure 20 varies. For example, when the number of intermediate electrodes 20a to 20d in each intermediate stack structure 20 is n, where "n" is a natural number equal to or greater than 2, the number of repetitions can be n-1.

[0182] The width and length of the opening 101 of the upper horizontal pattern UHP can increase sequentially with the increase of the vertical distance from the substrate 1. In other words, each upper horizontal pattern UHP can expose a portion of the upper horizontal pattern UHP or the horizontal layer HL disposed thereunder. Thus, the upper structure UST can have a first stepped structure formed along the first direction D1 and a second stepped structure formed along the second direction D2 on the connection area CNR.

[0183] refer to Figure 38 The second mask pattern MP2 can be formed to expose a portion of the upper structure UST. The second mask pattern MP2 can expose portions of the first and second stepped structures of the upper structure UST on the connection region CNR. In other words, the second mask pattern MP2 can fill a portion of the opening formed in each upper horizontal pattern UHP.

[0184] refer to Figure 39 The second mask pattern MP2 can be used as an etching mask for a second etching process to etch the upper structure UST and the thin layer structure 100 to a second etching depth. The second etching depth of the second etching process can be equal to or greater than twice the vertical pitch of the horizontal layer HL, as described above. In other words, portions of at least two upper horizontal patterns UHP and portions of at least two horizontal layers HL can be etched by the second etching process. In some embodiments, when the number of intermediate electrodes 20a to 20d of each intermediate stack structure 20 is n, where "n" is a natural number equal to or greater than 2, n horizontal layers HL can be etched by the second etching process. For example, four horizontal layers HL can be etched as follows: Figure 39 The area shown is etched by a second etching process.

[0185] The exposed portions of the first and second stepped structures of the upper structure UST can be etched by a second etching process, thus allowing the upper horizontal pattern UHP to have sidewalls that are substantially vertically aligned with each other and substantially parallel to the second direction D2, such as... Figure 39As shown. Furthermore, the exposed portions of the first and second stepped structures can be transferred to the horizontal layer HL via a second etching process, thus allowing the lower structure LST to be formed beneath the upper structure UST. The lower structure LST may include a plurality of lower horizontal patterns LHP, and each lower horizontal pattern LHP may have an opening 103 on the connection region CNR. The opening 103 of each lower horizontal pattern LHP may expose a portion of the lower horizontal pattern LHP or the horizontal layer HL disposed thereunder. In other words, the width and length of the opening 103 may sequentially increase with increasing vertical distance from the substrate 1.

[0186] Subsequently, a second trimming process can be performed to reduce the area (e.g., surface area) of the second mask pattern MP2. The sidewalls of the second mask pattern MP2 can be laterally moved a predetermined distance in the first direction D1 during the second trimming process. Here, the lateral movement distance of the sidewalls of the second mask pattern MP2 can correspond to the length of the intermediate pad area MP of the intermediate electrodes 20a to 20d described above in the first direction D1. The trimmed second mask pattern MP2t can expose a portion of the second stepped structure of the upper structure UST and a portion of the lower structure LST.

[0187] Next, the second etching process can use the modified second mask pattern MP2 as the etching mask to etch part of the upper structure UST and part of the lower structure LST. Therefore, as... Figure 40 As shown, the exposed portion of the second stepped structure of the upper structure UST in the second direction D2 can be transferred to the preceding lower structure LST to form the intermediate structure MST, and the lower structure LST can be formed below the intermediate structure MST. As described above, the intermediate structure MST can include a plurality of intermediate horizontal patterns MHP. The end portions of the intermediate horizontal patterns MHP can be arranged in the second direction D2 in the plan view and can be exposed. In other words, the intermediate horizontal patterns MHP can have a stepped structure formed in the second direction D2. Furthermore, the sidewalls of the intermediate horizontal patterns MHP of the intermediate structure MST, which are substantially parallel to the second direction D2, can be aligned substantially vertically with each other by a second etching process. The end portions of the lower horizontal patterns LHP of the lower structure LST formed below the intermediate structure MST can form a stepped structure in the first direction D1 and the second direction D2.

[0188] Subsequently, a second trimming process can be performed on the trimmed second mask pattern MP2t. Then, the second etching process and the second trimming process can be repeated alternately at least two or more times. The number of repetitions of the second etching process and the second trimming process can vary depending on the number of horizontal layers HL stacked on the substrate 1.

[0189] Because the second etching process and the second trimming process are repeated alternately, the length of the upper structure UST in the first direction D1 can be reduced (e.g., monotonically reduced or gradually reduced), and multiple intermediate structures MST can be formed below the upper structure UST, such as... Figure 40 As shown. Furthermore, the lower structure LST can be formed below the lowest intermediate structure in the intermediate structure MST.

[0190] In some embodiments, the lowest horizontal pattern LHP may have an opening that exposes the substrate 1.

[0191] The top surface of substrate 1, exposed through the opening of the lowest horizontal pattern LHP, can be recessed by a second etching process. Therefore, substrate 1 of the connection region CNR can have a recessed area.

[0192] then, Figure 34 The third mask pattern MP3 can be formed on a stacked structure including a lower structure LST, an intermediate structure MST, and an upper structure UST, and the stacked structure can be etched using the third mask pattern MP3 as an etching mask to form electrode structures ST1 and ST2 spaced apart from each other in the second direction D2, such as... Figure 41 As shown.

[0193] Figure 42 , 43 Views 4 and 44 are views illustrating interconnects electrically connected to electrode structures of 3D semiconductor memory devices according to some embodiments of the present invention. In the following, for ease of explanation, descriptions of the same technical features as those described above will be omitted or briefly mentioned.

[0194] refer to Figure 42 , 43 44, the substrate 1 may include first and second connection regions CNR1 and CNR2 spaced apart from each other in the first direction D1, and a cell array region CAR disposed between the first and second connection regions CNR1 and CNR2.

[0195] First and second electrode structures ST1 and ST2 can be disposed on substrate 1. First and second electrode structures ST1 and ST2 can extend in a first direction D1 and can be alternately arranged along a second direction D2. First and second electrode structures ST1 and ST2 can be spaced apart from each other in the second direction D2 and can be electrically insulated from each other.

[0196] In some embodiments, each of the first and second electrode structures ST1 and ST2 may have a stepped structure on each of the first and second connection regions CNR1 and CNR2. In some embodiments, the first and second electrode structures ST1 and ST2 may be mirror-symmetrical about an imaginary line substantially parallel to the first direction D1. In other words, the first and second electrode structures ST1 and ST2 may include a reference on each of the first and second connection regions CNR1 and CNR2. Figure 4 and 5 The description includes the lower pad area LP, the middle pad area MP, and the upper pad area UP.

[0197] In some embodiments, an interconnect structure including a contact plug CP and an interconnect line CL1 or CL2 can be connected to each of the first and second electrode structures ST1 and ST2. The contact plug CP and the interconnect line CL1 or CL2 can be connected to each electrode of each electrode structure ST1 and ST2.

[0198] In some embodiments, some contact plugs CP may be disposed on the pad area of ​​the second electrode structure ST2 on the first connection area CNR1 (see...). Figure 4 On the LP, MP, and UP), and other contact plugs CP can be disposed on the pad area of ​​the first electrode structure ST1 on the second connection area CNR2 (see LP, MP, and UP). Figure 4 The contacts CP can be connected to the electrodes forming the second electrode structure ST2 on the first connection region CNR1. The other contacts CP can be connected to the electrodes forming the first electrode structure ST1 on the second connection region CNR2.

[0199] Furthermore, the second interconnect CL2 can be electrically connected to the second electrode structure ST2 via the contact plug CP on the first connection area CNR1, and the first interconnect CL1 can be electrically connected to the first electrode structure ST1 via the contact plug CP on the second connection area CNR2.

[0200] In some embodiments, the first interconnect CL1 and the second interconnect CL2 may be disposed at the same distance / height (or the same level) from the substrate 1. In some embodiments, the first interconnect CL1 may be divided into a plurality of first line groups, and the first line groups may be disposed at different levels from each other. Similarly, the second interconnect CL2 may be divided into a plurality of second line groups, and the second line groups may be disposed at different levels from each other.

[0201] In some embodiments, each of the first and second interconnects CL1 and CL2 may include a first portion extending in a first direction D1 and a second portion extending in a second direction D2. The first portions of the first and second interconnects CL1 and CL2 may be arranged at intervals in the second direction D2, and the second portions of the first and second interconnects CL1 and CL2 may respectively contact the contact plug CP. However, the inventive concept is not limited to the above-described shape and arrangement of the first and second interconnects CL1 and CL2. In some embodiments, the shape and arrangement of the interconnects CL1 and CL2 may be varied.

[0202] The first interconnect line CL1 connected to the first electrode structure ST1 may overlap a portion of the second electrode structure ST2 in the plan view. The second interconnect line CL2 connected to the second electrode structure ST2 may overlap a portion of the first electrode structure ST1 in the plan view.

[0203] Figure 45 , 46 Views 4 and 47 are views illustrating the electrode structure of a 3D semiconductor memory device according to some embodiments of the present invention. In the following, for ease of explanation, descriptions of the same technical features as those described in the embodiments above will be omitted or briefly mentioned.

[0204] refer to Figure 45 and 46 The substrate 1 may include first and second connection regions CNR1 and CNR2, and a cell array region CAR disposed between the first and second connection regions CNR1 and CNR2. In some embodiments, a plurality of first cell array blocks BLK1 and a plurality of second cell array blocks BLK2 may be disposed on the substrate 1. The first and second cell array blocks BLK1 and BLK2 may be arranged alternately in a second direction D2. Each of the first and second cell array blocks BLK1 and BLK2 may include a pair of electrode structures ST1 and ST2, i.e., a first electrode structure ST1 and a second electrode structure ST2.

[0205] The first and second electrode structures ST1 and ST2 can extend on the substrate 1 in a first direction D1 and can be spaced apart from each other in a second direction D2. As described above, each of the first and second electrode structures ST1 and ST2 may include a lower stacked structure 10, an upper stacked structure 30, and a plurality of intermediate stacked structures 20 stacked between the lower stacked structure 10 and the upper stacked structure 30.

[0206] In some embodiments, each of the electrode structures ST1 and ST2 of the first connection region CNR1 and each of the electrode structures ST1 and ST2 of the second connection region CNR2 may be asymmetrical about the cell array region CAR. Specifically, each of the first and second electrode structures ST1 and ST2 may have a first stepped structure S1 formed on each of the first and second connection regions CNR1 and CNR2 in a first direction D1, and may have a second stepped structure S2 formed on one of the first and second connection regions CNR1 and CNR2 in a second direction D2. The second stepped structures S2 of the adjacent first and second electrode structures ST1 and ST2 may be mirror-symmetrical about an imaginary line substantially parallel to the first direction D1.

[0207] For example, the first and second electrode structures ST1 and ST2 of the first unit array block BLK1 may have a second stepped structure S2 formed on the second connection region CNR2 in the second direction D2. The first and second electrode structures ST1 and ST2 of the second unit array block BLK2 may have a second stepped structure S2 formed on the first connection region CNR1 in the second direction D2.

[0208] According to this embodiment, the second stepped structures S2 of the first unit array blocks BLK1, which are disposed at substantially the same level on the second connection region CNR2, can be laterally spaced apart from each other in the second direction D2. Similarly, the second stepped structures S2 of the second unit array blocks BLK2, which are disposed at substantially the same level on the first connection region CNR1, can be laterally spaced apart from each other in the second direction D2.

[0209] In some embodiments, in each first unit array block BLK1, the lower stack structure 10 of the first and second electrode structures ST1 and ST2 may have first and second stepped structures S1 and S2 formed in the first and second directions D1 and D2 respectively by the end portions of the lower electrodes on the second connection region CNR2. Furthermore, on the first connection region CNR1, at least two lower electrodes of the lower stack structure 10 of the first unit array block BLK1 may have sidewalls that are substantially vertically aligned with each other.

[0210] In each first unit array block BLK1, the intermediate stacked structure 20 of the first and second electrode structures ST1 and ST2 may have a third stepped structure S3 formed on the second connection region CNR2 through the end portions of the intermediate electrodes in the second direction D2. Furthermore, on the first connection region CNR1, at least two intermediate electrodes of the first unit array block BLK1 may have sidewalls that are substantially vertically aligned with each other.

[0211] In each of the first and second unit array blocks BLK1 and BLK2, the upper stacked structure 30 of the first and second electrode structures ST1 and ST2 may have a stepped structure formed in the first direction D1. Furthermore, the stepped structure of the upper stacked structure 30 of the first connection region CNR1 and the stepped structure of the upper stacked structure 30 of the second connection region CNR2 may be symmetrical about the unit array region CAR. Additionally, the upper dummy stacked structure 40 may be disposed on the end portion of the lowermost upper electrode in the upper electrode of the upper stacked structure 30.

[0212] In some implementations, because the second stepped structures S2 of electrode structures ST1 and ST2 are laterally spaced apart from each other on the first connection region CNR1, the process margin for forming the contact plugs and interconnects connected to electrode structures ST1 and ST2 can be increased.

[0213] according to Figure 47 In the embodiment shown, the first and second electrode structures ST1 and ST2 of the first unit array block BLK1 may have a first stepped structure S1 in the first direction D1, a second stepped structure S2 in the second direction D2, and a third stepped structure S3 in the second direction D2 on the second connection region CNR2. The first and second electrode structures ST1 and ST2 of the second unit array block BLK2 may have a shape that is the reverse of the shape of the first and second electrode structures ST1 and ST2 of the first unit array block BLK1.

[0214] Each of the first and second electrode structures ST1 and ST2 may have an asymmetrical stepped structure disposed on the first and second connection regions CNR1 and CNR2, respectively. In some embodiments, each of the first and second electrode structures ST1 and ST2 may include a first stepped structure S1 formed in a first direction D1, a second stepped structure S2 formed in a second direction D2, and a third stepped structure S3 formed in a second direction D2 on the first and second connection regions CNR1 and CNR2, and the number of electrodes constituting the second stepped structure S2 of the first connection region CNR1 may be different from the number of electrodes constituting the second stepped structure S2 of the second connection region CNR2.

[0215] According to some embodiments of the present invention, an upper structure having a pyramid-shaped stepped structure on the connection region can be formed on a thin layer structure comprising multiple vertically stacked horizontal layers, and this thin layer structure can be patterned using the upper structure as an etching mask. Therefore, an electrode structure with a stepped structure can be easily formed on the connection region.

[0216] While the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not restrictive but illustrative. Consequently, the scope of the inventive concept will be determined by the widest permissible interpretation of the claims and their equivalents, and should not be constrained or limited by the foregoing description.

[0217] This application claims priority to U.S. Provisional Patent Application No. 62 / 276,356, filed January 8, 2016 with the U.S. Patent and Trademark Office and Korean Patent Application No. 10-2016-0076700, filed June 20, 2016 with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method for manufacturing a three-dimensional semiconductor memory device, the method comprising: A thin-layer structure comprising vertically and alternately stacked insulating layers and horizontal layers is formed on a substrate including a unit array region and a connection region; A first mask pattern is formed, the first mask pattern having an opening that exposes a portion of the thin-layer structure in the connection area; The first etching process is performed using the first mask pattern as an etching mask to etch the thin layer structure; Perform a first trimming process to reduce the area of ​​the first mask pattern; The first etching process and the first trimming process are performed alternately and repeatedly to form an upper structure on the connection area; A second mask pattern is formed, which exposes a portion of the upper structure on the connection area and the lower portion of the thin layer structure on the connection area; The second mask pattern is used as an etching mask to perform a second etching process to etch the thin layer structure and the upper structure; Perform a second trimming process to reduce the area of ​​the second mask pattern; as well as The second etching process and the second trimming process are performed alternately and repeatedly to form a plurality of intermediate structures below the upper structure.

2. The method according to claim 1, wherein the area of ​​the opening is increased by the first trimming process.

3. The method according to claim 2, wherein the width and length of the opening are increased by the first trimming process.

4. The method of claim 1, wherein the first etching process is performed at a first etching depth.

5. The method of claim 4, wherein the first etching depth corresponds to the vertical pitch of the horizontal layer.

6. The method of claim 1, wherein the upper structure has a first stepped structure formed in a first direction and a second stepped structure formed in a second direction perpendicular to the first direction on the connection area.

7. The method of claim 6, wherein the second mask pattern exposes a portion of the first stepped structure and a portion of the second stepped structure.

8. The method of claim 7, wherein the second etching process is performed at a second etching depth.

9. The method of claim 8, wherein the second etching depth corresponds to at least twice the vertical pitch of the horizontal layer.

10. The method of claim 8, wherein the upper structure comprises a plurality of upper horizontal patterns stacked on the lower portion of the thin-layer structure. The plurality of upper horizontal patterns include sidewalls that are vertically aligned with each other by the second etching process.

11. The method of claim 10, wherein each of the intermediate structures has a third step structure formed in the second direction.

12. The method according to claim 11, wherein the number of steps in the third step structure is equal to the number of steps in the second step structure.

13. The method of claim 10, wherein each of the intermediate structures has a third stepped structure formed in the second direction, and The third-step structures are mirror-symmetric about an imaginary line parallel to the first direction.

14. The method of claim 6, further comprising: A third mask pattern is formed on the upper structure and the plurality of intermediate structures; as well as The third mask pattern is used as an etching mask to perform a third etching process to form electrode structures spaced apart in the second direction.

15. The method of claim 14, wherein forming the electrode structure includes forming a first trench that extends in the first direction and penetrates the upper structure and the plurality of intermediate structures over the cell array region and the connection region.

16. The method of claim 15, wherein forming the electrode structure further comprises forming a second trench and a third trench, the second trench extending in the first direction over the unit array region, and the third trench extending in the first direction over the connection region. The second trench is shorter than the first trench, and The third groove is spaced apart from the second groove.

17. A three-dimensional semiconductor memory device manufactured by the method according to claims 1 to 16.

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