Vacancy-based controllable doping p-type two-dimensional transistor and preparation method thereof

Abstract

The application discloses a kind of controllable doping p-type two-dimensional transistors based on space and preparation method thereof, mainly solve the problem that existing technology is difficult to realize accurate controllable doping.Solution includes: insulating substrate, two-dimensional material channel layer, source electrode and drain electrode located on both ends of two-dimensional material channel layer, gate dielectric layer located on two-dimensional material channel layer and source-drain electrode, gate electrode located on gate dielectric;By depositing a thick mask layer, the mask layer is thinned to form a patterned thin layer by lithography and etching, the two-dimensional material is ion bombarded through the treated mask layer, the two-dimensional material under the mask thin layer forms surface vacancies, then remove the mask, expose the two-dimensional material to oxygen flow to form surface charge transfer doping.The application can realize partition controllable doping without damaging the two-dimensional material and affecting the performance, effectively improve the conductivity of two-dimensional transistor.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and further relates to two-dimensional transistor technology, specifically a vacancy-based controllable doping p-type two-dimensional transistor and its fabrication method, which can be used to fabricate high-performance two-dimensional field-effect transistors. Background Technology

[0002] With the development of semiconductor device manufacturing technology, traditional silicon-based transistors have encountered a series of problems when shrinking to the nanometer scale, such as short-channel effects, increased power consumption, and difficulties in thermal management. These problems have constrained further miniaturization and performance improvement of transistors. Two-dimensional field-effect transistors (FETs) use two-dimensional semiconductor materials as channel materials. Utilizing the atomic-level thickness of two-dimensional materials, device size can be further reduced without sacrificing switching performance, thus breaking through the miniaturization limits of silicon-based transistors. Two-dimensional semiconductor materials, especially transition metal dichalcogenides such as molybdenum disulfide and tungsten diselenide, possess many superior properties as channel materials for FETs. Their atomic-level thickness and excellent electrical properties can significantly reduce leakage current and quiescent power consumption in the channel, making them ideal for low-power devices. Simultaneously, two-dimensional materials also exhibit good mobility, enabling fast switching and efficient signal transmission at low voltages, suitable for high-speed circuit applications. Furthermore, two-dimensional semiconductor materials possess excellent mechanical flexibility and transparency, making them widely applicable in flexible electronics, wearable devices, and other fields, providing more possibilities for the diversity of future electronic products. These characteristics of two-dimensional semiconductor materials make them promising candidates for next-generation electronic devices, especially high-efficiency, low-power nanoelectronic devices.

[0003] As Moore's Law approaches its limits, there is an urgent need for novel semiconductor materials with comprehensive and superior performance. While two-dimensional materials meet many of the performance requirements for novel semiconductor materials, there are still many problems that need to be solved.

[0004] Research on p-type two-dimensional transistors is relatively lagging due to the inherent properties of two-dimensional materials and the Fermi level pinning effect. Existing two-dimensional semiconductor materials, such as transition metal dichalcogenides, mostly exhibit intrinsic n-type conductivity, making two-dimensional materials with excellent p-type properties scarce. Furthermore, the Fermi level pinning effect makes it difficult to tune the Schottky barrier when metals are in contact with two-dimensional materials, which also significantly limits the realization of p-type two-dimensional transistors. The ideal method for CMOS-compatible mass production of p-type two-dimensional transistors is to p-type dope the two-dimensional material.

[0005] Currently, the common p-type doping methods for two-dimensional transistors in academia mainly involve substitutional doping by adding dopants during the growth of the two-dimensional material, and surface charge transfer doping on the surface of the already grown two-dimensional material. Substitutional doping can directly increase carrier concentration and reduce channel resistance, but this doping method introduces uncontrollable lattice disorder, severely reducing carrier mobility. Unlike substitutional doping, surface charge transfer doping uses dopants located outside the carrier pathway and does not introduce any lattice disorder, thus typically maintaining higher electromobility in 2D materials. In surface charge transfer doping, a common strategy is to oxidize the surface of TMDs like WSe2 using oxygen plasma or UV / ozone to form a self-confined oxide layer on top of the undamaged layer, such as WO3. x and WO x Se y These surface oxides generate strong hole doping in the underlying channel material. However, this doping method on the oxide surface is very uncontrollable, making it difficult to control the doping concentration and the resulting electrical properties.

[0006] Furthermore, both substitutional doping and surface charge transfer doping mentioned above are difficult to achieve precise partitioned doping. The p-type two-dimensional transistors fabricated using these two methods with uniform doping suffer from severe gate control problems, making it difficult to turn off the transistor. In silicon-based field-effect transistors, partitioned doping allows for the control of doping concentrations in different regions of the transistor channel, enabling precise control of the electric field distribution, thereby significantly improving carrier mobility, reducing source-drain resistance, and mitigating short-channel effects. However, compared to silicon-based devices, two-dimensional materials have atomically thin structures. The ion implantation partitioned doping methods commonly used in silicon-based devices can cause severe lattice damage to two-dimensional materials during the process, destroying their inherent structural integrity and electrical properties, leading to severe degradation of two-dimensional transistor performance. Therefore, conventional ion implantation partitioned doping techniques are also difficult to apply to two-dimensional materials.

[0007] Currently, research on two-dimensional transistors still lacks a precise and controllable doping technique that can effectively improve their conductivity while maintaining their gate control performance. This technological bottleneck limits the large-scale fabrication of high-performance two-dimensional transistors, especially high-performance p-type devices, making it difficult to meet the growing demand for high-performance two-dimensional transistors. Summary of the Invention

[0008] The purpose of this invention is to address the shortcomings of existing technologies by proposing a vacancy-based controllable doping method for p-type two-dimensional transistors and its fabrication, aiming to solve the problem of the difficulty in achieving high-performance p-type two-dimensional transistors using existing technologies. First, a thick mask layer is deposited. Then, the mask layer is partially thinned using photolithography and etching to form patterned partial thin layers. Ions bombard the two-dimensional material through the processed mask layer, creating surface vacancies in the two-dimensional material beneath the mask layer. The mask is then removed, exposing the two-dimensional material to an oxygen flow for oxidation, resulting in surface charge transfer doping. This invention enables controlled, partitioned doping without damaging the two-dimensional material and affecting its performance, effectively improving the conductivity of the two-dimensional transistor.

[0009] The technical solution to achieve the objective of this invention is as follows:

[0010] A vacancy-based controllable doped p-type two-dimensional transistor includes an insulating substrate 1, a two-dimensional material channel layer 2, a source electrode 3 and a drain electrode 4 located above the two ends of the two-dimensional material channel layer, a gate dielectric layer 5 located above the two-dimensional material channel layer and the source and drain electrodes, and a gate electrode 6 located above the gate dielectric.

[0011] The aforementioned two-dimensional material channel layer 2 adopts one of the two-dimensional semiconductor materials, which includes at least tungsten diselenide, molybdenum diselenide, and molybdenum disulfide; and is subjected to controllable surface charge transfer doping, that is, after partitioning vacancies on its surface, it undergoes natural oxidation treatment.

[0012] Furthermore, the aforementioned two-dimensional material channel layer 2 has a multi-layer structure.

[0013] Furthermore, the insulating substrate 1 is made of any one of SiO2 / Si, sapphire, or diamond; the gate dielectric 7 is made of any one of aluminum oxide, aluminum nitride, or silicon nitride; the gate electrode 8 is made of Ni / Au, Pd / Au, or Pt / Au metal; and the source electrode 5 and drain electrode 6 are both made of Pd / Au or Pt / Au or metals that are compatible with the electrical properties of two-dimensional materials.

[0014] A method for fabricating a vacancy-based controllable doped p-type two-dimensional transistor includes the following steps:

[0015] §1: Select the target substrate, and use acetone, isopropanol and deionized water to ultrasonically clean its surface, and then blow it dry with nitrogen to obtain a clean insulating substrate 1.

[0016] §2: Growth of two-dimensional material thin films to be transferred on the substrate surface using chemical vapor deposition;

[0017] §3: The two-dimensional material thin film grown was transferred onto insulating substrate 1 using PMMA-assisted transfer method;

[0018] §4: The two-dimensional material transferred on the insulating substrate (1) is coated with adhesive, pre-baked, photolithographically etched, and developed. Then, the isolation region is etched to array the two-dimensional material, so as to obtain the two-dimensional material channel layer to be doped for the transistor.

[0019] §5: A silicon dioxide layer is deposited on the surface of the two-dimensional material obtained in step §4 by plasma-enhanced chemical vapor deposition;

[0020] §6: Photoresist is uniformly coated on the surface of the silicon dioxide layer. After pre-baking, photolithography, and etching, the silicon dioxide layer above the two-dimensional material region to be doped is etched into a thin silicon dioxide layer.

[0021] §7: Precisely partitioned vacancies on the surface of two-dimensional materials are created by bombarding the surface of two-dimensional materials with high-energy hydrogen ions through a silicon dioxide mask layer, and the number of vacancies can be controlled according to different power and processing time.

[0022] §8: Removal of the silicon dioxide mask layer by wet etching;

[0023] §9: Two-dimensional materials with surface vacancies are exposed to an oxygen flow for oxidation to achieve precise and controllable surface charge transfer doping, resulting in a two-dimensional material channel layer 2 for transistors;

[0024] §10: The surface of the two-dimensional material channel layer 2 obtained in step §9 is subjected to photolithography and electron beam evaporation to deposit source and drain electrode metals. After the metals are deposited, the source electrode 3 and drain electrode 4 are formed by a lift-off process.

[0025] §11: A gate dielectric layer 5 is obtained by magnetron sputtering aluminum oxide, aluminum nitride, or silicon nitride on the surfaces of the two-dimensional material channel layer 2, source electrode 3, and drain electrode 4;

[0026] §12: The gate electrode 6 is fabricated on the surface of the gate dielectric layer 5 by photolithography, electron beam evaporation deposition of gate metal and lift-off process;

[0027] §13: The area above the source and drain electrodes is patterned by photolithography, and then the gate dielectric layer is etched to expose the source and drain electrodes, thus completing the fabrication of the device.

[0028] Compared with the prior art, the present invention has the following advantages:

[0029] First, this invention employs a two-dimensional material surface charge transfer doping method, which, compared to traditional substitutional doping, avoids introducing lattice disorder that leads to a decrease in carrier mobility. Furthermore, the surface charge transfer doping method used in this invention achieves this by first creating vacancies on the surface of the two-dimensional material and then naturally oxidizing it. This method is a low-temperature, low-energy doping technique, avoiding excessive damage to the surface of the two-dimensional material caused by conventional high-temperature, high-energy doping methods. Compared to conventional low-temperature, low-energy oxidation methods, it uses vacancies as binding sites for dopant atoms, improving both doping concentration and efficiency. Simultaneously, compared to directly performing high-power oxygen plasma treatment or UV / ozone oxidation and other two-dimensional material surface oxidation methods, the number of vacancies can be controlled by varying the power and processing time during vacancy creation, thereby controlling the doping concentration after natural oxidation to achieve controllable doping of the two-dimensional material.

[0030] Secondly, this invention bombards the surface of a two-dimensional material with high-energy hydrogen ions through a patterned, etched, and thinned silicon dioxide mask layer. During this process, surface vacancies are precisely created on the surface of the two-dimensional material beneath the thinned silicon dioxide layer, while the unetched thick silicon dioxide layer acts as a protective layer to prevent the underlying two-dimensional material from being bombarded by hydrogen ions. Subsequently, the surface vacancies of the two-dimensional material created by partitioning are subjected to oxidation doping treatment, ultimately achieving precise partitioning doping of the two-dimensional material and improving the electrical performance of the transistor.

[0031] Third, in this invention, a thin layer of silicon dioxide is used as a mask layer, and vacancies on the surface of two-dimensional materials are created non-contactly by means of high-energy hydrogen ions. Compared with the method of directly using high-energy ions to bombard the surface of two-dimensional materials to create vacancies, this method avoids excessive damage to the two-dimensional materials, and confines the creation of vacancies to the surface of two-dimensional materials, thus avoiding defects caused by lattice disorder inside the two-dimensional materials that affect performance.

[0032] Fourth, large-area, uniform two-dimensional material thin films can be grown, and the number of layers and crystal quality of the two-dimensional material can be controlled by adjusting parameters such as gas flow rate, reaction temperature and time, so as to mass-produce two-dimensional material field-effect transistors with different electrical properties.

[0033] Fifth, this invention uses PMMA wet transfer to achieve the transfer of two-dimensional material thin film layers, which can achieve uniform transfer on a large area substrate, effectively reducing mechanical damage to the molybdenum disulfide film during the transfer process, and helping to obtain higher quality films. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the device structure of the vacancy-based controllable doping p-type two-dimensional transistor in this invention;

[0035] Figure 2 This is a schematic diagram of the fabrication process of the two-dimensional transistor proposed in this invention. Detailed implementation method:

[0036] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] Example 1: Refer to Figure 1 The present invention provides a vacancy-based controllable doped p-type two-dimensional transistor, including an insulating substrate 1, a two-dimensional material channel layer 2, a source electrode 3 and a drain electrode 4 located above the two ends of the two-dimensional material channel layer, a gate dielectric layer 5 located above the two-dimensional material channel layer and the source and drain electrodes, and a gate electrode 6 located above the gate dielectric.

[0038] The aforementioned two-dimensional material channel layer 2 adopts one of the two-dimensional semiconductor materials, including tungsten diselenide, molybdenum diselenide, molybdenum disulfide, etc., and has a multi-layer structure; and it is subjected to controllable surface charge transfer doping, that is, after partitioning the vacancy on its surface, it is subjected to natural oxidation treatment.

[0039] The insulating substrate 1 is made of any one of the insulating materials SiO2 / Si, sapphire, and diamond; the gate dielectric 7 is made of any one of the insulating dielectric layers alumina, aluminum nitride, and silicon nitride; the gate electrode 8 is made of Ni / Au, Pd / Au, or Pt / Au metal; and the source electrode 5 and drain electrode 6 are both made of Pd / Au or Pt / Au or metals that are compatible with the electrical properties of two-dimensional materials.

[0040] Example 2: Refer to Figure 2 The present invention provides a method for fabricating a vacancy-based controllable doped p-type two-dimensional transistor, comprising the following steps:

[0041] Step §1: Select the target substrate, and use acetone, isopropanol and deionized water to ultrasonically clean its surface, and then blow it dry with nitrogen to obtain a clean insulating substrate 1.

[0042] Step §2: Grow the two-dimensional material thin film to be transferred on the substrate surface using chemical vapor deposition. The steps include the following:

[0043] 2a) Select the reaction precursors according to the type of two-dimensional material thin film to be grown, and place the different types of reaction precursors in the high-temperature zone and low-temperature zone of the tube furnace according to their reaction requirements.

[0044] 2b) Place the clean substrate used for growing two-dimensional material films in an area a few centimeters away from the high-temperature sample to facilitate film growth;

[0045] 2c) Set the working gas and keep the gas flow constant during the deposition process. Increase the temperature at a rate of 15-20℃ / min until the set working temperature is reached. Then, control the reaction time according to the required thickness of the two-dimensional material film to obtain the two-dimensional material film to be transferred.

[0046] Step §3: The grown two-dimensional material film is transferred onto the insulating substrate 1 using the PMMA-assisted transfer method, which includes the following steps:

[0047] Spin-coat PMMA onto the surface of the layer to be transferred and cure it on a hot plate at 90-120℃.

[0048] The sample is immersed in the solution required for substrate separation for two hours to separate the PMMA-to-transfer layer from its substrate.

[0049] The separated floating PMMA-to-transfer layer was transferred to the target substrate and cured. The PMMA was removed by soaking in acetone, then cleaned with IPA, and finally dried with nitrogen.

[0050] Step §4: The two-dimensional material transferred on the insulating substrate (1) is coated with adhesive, pre-baked, photolithographically etched, and developed. Then, the isolation region is etched to array the two-dimensional material to obtain the two-dimensional material channel layer to be doped for the transistor.

[0051] Step §5: A silicon dioxide layer is deposited on the surface of the two-dimensional material obtained in Step §4 using plasma-enhanced chemical vapor deposition. In this embodiment, the pre-cleaned sample is fixed on a base inside the PECVD reaction chamber, Ar gas is introduced to remove residual impurities in the reaction chamber, and the PECVD system is started under set conditions to begin SiO2 thin film deposition. After deposition is completed, pure Ar gas is introduced for 1 minute to clean the chamber and prevent contamination.

[0052] Step §6: Coat the surface of the silicon dioxide layer with photoresist, and after pre-baking, photolithography and etching, etch the silicon dioxide layer above the two-dimensional material region to be doped into a thin silicon dioxide layer.

[0053] Step §7: Precisely partitioned vacancy zones on the surface of a two-dimensional material are created by bombarding the surface of the two-dimensional material with high-energy hydrogen ions through a silicon dioxide mask layer. The number of vacancy zones can be controlled by different power and processing time. Specifically, the silicon dioxide mask layer sample that has been partitioned and thinned is placed in a reactive ion etching chamber and exposed to hydrogen plasma. The RF power and hydrogen gas flow rate in the RIE chamber are maintained at 100W and 50sccm, respectively, and the vacancy zone is created by bombarding the surface of the two-dimensional material with high-energy hydrogen ions through the mask layer.

[0054] Step §8: Remove the silicon dioxide mask layer by wet etching;

[0055] Step §9: The two-dimensional material with surface vacancies is exposed to an oxygen flow for oxidation to achieve precise and controllable surface charge transfer doping, thereby obtaining the two-dimensional material channel layer 2 of the transistor;

[0056] Step §10: The source and drain electrode metals are deposited on the surface of the two-dimensional material channel layer 2 obtained in step §9 by photolithography and electron beam evaporation. After the metals are deposited, the source electrode 3 and drain electrode 4 are formed by a lift-off process.

[0057] Step §11: A gate dielectric layer 5 is obtained by magnetron sputtering aluminum oxide, aluminum nitride, or silicon nitride onto the surfaces of the two-dimensional material channel layer 2, the source electrode 3, and the drain electrode 4. In this embodiment, the substrate is heated to a set temperature, and the appropriate target material and working gas are used according to the type of encapsulation protective layer. The gate dielectric layer to be etched is grown on the substrate or the two-dimensional material channel layer by controlling the sputtering time according to the required thickness using a magnetron sputtering system at the reaction chamber temperature.

[0058] Step §12: The gate electrode 6 is fabricated on the surface of the gate dielectric layer 5 by photolithography, electron beam evaporation deposition of gate metal and lift-off process;

[0059] Step §13: Pattern the area above the source and drain electrodes using photolithography, and then etch the gate dielectric layer to expose the source and drain electrodes, thus completing the fabrication of the device.

[0060] Example 3: The overall implementation steps of the transistor fabrication method proposed in this example are the same as in Example 2. A specific example is given below, using sapphire as the substrate, aluminum nitride as the gate dielectric layer, molybdenum diselenide as the two-dimensional material, and Pt / Au as the source / drain electrode metal, to further describe the fabrication process of this invention:

[0061] Step 1: Pretreatment of transistor substrate 1.

[0062] Sapphire was selected as the insulating substrate 1 for transistors. The substrate 1 was ultrasonically cleaned for 5 minutes each in acetone solution, isopropanol and deionized water, and then dried with nitrogen.

[0063] Step 2: Chemical vapor deposition of the two-dimensional material to be transferred on another sapphire substrate.

[0064] 2.1) The sapphire substrate was ultrasonically cleaned with acetone for 20 minutes. After cleaning, the substrate was rinsed with deionized water 2-3 times, then immersed in deionized water for ultrasonic cleaning for 15 minutes. Finally, the substrate treated above was dried with nitrogen.

[0065] 2.2) The molybdenum source is MoO3, and the selenium source is high-purity selenium powder. The MoO3 powder is placed in a quartz boat in the high-temperature zone, and the high-purity selenium powder is placed in the low-temperature zone of the furnace tube near the outlet. The cleaned sapphire substrates a and b are placed with their surfaces facing up in an area a few centimeters away from the MoO3 powder to facilitate the growth of MoSe2.

[0066] 2.3) Set up an argon-hydrogen mixture with argon and hydrogen gas flow rates of 100 sccm and 10 sccm, respectively. Maintain a constant gas flow during the deposition process. Turn on the tube furnace and set the heating rate to 15℃ / min to heat the MoO3 powder area to 800℃ and the selenium powder area to 300℃. After the temperature reaches the set value, maintain a constant temperature for about 5 minutes. At this time, the selenium vapor reacts with MoO3 on the substrate to generate molybdenum diselenide and grow the molybdenum diselenide film to be transferred.

[0067] 2.4) After the reaction is complete, turn off the heating and keep argon gas flowing until the system cools naturally to room temperature to avoid the oxidation of molybdenum diselenide at high temperatures;

[0068] Step 3: Transfer the two-dimensional material grown on the sapphire substrate to the insulating substrate 1.

[0069] 3.1) A small amount of PMMA solution is evenly dropped onto the surface of the MoSe2 / sapphire substrate. Using a spin coater, the PMMA layer is spin-coated at 4000 rpm for 1 minute, and then dried on a hot plate at 100°C for 10 minutes to cure the PMMA layer.

[0070] 3.2) Dissolve 55g of KOH solute in 300ml of deionized water and stir continuously until the solute is completely dissolved and the solution becomes a colorless and odorless liquid. Then immerse the sample in the prepared KOH solution for two hours to allow the PMMA-MoSe2 layer to gradually separate from the substrate.

[0071] 3.3) Rinse the PMMA-MoSe2 layer in deionized water. Using tweezers or other auxiliary tools, gently lift the PMMA / MoSe2 film floating on the water surface and slowly place it on the target substrate. Use a glass rod or scraper to gently press and remove air bubbles between the PMMA / MoSe2 film and the substrate to ensure full contact and adhesion. Let it stand for several hours to allow the film to fully adhere to the substrate.

[0072] 3.4) Soak the sample in acetone to remove PMMA, then wash with IPA, and finally dry with nitrogen.

[0073] Step 4: Array the two-dimensional material on the insulating substrate 1 by photolithography and etching.

[0074] The two-dimensional material surface transferred to substrate 1 is coated with photoresist, photolithographically etched, and developed to pattern the area to be etched; the process conditions are set with gas flow rate, reaction pressure, and RF power of 10 sccm, 30 mTorr, and 50 W, respectively, and etching time of about 3 min. Oxygen plasma is used to etch molybdenum diselenide to obtain isolation regions to array molybdenum diselenide and form the two-dimensional material channel layer 2 to be doped into transistors.

[0075] Step 5: Deposit a silicon dioxide layer on the surface of the two-dimensional material channel layer 2 by plasma-enhanced chemical vapor deposition.

[0076] 5.1) Clean the sample with deionized water and isopropanol using ultrasonic cleaning for 3 minutes each, then dry it with nitrogen gas;

[0077] 5.2) The process parameters are set as follows: operating temperature 200℃, operating pressure 800mTorr, RF power 40W, SiH4 gas flow rate 2sccm, O2 and Ar gas flow rates 50sccm and 10sccm respectively, and deposition time approximately 8 minutes.

[0078] 5.3) Fix the sample on the base inside the PECVD reaction chamber, start the PECVD system under the set conditions, and deposit a 40nm silicon dioxide layer on the surface of the two-dimensional material.

[0079] 5.4) After deposition, pure Ar gas is introduced to clean the chamber for 1 minute to prevent contamination.

[0080] Step 6: Photolithography and etching are used to etch the silicon dioxide above the two-dimensional material region to be doped into a thin layer.

[0081] Photoresist was coated on the sample surface, and the area to be etched was exposed and developed. CF4 plasma was used to etch the silicon dioxide above the two-dimensional material region to be doped into a thin layer of about 10 nm under the following process conditions: CF4 gas flow rate of 30 sccm, auxiliary gas flow rates of Ar and O2 gas of 10 sccm and 2 sccm, respectively, reaction pressure and RF power of 10 mTorr and 100 W, respectively, and etching time of about 3 min.

[0082] Step 7: Create vacancies on the surface of the two-dimensional material.

[0083] The sample with a patterned etched silicon dioxide mask layer on its surface was placed in a reactive ion etching chamber and exposed to hydrogen plasma. The RF power and hydrogen gas flow rate in the RIE chamber were maintained at 100W and 50sccm, respectively. Hydrogen ions partially penetrated the silicon dioxide thin layer and precisely created vacancies on the surface of the two-dimensional material below.

[0084] Step 8: Wet etching to remove the silicon dioxide mask layer.

[0085] Use a buffered oxide etching solution diluted 1:6. Gently immerse the sample in the solution, ensuring the liquid completely covers the sample surface. Let it stand in the solution or gently stir to promote uniform etching. After etching is complete, immediately remove the sample and rinse it quickly with plenty of deionized water to remove any residual etching solution components. Finally, rinse the sample with IPA and dry it with nitrogen.

[0086] Step 9: Perform oxidative doping on the vacancies.

[0087] The sample with the silicon dioxide layer removed was exposed to an oxygen flow to naturally oxidize and dope the vacancies on the surface of the fabricated two-dimensional material, resulting in a transistor-partitioned two-dimensional material channel layer 2.

[0088] Step 10: Fabricate source and drain electrodes 3 and 4.

[0089] 10.1) Coating the sample surface with photoresist, exposing it, and developing it to form the source and drain regions of the metal to be deposited;

[0090] 10.2) Mount the sample on the sample stage of the vapor deposition system and ensure that the sample surface is aligned with the target placement area;

[0091] 10.3) Select Pt as the target material and set the evaporation rate to [value missing]. To ensure the uniformity and adhesion of the platinum layer, the vacuum pump was turned on to evaporate to a high vacuum. The electron beam current was then gradually increased to begin depositing the Pt layer. After depositing to a thickness of 5 nm in the source-drain contact area, the electron beam was turned off to stop the deposition. The target material was then changed to Au, and the deposition rate was set to [value missing]. An Au layer with a thickness of 25 nm is then deposited on the contact area between the source and drain electrodes.

[0092] 10.4) After the vapor deposition is completed, allow the sample to cool in the chamber for a few minutes, then slowly release the gas to restore the pressure to normal, remove the sample, and place it in acetone for stripping. After removing the excess metal layer, the source electrode 3 and the drain electrode 4 are formed.

[0093] Step 11: Aluminum nitride is magnetron sputtered as the gate dielectric layer 5 on the surface of the two-dimensional material channel layer and the source / drain electrodes.

[0094] 11.1) In a magnetron sputtering system, aluminum nitride is used as the target material, and argon and nitrogen are set as working gases with flow rates of 20 sccm and 5 sccm, respectively. The working gas pressure, sputtering power, and sputtering temperature are 3 mTorr, 100 W, and 300 °C, respectively. An aluminum nitride thin film is sputtered on substrate 1 as the bottom layer 2 of the encapsulation protective layer.

[0095] 11.2) Install the aluminum nitride target on the target position of the magnetron sputtering equipment, and start the vacuum pump until the cavity reaches 10 °C. - 6 After the vacuum level is below Torr, nitrogen and argon are introduced, the flow rate is adjusted to the target working pressure and kept stable before sputtering begins. The sputtering time is about 10 minutes. A 50 nm thick aluminum nitride film is deposited on the two-dimensional material channel layer and the source and drain electrode surfaces as the gate dielectric layer 5.

[0096] 11.3) After cooling the sample to room temperature in the vacuum chamber, nitrogen gas is introduced to bring the chamber back to atmospheric pressure, the chamber is opened and the sample is removed.

[0097] Step 12: Fabricate gate electrode 6.

[0098] 12.1) Coating photoresist on the surface of the gate dielectric layer 5, exposing and developing it to form the gate region of the metal to be deposited;

[0099] 12.2) Mount the sample on the sample stage of the vapor deposition system and ensure that the sample surface is aligned with the target placement area;

[0100] 12.3) Select Pd as the target material and set the evaporation rate to [value missing]. To ensure the uniformity and adhesion of the Pd layer, the vacuum pump was turned on to evaporate to a high vacuum. The electron beam current was then gradually increased to begin depositing the Pd layer. After depositing to a thickness of 5 nm in the source-drain contact area, the electron beam was turned off to stop the deposition. The target material was then changed to Au, and the deposition rate was set to [value missing]. An Au layer with a thickness of 25 nm is then deposited on the contact area between the source and drain electrodes.

[0101] 12.4) After the vapor deposition is completed, allow the sample to cool in the chamber for a few minutes, then slowly release the gas to restore the pressure to normal, remove the sample, place it in acetone for stripping, remove the excess metal layer to form the gate electrode 6.

[0102] Step 13: Etch the gate dielectric layer to expose the source and drain electrodes.

[0103] 13.1) Coat the sample surface with photoresist, expose and develop the area to be etched;

[0104] 13.2) Using CF4 plasma, aluminum nitride was etched under the following process conditions: CF4 gas flow rate of 30 sccm, auxiliary gas Ar and O2 gas flow rates of 10 sccm and 2 sccm respectively, reaction pressure and RF power of 10 mTorr and 100 W respectively, and etching time of about 10 min. The source and drain electrodes were exposed after etching.

[0105] 13.3) After etching, remove the photoresist and clean the sample with acetone and IPA, then blow it dry with nitrogen to ensure that there are no residues on the surface.

[0106] Example 4: The overall implementation steps of the transistor fabrication method proposed in this example are the same as in Example 2. A specific example is given below to further describe the fabrication process of this invention: the substrate is diamond, the gate dielectric layer is aluminum nitride, the two-dimensional material is tungsten diselenide, and the source / drain electrode metal is Pd / Au.

[0107] Step a: Pretreatment of transistor substrate 1.

[0108] Diamond was selected as the insulating substrate 1 for the transistor. The substrate 1 was ultrasonically cleaned for 5 minutes each in acetone solution, isopropanol and deionized water, and then dried with nitrogen.

[0109] Step b: Chemical vapor deposition of the two-dimensional material to be transferred on a sapphire substrate.

[0110] b.1) Clean the sapphire substrate with acetone using ultrasonic cleaning for 20 minutes. After cleaning, rinse the substrate with deionized water 2-3 times, then immerse it in deionized water for ultrasonic cleaning for 15 minutes. Finally, use nitrogen to dry the substrate treated above.

[0111] b.2) The molybdenum source is WO3, and the selenium source is high-purity selenium powder. The WO3 powder is placed in the quartz boat in the high-temperature zone, and the high-purity selenium powder is placed in the low-temperature zone of the furnace tube near the outlet. The cleaned sapphire substrates a and b are placed with their surfaces facing up in an area a few centimeters away from the WO3 powder to facilitate the growth of WSe2.

[0112] b.3) Set up an argon-hydrogen mixture with argon and hydrogen gas flow rates of 100 sccm and 10 sccm, respectively. Maintain a constant gas flow during the deposition process. Turn on the tube furnace and set the heating rate to 15℃ / min. Heat the WO3 powder area to 800℃ and the selenium powder area to 300℃. After the temperature reaches the set value, maintain a constant temperature for about 5 minutes. At this time, the selenium vapor reacts with MoO3 on the substrate to generate tungsten diselenide and grow the tungsten diselenide film to be transferred.

[0113] b.4) After the reaction is complete, turn off the heating and keep the argon gas flowing until the system cools down to room temperature naturally to avoid oxidation of tungsten diselenide at high temperatures;

[0114] Step c: Transfer the two-dimensional material grown on the sapphire substrate to the insulating substrate 1.

[0115] c.1) Drop a small amount of PMMA solution evenly onto the surface of the WSe2 / sapphire substrate, spin coat at 4000 rpm for 1 minute using a spin coater, and then dry on a hot plate at 100°C for 10 minutes to cure the PMMA layer.

[0116] c.2) Dissolve 55g of KOH solute in 300ml of deionized water and stir continuously until the solute is completely dissolved and the solution becomes a colorless and odorless liquid. Then immerse the sample in the prepared KOH solution for two hours to allow the PMMA-WSe2 layer to gradually separate from the substrate.

[0117] c.3) Rinse the PMMA-WSe2 layer in deionized water. Using tweezers or other auxiliary tools, gently lift the PMMA / WSe2 film floating on the water surface and slowly place it on the target substrate. Use a glass rod or scraper to gently press and remove air bubbles between the PMMA / WSe2 film and the substrate to ensure full contact and adhesion. Let it stand for several hours to allow the film to fully adhere to the substrate.

[0118] c.4) Soak the sample in acetone to remove PMMA, then wash with IPA, and finally dry with nitrogen.

[0119] Step d: Array the two-dimensional material on the insulating substrate 1 by photolithography and etching.

[0120] The two-dimensional material surface transferred to substrate 1 is coated with photoresist, photolithographically etched, and developed to pattern the area to be etched; the process conditions are set with gas flow rate, reaction pressure, and RF power of 10 sccm, 30 mTorr, and 50 W, respectively, and etching time of about 3 min. Oxygen plasma is used to etch tungsten diselenide to obtain isolation regions to array tungsten diselenide and form the two-dimensional material channel layer 2 to be doped into transistors.

[0121] Step e: A silicon dioxide layer is deposited on the surface of the two-dimensional material channel layer 2 by plasma-enhanced chemical vapor deposition.

[0122] e.1) Clean the sample with deionized water and isopropanol using ultrasonic cleaning for 3 minutes each, then dry it with nitrogen gas;

[0123] e.2) Set the process parameters as follows: operating temperature 200℃, operating pressure 800mTorr, RF power 40W, SiH4 gas flow rate 2sccm, O2 and Ar gas flow rates 50sccm and 10sccm respectively, and deposition time approximately 8 minutes.

[0124] e.3) Fix the sample on the base inside the PECVD reaction chamber, start the PECVD system under the set conditions, and deposit a 40nm silicon dioxide layer on the surface of the two-dimensional material.

[0125] e.4) After deposition, pure Ar gas is introduced to clean the chamber for 1 minute to prevent contamination.

[0126] Step f: After photolithography, etching will etch the silicon dioxide above the region of the two-dimensional material to be doped into a thin layer.

[0127] Photoresist was coated on the sample surface, and the area to be etched was exposed and developed. CF4 plasma was used to etch the silicon dioxide above the two-dimensional material region to be doped into a thin layer of about 10 nm under the following process conditions: CF4 gas flow rate of 30 sccm, auxiliary gas flow rates of Ar and O2 gas of 10 sccm and 2 sccm, respectively, reaction pressure and RF power of 10 mTorr and 100 W, respectively, and etching time of about 3 min.

[0128] Step g: Create vacancies on the surface of the two-dimensional material.

[0129] The sample with a patterned etched silicon dioxide mask layer on its surface was placed in a reactive ion etching chamber and exposed to hydrogen plasma. The RF power and hydrogen gas flow rate in the RIE chamber were maintained at 100W and 50sccm, respectively. Hydrogen ions partially penetrated the silicon dioxide thin layer and precisely created vacancies on the surface of the two-dimensional material below.

[0130] Step h: Wet etching to remove the silicon dioxide mask layer

[0131] Use a buffered oxide etching solution diluted 1:6. Gently immerse the sample in the solution, ensuring the liquid completely covers the sample surface. Let it stand in the solution or gently stir to promote uniform etching. After etching is complete, immediately remove the sample and rinse it quickly with plenty of deionized water to remove any residual etching solution components. Finally, rinse the sample with IPA and dry it with nitrogen.

[0132] Step i: Oxidize and dope the vacancies.

[0133] The sample with the silicon dioxide layer removed was exposed to an oxygen flow to naturally oxidize and dope the vacancies on the surface of the fabricated two-dimensional material, resulting in a transistor-partitioned two-dimensional material channel layer 2.

[0134] Step j: Fabricate source and drain electrodes 3 and 4.

[0135] j.1) Coating the sample surface with photoresist, exposing it, and developing it to form the source and drain regions of the metal to be deposited;

[0136] j.2) Mount the partitioned doped sample on the sample stage of the vapor deposition system and ensure that the sample surface is aligned with the target placement area;

[0137] j.3) Select Pd as the target material and set the evaporation rate to [value missing]. To ensure the uniformity and adhesion of the Pd layer, the vacuum pump was turned on to evaporate to a high vacuum. The electron beam current was then gradually increased to begin depositing the Pd layer. After depositing to a thickness of 5 nm in the source-drain contact area, the electron beam was turned off to stop the deposition. The target material was then changed to Au, and the deposition rate was set to [value missing]. An Au layer with a thickness of 25 nm is then deposited on the contact area between the source and drain electrodes.

[0138] j.4) After the vapor deposition is completed, allow the sample to cool in the chamber for a few minutes, then slowly release the gas to restore the pressure to normal, remove the sample, and place it in acetone for stripping. After removing the excess metal layer, the source electrode 3 and the drain electrode 4 are formed.

[0139] Step k: Aluminum nitride is magnetron sputtered as the gate dielectric layer 5 on the surface of the two-dimensional material channel layer and the source / drain electrodes.

[0140] k.1) In the magnetron sputtering system, aluminum nitride is used as the target material, and argon and nitrogen are set as working gases with gas flow rates of 20 sccm and 5 sccm, respectively. The working gas pressure, sputtering power and sputtering temperature are 3 mTorr, 100 W and 300 °C, respectively. An aluminum nitride thin film is sputtered on substrate 1 as the bottom layer 2 of the encapsulation protective layer.

[0141] k.2) Install the aluminum nitride target on the target position of the magnetron sputtering equipment, and start the vacuum pump until the cavity reaches 10 °C. - 6 After the vacuum level is below Torr, nitrogen and argon are introduced, the flow rate is adjusted to the target working pressure and kept stable before sputtering begins. The sputtering time is about 10 minutes. A 50 nm thick aluminum nitride film is deposited on the two-dimensional material channel layer and the source and drain electrode surfaces as the gate dielectric layer 5.

[0142] k.3) After cooling the sample to room temperature in the vacuum chamber, introduce nitrogen gas to bring the chamber back to atmospheric pressure, open the chamber and remove the sample.

[0143] Step 1: Fabricate the gate electrode 6.

[0144] 1.1) Coating photoresist on the surface of the gate dielectric layer 5, exposing and developing it to form the gate region of the metal to be deposited;

[0145] 1.2) Mount the sample on the sample stage of the vapor deposition system and ensure that the sample surface is aligned with the target placement area;

[0146] 1.3) Select Pd as the target material and set the evaporation rate to [value missing]. To ensure the uniformity and adhesion of the Pd layer, the vacuum pump was turned on to evaporate to a high vacuum. The electron beam current was then gradually increased to begin depositing the Pd layer. After depositing to a thickness of 5 nm in the source-drain contact area, the electron beam was turned off to stop the deposition. The target material was then changed to Au, and the deposition rate was set to [value missing]. An Au layer with a thickness of 25 nm is then deposited on the contact area between the source and drain electrodes.

[0147] 1.4) After the vapor deposition is completed, allow the sample to cool in the chamber for a few minutes, then slowly release the gas to restore the pressure to normal, remove the sample, and place it in acetone for peeling. After removing the excess metal layer, the gate electrode 6 is formed.

[0148] Step m: Etch the gate dielectric layer to expose the source and drain electrodes.

[0149] m.1) Coat the sample surface with photoresist, expose and develop the area to be etched;

[0150] m.2) Aluminum nitride was etched using CF4 plasma under the following process conditions: CF4 gas flow rate of 30 sccm, auxiliary gas flow rates of Ar and O2 gas of 10 sccm and 2 sccm respectively, reaction pressure and radio frequency power of 10 mTorr and 100 W respectively, and etching time of about 10 min. The source and drain electrodes were exposed after etching.

[0151] m.3) After etching, remove the photoresist and clean the sample with acetone and IPA, then blow it dry with nitrogen to ensure that there are no residues on the surface.

[0152] Example 5: The overall implementation steps of the transistor fabrication method proposed in this example are the same as in Example 2. A specific example is given to further describe the fabrication process of this invention: the substrate is diamond, the gate dielectric layer is silicon nitride, the two-dimensional material is molybdenum diselenide, and the source / drain electrode metal is Pd / Au.

[0153] Step A: Pretreatment of transistor substrate 1.

[0154] Sapphire was selected as the insulating substrate 1 for transistors. The substrate 1 was ultrasonically cleaned for 5 minutes each in acetone solution, isopropanol and deionized water, and then dried with nitrogen.

[0155] Step B: Chemical vapor deposition of the two-dimensional material to be transferred on another sapphire substrate.

[0156] B.1) Clean the sapphire substrate with acetone using ultrasonic cleaning for 20 minutes. After cleaning, rinse the substrate with deionized water 2-3 times, then immerse it in deionized water for ultrasonic cleaning for 15 minutes. Finally, use nitrogen to dry the substrate treated above.

[0157] B.2) The molybdenum source is MoO3, and the sulfur source is high-purity sulfur powder. The MoO3 powder is placed in a quartz boat in the high-temperature zone, and the high-purity sulfur powder is placed in the low-temperature zone of the furnace tube near the outlet. The cleaned sapphire substrate is placed with the substrate surface facing up in an area a few centimeters away from the MoO3 powder to facilitate the growth of MoS3.

[0158] B.3) Set up an argon-hydrogen mixture with argon and hydrogen gas flow rates of 100 sccm and 10 sccm, respectively. Maintain a constant gas flow during the deposition process. Turn on the tube furnace and set the heating rate to 15℃ / min to heat the MoO3 powder area to 750℃ and the sulfur powder area to 200℃. After the temperature reaches the set value, maintain a constant temperature for about 5 minutes. At this time, sulfur vapor reacts with MoO3 on the substrate to generate molybdenum disulfide and grow a 10nm molybdenum disulfide film to be transferred.

[0159] B.4) After the reaction is complete, turn off the heating and keep the argon gas flowing until the system cools down to room temperature naturally to avoid the oxidation of molybdenum disulfide at high temperature.

[0160] Step C: Transfer the two-dimensional material grown on the sapphire substrate to the insulating substrate 1.

[0161] C.1) A small amount of PMMA solution is evenly dropped onto the surface of the MoS2 / sapphire substrate, and then spin-coated at 4000 rpm for 1 minute using a spin coater. The PMMA layer is then cured by drying on a hot plate at 100°C for 10 minutes.

[0162] C.2) Dissolve 55g of KOH solute in 300ml of deionized water and stir continuously until the solute is completely dissolved and the solution becomes a colorless and odorless liquid. Then immerse the sample in the prepared KOH solution for two hours to allow the PMMA-MoS2 layer to gradually separate from the substrate.

[0163] C.3) Rinse the PMMA-MoS2 layer in deionized water. Using tweezers or other auxiliary tools, gently lift the PMMA / MoS2 film floating on the water surface and slowly place it on the target substrate. Use a glass rod or scraper to gently press and remove air bubbles between the PMMA / MoS2 film and the substrate to ensure full contact and adhesion. Let it stand for several hours to allow the film to fully adhere to the substrate.

[0164] 3.4) Soak the sample in acetone to remove PMMA, then wash with IPA, and finally dry with nitrogen.

[0165] Step D: The two-dimensional material on the insulating substrate 1 is arrayed by photolithography and etching.

[0166] The two-dimensional material surface transferred to substrate 1 is coated with photoresist, photolithographically etched, and developed to pattern the area to be etched; the process conditions are set with gas flow rate, reaction pressure, and RF power of 10 sccm, 30 mTorr, and 50 W, respectively, and etching time of about 3 min. Oxygen plasma is used to etch molybdenum disulfide to obtain isolation regions to array molybdenum disulfide and form the two-dimensional material channel layer 2 to be doped into transistors.

[0167] Step E: A silicon dioxide layer is deposited on the surface of the two-dimensional material channel layer 2 by plasma-enhanced chemical vapor deposition.

[0168] E.1) Clean the sample with deionized water and isopropanol using ultrasonic cleaning for 3 minutes each, then dry it with nitrogen gas;

[0169] E.2) The process parameters are set as follows: operating temperature 200℃, operating pressure 800mTorr, RF power 40W, SiH2 gas flow rate 2sccm, O2 and Ar gas flow rates 50sccm and 10sccm respectively, and deposition time approximately 8 minutes.

[0170] E.3) Fix the sample on the base inside the PECVD reaction chamber, start the PECVD system under the set conditions, and deposit a 40nm silicon dioxide layer on the surface of the two-dimensional material.

[0171] E.4) After deposition, pure Ar gas is introduced to clean the chamber for 1 minute to prevent contamination.

[0172] Step F: Photolithography and etching are used to etch the silicon dioxide above the region of the two-dimensional material to be doped into a thin layer.

[0173] Photoresist was coated on the sample surface, and the area to be etched was exposed and developed. CF4 plasma was used to etch the silicon dioxide above the two-dimensional material region to be doped into a thin layer of about 10 nm under the following process conditions: CF4 gas flow rate of 30 sccm, auxiliary gas flow rates of Ar and O2 gas of 10 sccm and 2 sccm, respectively, reaction pressure and RF power of 10 mTorr and 100 W, respectively, and etching time of about 3 min.

[0174] Step G: Create vacancies on the surface of the two-dimensional material.

[0175] The sample with a patterned etched silicon dioxide mask layer on its surface was placed in a reactive ion etching chamber and exposed to hydrogen plasma. The RF power and hydrogen gas flow rate in the RIE chamber were maintained at 100W and 50sccm, respectively. Hydrogen ions partially penetrated the silicon dioxide thin layer and precisely created vacancies on the surface of the two-dimensional material below.

[0176] Step H: Wet etching to remove the silicon dioxide mask layer

[0177] Use a buffered oxide etching solution diluted 1:6. Gently immerse the sample in the solution, ensuring the liquid completely covers the sample surface. Let it stand in the solution or gently stir to promote uniform etching. After etching is complete, immediately remove the sample and rinse it quickly with plenty of deionized water to remove any residual etching solution components. Finally, rinse the sample with IPA and dry it with nitrogen.

[0178] Step I: Oxidize and dope the vacancies.

[0179] The sample with the silicon dioxide layer removed was exposed to an oxygen flow to naturally oxidize and dope the vacancies on the surface of the fabricated two-dimensional material, resulting in a transistor-partitioned two-dimensional material channel layer 2.

[0180] Step J: Fabricate source and drain electrodes 3 and 4.

[0181] J.1) Coating the sample surface with photoresist, exposing it, and developing it to form the source and drain regions of the metal to be deposited;

[0182] J.2) Mount the partitioned doped sample on the sample stage of the vapor deposition system and ensure that the sample surface is aligned with the target placement area;

[0183] J.3) Select Pd as the target material and set the evaporation rate to [value missing]. To ensure the uniformity and adhesion of the Pd layer, the vacuum pump was turned on to evaporate to a high vacuum. The electron beam current was then gradually increased to begin depositing the Pd layer. After depositing to a thickness of 5 nm in the source-drain contact area, the electron beam was turned off to stop the deposition. The target material was then changed to Au, and the deposition rate was set to [value missing]. An Au layer with a thickness of 25 nm is then deposited on the contact area between the source and drain electrodes.

[0184] J.4) After the vapor deposition is completed, allow the sample to cool in the chamber for a few minutes, then slowly release the gas to restore the pressure to normal, remove the sample, and place it in acetone for stripping. After removing the excess metal layer, the source electrode 3 and the drain electrode 4 are formed.

[0185] Step K: Silicon nitride is used as the gate dielectric layer 5 by magnetron sputtering on the surface of the two-dimensional material channel layer and the source / drain electrodes.

[0186] K.1) Under the process conditions of 20W power, 5sccm gas flow rate and about 10 minutes, the substrate surface is pretreated with low-power oxygen plasma to further improve the adhesion of silicon nitride film.

[0187] K.2) Mount the high-purity silicon target onto the cathode and ensure good contact between it and the magnetron sputtering system. Start the vacuum pump and evacuate the cavity to 10 °C. -6 After reaching a high vacuum of Torr, argon and nitrogen are introduced as working gases, with a flow rate of 15 sccm for both argon and nitrogen, and the working pressure is maintained at 3 mTorr.

[0188] K.3) After heating the sapphire substrate 1 to 300 degrees Celsius, a 50 nm thick silicon nitride thin film was deposited as the gate dielectric layer 7 under the process conditions of sputtering power of 150 W and sputtering time of 10 min.

[0189] K.4) After deposition, the sample is cooled to room temperature in the vacuum chamber, nitrogen gas is introduced to bring the chamber back to atmospheric pressure, the chamber is opened and the sample is taken out.

[0190] Step L: Fabricate the gate electrode 6.

[0191] L.1) Photoresist is coated on the surface of the gate dielectric layer 5, exposed, and developed to form the gate region of the metal to be deposited;

[0192] L.2) Mount the sample on the sample stage of the vapor deposition system and ensure that the sample surface is aligned with the target placement area;

[0193] L.3) Select Pd as the target material and set the evaporation rate to [value missing]. To ensure the uniformity and adhesion of the Pd layer, the vacuum pump was turned on to evaporate to a high vacuum. The electron beam current was then gradually increased to begin depositing the Pd layer. After depositing to a thickness of 5 nm in the source-drain contact area, the electron beam was turned off to stop the deposition. The target material was then changed to Au, and the deposition rate was set to [value missing]. An Au layer with a thickness of 25 nm is then deposited on the contact area between the source and drain electrodes.

[0194] L.4) After the vapor deposition is completed, allow the sample to cool in the chamber for a few minutes, then slowly release the gas to restore the pressure to normal, remove the sample, and place it in acetone for peeling. After removing the excess metal layer, the gate electrode 6 is formed.

[0195] Step M: Etch the gate dielectric layer to expose the source and drain electrodes.

[0196] M.1) Coat the sample surface with photoresist, expose and develop the area to be etched;

[0197] M.2) Silicon nitride was etched using CF4 plasma under the following process conditions: CF4 gas flow rate of 30 sccm, auxiliary gas flow rates of Ar and O2 gas of 10 sccm and 2 sccm respectively, reaction pressure and RF power of 10 mTorr and 100 W respectively, and etching time of about 10 min. The source and drain electrodes were exposed after etching.

[0198] M.3) After etching, remove the photoresist and clean the sample with acetone and IPA, then dry it with nitrogen to ensure that there are no residues on the surface.

[0199] Unless otherwise specified, the preparation methods used in the above specific embodiments are conventional methods; the reagents and materials used are commercially available unless otherwise specified. Parts of this invention not described in detail are common knowledge to those skilled in the art.

[0200] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and results of the present invention. For example, in addition to SiO2, sapphire, and diamond, other insulating substrate materials can be used for the insulating substrate; in addition to tungsten diselenide and molybdenum diselenide, other two-dimensional semiconductor materials such as tungsten disulfide, which can achieve p-type doping through oxidation, can be used for the two-dimensional material; the two-dimensional material thin film layer can be obtained not only by chemical vapor deposition and transfer but also by mechanical exfoliation and transfer; the gate dielectric layer can be made of aluminum oxide, aluminum nitride, and silicon nitride, but also by hafnium oxide, boron nitride, and other insulating dielectric materials; the method for preparing the gate dielectric can be chemical vapor deposition, atomic layer-by-layer deposition, etc., in addition to magnetron sputtering; the source / drain metal electrodes can be made of Pt / Au or Pd / Au, but other metals compatible with the p-type electrical properties of two-dimensional materials. However, these modifications and changes based on the concept of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a vacancy-based controllable doped p-type two-dimensional transistor, characterized in that, Includes the following steps: §1: Select the target substrate, and use acetone, isopropanol and deionized water to ultrasonically clean its surface, and then blow it dry with nitrogen to obtain a clean insulating substrate (1). §2: Growth of two-dimensional material thin films to be transferred on the substrate surface using chemical vapor deposition; §3: The two-dimensional material thin film grown was transferred onto an insulating substrate (1) using the PMMA-assisted transfer method; §4: The two-dimensional material transferred on the insulating substrate (1) is coated with adhesive, pre-baked, photolithographically etched, and developed. Then, the isolation region is etched to array the two-dimensional material, so as to obtain the two-dimensional material channel layer to be doped for the transistor. §5: A silicon dioxide layer is deposited on the surface of the two-dimensional material obtained in step §4 by plasma-enhanced chemical vapor deposition; §6: Photoresist is uniformly coated on the surface of the silicon dioxide layer. After pre-baking, photolithography, and etching, the silicon dioxide layer above the two-dimensional material region to be doped is etched into a thin silicon dioxide layer. §7: Precisely partitioned vacancies on the surface of two-dimensional materials are created by bombarding the surface of two-dimensional materials with high-energy hydrogen ions through a silicon dioxide mask layer, and the number of vacancies can be controlled according to different power and processing time. §8: Removal of the silicon dioxide mask layer by wet etching; §9: Two-dimensional materials with surface vacancies are exposed to oxygen flow for oxidation to achieve precise and controllable surface charge transfer doping, thereby obtaining a two-dimensional material channel layer for transistors (2); §10: The surface of the two-dimensional material channel layer (2) obtained in step §9 is subjected to photolithography and electron beam evaporation to deposit source and drain electrode metals. After the metals are deposited, the source electrode (3) and drain electrode (4) are formed by a stripping process. §11: A gate dielectric layer (5) is obtained by magnetron sputtering aluminum oxide, aluminum nitride or silicon nitride on the surface of the two-dimensional material channel layer (2), source electrode (3) and drain electrode (4); §12: The gate electrode (6) is fabricated on the surface of the gate dielectric layer (5) by photolithography, electron beam evaporation deposition of gate metal and lift-off process; §13: The area above the source and drain electrodes is patterned by photolithography, and then the gate dielectric layer is etched to expose the source and drain electrodes, thus completing the fabrication of the device.

2. The method according to claim 1, characterized in that: Step §2 uses chemical vapor deposition to grow a thin film of the two-dimensional material to be transferred on the substrate surface. The steps include the following: 2a) Select reaction precursors according to the type of two-dimensional material thin film to be grown, and place different types of reaction precursors in the high-temperature zone and low-temperature zone of the tube furnace according to their reaction requirements. 2b) Place the clean substrate used for growing the two-dimensional material film in an area a few centimeters away from the sample in the high-temperature zone to facilitate film growth; 2c) Set the working gas and keep the gas flow constant during the deposition process. Increase the temperature at a rate of 15-20 °C / min until the set working temperature is reached. Then, control the reaction time according to the required thickness of the two-dimensional material film to obtain the two-dimensional material film to be transferred.

3. The method according to claim 1, characterized in that: The PMMA-assisted transfer method in step §3 is implemented as follows: Spin-coat PMMA onto the surface of the layer to be transferred and cure it on a hot plate at 90-120°C. The sample is immersed in the solution required for substrate separation for two hours to separate the PMMA-to-transfer layer from its substrate. The separated floating PMMA-to-transfer layer was transferred to the target substrate and cured. The PMMA was removed by soaking in acetone, then cleaned with IPA, and finally dried with nitrogen.

4. The method according to claim 1, characterized in that: The plasma-enhanced chemical vapor deposition described in step §5 involves fixing the pre-cleaned sample onto a substrate inside the PECVD reaction chamber, introducing Ar gas to remove residual impurities in the reaction chamber, and starting the PECVD system under set conditions to begin SiO2 thin film deposition. After deposition, pure Ar gas is introduced to purge the chamber for 1 minute to prevent contamination.

5. The method according to claim 1, characterized in that: In step §7, the vacancy on the surface of the two-dimensional material is specifically created by placing the silicon dioxide mask layer sample, which has been thinned by partition etching, in a reactive ion etching chamber and exposing it to hydrogen plasma. The RF power and hydrogen gas flow rate in the RIE chamber are maintained at 100W and 50sccm, respectively, and the vacancy is created by bombarding the mask layer with high-energy hydrogen ions.

6. The method according to claim 1, characterized in that: The magnetron sputtering described in step §11 involves heating the substrate to a set temperature, using the appropriate target material and working gas according to the type of encapsulation protective layer, and growing the gate dielectric layer to be etched on the substrate or two-dimensional material channel layer by controlling the sputtering time according to the required thickness at the reaction chamber temperature through a magnetron sputtering system.

7. A controllably doped p-type two-dimensional transistor prepared by any one of claims 1-6, characterized in that, include: Insulating substrate (1), two-dimensional material channel layer (2), source electrode (3) and drain electrode (4) located above the two ends of the two-dimensional material channel layer, gate dielectric layer (5) located above the two-dimensional material channel layer and the source electrode and drain electrode, and gate electrode (6) located above the gate dielectric layer. The two-dimensional material channel layer (2) is made of one of the two-dimensional semiconductor materials, which includes at least tungsten diselenide, molybdenum diselenide, and molybdenum disulfide. It is then subjected to controllable surface charge transfer doping, that is, natural oxidation treatment after creating partitioned vacancies on its surface.

8. The transistor according to claim 7, characterized in that: The two-dimensional material channel layer (2) has a multi-layer structure.

9. The transistor according to claim 7, characterized in that, The insulating substrate (1) is made of any one of the insulating materials SiO2 / Si, sapphire, and diamond; the gate dielectric layer (5) is made of any one of the insulating dielectric layers aluminum oxide, aluminum nitride, and silicon nitride; the gate electrode (6) is made of Ni / Au, Pd / Au, or Pt / Au metal; the source electrode (3) and drain electrode (4) include Pd / Au and Pt / Au.

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