Power MOS drive circuit

Abstract

The present application discloses a power MOS driver circuit, comprising: a second NMOS transistor NM2, a third NMOS transistor NM3, and a clamping circuit 3 arranged between the second NMOS transistor NM2 and the third NMOS transistor NM3, wherein the source of the second NMOS transistor NM2 and the drain of the third NMOS transistor NM3 are connected to generate an output control square wave; and the clamping circuit 3 is used to limit the high level of the output control square wave.

Description

Technical Field

[0001] The present application relates to the technical field of power MOS drive circuits, and in particular to a power MOS drive circuit. Background Art

[0002] As an electronic switching device, power MOS transistors (MOS transistors) offer fast switching speeds, low conduction losses, and low manufacturing costs, making them widely used in power supply applications such as battery chargers and power adapters. Nearly all power supply products rely on electronic switches, and as the most widely used electronic switch, matching the device characteristics of power MOS transistors during use has become a key research topic, with ensuring their reliability being paramount.

[0003] The gate and source breakdown voltages of most current power MOS switches do not exceed 30V. The device characteristic of a power MOS switch is that as the gate-source voltage increases, its on-resistance decreases, resulting in lower switching losses and higher system efficiency. Conversely, as the gate-source voltage decreases, its on-resistance increases, resulting in greater switching losses and lower system efficiency. In practical applications, it is necessary to select an appropriate drive voltage (generally controlled between 10V and 20V) to minimize conduction losses while preventing the gate-source voltage from being too high, which could lead to breakdown damage.

[0004] The driving circuit of the traditional power MOS switch adopts Figure 2 The structure shown uses a Zener diode to solve the problem of outputting a high-level square wave when the power supply VCC is too high. However, when VCC is too low, due to the influence of the NMOS transistor NM2's conduction threshold VTH, the output high-level square wave will be lower than VCC by the NM2 transistor's threshold Vth, that is, VCC - Vth.

[0005] For this problem, refer to Figure 3 As shown, the traditional power MOS switch driver circuit is optimized by connecting a PMOS transistor PM2 in parallel with the second NMOS transistor NM2. When the power supply VCC is too low, the second NMOS transistor NM2 is turned on simultaneously with PM2, clamping the high-level output square wave to VCC. This solution solves the drive voltage issue when VCC is too low, but the current capability of a PMOS transistor is approximately one-third that of an NMOS transistor. Therefore, while providing the same drive capability, the PMOS transistor requires more area and is more expensive.

[0006] In the existing solutions for solving the problem that the power MOS switch cannot be started when the voltage of the power supply VCC in the power MOS driving circuit is too low, there are technical problems such as high cost and high power consumption of the power MOS driving circuit. No effective solution has been proposed so far. Summary of the Invention

[0007] The present disclosure provides a power MOS drive circuit to solve the technical problems of high cost and high power consumption of the power MOS drive circuit in the prior art, in which the power MOS switch cannot be started when the voltage of the power supply VCC in the power MOS drive circuit is too low.

[0008] According to one aspect of the present application, a power MOS driving circuit is provided, comprising: a second NMOS transistor, a third NMOS transistor, and a clamping circuit arranged between the second NMOS transistor and the third NMOS transistor, wherein the source of the second NMOS transistor and the drain of the third NMOS transistor are connected to generate an output control square wave; and the clamping circuit is used to limit the high level of the output control square wave.

[0009] Thus, a power MOS driver circuit provided by an embodiment of the present application outputs an output control square wave for activating a switch by connecting the source of a second NMOS transistor and the drain of a third NMOS transistor. The second NMOS transistor is configured to output a high level of the control square wave, and the third NMOS transistor is configured to output a low level of the control square wave. Furthermore, the present invention provides a clamping circuit at the connection between the second and third NMOS transistors, wherein the clamping circuit is configured to control the high level of the output control square wave. This achieves the technical effect of preventing the gate of the power MOS switch from being broken down due to the high level of the output control square wave being too high. Furthermore, the present invention, through a simple circuit structure, implements high and low voltage clamping for the gate drive of the power MOS switch. The high voltage prevents gate breakdown of the power MOS switch, while the low voltage prevents excessive conduction losses of the power MOS switch due to low drive voltage. This achieves the technical effect of saving circuit area and cost while providing sufficient drive capability. This further solves the technical problems of high cost and high power consumption of the power MOS driver circuit in existing solutions to the problem of being unable to activate the power MOS switch when the power supply VCC voltage in the power MOS driver circuit is too low.

[0010] Based on the detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings below, those skilled in the art will become more aware of the above and other objects, advantages and features of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Hereinafter, some specific embodiments of the present application will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0012] Figure 1 is a schematic diagram of a power MOS driving circuit according to an embodiment of the present application;

[0013] Figure 2 is a schematic diagram of a driving circuit of a conventional power MOS switch described in the background art; and

[0014] Figure 3 It is a schematic diagram of an optimized driving circuit of a traditional power MOS switch described in the background art. DETAILED DESCRIPTION

[0015] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0016] In order to enable those skilled in the art to better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0017] It should be noted that the terms "first," "second," and the like in the specification and claims of the present disclosure and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present disclosure described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0018] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0019] Figure 1 Schematic diagram of a power MOS drive circuit according to an embodiment of the present application. Figure 1 As shown, the power MOS driving circuit includes: a second NMOS transistor NM2, a third NMOS transistor NM3, and a clamping circuit 3 arranged between the second NMOS transistor NM2 and the third NMOS transistor NM3, wherein the source of the second NMOS transistor NM2 and the drain of the third NMOS transistor NM3 are connected to generate an output control square wave; and the clamping circuit 3 is used to limit the high level of the output control square wave.

[0020] As mentioned in the background technology, the traditional power MOS switch driving circuit adopts Figure 2 The structure shown in the figure uses a Zener diode to solve the problem of outputting a high level square wave when the power supply VCC is too high. However, when VCC is too low, due to the influence of the conduction threshold VTH of the NMOS transistor NM2, the high level of the output square wave will be lower than VCC by the threshold Vth of the NM2 transistor, that is, VCC-Vth. To solve this problem, refer to Figure 3 As shown, the traditional power MOS switch driver circuit is optimized by connecting a PMOS transistor PM2 in parallel with the second NMOS transistor NM2. When the power supply VCC is too low, the second NMOS transistor NM2 is turned on simultaneously with PM2, clamping the high-level output square wave to VCC. This solution solves the drive voltage issue when VCC is too low, but the current capability of a PMOS transistor is approximately one-third that of an NMOS transistor. Therefore, while providing the same drive capability, the PMOS transistor requires more area and is more expensive.

[0021] In view of this, this embodiment provides a power MOS driver circuit that connects the source of a second NMOS transistor NM2 and the drain of a third NMOS transistor NM3 to output an output control square wave for activating a power MOS switch. The second NMOS transistor NM2 is configured to output a high-level control square wave, while the third NMOS transistor NM3 is configured to output a low-level control square wave. Furthermore, the present invention provides a clamping circuit 3 between the second NMOS transistor NM2 and the third NMOS transistor NM3. When the high-level output control square wave is too high, the clamping circuit 3 controls the high-level output control square wave to not exceed the maximum voltage of the power MOS switch. This prevents the gate of the power MOS switch from being broken down due to the high-level output control square wave. Furthermore, the present invention, through a simple circuit structure, implements high- and low-voltage clamping for the gate drive of the power MOS switch. The high-voltage clamp prevents gate breakdown of the power MOS switch, while the low-voltage clamp prevents excessive conduction losses of the power MOS switch due to low-voltage drive. This achieves the technical effect of saving circuit area and cost while providing sufficient drive capability. This solves the technical problems of high cost and high power consumption of the power MOS drive circuit in the prior art in the existing solution for the problem that the power MOS switch cannot be started when the voltage of the power supply VCC in the power MOS drive circuit is too low.

[0022] Optionally, the power MOS driving circuit further includes: a level conversion circuit 2, wherein the second NMOS transistor NM2 and the third NMOS transistor NM3 are arranged in the level conversion circuit 2, and the level conversion circuit 2 is used to convert the received input control square wave into an output control square wave that can drive the power MOS switch.

[0023] Specifically, refer to Figure 1 As shown, the power MOS driver circuit further includes a level shifter circuit 2, wherein the second NMOS transistor NM2 and the third NMOS transistor NM3 are both disposed in the level shifter circuit 2. The level shifter circuit 2 is configured to convert an input control square wave into an output control square wave capable of driving the power MOS switch. Thus, the level shifter circuit 2 achieves the technical effect of controlling the on and off of the power MOS switch.

[0024] Optionally, the power MOS driving circuit further includes: a power supply circuit 1 , which is connected to the level conversion circuit 2 and is used to provide an input voltage to the level conversion circuit 2 .

[0025] Specifically, refer to Figure 1 As shown, the power supply circuit 1 is connected to the level conversion circuit 2 to provide control power to the level conversion circuit, that is, the power supply circuit 1 provides input voltage to the level conversion circuit 2.

[0026] Optionally, the power MOS driving circuit further includes: a power supply VCC, and the power supply circuit 1 includes: a current limiting circuit I DC , a first Zener diode ZD1, a first capacitor C1, a first NPN transistor NPN1 and a second NPN transistor NPN2, wherein the current limiting circuit I DC The positive terminal is connected to the power supply VCC, and the current limiting circuit I DC The negative end of the first Zener diode ZD1 is connected to the cathode of the first Zener diode ZD1; the cathode of the first Zener diode ZD1 is connected to the base of the first NPN transistor NPN1 and the base of the second NPN transistor NPN2, and the anode of the first Zener diode ZD1 is connected to the ground; the first capacitor C1 is connected in parallel with the first Zener diode ZD1; the base of the first NPN transistor NPN1 is connected to the cathode of the first Zener diode ZD1, the collector of the first NPN transistor NPN1 is connected to the power supply VCC, and the emitter of the first NPN transistor NPN1 is connected to the level conversion circuit 2; and the base of the second NPN transistor NPN2 is connected to the cathode of the first Zener diode ZD1, the collector of the second NPN transistor NPN2 is connected to the power supply VCC, and the emitter of the second NPN transistor NPN2 is connected to the level conversion circuit 2.

[0027] Specifically, refer to Figure 1 As shown, the power supply VCC provides power to the power MOS drive circuit. And the current limiting circuit I DC , its positive terminal is connected to the power supply VCC, its negative terminal is connected to the cathode of the first Zener diode ZD1, and the anode of the first Zener diode ZD1 is grounded. A first capacitor C1 is connected in parallel to both ends of the first Zener diode ZD1. The bases of the first NPN transistor NPN1 and the second NPN transistor NPN2 are both connected to the cathode of the first Zener diode ZD1, and the collectors of the first NPN transistor NPN1 and the second NPN transistor NPN2 are both connected to the power supply VCC. The emitter of the first NPN transistor NPN1 provides power to the level conversion circuit 2. The emitter of the second NPN transistor NPN2 is connected to the source of the PMOS transistor PM. The emitter of the first NPN transistor NPN1 provides power to the level conversion circuit 2, and the emitter of the second NPN transistor NPN2 provides power to the PMOS transistor PM. The first Zener diode ZD1 provides base clamping for the first NPN transistor NPN1 and the second NPN transistor NPN2 (where clamping is a measure to limit the potential to a specified potential), which is intended to prevent the emitters of the first NPN transistor NPN1 and the second NPN transistor NPN2 from providing an excessively high voltage to the level conversion circuit 2. DC The purpose is to provide base drive current to the first NPN transistor NPN1 and the second NPN transistor NPN2 without damaging the first Zener diode ZD1.

[0028] In addition, the first Zener diode ZD1 will function only when the voltage of the power source VCC reaches a preset start-up voltage of the first Zener diode ZD1 , thereby clamping the voltages of the emitters of the first NPN transistor NPN1 and the second NPN transistor NPN2 .

[0029] In addition, the emitter voltage of the first NPN transistor NPN1 and the second NPN transistor NPN2 = V ZD1 -0.7V(V ZD1 is the breakdown voltage of the first Zener diode ZD1, and 0.7 V is the voltage drop between the base and emitter of the NPN, which serves as the power supply voltage of the level conversion circuit 2 and the clamping circuit 3.

[0030] Optionally, the level conversion circuit 2 includes: a level converter 21, wherein the level converter 21 is used to receive an input control square wave and an input voltage of the emitter of the first NPN transistor NPN1, and convert the input control square wave into a high or low level that matches the input voltage, and the level converter 21 includes a first input terminal 211, a second input terminal 212, a first output terminal Q1 and a second output terminal Q2, wherein the first input terminal 211 of the level converter 21 is connected to the emitter of the first NPN transistor NPN1 for receiving the input voltage, and the second input terminal 212 of the level converter 21 is used to receive the input control square wave; and the first output terminal Q1 and the second output terminal Q2 of the level converter 21 are used to output the converted level signal.

[0031] Specifically, refer to Figure 1 As shown, the second input terminal 212 of the level shifter 21 is connected to the input control square wave, the first output Q1 of the level shifter 21 is connected to the gates of the PMOS transistor PM and the first NMOS transistor NM1, and the second output Q2 of the level shifter 21 is connected to the gate of the third NMOS transistor NM3. Thus, the level shifter 21 in the level shifter circuit 2 can convert the received input control square wave into a corresponding output voltage.

[0032] In addition, when the input voltage is 10V and the high and low levels of the input control square wave are ground and 5V respectively, the level converter 21 converts the high and low levels of the input control square wave into ground and 10V, that is, converts the high level of the input control square wave into the voltage of the emitter of the first NPN transistor NPN1.

[0033] Optionally, the level conversion circuit 2 further includes: a PMOS transistor PM, a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3, wherein the drain of the PMOS transistor PM is connected to the drain of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2, the source of the PMOS transistor PM is connected to the emitter of the second NPN transistor NPN2, the gate of the PMOS transistor PM is connected to the first output terminal Q1 of the level converter 21 and the gate of the first NMOS transistor NM1; the gate of the first NMOS transistor NM1 is connected to the first output terminal Q1 of the level converter 21, the drain of the first NMOS transistor NM1 is connected to the emitter of the second NPN transistor NPN2, and the gate of the PMOS transistor PM is connected to the emitter of the second NPN transistor NPN2. The drain of the PMOS transistor PM is connected to the gate of the second NMOS transistor NM2, and the source of the first NMOS transistor NM1 is connected to ground; the gate of the second NMOS transistor NM2 is connected to the drain of the PMOS transistor PM and the drain of the first NMOS transistor NM1, the drain of the second NMOS transistor NM2 is connected to the power supply VCC, and the source of the second NMOS transistor NM2 is connected to the drain of the third NMOS transistor NM3; and the gate of the third NMOS transistor NM3 is connected to the second output terminal Q2 of the level shifter 21, the drain of the third NMOS transistor NM3 is connected to the source of the second NMOS transistor NM2, and the source of the third NMOS transistor NM3 is connected to ground.

[0034] The drain of the PMOS transistor PM is connected to the drain of the first NMOS transistor NM1 and to the gate of the second NMOS transistor NM2. The source of the first NMOS transistor NM1 is grounded. The drain of the second NMOS transistor NM2 is connected to the power supply VCC. The source of the second NMOS transistor NM2 is connected to the drain of the third NMOS transistor NM3, generating an output control square wave. The source of the third NMOS transistor NM3 is grounded. These components can generate a control square wave for activating the MOS switch.

[0035] In addition, when the voltages of the first output terminal Q1 and the second output terminal Q2 are high, the third NMOS transistor NM3 is turned on, the first NMOS transistor NM1 is also turned on, and the PMOS transistor PM is turned off, so the output is low. At the same time, the second capacitor C2 is charged to V ZD1 -0.7V.

[0036] When the voltages of the first output terminal Q1 and the second output terminal Q2 are low, the third NMOS transistor NM3 is turned off, the first NMOS transistor NM1 is also turned off, and the PMOS transistor PM is turned on. At this time, the gate voltage of the second NMOS transistor NM2 is equal to V ZD1-0.7V, so the second NMOS transistor NM2 is turned on. Since the voltage on the second capacitor C2 always exists, the gate voltage of the second NMOS transistor NM2 = Vout + V C2 =Vout+V ZD1 -0.7V, as the output voltage rises, the gate voltage of the second NMOS transistor NM2 also rises, always higher than the output V ZD1 -0.7V (This voltage is several V higher than the threshold Vth of the NMOS transistor. Therefore, when the power supply VCC is very low, the second NMOS transistor NM2 is equivalent to a switch, and the high level of the output will be equal to the power supply VCC, rather than VCC-Vth. When the power supply VCC is relatively high, the gate voltage of the second NMOS transistor NM2 = Vout + V C2 =Vout+V ZD1 -0.7V>V ZD2 After that, the second capacitor C2 will discharge through the second Zener diode ZD2, and the gate of the second NMOS transistor NM2 will be clamped to V ZD2 , so the high level of the output is equal to V ZD2 -Vth.

[0037] In addition, for example: Vth = 3.0V (fixed), if you choose V ZD1 =V ZD2 =15.0V, then when VCC = 30V, when Q1 and Q2 are low, the gate voltage of the second NMOS transistor NM2 is 15V (equal to V ZD2),the output is equal to 12.0V. When VCC = 10V, when the voltages of the first output terminal Q1 and the second output terminal Q2 are low, since the second capacitor C2 is charged to 9.3V (10V - 0.7V) when the third NMOS transistor NM3 and the first NMOS transistor NM1 are turned on. Then when the first NMOS transistor NM1 and the third NMOS transistor NM3 are turned off, the PMOS transistor PM is turned on, and the gate of the second NMOS transistor NM2 is equal to 9.3V, the second NMOS transistor NM2 is turned on, and the output starts to rise. Since the second capacitor C2 does not discharge, the 9.3V voltage on the second capacitor C2 does not change. When the output rises, the voltage at the upper end of the second capacitor C2 (i.e., the end connected to the second NPN transistor NPN2) also rises with the output voltage (Vout + 9.3V). When Vout rises to 5.7V, the voltage at the upper end of C2 reaches 15V. When the output continues to rise, the second Zener diode ZD2 is broken down, and the voltage at the upper end of the second capacitor C2 is clamped at 15V. (During this period, PM is conducting, and the voltage at the upper end of the second capacitor C2 is equal to the voltage of the gate of NM2). When the output continues to rise, the gate voltage of the second NMOS transistor NM2 remains unchanged. At this time, the highest output is equal to VCC = 10V.

[0038] In addition, when the first Zener diode ZD1 is broken down, setting the base voltages of the first NPN transistor NPN1 and the second NPN transistor NPN2 is also setting the power supply voltage of the drive level conversion circuit 2. When the second Zener diode ZD2 is broken down, it is used to set the highest voltage of the output control square wave, that is, V ZD2 - Vth. The breakdown voltage of the first Zener diode ZD1 is V ZD1 , and the breakdown voltage of the second Zener diode ZD2 is V ZD2 . Among them, V ZD1 - 0.7V must be less than or equal to V ZD2 , so as to prevent direct conduction and leakage of the NPN2 and ZD2 path. V ZD2 - V ZD1 must also be less than the breakdown voltage BV EBO between the emitter E and the base B of the second NPN transistor NPN2 to prevent damage to the second NPN transistor NPN2. That is, - 0.7V < V ZD2 - V ZD1 < BV of NPN2 EBO 5].

[0039] Optionally, the clamping circuit 3 includes: a second capacitor C2 and a second Zener diode ZD2, wherein the first end of the second capacitor C2 is connected to the emitter of the second NPN transistor NPN2, and the second end of the second capacitor C2 is connected to the source of the second NMOS transistor NM2; and the cathode of the second Zener diode ZD2 is connected to the emitter of the second NPN transistor NPN2, and the anode of the second Zener diode ZD2 is connected to the ground.

[0040] Specifically, refer to Figure 1 As shown, one end of the second capacitor C2 is connected to the emitter of the second NPN transistor NPN2, and the other end of the second capacitor C2 is connected to the output. The cathode of the second Zener diode ZD2 is connected to the emitter of the second NPN transistor NPN2, and the anode of the second Zener diode ZD2 is grounded. The second Zener diode ZD2 clamps the highest level of the output control square wave when the power supply VCC voltage is high, thereby protecting the power MOS switch gate when the power supply VCC voltage is too high. The function of the second capacitor C2 is to clamp the highest level of the output control square wave to the power supply VCC when the power supply VCC voltage is low, preventing the power MOS drive voltage from being too low, thereby increasing conduction losses and reducing system efficiency.

[0041] Thus, a power MOS driver circuit provided by an embodiment of the present application outputs an output control square wave for starting the switch by connecting the source of the second NMOS transistor NM2 and the drain of the third NMOS transistor NM3. The second NMOS transistor NM2 is used to output a high level of the control square wave, and the third NMOS transistor NM3 is used to output a low level of the control square wave. Furthermore, the present invention provides a clamping circuit 3 at the connection between the second NMOS transistor NM2 and the third NMOS transistor NM3, wherein the clamping circuit 3 is used to control the high level of the output control square wave. This achieves the technical effect of preventing the high level of the output control square wave from being too high, causing the gate of the power MOS switch to breakdown. Furthermore, the present invention, through a simple circuit structure, implements high and low voltage clamping settings for the power MOS gate drive. The high voltage prevents the gate of the power MOS switch from breakdown, and the low voltage prevents excessive conduction losses of the power MOS switch caused by too low a drive voltage. This achieves the technical effect of saving circuit area and cost while providing sufficient drive capability. This solves the technical problems of high cost and high power consumption of the power MOS drive circuit in the prior art in the existing solution for the problem that the power MOS switch cannot be started when the voltage of the power supply VCC in the power MOS drive circuit is too low.

[0042] In addition, PMOS: P-channel metal oxide semiconductor FET, P-channel metal oxide semiconductor field effect transistor;

[0043] NMOS: N-channel metal oxide semiconductor FET, N-channel metal oxide semiconductor field effect transistor.

[0044] NPN:Negative Positive Negative transistor, NPN transistor.

[0045] In addition, the present invention is a driving circuit for a switching power MOS, referring to Figure 1 As shown, it includes a power supply circuit 1 (power supply generation circuit), a level conversion circuit 2 (drive level conversion circuit) and a clamp circuit 3 (power supply VCC high and low voltage clamp circuit). Figure 1 As shown, it only includes the current limiting circuit I DC , a first Zener diode ZD1, a first capacitor C1, a first NPN transistor NPN1 and a second NPN transistor NPN2, a level converter 21, a PMOS transistor PM, a second NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a second capacitor C2 and a second Zener diode ZD2.

[0046] Current limiting circuit I DC, its positive terminal is connected to the power supply VCC, the negative terminal is connected to the cathode of the first Zener diode ZD1, and the anode of the first Zener diode ZD1 is grounded; the first capacitor C1 is connected in parallel to the two ends of the first Zener diode ZD1; the bases of the first NPN transistor NPN1 and the second NPN transistor NPN2 are both connected to the cathode of the first Zener diode ZD1, and the collectors of the first NPN transistor NPN1 and the second NPN transistor NPN2 are both connected to the power supply VCC; the emitter of the first NPN transistor NPN1 provides power for the level converter; the emitter of the second NPN transistor NPN2 is connected to the source of the PMOS transistor PM; the second input terminal 212 of the level converter 21 is connected to the input control square wave, and the first output terminal Q1 of the level converter 21 is connected to the PMOS transistor PM and the first NMOS transistor NM1. The gate, the second output terminal Q2 of the level converter 21 is connected to the gate of the third NMOS transistor NM3; the drain of the PMOS transistor PM is connected to the drain of the first NMOS transistor NM1 and to the gate of the second NMOS transistor NM2, and the source of the first NMOS transistor is grounded; the drain of the second NMOS transistor NM2 is connected to the power supply VCC, the source of the second NMOS transistor NM2 is connected to the drain of the third NMOS transistor NM3, generating an output control square wave; the source of the third NMOS transistor NM3 is grounded; one end of the second capacitor C2 is connected to the emitter of the second NPN transistor NPN2, and the other end of the second capacitor C2 is connected to the output; the cathode of the second Zener diode ZD2 is connected to the emitter of the second NPN transistor NPN2, and the anode of the second Zener diode ZD2 is grounded.

[0047] Current limiting circuit I DC , its purpose is to provide base drive current for the first NPN transistor NPN1 and the second NPN transistor NPN2 without damaging the first Zener diode ZD1; the first Zener diode ZD1 provides base clamping for the first NPN transistor NPN1 and the second NPN transistor NPN2, its purpose is to prevent the voltage provided by the emitters of the first NPN transistor NPN1 and the second NPN transistor NPN2 from being too high; the emitter of the first NPN transistor NPN1 provides power supply for the level conversion circuit; the emitter of the second NPN transistor NPN2 provides power supply for the PMOS transistor PM; the second Zener diode ZD2 clamps the highest level of the output control square wave when the power supply VCC is high, thereby protecting the power MOS gate when VCC is too high; the function of the second capacitor C2 is to clamp the highest level of the output control square wave to VCC when VCC is low, thereby preventing the power MOS drive voltage from being too low, thereby increasing conduction loss and reducing system efficiency.

[0048] The present invention provides a driving circuit for a switching power MOS transistor (MOSFET). This circuit structure reduces the number of components in the circuit, simplifies the design, reduces static and dynamic power consumption, shrinks the effective area of ​​the integrated circuit chip, and reduces production costs. Furthermore, when the VCC power supply is too high, the high level of the output square wave is clamped to prevent damage to the gate of the MOSFET. When the VCC power supply is too low, the high level of the output square wave is clamped to VCC, providing sufficient driving capability for the MOSFET, reducing conduction losses, and improving system efficiency.

[0049] The embodiment of the present invention simplifies the design and reduces the cost. At the same time, the power MOS drive circuit applied to the switching power supply shown in the present invention can meet the driving requirements of most power supplies for power MOS switches.

[0050] Unless otherwise specifically stated, the relative arrangement of the parts and steps, the numerical expressions and the numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the drawings are not drawn according to actual proportional relationships. The techniques, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and equipment should be considered as part of the authorization specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as being merely exemplary and not as limitations. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that similar numbers and letters represent similar items in the following figures, and therefore, once an item is defined in one figure, it does not need to be further discussed in subsequent figures.

[0051] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship of a device or feature to other devices or features as shown in the figures. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figures. For example, if the device in the drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0052] In the description of the present disclosure, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "horizontal, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present disclosure and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present disclosure; the directional words "inside and outside" refer to the inside and outside relative to the outline of each component itself.

[0053] The above description is merely a preferred embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A power MOS driving circuit, characterized in that: include: A second NMOS transistor (NM2), a third NMOS transistor (NM3), and a clamping circuit (3) arranged between the second NMOS transistor (NM2) and the third NMOS transistor (NM3), wherein The source of the second NMOS transistor (NM2) is connected to the drain of the third NMOS transistor (NM3) to generate an output control square wave; as well as The clamping circuit (3) is used to limit the high level of the output control square wave; it also includes: a power supply (VCC) for providing voltage to the power MOS drive circuit, and the power supply circuit (1) includes: a current limiting circuit (IDC), a first Zener diode (ZD1), a first capacitor (C1), a first NPN transistor (NPN1) and a second NPN transistor (NPN2), wherein The positive terminal of the current limiting circuit (IDC) is connected to the power supply (VCC), and the negative terminal of the current limiting circuit (IDC) is connected to the cathode of the first Zener diode (ZD1); The cathode of the first Zener diode (ZD1) is connected to the base of the first NPN transistor (NPN1) and the base of the second NPN transistor (NPN2), and the anode of the first Zener diode (ZD1) is connected to the ground; The first capacitor (C1) is connected in parallel with the first Zener diode (ZD1); The base of the first NPN transistor (NPN1) is connected to the cathode of the first Zener diode (ZD1), the collector of the first NPN transistor (NPN1) is connected to the power supply (VCC), and the emitter of the first NPN transistor (NPN1) is connected to the level conversion circuit (2); and The base of the second NPN transistor (NPN2) is connected to the cathode of the first Zener diode (ZD1), the collector of the second NPN transistor (NPN2) is connected to the power supply (VCC), and the emitter of the second NPN transistor (NPN2) is connected to the level conversion circuit (2); The level conversion circuit (2) comprises: a level converter (21), wherein the level converter (21) is used to receive an input control square wave and an input voltage of the emitter of the first NPN transistor (NPN1), convert the input control square wave into a high or low level that matches the input voltage, and the level converter (21) comprises a first input terminal (211), a second input terminal (212), a first output terminal (Q1), and a second output terminal (Q2), wherein The first input terminal (211) of the level converter (21) is connected to the emitter of the first NPN transistor (NPN1) for receiving the input voltage, and the second input terminal (212) of the level converter (21) is used to receive the input control square wave; and The first output terminal (Q1) and the second output terminal (Q2) of the level converter (21) are used to output the converted level signal; The level conversion circuit (2) further comprises: a PMOS transistor (PM) and a first NMOS transistor (NM1), wherein The drain of the PMOS transistor (PM) is connected to the drain of the first NMOS transistor (NM1) and the gate of the second NMOS transistor (NM2), the source of the PMOS transistor (PM) is connected to the emitter of the second NPN transistor (NPN2), and the gate of the PMOS transistor (PM) is connected to the first output terminal (Q1) of the level converter (21) and the gate of the first NMOS transistor (NM1); The gate of the first NMOS transistor (NM1) is connected to the first output terminal (Q1) of the level converter (21), the drain of the first NMOS transistor (NM1) is connected to the drain of the PMOS transistor (PM) and the gate of the second NMOS transistor (NM2), and the source of the first NMOS transistor (NM1) is connected to the ground; The gate of the second NMOS transistor (NM2) is connected to the drain of the PMOS transistor (PM) and the drain of the first NMOS transistor (NM1), the drain of the second NMOS transistor (NM2) is connected to the power supply (VCC), and the source of the second NMOS transistor (NM2) is connected to the drain of a third NMOS transistor (NM3); and The gate of the third NMOS transistor (NM3) is connected to the second output terminal (Q2) of the level converter (21), the drain of the third NMOS transistor (NM3) is connected to the source of the second NMOS transistor (NM2), and the source of the third NMOS transistor (NM3) is connected to the ground; The clamping circuit (3) comprises: a second capacitor (C2) and a second Zener diode (ZD2), wherein A first terminal of the second capacitor (C2) is connected to the emitter of the second NPN transistor (NPN2), and a second terminal of the second capacitor (C2) is connected to the source of the second NMOS transistor (NM2); and A cathode of the second Zener diode (ZD2) is connected to an emitter of the second NPN transistor (NPN2), and an anode of the second Zener diode (ZD2) is connected to ground.

2. The power MOS driving circuit according to claim 1, characterized in that: Also includes: A level conversion circuit (2), wherein the second NMOS transistor (NM2) and the third NMOS transistor (NM3) are arranged in the level conversion circuit (2), and the level conversion circuit (2) is used to convert a received input control square wave into an output control square wave that can drive a power MOS switch.

3. The power MOS driving circuit according to claim 2, characterized in that: Also includes: A power supply circuit (1), the power supply circuit (1) being connected to the level conversion circuit (2) and being used for providing an input voltage to the level conversion circuit (2).

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