High-Speed I / O Interface Input Circuit

Abstract

The present invention provides a high-speed I / O interface input circuit, comprising: an interface module, where two common-mode level input interfaces are correspondingly connected to two differential signal input interfaces through two input resistors, for configuring and connecting the four interfaces to process differential signals and generate differential input signals; a high-voltage domain module, for converting the differential input signals in the high-voltage domain to obtain high-voltage domain current signals, where the input common-mode voltage V CM satisfies V CM ≥ 1.0 V, and the input differential-mode voltage V ID satisfies V ID ≥ 100 mV; a low-voltage domain module, for converting the high-voltage domain current signals in the low-voltage domain to obtain low-voltage domain voltage signals, and performing differential-to-single-ended conversion on the low-voltage domain voltage signals and then outputting; an output driving module, for driving and enhancing the single-ended signals and then outputting. Through the high-speed I / O interface input circuit provided by the present invention, the problem that the existing high-speed I / O interface input circuit cannot be compatible with different electrical specifications is solved.

Description

Technical Field

[0001] The present invention relates to an I / O interface circuit, and particularly to a high-speed I / O interface input circuit. Background Art

[0002] Input / output circuits are an important part of integrated circuit chips. In particular, input / output circuits involving high-speed signals are becoming increasingly common in current chip products. Process manufacturers usually only provide standard CMOS I / O interface input / output circuits with a signal rate not exceeding 100 MHz. When a chip product requires a high-speed input / output circuit, the designer must customize the design.

[0003] When a chip product requires a high-speed I / O interface input circuit, the designer must customize the design according to a certain electrical specification. Due to historical reasons, interface signal electrical specifications such as CML (Current Mode Logic), LVDS (Low Voltage Differential Signaling), LVECL (Low Voltage Emitter Coupled Logic), etc. are adopted in different electronic systems. Since the common-mode levels and swings of interface signals with different electrical specifications are different, it is difficult for the high-speed input circuit designed on a certain chip to be reused in new products with different electrical specifications. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a high-speed I / O interface input circuit to solve the problem that the existing high-speed I / O interface input circuit cannot be compatible with different electrical specifications.

[0005] To achieve the above purpose and other related purposes, the present invention provides a high-speed I / O interface input circuit, which includes: an interface module, a high-voltage domain module, a low-voltage domain module, and an output driver module.

[0006] The interface module includes 2 differential signal input interfaces and 2 common-mode level input interfaces. The 2 common-mode level input interfaces are correspondingly connected to the 2 differential signal input interfaces through 2 input resistors, and are used to configure and connect the 4 interfaces to process the differential signals and generate differential input signals.

[0007] The high-voltage domain module receives the differential input signal and is used to convert the differential input signal in the high-voltage domain to obtain a high-voltage domain current signal. Among them, the input common-mode voltage V CM satisfies V CM ≥1.0V, and the input differential-mode voltage V ID satisfies VID ≥100 mV;

[0008] The low-voltage domain module receives the high-voltage domain current signal, is used to convert the high-voltage domain current signal in the low-voltage domain to obtain a low-voltage domain voltage signal, and outputs the low-voltage domain voltage signal after differential-to-single-ended conversion;

[0009] The output driving module receives the single-ended signal and is used to output the single-ended signal after driving enhancement.

[0010] Optionally, the interface module further includes: 4 electrostatic protection units, connected to 4 interfaces, for filtering out signal interference.

[0011] Optionally, 2 differential signal input interfaces access the DC-coupled differential signal, and 2 common-mode level input interfaces are short-circuited and left floating to implement the DC coupling setting for the differential signal.

[0012] Optionally, 2 differential signal input interfaces access the AC-coupled differential signal through 2 capacitors, and 2 common-mode level input interfaces are short-circuited and connected to a fixed level to implement the AC coupling setting for the differential signal; wherein, the voltage value of the fixed level is greater than or equal to 1.0 V.

[0013] Optionally, 2 differential signal input interfaces access the DC-coupled differential signal, and 2 common-mode level input interfaces access different fixed levels to implement the hysteresis voltage setting for the differential signal; wherein, the fixed level accessed by the in-phase terminal common-mode level input interface is greater than the fixed level accessed by the anti-phase terminal common-mode level input interface, and the difference between the two is the set hysteresis voltage.

[0014] Optionally, the high-voltage domain module is implemented by a fully differential amplifier.

[0015] Optionally, the high-voltage domain module is implemented by a folded cascode amplifier.

[0016] Optionally, the high-voltage domain module includes: a current source, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor,

[0017] The gate terminals of the first NMOS transistor and the second NMOS transistor access the differential input signal, the source terminals of the first NMOS transistor and the second NMOS transistor are connected and grounded through the current source, the drain terminal of the first NMOS transistor is connected to the drain terminal of the first PMOS transistor, and the drain terminal of the second NMOS transistor is connected to the drain terminal of the second PMOS transistor;

[0018] The source terminals of the first PMOS transistor and the second PMOS transistor are connected to the high-voltage domain power supply voltage, the gate terminals of the first PMOS transistor and the second PMOS transistor are connected to the bias voltage, the drain terminal of the first PMOS transistor is connected to the source terminal of the third PMOS transistor, and the drain terminal of the second PMOS transistor is connected to the source terminal of the fourth PMOS transistor;

[0019] The gate terminals of the third PMOS transistor and the fourth PMOS transistor are connected to the bias voltage, and the drain terminals of the third PMOS transistor and the fourth PMOS transistor serve as the output terminals of the high-voltage domain module;

[0020] Wherein, the threshold voltages of the first NMOS transistor and the second NMOS transistor are less than 0.5V, and the overdrive voltage of the current source is less than 0.2V.

[0021] Optionally, the low-voltage domain module uses a current mirror to convert the high-voltage domain current signal in the low-voltage domain to obtain the low-voltage domain voltage signal.

[0022] Optionally, the low-voltage domain module includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor,

[0023] The drain terminals of the third NMOS transistor and the fourth NMOS transistor are correspondingly connected to the high-voltage domain current signal, the source terminals of the third NMOS transistor and the fourth NMOS transistor are grounded, the gate terminal of the third NMOS transistor is connected to its drain terminal and the gate terminal of the fifth NMOS transistor, and the gate terminal of the fourth NMOS transistor is connected to its drain terminal and the gate terminal of the sixth NMOS transistor;

[0024] The source terminals of the fifth NMOS transistor and the sixth NMOS transistor are grounded, the drain terminal of the fifth NMOS transistor is connected to the drain terminal of the fifth PMOS transistor and serves as the output terminal of the low-voltage domain module, and the drain terminal of the sixth NMOS transistor is connected to the drain terminal of the sixth PMOS transistor;

[0025] The source terminals of the fifth PMOS transistor and the sixth PMOS transistor are connected to the low-voltage domain power supply voltage, the gate terminal of the fifth PMOS transistor is connected to the gate terminal of the sixth PMOS transistor, and the gate terminal of the sixth PMOS transistor is connected to its drain terminal.

[0026] Optionally, the output driving module is implemented by an inverter chain with gradually increasing width-to-length ratios.

[0027] Optionally, the output driving module is implemented by a 3-stage inverter chain, wherein the width-to-length ratios of the 3-stage inverter chain are gradually increased in an arithmetic progression manner.

[0028] As described above, the high-speed I / O interface input circuit of the present invention proposes a high-speed I / O interface input circuit with a maximum speed of up to 1.5 GHz through the design of an interface module, a high-voltage domain module, a low-voltage domain module, and an output driver module. It can be compatible with three electrical specifications, namely CML, LVDS, and LVECL, improving the applicability of chip products using this high-speed I / O interface input circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It shows a schematic diagram of the high-speed I / O interface input circuit of the present invention.

[0030] Figure 2 It shows a schematic diagram of the high-speed I / O interface input circuit of the present invention for DC coupling configuration of four interfaces.

[0031] Figure 3 It shows a schematic diagram of the high-speed I / O interface input circuit of the present invention for AC coupling configuration of four interfaces.

[0032] Figure 4 It shows a schematic diagram of the high-speed I / O interface input circuit of the present invention for hysteresis voltage configuration of four interfaces. <~

[0033] Figure 5 It shows a schematic diagram of the high-voltage domain module and the low-voltage domain module in the high-speed I / O interface input circuit of the present invention.

[0034] DESCRIPTION OF REFERENCE NUMERALS

[0035] 10 High-speed I / O interface input circuit

[0036] 100 Interface module

[0037] 101 Electrostatic protection unit

[0038] 200 High-voltage domain module

[0039] 300 Low-voltage domain module

[0040] 400 Output driver module DETAILED DESCRIPTION OF THE INVENTION

[0041] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] Please refer to Figures 1 to 5It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Although only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation, the form, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex.

[0043] As Figure 1 shown, this embodiment provides a high-speed I / O interface input circuit. The high-speed I / O interface input circuit 10 includes: an interface module 100, a high-voltage domain module 200, a low-voltage domain module 300, and an output driver module 400.

[0044] The interface module 100 includes two differential signal input interfaces IN-P, IN-N and two common-mode level input interfaces CM-P, CM-N. The two common-mode level input interfaces CM-P, CM-N are correspondingly connected to the two differential signal input interfaces IN-P, IN-N through two input resistors R1, R2, and are used to configure and connect the four interfaces IN-P, IN-N, CM-P, CM-N to process the differential signal and generate differential input signals INP, INN. It should be noted that the statement in this embodiment that "the two common-mode level input interfaces CM-P, CM-N are correspondingly connected to the two differential signal input interfaces IN-P, IN-N through two input resistors R1, R2" means that "the common-mode level input interface CM-P is connected to the differential signal input interface IN-P through the input resistor R1, and the common-mode level input interface CM-N is connected to the differential signal input interface IN-N through the input resistor R2".

[0045] Specifically, the resistance values of the two input resistors R1, R2 are the same, usually 50Ω; an external resistor can be used, or the PCB metal trace inside the chip can be used. In actual applications, in order to simplify the interface circuit design, the PCB metal trace is usually used to implement it.

[0046] Specifically, in one implementation manner, the two differential signal input interfaces IN-P, IN-N are connected to the DC-coupled differential signal, and the two common-mode level input interfaces CM-P, CM-N are short-circuited and suspended, so as to implement the DC-coupling setting of the differential signal (as Figure 2 shown).

[0047] In another implementation manner, the two differential signal input interfaces IN-P, IN-N are correspondingly connected to the AC-coupled differential signal through two capacitors C1, C2, and the two common-mode level input interfaces CM-P, CM-N are short-circuited and connected to a fixed level V CM , so as to implement the AC-coupling setting of the differential signal; wherein, the fixed level V CMThe voltage value is greater than or equal to 1.0V (such as Figure 3 shown). It should be noted that the voltage value of the fixed level V CM can be selected between 1.0V - V DD according to the requirements of the common - mode level for specific applications (including the endpoint values), where V DD is the system power supply voltage.

[0048] In another embodiment, two differential - signal input interfaces IN - P and IN - N are connected to a DC - coupled differential signal, and two common - mode level input interfaces CM - P and CM - N are connected to different fixed levels, so as to implement the setting of the hysteresis voltage for the differential signal; among them, the fixed level V CM+ connected to the in - phase - end common - mode level input interface CM - P is greater than the fixed level V CM- connected to the anti - phase - end common - mode level input interface CM - N, and the difference between the two (that is, V CM+ -V CM- ) is the set hysteresis voltage (such as Figure 4 shown). It should be noted that the voltage values of the two fixed levels V CM+ and V CM- can be set according to the requirements of the DC operating point for specific applications, and the set hysteresis voltage is a system set value.

[0049] In practical applications, according to different application requirements, the four interfaces IN - P, IN - N, CM - P, and CM - N can be configured and connected as described above, so as to implement the functions of DC - coupling setting, AC - coupling setting, common - mode level setting, and hysteresis - voltage setting of the differential signal.

[0050] Furthermore, the interface module 100 further includes: four electrostatic protection units 101, which are connected to the four interfaces IN - P, IN - N, CM - P, and CM - N, and are used to filter out signal interference. In practical applications, the electrostatic protection unit 101 can adopt any existing circuit that can achieve the electrostatic protection function, and the specific circuit composition of this embodiment is not limited.

[0051] The high - voltage domain module 200 receives the differential input signals INP and INN, and is used to convert the differential input signals INP and INN into high - voltage domain current signals in the high - voltage domain. Among them, the input common - mode voltage V CM of the high - voltage domain module 200 satisfies V CM ≥1.0V, and the input differential - mode voltage V ID satisfies V ID ≥100mV. In practical applications, if the design margin of the circuit is not considered much, the input differential - mode voltage V ID can be made to satisfy V ID≥150 mV; for a specific application system, the input common-mode voltage V CM should satisfy 1.0 V ≤ V CM ≤ V DD .

[0052] Specifically, the high-voltage domain module 200 is implemented by a fully differential amplifier to achieve the conversion of high-speed differential signals around 1 GHz; further, the high-voltage domain module 200 is implemented by a folded cascode amplifier to achieve the conversion of high-speed differential signals up to 1.5 GHz by improving the frequency response characteristics of the circuit.

[0053] As an example, the high-voltage domain module 200 includes: a current source I1, a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, and a fourth PMOS transistor PM4; the gate terminals of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected to the differential input signals INP and INN, the source terminals of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected and grounded through the current source I1, the drain terminal of the first NMOS transistor NM1 is connected to the drain terminal of the first PMOS transistor PM1, and the drain terminal of the second NMOS transistor NM2 is connected to the drain terminal of the second PMOS transistor PM2; the source terminals of the first PMOS transistor PM1 and the second PMOS transistor PM2 are connected to the high-voltage domain power supply voltage VDDH, the gate terminals of the first PMOS transistor PM1 and the second PMOS transistor PM2 are connected to the bias voltage Vbias, the drain terminal of the first PMOS transistor PM1 is connected to the source terminal of the third PMOS transistor PM3, and the drain terminal of the second PMOS transistor PM2 is connected to the source terminal of the fourth PMOS transistor PM4; the gate terminals of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are connected to the bias voltage Vbias, and the drain terminals of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are used as the output terminals of the high-voltage domain module 200; wherein, the threshold voltages of the first NMOS transistor NM1 and the second NMOS transistor NM2 are less than 0.5 V, and the overdrive voltage of the current source I1 is less than 0.2 V (as Figure 5 shown). Optionally, to optimize the circuit performance, the threshold voltages of the first NMOS transistor NM1 and the second NMOS transistor NM2 are less than 0.25 V, and the overdrive voltage of the current source I1 is less than 0.15 V.

[0054] In this embodiment, the current source I1 is implemented by using the on-chip bandgap reference, and the first NMOS transistor NM1, the second NMOS transistor NM2, the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, and the fourth PMOS transistor PM4 are all implemented by using high-voltage devices. By using NMOS transistors with low threshold voltages and a current source with a low overdrive voltage to design the input common-mode voltage V CM and the input differential-mode voltage V ID , so that the input common-mode voltage V CM satisfies V CM ≥1.0 V, and the input differential-mode voltage V ID satisfies V ID ≥100 mV, thereby realizing the conversion and processing of high-speed differential signals with different electrical specifications, that is, realizing the compatibility of high-speed differential signals of three electrical specifications: CML, LVDS, and LVECL. In practical applications, through size design, the first NMOS transistor NM1 and the second NMOS transistor NM2 can have low threshold voltages that meet the requirements, and the current source I1 can have an overdrive voltage that meets the requirements.

[0055] The low-voltage domain module 300 receives the high-voltage domain current signal, and is used to convert the high-voltage domain current signal into a low-voltage domain voltage signal in the low-voltage domain, and output the low-voltage domain voltage signal after differential-to-single-ended conversion.

[0056] Specifically, the low-voltage domain module 300 uses a current mirror to convert the high-voltage domain current signal into the low-voltage domain voltage signal in the low-voltage domain. In this embodiment, by using current to transmit signals between the high-voltage domain and the low-voltage domain, the problem of signal duty cycle change caused by level conversion is eliminated, and the signal accuracy is improved.

[0057] As an example, the low-voltage domain module 300 includes: a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a fifth PMOS transistor PM5, and a sixth PMOS transistor PM6; the drain terminals of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are correspondingly connected to the high-voltage domain current signal, the source terminals of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are grounded, the gate terminal of the third NMOS transistor NM3 is connected to its drain terminal and the gate terminal of the fifth NMOS transistor NM5, and the gate terminal of the fourth NMOS transistor NM4 is connected to its drain terminal and the gate terminal of the sixth NMOS transistor NM6; the source terminals of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are grounded, the drain terminal of the fifth NMOS transistor NM5 is connected to the drain terminal of the fifth PMOS transistor PM5 and serves as the output terminal of the low-voltage domain module 300, and the drain terminal of the sixth NMOS transistor NM6 is connected to the drain terminal of the sixth PMOS transistor PM6; the source terminals of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are connected to the low-voltage domain power supply voltage VDDL, the gate terminal of the fifth PMOS transistor PM5 is connected to the gate terminal of the sixth PMOS transistor PM6, and the gate terminal of the sixth PMOS transistor PM6 is connected to its drain terminal (as Figure 5 shown).

[0058] In this embodiment, the third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the fifth PMOS transistor PM5, and the sixth PMOS transistor PM6 are all implemented by low-voltage devices. The third NMOS transistor NM3 and the fifth NMOS transistor NM5 form a current mirror for mirroring a high-voltage domain current signal generated by the high-voltage domain module 200 to the drain terminal of the fifth NMOS transistor NM5 and generating a corresponding low-voltage domain voltage signal; the fourth NMOS transistor NM4 and the sixth NMOS transistor NM6 form a current mirror for mirroring another high-voltage domain current signal generated by the high-voltage domain module 200 to the drain terminal of the sixth NMOS transistor NM6 and generating a corresponding low-voltage domain voltage signal; the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 perform differential-to-single-ended conversion and then output. In practical applications, the high-voltage domain power supply voltage VDDH can be 3.3V, and the low-voltage domain power supply voltage VDDL can be 1.2V. Of course, the specific values can also be set according to actual requirements.

[0059] The output driving module 400 receives a single-ended signal and is used to drive and enhance the single-ended signal and then output it to the core circuit of the chip for subsequent processing.

[0060] Specifically, the output driving module 400 is implemented by an inverter chain with a gradually increasing aspect ratio, where the number of stages of the inverter chain is greater than or equal to 2. Further, the output driving module 400 is implemented by a 3-stage inverter chain, where the aspect ratios of the 3-stage inverter chain are increased gradually in an arithmetic progression manner. In practical applications, the difference in aspect ratios between adjacent two-stage inverters can be determined according to the swing of the output signal in specific applications, and the specific value thereof is not limited in this embodiment.

[0061] In summary, for a high-speed I / O interface input circuit of the present invention, through the design of an interface module, a high-voltage domain module, a low-voltage domain module, and an output driving module, a high-speed I / O interface input circuit with a maximum speed of up to 1.5 GHz is proposed, which can be compatible with three electrical specifications of CML, LVDS, and LVECL, improving the applicability of chip products using the high-speed I / O interface input circuit. Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0062] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A high-speed I / O interface input circuit, characterized in that, The high-speed I / O interface input circuit includes: an interface module, a high-voltage domain module, a low-voltage domain module, and an output driver module. The interface module includes two differential signal input interfaces and two common-mode level input interfaces. The two common-mode level input interfaces are correspondingly connected to the two differential signal input interfaces through two input resistors, and are used to configure and connect the four interfaces to process the differential signal and generate a differential input signal. The high-voltage domain module receives the differential input signal and is used to convert the differential input signal in the high-voltage domain to obtain a high-voltage domain current signal. Among them, the input common-mode voltage V CM satisfies V CM ≥1.0V, and the input differential-mode voltage V ID satisfies V ID ≥100mV; The low-voltage domain module receives the high-voltage domain current signal, and is used to convert the high-voltage domain current signal in the low-voltage domain to obtain a low-voltage domain voltage signal, and output the low-voltage domain voltage signal after differential-to-single-ended conversion; wherein, the low-voltage domain module uses a current mirror to convert the high-voltage domain current signal in the low-voltage domain to obtain the low-voltage domain voltage signal. The output driver module receives a single-ended signal and is used to drive and enhance the single-ended signal and then output it.

2. The high-speed I / O interface input circuit according to claim 1, wherein The interface module further includes: four electrostatic protection units, which are connected to the four interfaces and are used to filter out signal interference.

3. The high-speed I / O interface input circuit according to claim 1 or 2, wherein Two differential signal input interfaces are connected to a DC-coupled differential signal, and two common-mode level input interfaces are short-circuited and left floating to implement DC-coupling setting for the differential signal.

4. The high-speed I / O interface input circuit according to claim 1 or 2, characterized in that, Two differential signal input interfaces are correspondingly connected to an AC-coupled differential signal through two capacitors, and two common-mode level input interfaces are short-circuited and connected to a fixed level to implement AC-coupling setting for the differential signal; wherein, the voltage value of the fixed level is greater than or equal to 1.0V.

5. The high-speed I / O interface input circuit according to claim 1 or 2, characterized in that, Two differential signal input interfaces are connected to a DC-coupled differential signal, and two common-mode level input interfaces are connected to different fixed levels to implement hysteresis voltage setting for the differential signal; wherein, the fixed level connected to the in-phase common-mode level input interface is greater than the fixed level connected to the anti-phase common-mode level input interface, and the difference between the two is the set hysteresis voltage.

6. The high-speed I / O interface input circuit according to claim 1 or 2, wherein The high-voltage domain module is implemented by a fully differential amplifier.

7. The high-speed I / O interface input circuit according to claim 6, characterized in that, The high-voltage domain module is implemented by a folded cascode amplifier.

8. The high-speed I / O interface input circuit according to claim 7, wherein The high-voltage domain module includes: a current source, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The gate terminals of the first NMOS transistor and the second NMOS transistor are connected to the differential input signal. The source terminals of the first NMOS transistor and the second NMOS transistor are connected together and grounded through the current source. The drain terminal of the first NMOS transistor is connected to the drain terminal of the first PMOS transistor, and the drain terminal of the second NMOS transistor is connected to the drain terminal of the second PMOS transistor. The source terminals of the first PMOS transistor and the second PMOS transistor are connected to the high-voltage domain power supply voltage. The gate terminals of the first PMOS transistor and the second PMOS transistor are connected to a bias voltage. The drain terminal of the first PMOS transistor is connected to the source terminal of the third PMOS transistor, and the drain terminal of the second PMOS transistor is connected to the source terminal of the fourth PMOS transistor. The gate terminals of the third PMOS transistor and the fourth PMOS transistor are connected to the bias voltage, and the drain terminals of the third PMOS transistor and the fourth PMOS transistor are used as the output terminals of the high-voltage domain module. Among them, the threshold voltages of the first NMOS transistor and the second NMOS transistor are less than 0.5V, and the overdrive voltage of the current source is less than 0.2V.

9. The high-speed I / O interface input circuit according to claim 1, wherein The low-voltage domain module includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor. The drain terminals of the third NMOS transistor and the fourth NMOS transistor are correspondingly connected to the high-voltage domain current signal. The source terminals of the third NMOS transistor and the fourth NMOS transistor are grounded. The gate terminal of the third NMOS transistor is connected to its drain terminal and the gate terminal of the fifth NMOS transistor. The gate terminal of the fourth NMOS transistor is connected to its drain terminal and the gate terminal of the sixth NMOS transistor. The source terminals of the fifth NMOS transistor and the sixth NMOS transistor are grounded. The drain terminal of the fifth NMOS transistor is connected to the drain terminal of the fifth PMOS transistor and serves as the output terminal of the low-voltage domain module. The drain terminal of the sixth NMOS transistor is connected to the drain terminal of the sixth PMOS transistor. The source terminals of the fifth PMOS transistor and the sixth PMOS transistor are connected to the low-voltage domain power supply voltage. The gate terminal of the fifth PMOS transistor is connected to the gate terminal of the sixth PMOS transistor, and the gate terminal of the sixth PMOS transistor is connected to its drain terminal.

10. The high-speed I / O interface input circuit according to claim 1 or 2, characterized in that, The output driving module is implemented by an inverter chain with gradually increasing aspect ratios.

11. The high-speed I / O interface input circuit according to claim 10, wherein The output driving module is implemented by a 3-stage inverter chain. Among them, the aspect ratios of the 3-stage inverter chain are gradually increased in an arithmetic progression manner.

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