Analog-to-digital converter

Abstract

An analog-to-digital converter (ADC) is disclosed, comprising a charge-sharing module, a common-mode voltage compensation module, and a comparator. The charge-sharing module samples the signal to be converted and subtracts it from a target reference voltage to provide a positive-phase output voltage and a negative-phase output voltage. The comparator compares the positive-phase and negative-phase output voltages to obtain a logic signal corresponding to the comparison result between the target reference voltage and the signal to be converted. The common-mode voltage compensation module compensates for the distributed charge of the charge-sharing module to pull the output common-mode voltage of the charge-sharing module toward a desired value. The common-mode voltage compensation module in this ADC pulls the output common-mode voltage of the charge-sharing module toward a desired value, reducing the deviation between the actual input common-mode voltage of the comparator and the standard value, improving the reliability of the comparator's comparison result, and thus improving the conversion accuracy and reliability of the ADC.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically, to analog-to-digital converters. Background Technology

[0002] With the rapid development of technologies such as integrated circuits, computer technology, medical technology, and wireless sensor networks, people are constantly pursuing portable and intelligent electronic products, such as smart home and health-related home electronic devices. Among these, the analog-to-digital converter (ADC) plays a crucial role as the link between the analog and digital signal worlds. Sensors perceive and collect various analog signals from the real world, converting them into processable digital signals using the ADC, thereby controlling devices to make various responses.

[0003] Successive approximation analog-to-digital converters (SAR ADCs) have the advantages of low power consumption and high accuracy, and are therefore widely used in fields such as wireless sensor networks and biomedicine where power consumption and accuracy are required.

[0004] Reference Figure 1 The signal to be converted, Vin, is processed into a positive input voltage Vinp and a negative input voltage Vinn based on the power supply voltage VDD. These are then provided to the first and second rails of the analog-to-digital converter (ADC) system, respectively. The ADC system samples the signal to be converted based on these positive and negative input voltages Vinp and Vinn. The first and second rails are also connected to a first capacitor array and a second capacitor array (the two capacitor arrays, Cdac, are symmetrically structured). By adjusting the access of the reference voltage (including the first reference voltage Vrefp and the second reference voltage Vrefn) through the first and second capacitor arrays, charge is distributed. This allows for the subtraction of the positive and negative input voltages Vrefp and Vrefn with the target reference voltage Vdac, providing a positive output voltage Vop and a negative output voltage Von on the first and second rails, respectively, with Vop - Von = Vin - Vdac. Comparator 120 compares the positive and negative output voltages Vop and Von to directly obtain the comparison result between the signal to be converted, Vin, and the target reference voltage, thus achieving analog-to-digital conversion.

[0005] The input common-mode voltage of comparator 120 is equal to half the sum of the positive output voltage Vop and the negative output voltage Von. The sum of the positive output voltage Vop and the negative output voltage Von is related to the sum of the positive input voltage Vinp and the negative input voltage Vinn. The sum of the positive input voltage Vinp and the negative input voltage Vinn is equal to the power supply voltage VDD. However, the power supply voltage VDD may fluctuate, causing the actual input common-mode voltage of comparator 120 to fluctuate with the power supply voltage VDD. As a result, the reliability of operation is easily affected by power supply interference. Summary of the Invention

[0006] In view of the above problems, the purpose of this invention is to provide an analog-to-digital converter (ADC) that reduces the interference resistance of the ADC, improves the conversion accuracy and reliability of the ADC, and improves the system efficiency.

[0007] According to one aspect of the present invention, an analog-to-digital converter includes:

[0008] The charge distribution and holding module is used to sample the signal to be converted and subtract the signal to be converted from the target reference voltage through charge distribution. It outputs a positive output voltage and a negative output voltage on the first and second electric rails, respectively. The difference between the positive output voltage and the negative output voltage is equal to the difference between the signal to be converted and the target reference voltage.

[0009] A common-mode voltage compensation module, connected to the first and second electric rails, is used to inject common-mode charge to compensate for the distributed charge of the charge distribution and holding module, thereby reducing the difference between the output common-mode voltage of the charge distribution and holding module and the expected value.

[0010] A comparator is used to provide a logic signal based on a comparison of the positive output voltage and the negative output voltage, the logic signal corresponding to the target digital signal for analog-to-digital conversion.

[0011] Optionally, the signal to be converted is processed into a positive input voltage and a negative input voltage according to the power supply voltage. The difference between the positive input voltage and the negative input voltage is equal to the signal to be converted, and the sum of the positive input voltage and the negative input voltage is equal to the power supply voltage. The charge distribution and holding module includes:

[0012] A first capacitor array and a second capacitor array, one end of which are respectively connected to the first and second electrical rails, and the other end is used to connect to a first or a second reference voltage, so as to perform subtraction processing between the signal to be converted and the target reference voltage according to the connected reference voltage.

[0013] One end of the first rail and the second rail respectively receives the input terminals of the positive phase input voltage and the negative phase input voltage, and the other end respectively provides the positive phase output voltage and the negative phase output voltage.

[0014] Optionally, the common-mode voltage compensation module includes:

[0015] A first compensation capacitor and a second compensation capacitor are connected, with their first terminals connected to the first and second electrical rails respectively, and their second terminals receiving a first voltage and a second voltage respectively via a first switch and a second switch, switching between the first voltage and the second voltage.

[0016] When the voltage at the second terminals of the first compensation capacitor and the second compensation capacitor is switched from the first voltage to the second voltage, the difference between the output common-mode voltage of the charge distribution holding module and the expected value decreases.

[0017] The common-mode output voltage of the charge distribution and holding module is equal to half the sum of the positive-phase output voltage and the negative-phase output voltage.

[0018] Optionally, the first switch and the second switch are alternately switched on.

[0019] Optionally, the output common-mode voltage of the charge distribution and holding module satisfies Vcmout=Vcm0+E1, E1=(Vcmref-Vcmin)×Cdac÷(Cdac+Cc)+(V2-V1)×Cc÷(Cdac+Cc),

[0020] Wherein, Vcmout is the output common-mode voltage of the charge distribution and holding module, Vcm0 is the expected value of the output common-mode voltage of the charge distribution and holding module, Vcmref is the reference common-mode voltage of the charge distribution and holding module, Vcmin is the input common-mode voltage of the charge distribution and holding module, Cdac is the capacitance value of the first capacitor array or the second capacitor array, Cc is the capacitance value of the first compensation capacitor and the second compensation capacitor, V1 is the first voltage, V2 is the second voltage, and E1 is the power supply error.

[0021] The input common-mode voltage of the charge distribution and holding module is half of the power supply voltage. The difference between the second voltage and the first voltage is obtained based on the power supply voltage. The capacitance values ​​of the first compensation capacitor and the second compensation capacitor are obtained based on the effective range of the power supply error and the obtained first voltage and second voltage.

[0022] Alternatively, by making the power supply error close to zero, the range of the output common-mode voltage of the charge distribution holding module is made to be within the effective value range of the input common-mode voltage of the comparator.

[0023] Optionally, the second voltage is greater than the first voltage, and the first voltage and the second voltage are obtained based on any one of the power supply voltage or its voltage division, the reference voltage or its voltage division.

[0024] Optionally, the capacitance values ​​of the first compensation capacitor and the second compensation capacitor are determined based on the first voltage and the second voltage.

[0025] Optionally, the output common-mode voltage of the analog-to-digital converter also satisfies Vcmout=Vcm0+E1+E2, where E2 is a fixed error, and the capacitance values ​​of the first compensation capacitor and the second compensation capacitor are also adjusted according to the fixed error.

[0026] Optionally, the first compensation capacitor and the second compensation capacitor are obtained by connecting a unit capacitor in series and parallel, wherein the capacitance value of the unit capacitor is consistent with the minimum capacitance value in the first capacitor array and the second capacitor array.

[0027] Optionally, the capacitance values ​​of the first compensation capacitor and the second compensation capacitor are consistent with half the capacitance value of the first capacitor array or the second capacitor array.

[0028] Optionally, it also includes:

[0029] An active amplifier unit is used to provide the second voltage and the first voltage, wherein the first voltage and the second voltage satisfy V2-V1=VDD*Cdac / (2*Cc).

[0030] Wherein, VDD is the power supply voltage, and the first voltage and the second voltage are obtained based on the power supply voltage and the capacitance value of the first compensation capacitor.

[0031] Optionally, it also includes:

[0032] The successive approximation control logic module is used to control the switching of the access states of the first reference voltage and the second reference voltage of the first capacitor array and the second capacitor array of the charge distribution holding module according to the logic signal provided by the comparator, and to adjust the target reference voltage.

[0033] Optionally, compensation for the distributed charge of the charge distribution and holding module is performed by comparing the signal to be converted with at least a portion of the target reference voltages among a plurality of target reference voltages.

[0034] The analog-to-digital converter provided by this invention includes a charge distribution and holding module, a common-mode voltage compensation module, and a comparator. The charge distribution and holding module samples the signal to be converted and subtracts it from a target reference voltage to provide a positive-phase output voltage and a negative-phase output voltage. The comparator compares the positive-phase output voltage and the negative-phase output voltage to obtain a logic signal, which corresponds to the comparison result between the signal to be converted and the target reference voltage. The common-mode voltage compensation module compensates for the distributed charge of the charge distribution and holding module to pull the output common-mode voltage of the charge distribution and holding module toward the desired value, thereby reducing the deviation between the actual input common-mode voltage of the comparator and the standard value, improving the reliability of the comparator's comparison result, and improving the conversion accuracy and reliability of the analog-to-digital converter. Attached Figure Description

[0035] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0036] Figure 1 A schematic diagram of the structure of a successive approximation analog-to-digital converter according to the prior art is shown;

[0037] Figure 2 A schematic diagram of an analog-to-digital converter according to an embodiment of the present invention is shown;

[0038] Figure 3 A schematic diagram of compensation control for an analog-to-digital converter according to an embodiment of the present invention is shown. Detailed Implementation

[0039] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0040] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0041] Figure 1 A schematic diagram of the structure of an analog-to-digital converter according to the prior art is shown.

[0042] Reference Figure 1The analog-to-digital converter 100 is a charge redistribution type analog-to-digital converter, including a charge distribution and holding module 110, a comparator 120, and a successive approximation control logic module 130. The charge distribution and holding module 110 receives a positive input voltage Vinp and a negative input voltage Vinn to receive charge, and receives a first reference voltage Vrefp and a second reference voltage Vrefn to control the distribution. It controls the output voltages of the positive output voltage Vop and the negative output voltage Von. The comparator 120 compares the positive output voltage Vop and the negative output voltage Von provided by the charge distribution and holding module 110 and provides a logic signal Dout.

[0043] Vop-Von = Vin-Vdac, where Vdac is the target reference voltage. The target reference voltage is adjusted by the charge distribution holding module 110 to confirm the voltage of the signal Vin to be processed by comparing it with different target reference voltages.

[0044] The first reference voltage Vrefp and the second reference voltage Vrefn correspond to the reference voltage. The positive input voltage Vinp and the negative input voltage Vinn are obtained by processing the signal to be converted Vin and the power supply voltage VDD, where Vinp-Vinn=Vin and Vinp+Vinn=VDD.

[0045] In this embodiment, the charge distribution and holding module 110 includes a first electric rail and a second electric rail. The first electric rail is connected to a positive input voltage Vinp through a switch S1 and outputs a positive output voltage Vop. The second electric rail is connected to a negative input voltage Vinn through a switch S2 and outputs a negative output voltage Von.

[0046] The two capacitor arrays Cdac are symmetrically structured, with one end connected to the first and second electrical rails respectively. The other end is controlled by the switch array 111 to allow each capacitor to receive the first reference voltage Vrefp or the second reference voltage Vrefn. In this embodiment, the capacitor array Cdac includes 7 capacitors (corresponding to B0 to B6). The capacitance increases sequentially from B0 to B6 in powers of 2. Taking the capacitance of the capacitor corresponding to B0 as the unit capacitance C, the capacitances are C, 2C, 4C, 8C, 16C, and 32C, corresponding to the conversion of eight-bit binary numbers.

[0047] After obtaining a logic signal Dout, the successive approximation control logic 130 adjusts the switch array 111 according to the value of the logic signal Dout to adjust the target reference voltage Vdac, making it closer to the signal Vin to be processed. The comparison is repeated several times to confirm the value of the signal Vin to be processed and output the converted digital value Dn.

[0048] In this circuit, the output common-mode voltage Vcmout of the charge distribution and holding module 110 satisfies Vcmout=(Vop+Von) / 2, the reference common-mode voltage Vcmref satisfies Vcmref=(Vrefp+Vrefn) / 2, and the input common-mode voltage Vcmin satisfies Vcmin=(Vinp+Vinn) / 2. Furthermore, Vcmout=Vcm0+(Vcmref-Vcmin), Vinp+Vinn=VDD, where VDD is the power supply voltage. Since the power supply voltage generally has noise interference, the actual output common-mode voltage Vcmout deviates from the expected value Vcm0. If this deviation exceeds the dynamic compatibility range of the input common-mode voltage of the subsequent comparator 120 (when the input common-mode voltage of the comparator 120 is within the dynamic compatibility range, the accuracy of the comparison result can be guaranteed), it will reduce the working reliability of the comparator 120, reduce the accuracy of the comparison between the positive phase output voltage Vop and the negative phase output voltage Von, reduce the reliability of the provided logic signal Dout, and thus affect the conversion accuracy of the analog-to-digital converter 100 and the system performance.

[0049] Figure 2 A schematic diagram of an analog-to-digital converter according to an embodiment of the present invention is shown. The basic structure of the analog-to-digital converter 200 of this embodiment is similar to... Figure 1 The basic structure of the prior art analog-to-digital converter 100 shown is the same, and its basic specific structure will not be described in detail here.

[0050] Further reference Figure 2 In this embodiment of the invention, the analog-to-digital converter 200 is provided with a common-mode voltage compensation module on the output rail of the charge distribution and holding module 110 to compensate for the distributed charge of the charge distribution and holding module 110, thereby reducing the deviation between the actual output common-mode voltage and the expected value and improving the system accuracy.

[0051] In this embodiment, the common-mode voltage compensation module includes two compensation capacitors Cc. One end of each compensation capacitor Cc is connected to the first and second electric rails, respectively, and the other end of each capacitor receives the first voltage V1 and the second voltage V2 through the first switch P1 and the second switch P2, respectively.

[0052] In this configuration, the first switch P1 and the second switch P2 are complementary in conduction. Specifically, this can be achieved by using switches with the same conduction conditions and controlling them with two control signals that have opposite control timings, or by limiting switches with opposite conduction conditions and controlling them with the same control signal.

[0053] It is understood that the common-mode voltage compensation module of this application can also be designed in comparator 120 and coupled to the input terminal of comparator 120, which can improve the dynamic compatibility range of the input common-mode voltage corresponding to the effective operation of comparator 120.

[0054] Figure 3 A schematic diagram of compensation control for an analog-to-digital converter according to an embodiment of the present invention is shown. The dashed line corresponds to the compensated output common-mode voltage.

[0055] Further reference Figure 3 In this embodiment of the invention, the analog-to-digital converter 200 controls the first switch P1 and the second switch P2 to conduct in a time-division multiplexing manner (or conduct alternately, achieving overall switching between the first voltage V1 and the second voltage V2) through the compensation control clock CLKp. This controls the receiving voltage at the other end of the two compensation capacitors Cc to switch between the first voltage V1 and the second voltage V2. When the second switch P2 is on, the receiving voltage at the other end of the two compensation capacitors Cc switches from the first voltage V1 to the second voltage V2. Through charge compensation, the output common-mode voltage Vcmout is adjusted to the desired value Vcm0 and maintained at the desired value Vcm0. That is, when the output common-mode voltage Vcmout deviates from the desired value Vcm0, by switching the receiving voltage at the other end of the two compensation capacitors Cc, the charge of the capacitor arrays corresponding to the first and second electric rails is compensated, and the output common-mode voltage Vcmout can be pulled back to the desired value.

[0056] In this system, the second voltage V2 is greater than the first voltage V1. The receiving voltage at the other end of the two compensation capacitors Cc switches from the first voltage V1 to the second voltage V2 to compensate for the output common-mode voltage Vcmout. The timing of this switching compensation can be varied, depending on factors such as control convenience or the required system accuracy. For example, it can be performed throughout the entire process after the analog-to-digital converter samples the signal Vin to be converted, or during the approximation comparison of partial bits of the binary number (when the analog signal input value Vin is close to the target reference voltage Vdac value required for the comparison of the corresponding bit), or when the system's own error correction capability is insufficient, ensuring the accuracy of the analog-to-digital conversion. Specifically, the compensation for the distributed charge of the charge distribution and holding module 110 is performed during the comparison of the signal to be converted with at least some of the target reference voltages among multiple target reference voltages. This compensation targets the conversion operation of the digital values ​​of partial bits in the analog-to-digital conversion, improving the accuracy of the analog-to-digital conversion of error-prone bits.

[0057] For the analog-to-digital converter 200 of this embodiment, its output common-mode voltage satisfies: Vcmout=Vcm0+E1, E1=(Vcmref-Vcmin)×Cdac÷(Cdac+Cc)+(V2-V1)×Cc÷(Cdac+Cc), where Vcmout is the output common-mode voltage, Vcm0 is the expected value of the output common-mode voltage, Vcmref is the reference common-mode voltage, Vcmin is the input common-mode voltage, Cdac is the capacitance value of the two capacitor arrays Cdac (the structure is symmetrical and the capacitance values ​​of the two capacitor arrays are equal), Cc is the capacitance value of the two compensation capacitors Cc, V1 is the first voltage, V2 is the second voltage, and E1 is the power supply error.

[0058] The analog-to-digital converter 200 of this embodiment of the invention, by designing the selection of the first voltage V1, the second voltage V2 and the compensation capacitor Cc, regulates the power supply error E1 to be zero or within a certain range, so that the output common-mode voltage Vcmout of the charge distribution holding module 110 is consistent with the expected value Vcm0 within the error allowable range, and the actual output value of the output common-mode voltage Vcmout fluctuating with the power supply is within the effective value range of the input common-mode voltage of the corresponding comparator 120, thus ensuring the accuracy of the logic signal Dout provided by the comparator 120 after processing.

[0059] In an optional embodiment, Cc = Cdac / 2, V2 = VDD, V1 = GND, which makes E1 = Vcmref × 2 / 3. The first reference voltage Vrefp (e.g., 4.5V) and the second reference voltage Vrefn (e.g., ground GND) are stable reference values, corresponding to a stable reference common-mode voltage Vcmref, thus making the final output common-mode voltage Vcmout a stable value. This easily eliminates the influence of the power supply voltage VDD on the output common-mode voltage Vcmout. The reference voltage corresponds to the range of the analog-to-digital converter; different selections correspond to different output common-mode voltages Vcmout, and the specifications of comparator 120 are also adaptively selected.

[0060] In an optional embodiment, an active amplification unit is also provided to provide a first voltage V1 and a second voltage V2, such that V2-V1=VDD*Cdac / (2*Cc). In a specific embodiment, V1=gnd, V2=(VDD-4.096V)*K, Cc=2C. The gain amplification requirement of K (e.g., 33.5) is achieved through an operational amplifier circuit, a programmable gain amplifier (PGA), or a variable gain amplifier (VGA) (the specific structure is not detailed here). This can also eliminate the power supply voltage VDD term in the power supply error E1. At the same time, Cc=2C, with a small capacitance value, corresponds to a small area for the first compensation capacitor and the second compensation capacitor, which can reduce the area occupied by the common-mode voltage compensation module. The smaller Cc is, the greater the gain amplification requirement. The actual selection depends on the specific situation and is not detailed here.

[0061] In one specific embodiment, Vcmref = 2.25V, Vcmin = 2.5V, Cdac = 134C, V2 = 5V = VDD, V1 = 0V. Let Vcmout = Vcm0, and we can derive Cc ≈ 6.7C, which can make the power supply error E1 zero. Here, C is the unit capacitance. Based on the estimated value of the fixed error E2 caused by other interference factors, corresponding to Vcmref = Vcm0 + E1 + E2, we can further derive and adjust C to obtain Cc = 6.85C, which can effectively compensate the output common-mode voltage of the charge distribution and holding module 110 of the eight-bit binary analog-to-digital converter 200 in this embodiment to the expected value.

[0062] Specifically, based on the dynamic comparability range of the input common-mode voltage of the comparator 120 at the back end, the compensation target of E1 (or E1+E2) is a range value. For example, if the comparator 120 can guarantee output accuracy within a dynamic comparability range of ±100mV for its input common-mode voltage (the overall range is 0.9V±100mV, where 0.9V is the standard value of the input common-mode voltage of the comparator 120, corresponding to Vcm0=0.9V), then E1 can be controlled to adjust V1 according to the possible fluctuations of the reference voltage and the power supply voltage. The values ​​of V2 and Cc should be such that E1 is within ±100mV (i.e., the power supply error is within the dynamic compatibility range of the input common-mode voltage of comparator 120). Taking the above specific embodiment as an example, the capacitance value of Cc can also be designed as 7C or 5C. The final compensated output common-mode voltage Vcmout is greater than or less than the expected value Vcm0 within the ±100mV error range, which can ensure the comparison accuracy of comparator 120 and the reliability of analog-to-digital conversion of analog-to-digital converter 200.

[0063] The compensation capacitor Cc is obtained by connecting the unit capacitor in series and parallel, and the capacitance value of the compensation capacitor Cc is designed to be a multiple of that of the unit capacitor.

[0064] The analog-to-digital converter provided by this invention includes a charge distribution and holding module, a common-mode voltage compensation module, and a comparator. The first and second rails of the charge distribution and holding module are respectively connected to a first capacitor array and a second capacitor array. The signal to be converted is sampled onto one plate of the first and second capacitor arrays, and then connected to a reference voltage through the other plate of the first and second capacitor arrays. Charge is distributed, and subtraction is performed to provide a positive-phase output voltage and a negative-phase output voltage. The comparator provides a logic signal based on the comparison of the positive-phase output voltage and the negative-phase output voltage. This logic signal corresponds to the magnitude of the signal to be converted and the target reference voltage, thereby realizing analog-to-digital conversion. The common-mode voltage compensation module compensates for the distributed charge of the charge distribution and holding module, which can reduce the difference between the output common-mode voltage of the charge distribution and holding module and the expected value, and correspondingly reduce the difference between the actual input common-mode voltage of the comparator and the standard value, thereby improving the reliability of the comparator's comparison result.

[0065] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An analog-to-digital converter, comprising: a charge sharing and holding module configured to sample a signal to be converted and to perform a subtraction of the signal to be converted from a target reference voltage by charge sharing, and to output a positive-phase output voltage and a negative-phase output voltage on a first rail and a second rail, respectively, the difference between the positive-phase output voltage and the negative-phase output voltage being equal to the difference between the signal to be converted and the target reference voltage; a common-mode voltage compensation module connected to the first rail and the second rail, and configured to inject a common-mode charge to compensate for the shared charge of the charge sharing and holding module, and to reduce the difference between the output common-mode voltage of the charge sharing and holding module and a desired value; a comparator configured to provide a logic signal based on a comparison of the positive-phase output voltage and the negative-phase output voltage, the logic signal corresponding to a target digital signal of an analog-to-digital conversion, wherein the common-mode voltage compensation module comprises: a first compensation capacitor and a second compensation capacitor, the first ends of the first compensation capacitor and the second compensation capacitor being connected to the first rail and the second rail, respectively, the second ends of the first compensation capacitor and the second compensation capacitor being configured to receive a first voltage through a first switch and a second voltage through a second switch, respectively, wherein the analog-to-digital converter is configured to control the first switch and the second switch to be turned on at different times by a compensation control clock, such that the second ends of the first compensation capacitor and the second compensation capacitor are switched between the first voltage and the second voltage, wherein the difference between the output common-mode voltage of the charge sharing and holding module and the desired value is reduced when the second ends of the first compensation capacitor and the second compensation capacitor are switched from the first voltage to the second voltage, wherein the output common-mode voltage of the charge sharing and holding module is equal to half of the sum of the positive-phase output voltage and the negative-phase output voltage.

2. The analog-to-digital converter of claim 1, wherein, wherein the signal to be converted is processed into a positive-phase input voltage and a negative-phase input voltage based on a power supply voltage, the difference between the positive-phase input voltage and the negative-phase input voltage being equal to the signal to be converted, and the sum of the positive-phase input voltage and the negative-phase input voltage being equal to the power supply voltage, and wherein the charge sharing and holding module comprises: a first capacitor array and a second capacitor array, one end of the first capacitor array and the second capacitor array being connected to the first rail and the second rail, respectively, and the other end being configured to access a first reference voltage or a second reference voltage to perform the subtraction of the signal to be converted from a target reference voltage based on the accessed reference voltage, wherein one end of the first rail and the second rail is configured to receive an input end of the positive-phase input voltage and the negative-phase input voltage, respectively, and the other end is configured to provide the positive-phase output voltage and the negative-phase output voltage, respectively.

3. The analog-to-digital converter of claim 2, wherein, the first switch and the second switch are configured to be turned on at different times.

4. The analog-to-digital converter of claim 2, wherein The output common-mode voltage of the charge distribution holding module satisfies Vcmout=Vcm0+E1, E1=(Vcmref-Vcmin)×Cdac÷(Cdac+Cc)+(V2-V1)×Cc÷(Cdac+Cc), Wherein, Vcmout is the output common-mode voltage of the charge distribution holding module, Vcm0 is the expected value of the output common-mode voltage of the charge distribution holding module, Vcmref is the reference common-mode voltage of the charge distribution holding module, Vcmin is the input common-mode voltage of the charge distribution holding module, Cdac is the capacitance value of the first capacitor array or the second capacitor array, Cc is the capacitance value of the first compensation capacitor and the second compensation capacitor, V1 is the first voltage, V2 is the second voltage, E1 is the power error, The input common-mode voltage of the charge distribution holding module is half of the power voltage, the difference between the second voltage and the first voltage is obtained according to the power voltage, and the capacitance values of the first compensation capacitor and the second compensation capacitor are obtained according to the effective range of the power error, the obtained first voltage and the second voltage.

5. The analog-to-digital converter of claim 4, wherein, By making the power error approach zero, the range of the output common-mode voltage of the charge distribution holding module is within the effective value range of the input common-mode voltage of the comparator.

6. The analog-to-digital converter of claim 5, wherein, The second voltage is greater than the first voltage, and the first voltage and the second voltage are obtained according to any one of the power voltage or a divided voltage thereof, the reference voltage or a divided voltage thereof.

7. The analog-to-digital converter of claim 6, wherein, The capacitance values of the first compensation capacitor and the second compensation capacitor are determined according to the first voltage and the second voltage.

8. The analog-to-digital converter of claim 7, wherein, The output common-mode voltage of the analog-to-digital converter also satisfies Vcmout=Vcm0+E1+E2, wherein E2 is a fixed error, and the capacitance values of the first compensation capacitor and the second compensation capacitor are also adjusted according to the fixed error.

9. The analog-to-digital converter of claim 2, wherein, The first compensation capacitor and the second compensation capacitor are obtained by series and parallel connection of unit capacitors, and the capacitance value of the unit capacitor is consistent with the minimum capacitance value in the first capacitor array and the second capacitor array.

10. The analog-to-digital converter of claim 4, wherein, The capacitance values of the first compensation capacitor and the second compensation capacitor are consistent with half of the capacitance value of the first capacitor array or the second capacitor array.

11. The analog-to-digital converter of claim 4, wherein, Further comprising: An active amplification unit for providing the second voltage and the first voltage, the first voltage and the second voltage satisfying V2-V1 = VDD * Cdac / (2*Cc), Wherein, VDD is the power voltage, and the first voltage and the second voltage are obtained according to the power voltage and the capacitance value of the first compensation capacitor.

12. The analog-to-digital converter of claim 2, wherein, Also included are: successive approximation control logic for controlling switching of access states of first and second reference voltages of first and second capacitor arrays of the charge distribution hold module based on logic signals provided by the comparator, to adjust the target reference voltage.

13. The analog-to-digital converter of claim 12, wherein, compensation for distributed charge of the charge distribution hold module is made in comparison of the signal to be converted to at least some of a plurality of target reference voltages.

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