image sensor

Abstract

An image sensor includes a pixel array including a plurality of pixels connected to row lines extending in a first direction and column lines extending in a second direction intersecting the first direction, a ramp voltage generator configured to output a ramp voltage, a plurality of comparators each including a first input terminal to which the ramp voltage is input and a second input terminal connected to one of the column lines, and a replica circuit having a structure identical to that of a portion of the comparators. Each of the comparators includes a plurality of transistors, a first auto-zero transistor connected to the first input terminal, a second auto-zero transistor connected to the second input terminal, and a wiring connected to the plurality of transistors, the first auto-zero transistor, and the second auto-zero transistor.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0113790, filed on September 7, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to an image sensor. Background Technology

[0004] An image sensor is a semiconductor-based sensor that generates electrical signals in response to external light, and may include a pixel array with multiple pixels and logic circuitry for driving the pixel array and generating an image. The logic circuitry may include multiple comparators for receiving the electrical signals and converting them into digital signals. However, there may be problems where the comparators included in the image sensor cannot be fully utilized due to the processing results and temperature distribution of the semiconductor chip integrated with the image sensor. Therefore, it may be necessary to improve the input range of the comparators. Summary of the Invention

[0005] An image sensor is provided that has an improved input range by transferring information acquired using a replication circuit to a ramp voltage generator.

[0006] According to an example embodiment, an image sensor includes: a pixel array comprising a plurality of pixels connected to row lines extending in a first direction and column lines extending in a second direction intersecting the first direction; a ramp voltage generator configured to output a ramp voltage; a plurality of comparators, each of the plurality of comparators including a first input terminal to which the ramp voltage is input and a second input terminal connected to one of the column lines; and a replication circuit having a structure identical to a portion of the comparators. Each of the comparators includes: a plurality of transistors; a first auto-zero transistor connected to the first input terminal; a second auto-zero transistor connected to a second input terminal; and wiring connected to the plurality of transistors, the first auto-zero transistor, and the second auto-zero transistor. The gate terminal of the first auto-zero transistor is connected to a first wiring within the wiring. The gate terminal of the second auto-zero transistor is connected to a second wiring different from the first wiring within the wiring.

[0007] According to an example embodiment, an image sensor includes a pixel array including a plurality of pixels, a plurality of comparators each of which includes a first input terminal, a second input terminal, a first auto-zeroing switch connected to the first input terminal, and a second auto-zeroing switch connected to the second input terminal, a replica circuit including the same devices as a portion of devices included in each of the plurality of comparators and configured to output a sense signal corresponding to an auto-zeroing voltage of each of the plurality of comparators and a common node voltage, and a ramp voltage generator configured to compensate for a ramp voltage based on the output sense signal and output the compensated ramp voltage to the first input terminal of each of the plurality of comparators. The sense signal corresponds to a threshold voltage of an input transistor connected to the first input terminal of each of the plurality of comparators. Each of the plurality of comparators is configured to generate an output signal by comparing a pixel voltage output from the pixel array and a reset voltage with the output ramp voltage.

[0008] According to an example embodiment, an image sensor includes a pixel array including a plurality of pixels, a ramp voltage generator configured to output a ramp voltage, a plurality of comparators configured to generate an output signal by comparing a reset voltage and a pixel voltage output by the pixel array with the output ramp voltage, and a sensing circuit configured to sense a threshold voltage of an input transistor included in the plurality of comparators and output a control signal for compensating for the ramp voltage to the ramp voltage generator. The ramp voltage is compensated for based on the output control signal. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other aspects, features, and advantages of embodiments of the disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating an image sensor according to an example embodiment;

[0011] Figure 2 is a block diagram illustrating a pixel array and a readout circuit in an image sensor according to an example embodiment;

[0012] Figure 3 and Figure 4 is a circuit diagram illustrating a pixel included in a pixel array in an image sensor according to an example embodiment;

[0013] Figure 5 is a graph illustrating a correlated double sampling operation of an image sensor according to an example embodiment;

[0014] Figure 6 is a circuit diagram illustrating a comparator included in an image sensor according to an example embodiment;

[0015] Figure 7 and Figure 8 is a diagram illustrating an operation of an image sensor according to an example embodiment;

[0016] Figure 9 is a block diagram illustrating an image sensor according to an example embodiment;

[0017] Figure 10A and Figure 10B is a circuit diagram illustrating a replica circuit and a digital converter included in an image sensor according to an example embodiment;

[0018] Figure 11 is a diagram illustrating an operation of generating a ramp voltage performed by a ramp voltage generator included in an image sensor according to an example embodiment;

[0019] Figure 12A , Figure 12B , Figure 12C , Figure 12D and Figure 12E are diagrams illustrating a compensation operation in an image sensor according to an example embodiment;

[0020] Figure 13 is a block diagram illustrating an image sensor according to an example embodiment;

[0021] Figure 14 is a block diagram illustrating an EDS test process of an example in which a test circuit is included in an image sensor according to an example embodiment;

[0022] Figure 15A and Figure 15B are diagrams illustrating an image sensor according to an example embodiment; and

[0023] Figure 16 and Figure 17 are diagrams illustrating an electronic device including an image sensor according to an example embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the disclosure will be described below with reference to the accompanying drawings.

[0025] Figure 1 is a block diagram illustrating an image sensor according to an example embodiment.

[0026] Referring to Figure 1 , an image sensor 1 according to an example embodiment can include a pixel array 10 and a controller 20, which can include a row driver 21, a readout circuit 22, a column driver 23, and a control logic 24.

[0027] The image sensor 1 can generate image data by converting light received from the outside into an electrical signal. The pixel array 10 included in the image sensor 1 can include a plurality of connected pixels PX connected to a plurality of row lines extending in a first direction and a plurality of column lines extending in a second direction intersecting the first direction. The plurality of pixels PX can include a photoelectric conversion element (such as a photodiode PD) that generates an electric charge in response to an optical signal incident from the outside.

[0028] Each of the plurality of pixels PX can include a pixel circuit for generating a pixel signal from an electric charge generated by the photodiode. For example, the pixel circuit can include a transfer transistor, a drive transistor, a selection transistor, a reset transistor, and a floating diffusion.

[0029] The pixel circuit can output a reset voltage and a pixel voltage. The pixel voltage can correspond to an electric charge generated by the photodiode included in each of the plurality of pixels PX and stored in the floating diffusion. In an example embodiment, two or more pixels PX adjacent to each other can form a single pixel group, and the two or more pixels PX included in the pixel group can share at least a portion of the transfer transistor, the drive transistor, the selection transistor, and the reset transistor.

[0030] The row driver 21 can drive the pixel array 10 by inputting a drive signal to the plurality of row lines. For example, the drive signal can include a transfer control signal for controlling the transfer transistor of the pixel circuit, a reset control signal for controlling the reset transistor, a selection control signal for controlling the selection transistor.

[0031] The readout circuit 22 can include a plurality of comparators and a counter circuit that converts an output of each of the comparators into a digital signal. The readout circuit 22 can include a ramp voltage generator for generating a ramp voltage to be compared with the reset voltage and the pixel voltage input from the pixel array 10.

[0032] The column driver 23 can include a latch that temporarily stores a digital signal and an amplifier circuit, and can process the digital signal received from the readout circuit 22. The row driver 21, the readout circuit 22, and the column driver 23 can be controlled by the control logic 24.

[0033] The control logic 24 can include a timing controller for controlling the operation timing of the row driver 21, the readout circuit 22, and the column driver 23, and an image signal processor for processing image data. In an example embodiment, the image signal processor can be included in an external processor connected to be able to communicate with the image sensor 1.

[0034] Figure 2 is a block diagram illustrating a pixel array and a readout circuit in an image sensor according to an example embodiment.

[0035] Reference Figure 2 The image sensor 100 according to an example embodiment may include a pixel array 110 and a controller for driving the pixel array 110. The controller may include a row driver 120 and a readout circuit 130. The readout circuit 130 may include a plurality of comparators 131, a ramp voltage generator 132, and a data bus (DBS) circuit 133. However, the example embodiment is not limited thereto, and the readout circuit 130 may also include other elements as needed.

[0036] The pixel array 110 of the image sensor according to the example embodiment may include a plurality of pixels PX arranged at the points where multiple row lines (ROW) and multiple column lines (COL) intersect each other. 11 To PX MN The row driver 120 can control multiple pixels (PX) via multiple row line ROW input signals. 11 To PX MN In an example embodiment, the image sensor can be configured by making pixels PX connected to the row lines... 11 To PX MN A rolling shutter method that sequentially exposes light to a pixel PX 11 To PX MN Simultaneously, it operates using a global shutter method that exposes the device to light.

[0037] The row driver 120 can select one of multiple row lines (ROWs) during a predetermined horizontal period. For example, it can drive a selection drive line among multiple row lines and a pixel (PX) connected to the selection drive line. 11 To PX MN The time to read the reset voltage and pixel voltage can be defined as a horizontal period.

[0038] The frame period of an image sensor can be defined as the frame rate from all pixels PX included in the pixel array 110. 11 To PX MN The time taken to read the reset voltage and pixel voltage. For example, the frame period can be equal to or greater than the product of the number of row lines and the horizontal period. As the frame period of the image sensor becomes shorter, the image sensor can generate more image frames within the same time period.

[0039] The plurality of comparators 131 included in the image sensor 100 according to the example embodiment may each include an amplifier. The amplifier included in each of the plurality of comparators 131 may be an operational transconductance amplifier (OTA).

[0040] Comparator 131 can be connected to pixel PX via column lines. 11 To PX MNFor example, the comparators 131 can obtain the reset voltage and the pixel voltage from the selected pixels connected to the selected row line selected by the row driver 120 among the plurality of pixels PX 11 to PX MN The reset voltage and the pixel voltage output from the pixels PX

[0041] In an example embodiment, the comparators 131 can be samplers, and can be Correlated Double Samplers (CDS). Each of the comparators 131 can include a first input terminal connected to one of the column lines COL and a second input terminal that receives a ramp voltage output through the ramp voltage generator 132. The reset voltage and the pixel voltage output from the pixels PX 11 to PX MN The reset voltage and the pixel voltage can be input to the first input terminal. The comparators 131 can perform correlated double sampling, can compare each of the reset voltage and the pixel voltage with the ramp voltage, and can output a comparison result.

[0042] The DBS circuit 133 can convert the comparison result output from the comparators 131 into digital data DATA, and can output the data. The DBS circuit 133 can include a counter circuit. The DBS circuit 133 can be implemented as an analog-to-digital converter together with other components.

[0043] The ramp voltage generator 132 can include an array of current cells including unit current cells that generate a ramp voltage input to the second input terminal of the comparators 131. The ramp voltage generator 132 can generate a ramp voltage through sequential operations of turning on and off of the unit current cells. The amplitude of the ramp voltage can be determined based on the number of unit current cells actually operated in the ramp voltage generator 132. For example, the number of unit current cells included in the ramp voltage generator 132 can be determined according to the number of bits of the digital data DATA. As an example, when the digital data DATA is 10-bit data, the ramp voltage generator 132 can include 1024 or more unit current cells.

[0044] Figure 3 and Figure 4 is a circuit diagram illustrating a pixel included in a pixel array in an image sensor according to an example embodiment.

[0045] Referring to Figure 3 , a pixel included in an image sensor according to an example embodiment can include a photodiode PD for generating a charge in response to light and a pixel circuit PX for processing the charge generated by the photodiode PD and outputting an electrical signal. For example, the pixel circuit PX can include a floating diffusion FD, a reset transistor RX, a drive transistor DX, a selection transistor SX, and a transfer transistor TX.

[0046] The reset transistor RX can be connected between a power supply node for supplying a power supply voltage VDD and the floating diffusion FD, and can be controlled by a reset control signal RG. For example, when the reset transistor RX is turned on, the voltage of the floating diffusion FD can be reset to the power supply voltage VDD. When the voltage of the floating diffusion FD is reset, the selection transistor SX can be turned on by a selection control signal SEL, and the reset voltage can be output to the column line COL.

[0047] In an example embodiment, the photodiode PD can generate electrons or holes as primary charge carriers in response to light. When the reset voltage is output to the column line COL and the transfer transistor TX is turned on by a transfer control signal TG, the charge generated by the photodiode PD exposed to light can move to the capacitor C FD The drive transistor DX can operate as a source follower amplifier for amplifying the voltage of the floating diffusion FD. When the selection transistor SX is turned on by the selection control signal SEL, the pixel voltage based on the charge generated by the photodiode PD can be output to the column line COL.

[0048] Each of the reset voltage and the pixel voltage can be detected by a readout circuit connected to the column line COL. The readout circuit can include a plurality of comparators having first input terminals and second input terminals, the comparators can receive a ramp voltage through the first input terminals. The comparators can compare the ramp voltage input to the first input terminals with the reset voltage and the pixel voltage input to the second input terminals.

[0049] The DBS circuit can be connected to output terminals of the comparators, the DBS circuit can output reset data corresponding to a comparison result of the ramp voltage and the reset voltage and pixel data corresponding to a comparison result of the ramp voltage and the pixel voltage. The controller can generate image data with a pixel signal corresponding to a difference between the reset data and the pixel data.

[0050] The magnitude of the pixel voltage can be determined by the amount of charge generated by the photodiode PD and transferred to the floating diffusion FD and a conversion gain of the pixel circuit PX. The conversion gain of the pixel circuit PX can correspond to a voltage change caused by the charge, and can be inversely proportional to the capacitance of the floating diffusion FD. In other words, when the capacitance of the floating diffusion FD increases, the conversion gain of the pixel circuit PX can decrease, and when the capacitance of the floating diffusion FD decreases, the conversion gain of the pixel circuit PX can increase.

[0051] The conversion gain can affect the performance of the image sensor. For example, when the conversion gain of the pixel circuit PX is set to correspond to a low brightness environment, an image signal generated in a high brightness environment can exceed the dynamic range of the image sensor, and thus, the quality of the image can be degraded. When the conversion gain of the pixel circuit PX is set to correspond to a high brightness environment, the driving transistor DX can not be sufficiently driven in a low brightness environment, and thus, the quality of the image can be degraded.

[0052] Referring to Figure 4 In the image sensor according to an example embodiment, in order to solve the above-described problems, the pixel circuit PX can further include a switching device SW connected between the reset transistor RX and the floating diffusion FD. The on and off of the switching device SW can be controlled by a switching control signal SG.

[0053] The image sensor according to an example embodiment can turn the switching device SW on or off to dynamically adjust the conversion gain of the pixel circuit PX. In addition, the image sensor can determine whether to turn the switching device SW on or off in consideration of the length of the exposure time in which the photodiode PD is exposed to light to obtain a pixel signal, and can generate a single resultant image using pixel signals obtained from different exposure time periods. Accordingly, the noise performance and the dynamic range of the image sensor can be improved.

[0054] As an example, when the switching device SW is off, the capacitance of the floating diffusion FD storing the charge generated by the photodiode PD can be determined as a first capacitance C FD1 When the switching device SW is on, the capacitance of the floating diffusion FD can be determined as a sum of the first capacitance C FD1 and a second capacitance C FD2 In other words, by turning the switching device SW off, the capacitance of the floating diffusion FD can be reduced, and the conversion gain can be increased, and by turning the switching device SW on, the capacitance of the floating diffusion FD can be increased, and the conversion gain can be reduced. For example, the switching device SW can be turned off when the amount of light is relatively small, and can be turned on when the amount of light is relatively large.

[0055] Figure 5 FIG. 10 is a diagram illustrating a correlated double sampling operation of an image sensor according to an example embodiment.

[0056] Referring to Figure 4 and Figure 5 The reset transistor RX can be turned on by a reset control signal RG, and thus, the voltage of the floating diffusion FD can be reset. In this case, the switching device SW can be turned on together with the reset transistor RX by the switching control signal SG, and thus, the voltage of the floating diffusion FD can be reset.

[0057] When the voltage of the floating diffusion FD is reset, the reset transistor RX and the switch device SW can be turned off, and the comparator CDS of the readout circuit can read out the reset voltage V RT from the pixel by selecting the control signal SEL RT .

[0058] As an example, after the reset voltage V RT is read out, when the transfer transistor TX is turned on and the charge of the photodiode PD is moved to the floating diffusion FD, the switch device SW can remain in the off state. Thus, the capacitance of the floating diffusion FD can be determined as a first capacitance C FD1 . The conversion gain of the pixel can be determined as a first value corresponding to the first capacitance C FD1 . In other words, when the conversion gain of the pixel has the first value, the image sensor can move the charge of the photodiode PD to the floating diffusion FD, and can read out the pixel voltage V PX .

[0059] The comparator CDS performing the correlated double sampling operation can read out the reset voltage V RT and the pixel voltage V PX during a single horizontal period, and the controller of the image sensor can obtain a pixel signal corresponding to the difference between the reset voltage V RT and the pixel voltage V PX .

[0060] In an example embodiment, the on timing of the switch device SW can be changed. For example, after a single horizontal cycle, the image sensor can turn on the switch device SW. When the switch device SW is turned on, the capacitance of the floating diffusion FD can be determined as a sum of the first capacitance C FD1 and a second capacitance C FD2 , and thus, the conversion gain of the pixel can have a second value corresponding to the sum of the first capacitance C FD1 and the second capacitance C FD2 . The second value can be smaller than the first value.

[0061] When the conversion gain of the pixel has the second value, the comparator CDS can obtain the reset voltage V RT and the pixel voltage V PX by a similar process. Likewise, the controller of the image sensor can obtain a new pixel signal during a new horizontal period. The image sensor can generate an image frame with the pixel signals acquired sequentially.

[0062] Figure 6is a circuit diagram showing a comparator included in an image sensor according to an example embodiment.

[0063] Referring to Figure 6 In an example embodiment, the comparator can be a correlated double sampling comparator (CDS), and can include a plurality of transistors. The comparator CDS can include a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, and a second NMOS transistor NM2. However, the configuration of the comparator CDS and the number of transistors can vary in example embodiments.

[0064] The first PMOS transistor PM1 and the second PMOS transistor PM2 can be connected to a power supply node for supplying a power supply voltage VDD DD The first NMOS transistor NM1 and the second NMOS transistor NM2 can be connected to a current source CS for supplying a bias current.

[0065] The gate of the first NMOS transistor NM1 can provide a first input terminal IN1 of the comparator CDS, and the gate of the second NMOS transistor NM2 can provide a second input terminal IN2 of the comparator CDS. In an example embodiment, the first input terminal IN1 can be connected to an output terminal of a ramp voltage generator for generating a ramp voltage, and the second input terminal IN2 can be connected to a pixel of the image sensor through a column line.

[0066] The first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, and the second NMOS transistor NM2 can provide an amplifier circuit. In an example embodiment, the amplifier circuit can be implemented as an OTA circuit. In an example embodiment, the first PMOS transistor PM1 and the second PMOS transistor PM2 can have the same size, and the first NMOS transistor NM1 and the second NMOS transistor NM2 can have the same size. The first PMOS transistor PM1 and the second PMOS transistor PM2 and the first NMOS transistor NM1 and the second NMOS transistor NM2 can have the same size or different sizes.

[0067] In the image sensor according to the example embodiment, the comparator CDS can include a first auto-zero switch AZ1 connected to the first input terminal IN1 and a second auto-zero switch AZ2 connected to the second input terminal IN2. The first auto-zero switch AZ1 and the second auto-zero switch AZ2 can be used to control an auto-zero operation of the image sensor. The first auto-zero switch AZ1 and the second auto-zero switch AZ2 can be implemented as transistors, and can receive different control signals through respective gate terminals. Accordingly, the turn-on and turn-off operations of the first auto-zero switch AZ1 and the second auto-zero switch AZ2 can be independently controlled.

[0068] In the image sensor according to the example embodiment, the plurality of transistors included in the comparator CDS can be connected to each other through a plurality of wirings. For example, the gate terminal of the first auto-zero switch AZ1 can be connected to a first wiring, and the gate terminal of the second auto-zero switch AZ2 can be connected to a second wiring. The first wiring and the second wiring can transmit different signals, and a first auto-zero signal AZS1 can be transmitted through the first wiring, and a second auto-zero signal AZS2 can be transmitted through the second wiring. The first wiring and the second wiring can be physically separated from each other.

[0069] The turn-on and turn-off timing of the first auto-zero switch AZ1 and the second auto-zero switch AZ2 in the auto-zero operation can be controlled differently from each other by the first auto-zero signal AZS1 and the second auto-zero signal AZS2. For example, in the image sensor according to the example embodiment, the second auto-zero switch AZ2 can be turned off after the first auto-zero switch AZ1 included in each comparator CDS is turned off during the auto-zero operation. In other words, only the first auto-zero switch AZ1 can be turned off while the second auto-zero switch AZ2 remains in the turn-on state.

[0070] In addition, only one of the first auto-zero switch AZ1 and the second auto-zero switch AZ2 can be selectively turned on while the other remains in the turn-off state. As an example, the first auto-zero switch AZ1 can be turned on before the second auto-zero switch AZ2, or the second auto-zero switch AZ2 can be turned on before the first auto-zero switch AZ1. Alternatively, in the example embodiment, the first auto-zero switch AZ1 and the second auto-zero switch AZ2 can be turned on at the same time.

[0071] In the image sensor according to the example embodiment, a node to which the first NMOS transistor NM1 and the second NMOS transistor NM2 are commonly connected can be defined as a common node N2, and a voltage applied to the common node N2 can be defined as a common node voltage. In addition, a node to which the first PMOS transistor PM1 and the second PMOS transistor PM2 are commonly connected can be defined as an auto-zero node N1, and a voltage applied to the auto-zero node N1 can be defined as an auto-zero voltage.

[0072] In the image sensor according to the example embodiment, the first auto-zero switch AZ1 can be connected to the auto-zero node N1, and the second auto-zero switch AZ2 can be connected to the output terminal of the comparator CDS.

[0073] The configuration of the comparator CDS included in the image sensor according to the example embodiment is not limited to the above-described example embodiment, and can further include other elements as needed. For example, an output transistor that provides an output terminal, an additional current source that supplies an additional bias current, and a MOS capacitor for limiting the bandwidth of an output signal can also be included.

[0074] Figure 7 and Figure 8 are diagrams illustrating the operation of the image sensor according to the example embodiment.

[0075] Figure 7 An example embodiment in which a single auto-zero signal AZS included in the comparator in the image sensor according to the example embodiment is used to control the first auto-zero switch and the second auto-zero switch is illustrated. Referring to Figure 7 When the first auto-zero switch and the second auto-zero switch are controlled using the single auto-zero signal AZS, the pixel voltage that can be input to the comparator can be limited to a first input range IR1.

[0076] According to the example embodiment illustrated in Figure 7 , the first auto-zero switch and the second auto-zero switch can be turned on at the same time by the auto-zero signal AZS, and the comparator can be initialized. When the comparator is initialized, the voltage level of the input node and / or the output node of the comparator can be equal to the auto-zero voltage V AZ . For the operation of reading out the reset voltage, a first offset voltage V offset1 can be added to the ramp voltage RMP, which can decrease after the selection control signal SEL is activated. Once the readout operation of the reset voltage is completed, the predetermined offset voltage can be added to the ramp voltage RMP again.

[0077] The pixel voltage PIX can be held at the reset voltage until the transfer control signal TG is activated. Once the transfer control signal TG is activated and the charge accumulated in the photodiode is moved to the floating diffusion, the pixel voltage PIX can be reduced as shown in Figure 7 .

[0078] For the operation of reading out the image signal, the ramp voltage RMP can be reduced again. After the operation of reading out the image signal is completed, when the reset control signal RG is activated, the pixel voltage PIX can return to the initial level. In the operation described with reference to Figure 7 , the minimum value V min of the ramp voltage RMP can be larger than the difference from the initial level of the pixel voltage PIX.

[0079] The readout operation of the image sensor according to the example embodiment can include a counting operation of detecting the number of times that the ramp voltage RMP is larger than the pixel voltage PIX. For example, the counting operation can be performed by the DBS circuit, and can be implemented in various ways such as bit shifting or up-counting.

[0080] In the example embodiment, by controlling the first auto-zero switch included in the comparator via the first auto-zero signal AZS1 and the second auto-zero switch via the second auto-zero signal AZS2, the input range of the comparator can be increased.

[0081] With reference to Figure 6 and Figure 8 , the first auto-zero signal AZS1 can be input to the first auto-zero switch AZ1 through a first wiring, and the second auto-zero signal AZS2 can be input to the second auto-zero switch AZ2 through a second wiring. As an example, the first auto-zero signal AZS1 can be deactivated before the second auto-zero signal AZS2, and the first auto-zero switch AZ1 can be turned off before the second auto-zero switch AZ2.

[0082] By differently controlling the on-off timing of the first auto-zero switch AZ1 and the second auto-zero switch AZ2, the initial value of the ramp voltage RMP can be larger than the initial value of the ramp voltage RMP shown in Figure 7 . For example, in a state in which the first auto-zero signal AZS1 is deactivated and the second auto-zero signal AZS2 is activated, the compensation voltage V c can be added to the ramp voltage RMP. Because the compensation voltage V c can be applied in both input terminals of the comparator at the same time by the on-off state of the first auto-zero switch AZ1 and the second auto-zero switch AZ2, the pixel voltage PIX can be increased by as much as the compensation voltage V c , similarly to the ramp voltage RMP.

[0083] According to Figure 8 the example embodiment shown in FIG. 1, the first offset voltage V Figure 7 offset voltage V offset1 may be added to the ramp voltage RMP for the operation of reading out the reset voltage. In other words, the second offset voltage V offset2 (the sum of the first offset voltage V offset1 and the compensation voltage V c ) can be added for the operation of reading out the reset voltage. Thus, after the termination of the comparison operation, the value of the pixel voltage PIX can be greater than the value of the ramp voltage RMP by the compensation voltage V c .

[0084] In the operation described with reference to Figure 8 , the second input range IR2 corresponding to the difference between the minimum value V min of the ramp voltage RMP and the initial level of the pixel voltage PIX can be the input range of the comparator. The second input range IR2 can have a value greater than the first input range IR1 by the compensation voltage V c described with reference to Figure 7 .

[0085] As an example, with reference to Figure 6 , the compensation voltage V c may be a voltage corresponding to the threshold voltage of the first NMOS transistor NM1 of the comparator CDS. The compensation voltage V c may be a value between 50 mV and 700 mV. However, example embodiments are not limited thereto, and the compensation voltage V c may be a value of 700 mV or more. In addition, the compensation voltage V c may be a voltage corresponding to the sum of the threshold voltage and the tolerance voltage used for the image sensor. The tolerance voltage can be determined based on the distribution of the threshold voltage.

[0086] For example, by the compensation voltage V c , the input range of the comparator CDS can be increased by about 50% from the first input range IR1 to the second input range IR2. In other words, the second input range IR2 can be about 1.5 times the first input range IR1. However, example embodiments are not limited thereto, and the second input range IR2 can be between 1 to 1.5 times the first input range IR1, or can be greater than 1.5 times the first input range IR1.

[0087] The image sensor according to the example embodiment can increase the input range of the comparator by compensating for the ramp voltage RMP generated by the ramp voltage generator as described above. However, because the threshold voltage of the first NMOS transistor NM1 can vary according to the distribution of the processing result value and the temperature, the compensation voltage V c may vary according to the environment. Thus, it can be required to sense the compensation voltage V c and input the voltage in the form of a control signal to the ramp voltage generator.

[0088] In the following description, reference will be made to Figures 9 to 14 a method of inputting a control signal to the ramp voltage generator using a replica circuit or a test circuit and a method of operating the ramp voltage generator will be described.

[0089] Figure 9 is a block diagram illustrating an image sensor according to an example embodiment.

[0090] Referring to Figure 9 , the image sensor 200 according to the example embodiment can include a pixel array 210 and a controller for driving the pixel array 210. The controller can include a row driver 220 and a readout circuit 230. The readout circuit 230 can include a plurality of comparators 231, a ramp voltage generator 232, and a DBS circuit 233. The readout circuit 230 can include a sensing circuit 235 for outputting and inputting a compensation signal to the ramp voltage generator 232. The sensing circuit 235 can include a replica circuit 236 and a digital converter 237.

[0091] The other elements of the pixel array 210 included in the image sensor 200 shown in Figure 9 may be operated similarly to those of the image sensor 100 shown in Figure 2 . The sensing circuit 235 can have the same structure as at least a portion of each of the comparators 231. As an example, the sensing circuit 235 can include a portion of the elements included in each of the comparators 231. In the image sensor 200 according to the example embodiment, the sensing circuit 235 can include a replica input transistor corresponding to an input transistor connected to the first input terminal of each of the comparators 231.

[0092] As an example, the replica circuit 236 included in the sensing circuit 235 can detect a sensing signal to obtain a replica threshold voltage of a replica input transistor corresponding to a threshold voltage of the input transistor. The sensing signal can be input to the digital converter 237, and can be converted into a digital signal, and the replica threshold voltage obtained from the sensing signal can be input to the ramp voltage generator 232 in the form of a control signal for compensating the ramp voltage. However, the process of inputting the control signal of the ramp voltage to the ramp voltage generator 232 is not limited thereto, and can be operated by a different procedure according to the configuration of the sensing circuit 235.

[0093] In the image sensor 200 according to the example embodiment, the operation of the sensing circuit 235 including the replica circuit 236 and the digital converter 237 can be performed at least once. For example, when the image sensor 200 is initially operated, the replica circuit 236 can collect a sensing signal, and can transmit a control signal to the ramp voltage generator 232. However, the example embodiment is not limited thereto, and the replica circuit 236 can collect a sensing signal in every at least one or more frames during the operation of the image sensor 200, and can transmit a control signal to the ramp voltage generator 232.

[0094] Figure 10A and Figure 10B is a circuit diagram illustrating a replica circuit and a digital converter included in an image sensor according to an example embodiment.

[0095] Referring to Figure 10A , the readout circuit 230a included in the image sensor according to the example embodiment can include a replica circuit 236a, a digital converter 237a, and a ramp voltage generator 232a. The replica circuit 236a can include the same elements as at least a part of elements included in each of the comparators.

[0096] As an example, referring back to the comparator (CDS) illustrated in Figure 6 , the replica circuit 236a can include a first replica NMOS transistor NM1a and a first replica PMOS transistor PM1a corresponding to a first NMOS transistor NM1 and a first PMOS transistor PM1 included in the comparator CDS, respectively.

[0097] A node to which the first replica NMOS transistor NM1a and the first replica PMOS transistor PM1a are commonly connected can correspond to the auto-zero node N1, and can be defined as a replica auto-zero node N1a. A voltage of the replica auto-zero node N1a can be a replica auto-zero voltage corresponding to the auto-zero voltage.

[0098] Likewise, the node connected to the output transistor OTa can correspond to the common node N2, and can be defined as a replica common node N2a. The voltage of the replica common node N2a can be a replica common node voltage corresponding to the common node voltage.

[0099] The replica circuit 236a can output the replica auto-zero voltage as a first sensing signal, and can output the replica common node voltage as a second sensing signal.

[0100] In the image sensor according to an example embodiment, the replica circuit 236a can further include a selection circuit (MUX) that sequentially outputs the first sensing signal and the second sensing signal by a timing signal. For example, the selection circuit MUX can be implemented as a multiplexer. The digitizer 237a can include a single analog-to-digital converter ADC_d. The analog-to-digital converter ADC_d can receive the first sensing signal and the second sensing signal sequentially output from the replica circuit 236a, and can convert the signals into digital signals.

[0101] Referring to Figure 10B The readout circuit 230b included in the image sensor according to an example embodiment can include a replica circuit 236b, a digitizer 237b, and a ramp voltage generator 232b. The replica circuit 236b can include the same elements as at least a portion of elements included in each of the comparators. For example, the readout circuit 230b can have a structure similar to that of the readout circuit 230a described with reference to Figure 10A

[0102] In the image sensor according to an example embodiment, the digitizer 237b can include two analog-to-digital converters ADC_d1 and ADC_d2. For example, the analog-to-digital converters ADC_d1 and ADC_d2 can receive sensing signals from the replica circuit 236b. For example, the first analog-to-digital converter ADC_d1 can receive a voltage of a replica auto-zero node N1b as a first sensing signal, and the second analog-to-digital converter ADC_d2 can receive a voltage of a replica common node N2b as a second sensing signal. The received first and second sensing signals can be converted into digital signals.

[0103] In Figure 10A and Figure 10B ​In the meantime, the digital converters 237a and 237b can further include a logic circuit LC_d. The logic circuit LC_d can detect a replica threshold voltage corresponding to a threshold voltage of the first NMOS transistor NM1 using the first and second sensing signals received from the replica circuits 236a and 236b. The logic circuit LC_d can also detect a margin voltage for operation of the image sensor as well as the replica threshold voltage. The replica threshold voltage and / or the margin voltage can be input to the ramp voltage generator 232 in the form of a control signal for compensating the ramp voltage.

[0104] The digital converters 237a and 237b can determine a compensation level of the ramp voltage. In an example embodiment, the compensation level can be determined according to the replica threshold voltage detected by the logic circuit LC_d. Alternatively, the compensation level can be determined taking into account the margin voltage for operation of the image sensor as well as the replica threshold voltage. As an example, the compensation level can correspond to a sum of the replica threshold voltage and the margin voltage for operation of the image sensor.

[0105] In the image sensor according to an example embodiment, the digital converters 237a and 237b can output a control signal including information on the compensation level. The output control signal can be input to the ramp voltage generators 232a and 232b, and the ramp voltage can be compensated.

[0106] In the image sensor according to an example embodiment, the ramp voltage generators 232a and 232b can include a controller CT and a digital-to-analog converter DAC. The controller CT can receive a clock signal CLK and include an array of current cells for determining an amplitude of a generated ramp voltage. The digital-to-analog converter (DAC) can convert a digital signal obtained from the array of current cells into an analog signal to input the signal to the comparator.

[0107] The resolutions of the analog-to-digital converters ADC_d, ADC_d1, and ADC_d2 included in the digital converters 237a and 237b can be less than a resolution of an analog-to-digital converter for converting an output signal of the comparator into a digital signal. For example, in the image sensor according to an example embodiment, the analog-to-digital converter for converting an output signal of the comparator into a digital signal can be the DBS circuit.

[0108] As an example, the analog-to-digital converters ADC_d, ADC_d1, and ADC_d2 can have a resolution of 4 bits or 5 bits, and the DBS circuit can have a resolution of about 10 bits. In other words, the analog-to-digital converters ADC_d, ADC_d1, and ADC_d2 can output 4-bit or 5-bit signals, and the DBS circuit can output a digital pixel signal of about 10 bits, however, example embodiments thereof are not limited thereto, and the resolution of each device can be greater or less than the aforementioned example embodiments. The resolution of the analog-to-digital converters ADC_d, ADC_d1, and ADC_d2 can be determined by the magnitude of the compensation voltage, and the resolution of the DBS circuit can be determined by the generated ramp voltage, the reset voltage, and the pixel voltage.

[0109] Figure 11 FIG. 1 is a diagram illustrating an operation of generating a ramp voltage by a ramp voltage generator included in an image sensor according to an example embodiment.

[0110] Referring to Figure 11 The ramp voltage generator can include a current cell array CCA having a plurality of unit current cells CC[1,1] to CC[m,n], and can further include a row selector 240 and a column selector 250 for outputting a signal for driving the plurality of unit current cells CC[1,1] to CC[m,n].

[0111] The plurality of unit current cells CC[1,1] to CC[m,n] can be disposed at points where rows and columns intersect each other, and can be driven in order by the row selector 240 and the column selector 250. For example, when the row selector 240 activates one row, the column selector 250 can drive the plurality of unit current cells CC[1,1] to CC[m,n] by sequentially activating or deactivating the columns. In the image sensor according to an example embodiment, the ramp voltage generator can output a ramp voltage by driving the plurality of unit current cells CC[1,1] to CC[m,n].

[0112] However, example embodiments thereof are not limited thereto, and the arrangement of the plurality of unit current cells included in the ramp voltage generator is not limited to the form of multiple rows and multiple columns, and can be driven in various ways. For example, the plurality of unit current cells can be grouped into a single group, and can be driven in units of groups.

[0113] In the image sensor according to an example embodiment, the current cell array CCA included in the slope voltage generator can include x (n x m = x) unit current cells CC[1,1] to CC[m,n] in total. For example, the current cell array CCA can include 32 columns (n = 32) and 48 rows (m = 48) in total. Accordingly, the total number of the unit current cells CC[1,1] to CC[m,n] can be 1536. However, example embodiments are not limited thereto, and the number of the unit current cells CC[1,1] to CC[m,n] can vary in example embodiments.

[0114] In the image sensor according to an example embodiment, the x unit current cells CC[1,1] to CC[m,n] can include a first current cell group CCG1 and a second current cell group CCG2. For example, the first current cell group CCG1 can include the unit current cells CC[1,1] to CC[k,n] for generating the slope voltage except for the compensation voltage. The second current cell group CCG2 can include the unit current cells CC[k+1,1] to CC[m,n] for generating the compensation voltage. The unit current cells CC[1,1] to CC[k,n] included in the first current cell group CCG1 can be the unit current cells CC[1,1] to CC[k,n] from the first column to the k-th column, and the unit current cells CC[k+1,1] to CC[m,n] included in the second current cell group CCG2 can be the unit current cells CC[k+1,1] to CC[m,n] from the k+1-th column to the m-th column. However, example embodiments are not limited thereto, and the current cell array CCA can include three or more current cell groups. In addition, the unit current cells CC[1,1] to CC[m,n] included in each current cell group can be arranged in various ways.

[0115] The number of the unit current cells CC[1,1] to CC[m,n] included in the first current cell group CCG1 and the second current cell group CCG2 can be determined according to the range of the output voltage output by a single unit current cell and the voltage level. The voltage level output by a single unit current cell can relate to how accurately the voltage to be output can be output. As an example, in the case where 100 units output an arbitrary voltage between 0 mV and 100 mV, the output voltage can be adjusted in units of 1 mV. In the case where 1000 units output an arbitrary voltage between 0 mV and 100 mV, the output voltage can be adjusted in units of 0.1 mV, so that the voltage to be output can be output more accurately.

[0116] For the purpose of description Figures 11 to 12EAs shown in the graphs, it can be assumed that a voltage level output by a single unit current cell in the image sensor according to an example embodiment is about 1 mV. However, example embodiments are not limited thereto, and the number of unit current cells and the level of voltage output by a single unit current cell can vary in example embodiments.

[0117] As an example, when the ramp voltage generated by the first current cell group CCG1 has a value between 0 mV and 1000 mV except for the compensation voltage, the first current cell group CCG1 can include 1024 unit current cells CC[1,1] to CC[32,32]. When the compensation voltage generated by the second current cell group CCG2 has a value between 0 mV and 500 mV, the second current cell group CCG2 can include 512 unit current cells CC[33,32] to CC[48,32]. However, example embodiments are not limited thereto, and the number of unit current cells included in each current cell group can vary in example embodiments.

[0118] Figure 12A , Figure 12B , Figure 12C , Figure 12D and Figure 12E are graphs showing a compensation operation in an image sensor according to an example embodiment.

[0119] Referring to Figure 11 and Figure 12A , the second current cell group CCG2 for generating a compensation voltage can include a plurality of threshold voltage current cells CC th and a plurality of margin voltage current cells CC sm In this case, the compensation voltage can include a replica threshold voltage corresponding to a threshold voltage of an input transistor of a comparator included in the image sensor according to an example embodiment and a margin voltage considering a distribution of the threshold voltage.

[0120] The plurality of threshold voltage current cells CC th may be defined as current cells for adding a compensation voltage corresponding to a replica threshold voltage. The plurality of margin voltage current cells CC sm may be defined as current cells for applying a compensation voltage corresponding to a margin voltage.

[0121] In the image sensor according to an example embodiment, the ramp voltage generator can activate at least a portion of the plurality of threshold voltage current cells CC th to compensate for the ramp voltage. The ramp voltage generator can activate at least a portion of the plurality of margin voltage current cells CC sm and at least a portion of the plurality of threshold voltage current cells CC th ​

[0122] As an example, the threshold voltage current cell CC th may be 16 x 32 unit current cells, the margin voltage current cell CC sm may be 2 x 32 unit current cells. However, example embodiments thereof are not limited thereto, and the threshold voltage current cell CC th and the margin voltage current cell CC sm may vary in number and shape according to the magnitude of the compensation voltage.

[0123] Referring to Figure 12B , in the image sensor in example embodiments, the ramp voltage can be compensated by the threshold voltage of the input transistor without considering the margin voltage. The unit current cell can be activated in a unit of each cell. For example, the unit current cell can include an activated cell SC and a non-activated cell USC. As indicated by the current cell shown in Figure 12B , the ramp voltage generator can generate a compensation voltage of about 100 mV using the activated unit current cell SC.

[0124] Referring to Figure 12C , in the image sensor according to example embodiments, the ramp voltage can be compensated by the threshold voltage of the input transistor without considering the margin voltage. The unit current cell can be activated in a unit of a row. For example, the unit current cell can include an activated cell SC and a non-activated cell USC. As indicated by the current cell shown in Figure 12C , the ramp voltage generator can generate a compensation voltage of about 128 mV using the activated unit current cell SC.

[0125] Referring to Figure 12D , in the image sensor according to example embodiments, the ramp voltage can be compensated by the threshold voltage of the input transistor without considering the margin voltage. For example, the unit current cell can include an activated cell SC and a non-activated cell USC. As indicated by the current cell shown in Figure 12D , a compensation voltage of about 512 mV can be generated when all of the threshold voltage activation cells CC th are activated.

[0126] Referring to Figure 12E , in the image sensor according to example embodiments, the ramp voltage can be compensated by considering the margin voltage and the threshold voltage of the input transistor. For example, the unit current cell can include an activated cell SC and a non-activated cell USC. The activated unit current cell SC can include at least a portion of the threshold voltage current cell CC th and at least a portion of the margin voltage current cell CC sm . According to Figure 12EThe slope voltage generator can generate a compensation voltage of approximately 170 mV using the activated unit current cell SC.

[0127] However, Figures 12B to 12E The example embodiments illustrated in

[0128] In the image sensor according to the example embodiments, the generated compensation voltage can be added to the slope voltage during the auto-zero operation. Because the compensation voltage is reflected together to both input terminals of the comparator, the pixel voltage can increase as much as the compensation voltage as the slope voltage. Accordingly, the input range of the pixel voltage in the comparator can be improved by the increased compensation voltage.

[0129] Figure 13 is a block diagram illustrating an image sensor according to example embodiments.

[0130] Referring to Figure 13 , the image sensor 300 according to the example embodiments can include a pixel array 310 and a controller for driving the pixel array 310. The controller can include a row driver 320 and a readout circuit 330. The readout circuit 330 can include a plurality of comparators 331, a slope voltage generator 332, and a DBS circuit 333. The readout circuit 330 can further include a sensing circuit for outputting a control signal and inputting the control signal to the slope voltage generator 332. The sensing circuit can be configured as a test circuit 338.

[0131] The other elements of the pixel array 310 included in Figure 13 the image sensor 300 illustrated in Figure 2 may operate similarly to those of the image sensor 100 illustrated in

[0132] As an example, in the image sensor 300 according to the example embodiments, the test circuit 338 can detect the threshold voltage by performing an electrical die sorting (EDS) test in a stage in which a wafer is completed in each process for manufacturing the image sensor 300. The detected threshold voltage can be input to the slope voltage generator 332 in the form of a control signal for compensating the slope voltage. However, the process of outputting the control signal of the slope voltage from the test circuit 338 and inputting the signal to the slope voltage generator 332 is not limited thereto, and can operate in various ways according to the configuration of the test circuit 338.

[0133] Figure 14 is a block diagram illustrating an example of an EDS test process of a test circuit included in an image sensor according to an example embodiment.

[0134] Referring to Figure 14 When a plurality of semiconductor wafers is produced by applying a semiconductor process to the wafer W, the wafer W can be produced. The plurality of semiconductor wafers included in the wafer W can include a semiconductor device. The semiconductor device can be an image sensor described according to an example embodiment.

[0135] After the wafer (W) is produced, an EDS test 501 can be performed using a test circuit included in an image sensor according to an example embodiment, so that threshold voltage data of an input transistor included in a comparator can be detected. However, example embodiments are not limited thereto, and the EDS test 501 can be performed a plurality of times according to conditions such as temperature.

[0136] After the EDS test 501 is completed, fusing 502 to write information in a one-time programmable (OTP) region can be performed. The fusing 502 can include writing threshold voltage determined through the EDS test 501 in the OTP region.

[0137] Once the fusing 502 is completed, each semiconductor wafer including an image sensor can be separated from the wafer W by applying a scribe process 503, and a package assembly process 504 can also be applied. When the image sensor is produced as a package through the package assembly process 504, a package test 505 can be performed, and the product can be shipped.

[0138] Referring to Figure 14 a series of processes described above, a process of detecting threshold voltage in an image sensor can be performed using an OTP region. In an image sensor according to an example embodiment, threshold voltage written through the above process can be transmitted to a ramp voltage generator in the form of a control signal, and can be used to compensate for a ramp voltage.

[0139] Figure 15A and Figure 15B is a diagram illustrating an image sensor according to an example embodiment.

[0140] Referring to Figure 15A , an image sensor 600a according to an example embodiment can include a first layer 610 and a second layer 620. The first layer 610 and the second layer 620 can be stacked in a vertical direction.

[0141] The first layer 610 can include a pixel array 611, and the second layer 620 can include logic circuits 621 and 622. The pixel array 611 can be connected to the logic circuits 621 and 622 through a plurality of row lines and a plurality of column lines.

[0142] As an example, the pixel array 611 can include normal pixels and autofocus pixels. The number of normal pixels can be greater than the number of autofocus pixels, and each of the autofocus pixels can include a plurality of photodiodes. In addition, when a D-cut lens is provided on a front surface of the pixel array 611, the autofocus pixels can include first autofocus pixels in which photodiodes are arranged in a direction of an edge of the D-cut lens and second autofocus pixels in which photodiodes are arranged in a direction different from the direction of the edge of the D-cut lens. In a vertical direction in which the first layer 610 and the second layer 620 are stacked, a height of the first autofocus pixels can be less than a height of the second autofocus pixels.

[0143] The logic circuits 621 and 622 can include a first logic circuit 621 and a second logic circuit 622. The first logic circuit 621 can include a row driver for driving the pixel array 611, a readout circuit, a column driver, and a control logic. In the image sensor 600a according to the example embodiment, the first logic circuit 621 can include a sensing circuit for sensing a replica threshold voltage corresponding to a threshold voltage of an input transistor of a comparator. The second logic circuit 622 can include a power supply circuit, an input / output interface, and an image signal processor. The area occupied by each of the first logic circuit 621 and the second logic circuit 622 and the arrangement form thereof can vary.

[0144] Referring to Figure 15B , the image sensor 600b can include the first layer 610, the second layer 620, and a third layer 630 provided between the first layer 610 and the second layer 620. The first layer 610 and the second layer 620 can be similar to the example embodiments described with reference to Figure 15A The third layer 630 can include a memory device array 631, which can include memory devices such as a metal-insulator-metal (MIM) capacitor, a charge trapping device, a magnetic tunnel junction (MTJ) device, and a germanium (Ge)-antimony (Sb)-tellurium (Te) device (GST). The memory devices can be connected to the pixels formed on the first layer 610 and / or any one or any combination of the logic circuits 621 and 622.

[0145] The configurations of the image sensors 600a and 600b are not limited to the examples shown in Figure 15A and Figure 15B , and can vary. As an example, a portion of the logic circuits 621 and 622 (e.g., at least a portion of the first logic circuit 621) can be provided on the first layer 610 together with the pixel array 611.

[0146] Figure 16 and Figure 17is a diagram illustrating an electronic device including an image sensor according to an example embodiment.

[0147] Referring to Figure 16 , the electronic device 1000 can include a camera module group 1100, an application processor 1200, a power management integrated circuit (PMIC) 1300, and an external memory 1400.

[0148] The camera module group 1100 can include a plurality of camera modules 1100a, 1100b, and 1100c. This diagram illustrates an example embodiment in which three camera modules 1100a, 1100b, and 1100c are arranged, an example embodiment of which is not limited thereto. In an example embodiment, the camera module group 1100 can be modified to include only two camera modules. In addition, in an example embodiment, the camera module group 1100 can be modified to include n (where n is a natural number equal to or greater than 4) camera modules. In addition, in an example embodiment, any one or any combination of the plurality of camera modules 1100a, 1100b, and 1100c included in the camera module group 1100 can include the image sensor described in one of the example embodiments with reference to Figures 1 to 1 5.

[0149] In the following description, a detailed configuration of the camera module 1100b will be described in more detail with reference to Figure 17 , and the following description can also be applied to the other camera modules 1100a and 1100c according to an example embodiment.

[0150] Referring to Figure 17 , the camera module 1100b can include a prism 1105, an optical path folding element (OPFE) 1110, an actuator 1130, an image sensing device 1140, and a storage unit 1150.

[0151] The prism 1105 can include a reflection surface 1107 formed of a light-reflecting material, and can change a path of light L incident from the outside.

[0152] In an example embodiment, the prism 1105 can change a path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. In addition, the prism 1105 can rotate the reflection surface 1107 formed of a light-reflecting material in a direction A around a center axis 1106, or can rotate the center axis 1106 in a direction B, so that the path of light L incident in the first direction X can be changed to the vertical second direction, in which case the OPFE 1110 can also move in a third direction Z perpendicular to the first direction X and the second direction Y.

[0153] In an example embodiment, as illustrated in the drawing, the maximum rotation angle of the prism 1105 in the A direction can be equal to or less than 15 degrees in the positive (+) A direction, and can be greater than 15 degrees in the negative (-) A direction. However, example embodiments thereof are not limited thereto.

[0154] In an example embodiment, the prism 1105 can move an angle of about 20 degrees, between 10 degrees and 20 degrees, or between 15 degrees and 20 degrees in the positive (+) or negative (-) B direction. The prism 1105 can move the same angle in the positive (+) or negative (-) direction, or can move similar angles that differ by about one degree.

[0155] In an example embodiment, the prism 1105 can move the reflection surface 1107 of the light reflection material in a third direction (for example, the Z direction) that is parallel to the extension direction of the central axis 1106.

[0156] For example, the OPFE 1110 can include an optical lens group consisting of m (where m is a natural number) optical lenses. The m lenses can move in the second direction Y, and can change the optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom ratio of the camera module 1100b is Z, when the m optical lenses included in the OPFE 1110 move, the optical zoom ratio of the camera module 1100b can become 3Z or 5Z or higher than 5Z.

[0157] The actuator 1130 can move the OPFE 1110 or the optical lens (hereinafter, referred to as an optical lens) to a position. For example, the actuator 1130 can adjust the position of the optical lens so that the image sensor 1142 can be disposed at the focal distance of the optical lens for accurate sensing.

[0158] The image sensing device 1140 can include an image sensor 1142, control logic 1144, and a memory 1146. The image sensor 1142 can sense an image of a sensing target with the light L provided through the optical lens. The control logic 1144 can control the overall operation of the camera module 1100b. For example, the control logic 1144 can control the operation of the camera module 1100b according to a control signal provided through a control signal line CSLb.

[0159] The memory 1146 can store information for operating the camera module 1100b, such as calibration data 1147. The calibration data 1147 can include information about which the camera module 1100b generates image data with light L provided from the outside. For example, the calibration data 1147 can include information about the degree of rotation described above, information about the focal length, information about the optical axis, etc. When the camera module 1100b is implemented as a multi-state camera in which the focal length changes according to the position of the optical lens, the calibration data 1147 can include information about the focal length value and auto-focusing for each position (or each state) of the optical lens.

[0160] The storage unit 1150 can store image data sensed by the image sensor 1142. The storage unit 1150 can be disposed outside the image sensing device 1140, and can be implemented in a form in which a sensor chip is stacked with the image sensing device 1140. In an example embodiment, the storage unit 1150 can be implemented as an electrically erasable programmable read-only memory (EEPROM), but the example embodiment is not limited thereto.

[0161] Referring to Figure 16 and Figure 17 In an example embodiment, each of the plurality of camera modules 1100a, 1100b, and 1100c can include the actuator 1130. Accordingly, each of the plurality of camera modules 1100a, 1100b, and 1100c can include the same or different calibration data 1147 according to the operation of the actuator 1130 included therein.

[0162] In an example embodiment, a camera module (for example, 1100b) among the plurality of camera modules 1100a, 1100b, 1100c can be configured as a camera module having a folded lens shape that can include the prism 1105 and the OPFE 1110 described above, and the other camera modules (for example, 1100a and 1100c) can be configured as vertical type camera modules that do not include the prism 1105 and the OPFE 1110, but the example embodiment is not limited thereto.

[0163] In an example embodiment, for example, a camera module (for example, 1100c) among the plurality of camera modules 1100a, 1100b, and 1100c can be configured as a depth camera having a vertical type that extracts depth information with infrared rays (IR). In this case, the application processor 1200 can merge image data provided from the depth camera with image data provided from another camera module (for example, 1100a or 1100b), and can provide a 3D depth image.

[0164] In an example embodiment, at least two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c can have different fields of view. In this case, for example, optical lenses of at least two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c can be different from each other, but an example embodiment is not limited thereto.

[0165] Further, in an example embodiment, fields of view of the plurality of camera modules 1100a, 1100b, and 1100c can be different. In this case, optical lenses included in the plurality of camera modules 1100a, 1100b, and 1100c can also be different from each other, but an example embodiment is not limited thereto.

[0166] In an example embodiment, the plurality of camera modules 1100a, 1100b, and 1100c can be physically separated from each other. That is, a sensing area of a single image sensor 1142 can not be divided into several areas for the plurality of camera modules 1100a, 1100b, and 1100c, but an image sensor 1142 relied on can be disposed in each of the plurality of camera modules 1100a, 1100b, and 1100c.

[0167] Referring back to Figure 16 The application processor 1200 can include an image processing device 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 can be separated from the plurality of camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the plurality of camera modules 1100a, 1100b, and 1100c can be separated from each other as separate semiconductor chips.

[0168] The image processing device 1210 can include a plurality of sub-image processors 1212a, 1212b, and 1212c, an image generator 1214, and a camera module controller 1216.

[0169] The image processing device 1210 can include a plurality of sub-image processors 1212a, 1212b, and 1212c corresponding to the number of the plurality of camera modules 1100a, 1100b, and 1100c.

[0170] Image data generated from each of the camera modules 1100a, 1100b, and 1100c can be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c through image signal lines ISLa, ISLb, and ISLc, which are separated from each other. For example, image data generated by the camera module 1100a can be provided to the sub-image processor 1212a through the image signal line ISLa, image data generated by the camera module 1100b can be provided to the sub-image processor 1212b through the image signal line ISLb, and image data generated by the camera module 1100c can be provided to the sub-image processor 1212c through the image signal line ISLc. For example, the image data transmission can be performed with a camera serial interface (CSI) based on a mobile industry processor interface (MIPI), but example embodiments are not limited thereto.

[0171] In example embodiments, a single sub-image processor can be arranged to correspond to a plurality of camera modules. For example, the sub-image processor 1212a and the sub-image processor 1212c can not be separated from each other as shown in the drawing, but can be integrated with each other as a single sub-image processor, image data provided from the camera module 1100a and the camera module 1100c can be selected by a selection element (e.g., a multiplexer), and can be provided to the integrated sub-image processor.

[0172] Image data provided to each of the sub-image processors 1212a, 1212b, and 1212c can be provided to the image generator 1214. The image generator 1214 can generate an output image with the image data provided from each of the sub-image processors 1212a, 1212b, and 1212c according to an image generation signal or a mode signal.

[0173] For example, the image generator 1214 can merge at least a part of the image data generated by the camera modules 1100a, 1100b, and 1100c having different fields of view according to the image generation signal or the mode signal, thereby generating an output image. In addition, the image generator 1214 can select one of the image data generated by the camera modules 1100a, 1100b, and 1100c having different fields of view, and can generate an output image.

[0174] In example embodiments, the image generation signal can include a zoom signal or a zoom factor. In addition, in example embodiments, for example, the mode signal can be a signal based on a mode selected by a user.

[0175] When the image generation signal is a zoom signal (zoom factor) and the camera modules 1100a, 1100b, 1100c have different viewing fields, the image generator 1214 can perform different operations according to the type of the zoom signal. For example, when the zoom signal is a first signal, after the image data output by the camera module 1100a is merged with the image data output by the camera module 1100c, an output image can be generated using the merged image signal and the image data output by the camera module 1100b which is not used in the merging. In the case where the zoom signal is a second signal different from the first signal, the image generator 1214 does not perform image data merging, and can generate an output image which selects one of the image data output by the camera modules 1100a, 1100b, 1100c. However, example embodiments thereof are not limited thereto, and the method of processing image data can be changed as necessary.

[0176] In example embodiments, the image generator 1214 can receive a plurality of image data having different exposure times from any one or any combination of the plurality of sub-image processors 1212a, 1212b, and 1212c, and can perform a high dynamic range (HDR) process on the plurality of image data, thereby generating merged image data having an increased dynamic range.

[0177] The camera module controller 1216 can provide a control signal to each of the camera modules 1100a, 1100b, and 1100c. The control signal generated by the camera module controller 1216 can be provided to the corresponding camera modules 1100a, 1100b, and 1100c through the control signal lines CSLa, CSLb, and CSLc which are separated from each other.

[0178] One of the plurality of camera modules 1100a, 1100b, and 1100c (e.g., 1100b) can be designated as a master camera and the other camera modules (e.g., 1100a and 1100c) can be designated as slave cameras according to the image generation signal including the zoom signal or the mode signal. Such information can be included in the control signal and can be provided to the corresponding camera modules 1100a, 1100b, and 1100c through the control signal lines CSLa, CSLb, and CSLc which are separated from each other.

[0179] The camera modules operating as the master camera and the slave camera can be changed according to the zoom factor or the operation mode signal. For example, when the field of view of the camera module 1100a is wider than that of the camera module 1100b and the zoom factor has a low zoom ratio, the camera module 1100b can operate as the master camera and the camera module 1100a can operate as the slave camera. When the zoom factor has a high zoom ratio, the camera module 1100a can operate as the master camera and the camera module 1100b can operate as the slave camera.

[0180] In an example embodiment, the control signal provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c can include a synchronization enable signal. For example, when the camera module 1100b is a master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 can transmit a synchronization enable signal to the camera module 1100b. The camera module 1100b receiving such a synchronization enable signal can generate a synchronization signal based on the provided synchronization enable signal, and can provide the generated synchronization signal to the camera modules 1100a and 1100c through a synchronization signal line SSL. The camera module 1100b as well as the camera modules 1100a and 1100c can synchronize with the synchronization signal, and can transmit image data to the application processor 1200.

[0181] In an example embodiment, the control signal provided by the camera module controller 1216 to the plurality of camera modules 1100a, 1100b, and 1100c can include mode information according to a mode signal. The plurality of camera modules 1100a, 1100b, and 1100c can operate in a first operation mode and a second operation mode with respect to a sensing speed based on the mode information.

[0182] The plurality of camera modules 1100a, 1100b, and 1100c can generate image signals at a first rate (e.g., generate image signals at a first frame rate) in the first operation mode, can encode the image signals at a second rate (e.g., encode image signals at a second frame rate higher than the first frame rate), and can transmit the encoded image signals to the application processor 1200. In this case, the second rate can be 30 times or less of the first rate.

[0183] The application processor 1200 can store the received image signals, the encoded image signals in an internal memory 1230 provided therein or an external memory 1400 external to the application processor 1200, after which the application processor 1200 can read out the encoded image signals from the internal memory 1230 or the external memory 1400, and can display image data generated based on the decoded image signals. For example, corresponding sub-processors among the plurality of sub-image processors 1212a, 1212b, and 1212c of the image processing apparatus 1210 can perform decoding, and can perform image processing on the decoded image signals.

[0184] The plurality of camera modules 1100a, 1100b, and 1100c can generate image signals at a third rate lower than the first rate (e.g., generate image signals at a third frame rate lower than the first frame rate) in the second operation mode, and can transmit the image signals to the application processor 1200. The image signals provided to the application processor 1200 can not have been encoded. The application processor 1200 can perform image processing on the received image signals, or can store the image signals in the internal memory 1230 or the external memory 1400.

[0185] The PMIC 1300 can supply a power (such as a power voltage) to each of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the PMIC 1300 can supply a first power to the camera module 1100a through a power signal line PSLa, can supply a second power to the camera module 1100b through a power signal line PSLb, and can supply a third power to the camera module 1100c through a power signal line PSLc under the control of the application processor 1200.

[0186] The PMIC 1300 can generate a power corresponding to each of the plurality of camera modules 1100a, 1100b, 1100c in response to a power control signal PCON from the application processor 1200, and can also adjust the level of the power. The power control signal PCON can include a power adjustment signal for each operation mode of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the operation mode can include a low power mode, and in this case, the power control signal PCON can include information about the camera module operating in the low power mode and the determined power level. The level of the power supplied to the plurality of camera modules 1100a, 1100b, and 1100c can be the same as or different from each other. In addition, the level of the power can be dynamically changed.

[0187] According to the foregoing example embodiment, the image sensor can obtain information corresponding to the threshold voltage of the input transistor included in the comparator with the replica circuit, and can transmit the information to the slope voltage generator, thereby compensating for the slope voltage input to the comparator. Accordingly, the input range of the comparator can be used regardless of the distribution of the processing result values of the semiconductor chip in which the image sensor is integrated and the temperature. In addition, by lowering the power voltage for the operation of the image sensor, power consumption can be reduced.

[0188] Although the example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes can be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. An image sensor comprising: a pixel array including a plurality of pixels connected to row lines extending in a first direction and column lines extending in a second direction intersecting the first direction; a ramp voltage generator configured to output a ramp voltage; a plurality of comparators, each of the plurality of comparators including: a first input terminal to which the ramp voltage is input; and a second input terminal connected to one of the column lines; and a replica circuit including a structure identical to that of a portion of the plurality of comparators, wherein each of the plurality of comparators includes: a plurality of transistors; a first auto-zero transistor connected to the first input terminal; a second auto-zero transistor connected to the second input terminal; and a wiring connected to the plurality of transistors, the first auto-zero transistor, and the second auto-zero transistor, wherein a gate terminal of the first auto-zero transistor is connected to a first wiring among the wiring, wherein a gate terminal of the second auto-zero transistor is connected to a second wiring different from the first wiring among the wiring, wherein the replica circuit is configured to sense a replica threshold voltage corresponding to a threshold voltage of an input transistor among the plurality of transistors connected to the first input terminal, and wherein the ramp voltage compensated with the sensed replica threshold voltage is input to the first input terminal of the comparator.

2. The image sensor of claim 1, wherein, In an auto-zero operation, the first auto-zero transistor is turned off before the second auto-zero transistor is turned off.

3. The image sensor of claim 1, wherein, The replica threshold voltage is between 50 mV and 700 mV.

4. The image sensor of claim 1, wherein, After the auto-zero operation, an initial value of the ramp voltage is a sum of an auto-zero voltage and the sensed replica threshold voltage.

5. The image sensor of claim 1, wherein, After the auto-zero operation, an initial value of the ramp voltage is a sum of an auto-zero voltage, the sensed replica threshold voltage, and a margin voltage determined based on a distribution of threshold voltages of the input transistor.

6. An image sensor comprising: a pixel array including a plurality of pixels; a plurality of comparators, each of the plurality of comparators including a first input terminal, a second input terminal, a first auto-zero switch connected to the first input terminal, and a second auto-zero switch connected to the second input terminal; a replica circuit including devices identical to at least a portion of devices included in each of the plurality of comparators, and configured to output a sensing signal corresponding to an auto-zero voltage and a common node voltage of each of the plurality of comparators; and a ramp voltage generator configured to compensate a ramp voltage based on the output sensing signal, and output the compensated ramp voltage to the first input terminal of each of the plurality of comparators, wherein the sensing signal corresponds to a threshold voltage of an input transistor connected to the first input terminal of each of the plurality of comparators, and wherein each of the plurality of comparators is configured to generate an output signal by comparing a pixel voltage output from the pixel array and a reset voltage with the output ramp voltage.

7. The image sensor of claim 6, wherein, The replica circuit further includes a selection circuit configured to sequentially output a first sense signal corresponding to the auto-zero voltage and a second sense signal corresponding to the common node voltage. 8.The image sensor of claim 6, further comprising a digital converter configured to generate a control signal for compensating the ramp voltage using the output sense signal, and transmit the generated control signal to the ramp voltage generator.

9. The image sensor of claim 8, wherein, The digital converter includes a single analog-to-digital converter configured to sequentially receive a first sense signal corresponding to the auto-zero voltage and a second sense signal corresponding to the common node voltage from the replica circuit through a timing signal.

10. The image sensor of claim 8, wherein, The digital converter includes two analog-to-digital converters configured to respectively receive a first sense signal corresponding to the auto-zero voltage and a second sense signal corresponding to the common node voltage from the replica circuit.

11. The image sensor of claim 8, wherein, The digital converter includes at least one analog-to-digital converter having a resolution less than a resolution of an analog-to-digital converter used to convert an output signal of the comparator into a digital signal.

12. The image sensor of claim 8, wherein, The digital converter includes a logic circuit configured to determine a compensation level of the ramp voltage based on the threshold voltage and a tolerance voltage for an operation of the image sensor.

13. The image sensor of claim 8, wherein, The replica circuit is further configured to collect the sense signal based on the image sensor initially operating, and transmit the generated control signal to the ramp voltage generator through the digital converter.

14. The image sensor of claim 8, wherein, The replica circuit is further configured to collect the sense signal in every frame or every multiple frames while the image sensor is operating, and transmit the generated control signal to the ramp voltage generator through the digital converter.

15. The image sensor of claim 6, wherein, Each of the plurality of comparators is further configured to perform correlated double sampling to generate the output signal. 16.An image sensor comprising: a pixel array including a plurality of pixels; a ramp voltage generator configured to output a ramp voltage; a plurality of comparators configured to generate an output signal by comparing a reset voltage and a pixel voltage output by the pixel array with the output ramp voltage; and a sense circuit configured to sense a threshold voltage of an input transistor included in the plurality of comparators, and output a control signal for compensating the ramp voltage to the ramp voltage generator, wherein the ramp voltage is compensated based on the output control signal.

17. The image sensor of claim 16, wherein, The sense circuit includes a replica circuit including a replica input transistor corresponding to the input transistor included in the plurality of comparators, and wherein the sense circuit is further configured to sense the threshold voltage by sensing a replica threshold voltage of the replica input transistor.

18. The image sensor of claim 16, wherein, The sense circuit includes a test circuit configured to sense the threshold voltage, and wherein the ramp voltage is compensated using the sensed threshold voltage.

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