Virtual chip and method for virtualizing serial port peripherals in chip

Abstract

The present invention discloses a method for a virtual chip and a serial port peripheral in a virtual chip, wherein the virtual chip includes a virtual CPU and a virtual serial port peripheral, the virtual serial port peripheral includes a virtual control register, a virtual data register and a virtual status register that simulate the control register, data register and status register of the chip serial port peripheral, and the virtual CPU can read and write data to the virtual control register, the virtual data register and the virtual status register. According to the virtual chip of the above technical solution, through the virtual serial port peripheral, in combination with the serial port of a computer, the simulation of the real serial port of the chip is realized, and physical data can be directly used, so that the virtual device and the real object can share the model and application layer tools and software, thereby improving the debugging efficiency and convenience.

Description

Technical Field

[0001] The invention belongs to the technical field of chip virtual simulation, and in particular relates to a method for virtualizing a chip and a serial port peripheral in the virtual chip. Background Art

[0002] The compiler for embedded development integrates debugging functions, but the interface in the debugging environment is low-level, and the data variables observed are all from the machine perspective, and physical data cannot be used directly, which is inconvenient to use. Existing simulation software provides data to high-level language interfaces, and by reading files and other data streams, it is necessary for embedded software to adapt the interface or provide variable addresses. In the former method, the embedded software adds code outside the control task; in the latter method, the address changes when the software is iterated, and the variable address of the new version of the software needs to be queried and updated, which affects the debugging efficiency. Summary of the invention

[0003] Purpose of the invention: The purpose of the present invention is to propose a method for a virtual chip and a serial port peripheral in a virtual chip, which can directly simulate the real serial port communication process through the virtual serial port peripheral, directly use physical data, and realize that virtual devices and physical objects can share models and application layer tools and software, thereby improving debugging efficiency and convenience.

[0004] Another object of the present invention is to propose a method for virtualizing serial port peripherals within a chip, which can realize the virtualization of serial port peripherals within a real chip, increase the authenticity of the embedded target code running in the virtual chip, and the debugged embedded software target code does not need to be modified and can be directly delivered without interface adaptation.

[0005] Technical solution: The virtual chip described in the present invention includes a virtual CPU and a virtual serial port peripheral. The virtual serial port peripheral includes a virtual control register, a virtual data register and a virtual status register that simulate the control register, data register and status register of the chip serial port peripheral. The virtual CPU can read and write data to the virtual control register, the virtual data register and the virtual status register.

[0006] Furthermore, the virtual CPU and the virtual serial port peripheral run in parallel.

[0007] Furthermore, the virtual data register uses a circular queue to store high-speed data.

[0008] Furthermore, the virtual CPU includes an instruction counter, and the instruction counter is used to record the number of instructions executed by the virtual chip.

[0009] Furthermore, the virtual serial port peripheral device includes a data processing clock, and the data processing clock is used to record the data processing time of the virtual serial port peripheral device.

[0010] The method for virtualizing a serial port peripheral in a chip according to the present invention comprises the following steps:

[0011] S1: Read the configuration file to open the computer's serial port and start the corresponding virtual serial port peripheral;

[0012] S2: Check the values ​​of the virtual control register and the virtual status register of the virtual serial port peripheral to determine whether to update the virtual CPU system time or the data processing clock of the virtual serial port peripheral;

[0013] S3: Detect whether the increment of the instruction controller reaches the instruction number corresponding to the data processing clock. If so, perform the data processing task of the virtual serial port peripheral.

[0014] S4: Determine whether there is an interrupt request and jump to the corresponding service program according to the interrupt request.

[0015] Further, the S2 step includes:

[0016] S2.1: Check the control register value of the virtual serial port peripheral. When the control register value changes, according to the bit field definition, simulate the function of setting the baud rate, parity, data bit and stop bit of the computer serial port, calculate the time required to receive a byte according to the baud rate, and update the value of the data processing clock.

[0017] Furthermore, the S3 step further includes:

[0018] S3.1: Check whether the value of the virtual data register has changed. If it has changed and the virtual control register enables serial port transmission, and the computer serial port is open, the data written into the virtual data register will be sent directly through the computer serial port;

[0019] S3.2: If the virtual control register enables serial port reception and the computer serial port is open, a byte is popped out from the receive data ring queue and set to the virtual data register, and the receive flag bit of the virtual status register is set to 1; at the same time, if the receive interrupt is enabled in the virtual control register, a receive interrupt request is sent to the virtual CPU.

[0020] Furthermore, the S3 step further includes:

[0021] S3.3: Check the value of the virtual status register, and clear the flag or interrupt status according to the value before and after the virtual status register changes.

[0022] Beneficial effects: Compared with the prior art, the present invention has the following advantages: it has a virtual serial port peripheral that runs consistently with the serial port peripheral in a real chip, can directly use physical data, and the debugged embedded software target code can remain consistent with that at the time of delivery, without the need for interface adaptation. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a principle block diagram of a virtual chip according to an embodiment of the present invention;

[0024] Figure 2 The present invention is a flowchart of a method for virtualizing a serial port peripheral device within a chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0026] Reference Figure 1 According to an embodiment of the present invention, a virtual chip includes a CPU and a virtual serial port peripheral. The virtual serial port peripheral includes a virtual control register, a virtual data register and a virtual status register that simulate the control register, data register and status register of the chip serial port peripheral, and the virtual CPU can read and write data to the virtual control register, the virtual data register and the virtual status register. The virtual control register contains various control setting bits of the control register of the real serial port peripheral, such as the setting bits of the serial port communication parameters, the information of the serial port communication parameters, and the receiving or sending interrupt enable and the data receiving or sending enable bit. The virtual data register is used to temporarily store the data received or to be sent, and the virtual status register includes various status indication bits of the status register of the real serial port peripheral, such as data receiving or sending, interrupt flag bit, etc. The virtual CPU simulates the sending and receiving of external data by synchronizing with the data in the virtual data register, and can obtain the status of the virtual serial port peripheral and configure the working parameters of the virtual serial port by accessing and setting the virtual control register and the virtual status register.

[0027] According to the virtual chip of the above technical solution, the virtual serial port peripheral simulates the real serial port as a bridge between the virtual CPU and the computer, simulating the serial port communication between the real chip and the peripheral. The embedded target code that needs to be debugged is run in the above virtual chip, and the embedded software can read, write or send and receive data through the virtual serial port peripheral and the interface layer software or the computer physical serial port. Compared with the traditional additional writing of control code to write the data stream directly to the variable address of the embedded software, this technical solution can provide an environment closer to the real hardware for the debugging of embedded software, and has good portability. At the same time, since the virtual serial port peripheral works in the same way as the real chip serial port peripheral, there is no need to write additional debugging code. The debugged target code can be directly used for the real object and can be delivered directly after debugging. At the same time, fault injection can also be tested to verify the serial port peripheral faults in the chip such as occasional parity errors, interrupt blocking and electromagnetic interference.

[0028] In this embodiment, the virtual serial port peripheral runs in parallel with the virtual CPU. The virtual serial port peripheral can be regarded as a component of the virtual chip, and the number of serial ports of the virtual chip can be set by the load quantity. At the same time, in order to solve the problem that the virtual CPU is slower than the real chip, the virtual data register of the virtual serial port peripheral stores high-speed data through a circular queue in the data processing task, and the circular queue serves as a buffer for high-speed data. The virtual CPU also includes an instruction counter, which is used to record the number of instructions run by the virtual chip, and the virtual serial port peripheral also includes a data processing clock, which is used to record the data processing time of the virtual serial port peripheral.

[0029] Reference Figure 2 In this embodiment, the virtual chip can debug the embedded target code by using the following method:

[0030] S1: Read the configuration file to open the computer's serial port and start the corresponding virtual serial port peripheral;

[0031] S2: Check the values ​​of the virtual control register and the virtual status register of the virtual serial port peripheral to determine whether to update the virtual CPU system time or the data processing clock of the virtual serial port peripheral;

[0032] S3: Detect whether the increment of the instruction controller reaches the instruction number corresponding to the data processing clock. If so, perform the data processing task of the virtual serial port peripheral.

[0033] S4: Determine whether there is an interrupt request and jump to the corresponding service program according to the interrupt request.

[0034] The configuration file in step S1 may be the channel number of the computer serial port corresponding to the virtual serial port peripheral. When simulating the operation of the serial port peripheral, the baud rate setting, data receiving and sending functions are simulated by operating the computer serial port.

[0035] In step S2, when the value of the virtual control register ESCIx_CRn changes, the baud rate, parity check, data bit and stop bit of the corresponding computer serial port are set according to the bit threshold definition of the virtual control register ESCIx_CRn. The time required to receive one byte is calculated according to the baud rate and stored in the data processing clock.

[0036] For example, register regs.ESCIa_CR1.bit.PE, this bit indicates whether there is parity check, and the parity check of the corresponding computer serial port is set according to this value.

[0037] In specific implementation, when calculating the baud rate, the tolerance range is allowed to use the standard baud rate to open the computer serial port. If the calculated baud rate is within the range of [115200*0.95, 115200*1.05], the baud rate of 115200bps is used.

[0038] In the specific implementation, the time required to receive one byte is calculated according to the baud rate. In order to simulate the serial port receiving data, a data processing task of the serial port peripheral in the virtual chip is set, and the interval time is the time to receive one byte. If the serial port is set to "115200bps, n, 8, 1", it takes 86.81us to receive one byte. Then according to the chip system clock such as 100MHz, the timing is calculated to be equivalent to executing 8681 instructions. Therefore, it is set to receive 1 byte of data from the circular queue every time 8681 instructions are run. This is a buffering measure designed to solve the speed mismatch. The external interface has high real-time performance and fast response time; while the virtual CPU runs slower than the actual time. Therefore, when the actual external entity serial port data is received, it is first stored in the buffer. The virtual CPU reads a data from the buffer according to the number of instructions executed.

[0039] When the value of the virtual data register ESCIx_DR changes, it means that there is data to be sent. At this time, if the chip serial port sending of the virtual control register ESCIx_CRn is enabled and the corresponding computer serial port is open, the value written to the virtual data register ESCIx_DR will be sent through the corresponding computer serial port to the external device or looped back to another serial port of another computer and passed to the interface layer software.

[0040] When the chip serial port reception of the virtual control register ESCIx_CRn is enabled, it means that there is data to be received, and the computer serial port is open, then a byte is popped out from the receive data ring queue, set to the virtual data register ESCIx_DR, and the receive flag of the virtual status register ESCIx_SR is set to 1. If the receive interrupt is enabled in the virtual control register ESCIx_CRn at this time, a receive interrupt request is sent to the virtual CPU, and the virtual CPU executes the receive interrupt task to synchronize the data in the virtual data register ESCIx_DR to the corresponding address of the embedded target code. In practice, if no byte is popped out of the data ring queue, it jumps out directly. The size of the ring queue needs to take into account the margin, which is generally set to 4 times the maximum receive length. The cycle of the external data and the ratio of the virtual CPU speed to the real time need to be proportionally enlarged to reduce the matching error.

[0041] After executing the data processing task, check the value of the virtual status register ESCIx_SR and clear the flag or interrupt status that needs to be cleared.

Claims

1. A method for virtualizing serial port peripherals in a chip, It is characterized in that The virtual chip includes a virtual CPU and a virtual serial port peripheral, wherein the virtual serial port peripheral includes a virtual control register, a virtual data register and a virtual status register which simulate the control register, data register and status register of the chip serial port peripheral, and the virtual CPU reads and writes data to the virtual control register, the virtual data register and the virtual status register; the embedded target code to be debugged runs on the virtual chip; the virtual data register uses a circular queue to store high-speed data; the method of the serial port peripheral in the virtual chip includes the following steps: S1: Read the configuration file to open the computer's serial port and start the corresponding virtual serial port peripheral; S2: Check the values ​​of the virtual control register and the virtual status register of the virtual serial port peripheral to determine whether to update the virtual CPU system time or the data processing clock of the virtual serial port peripheral; S3: Detect whether the increment of the instruction controller reaches the instruction number corresponding to the data processing clock. If so, perform the data processing task of the virtual serial port peripheral. S4: Determine whether there is an interrupt request, and jump to the corresponding service program according to the interrupt request; The S2 step includes: S2.1: Check the control register value of the virtual serial port peripheral. When the control register value changes, according to the bit field definition, simulate the function of setting the baud rate, parity, data bit and stop bit of the computer serial port, calculate the time required to receive a byte according to the baud rate, and update the value of the data processing clock; The S3 step further includes: S3.1: Check whether the value of the virtual data register has changed. If it has changed and the virtual control register enables serial port transmission, and the computer serial port is open, the data written into the virtual data register will be sent directly through the computer serial port; S3.2: If the virtual control register enables serial port reception and the computer serial port is open, a byte is popped out from the receive data ring queue and set to the virtual data register, and the receive flag bit of the virtual status register is set to 1; at the same time, if the receive interrupt is enabled in the virtual control register, a receive interrupt request is sent to the virtual CPU; S3.3: Check the value of the virtual status register, and clear the flag or interrupt status according to the value before and after the virtual status register changes.

2. The method for virtualizing serial port peripherals in a chip according to claim 1, It is characterized in that The virtual CPU and the virtual serial port peripheral run in parallel.

3. The method for virtualizing serial port peripherals in a chip according to claim 1, It is characterized in that The virtual CPU includes an instruction counter, and the instruction counter is used to record the number of instructions executed by the virtual chip.

4. The method for virtualizing serial port peripherals in a chip according to claim 1, It is characterized in that The virtual serial port peripheral comprises a data processing clock, and the data processing clock is used to record the data processing time of the virtual serial port peripheral.

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