A page buffer, a storage device and an operating method thereof, and a memory system

Abstract

The embodiments of the present disclosure disclose a page buffer, a storage device and an operating method thereof and a memory system, the page buffer comprising: a first latch for storing program verification information, a second latch for storing first bit line forcing information and a dynamic latch for storing second bit line forcing information; wherein the first bit line forcing information is different from the second bit line forcing information; wherein the dynamic latch comprises a control switch electrically connected with the second latch, and is configured to latch information through a parasitic capacitor electrically connected with the control switch.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a page buffer, a storage device and an operating method thereof, and a memory system. BACKGROUND

[0002] Semiconductor memories can be roughly divided into two categories depending on whether they retain stored data when power is off; the two categories of semiconductor memories are: volatile memories, which lose stored data when power is off, and non-volatile memories, which retain stored data when power is off. Non-volatile memories have a good random access time characteristic because storage cells are respectively connected to bit lines and word lines. Non-volatile memories can include a plurality of storage cells connected in series on a bit line, and each storage cell string can be arranged with only one contact, thus having a good integration characteristic.

[0003] As the integration of memories is improved, the area of the region occupied by the page buffer is limited in the peripheral circuit of the memory and there is a demand for its area to be reduced, thus the number of elements constituting the page buffer also needs to be streamlined. SUMMARY

[0004] In view of the above, the embodiments of the present disclosure provide a page buffer, a storage device and an operating method thereof, and a memory system to solve at least one problem in the prior art.

[0005] To achieve the above object, the technical solutions of the embodiments of the present disclosure are as follows:

[0006] In a first aspect, the embodiments of the present disclosure provide a page buffer, comprising: a first latch for storing program verification information, a second latch for storing first bit line force information, and a dynamic latch for storing second force information; wherein the first bit line force information and the second bit line force information are different.

[0007] The dynamic latch comprises a control switch electrically connected to the second latch, and is configured to latch information through a parasitic capacitor electrically connected to the control switch.

[0008] In an optional implementation, the second latch is electrically connected to a first end of the control switch, and in the case where the control switch is controlled to be open, the information stored in the second latch is transmitted to a second end of the control switch and stored through the parasitic capacitor electrically connected to the second end.

[0009] In an alternative embodiment, during the first sensing operation based on the first forced sensing voltage, the second latch is configured to store information for distinguishing, among the storage units that fail the program verify, the storage units to be subjected to the first bit line forcing operation based on the first forced sensing voltage, as first bit line forcing information.

[0010] In an alternative embodiment, before the second sensing operation based on the second forced sensing voltage, the dynamic latch is configured to open the control switch so that the current first bit line forcing information from the second latch is latched through the parasitic capacitor.

[0011] In an alternative embodiment, during the second sensing operation based on the second forced sensing voltage, the second latch is configured to store information for distinguishing, among the storage units that fail the program verify, the storage units to be subjected to the second bit line forcing operation based on the second forced sensing voltage, as second bit line forcing information.

[0012] In an alternative embodiment, after the third sensing operation based on the program verify voltage, the dynamic latch is configured to output the first bit line forcing information stored by the parasitic capacitor to a sensing node of the page buffer, and latch the second bit line forcing information from the second latch when the control switch is open; the second latch is configured to store the first bit line forcing information at the sensing node.

[0013] In an alternative embodiment, the first forced sensing voltage is lower than the second forced sensing voltage.

[0014] In an alternative embodiment, the second forced sensing voltage is lower than the program verify voltage.

[0015] In an alternative embodiment, further comprising: a first pre-charge circuit for generating the first forced programming voltage; the first pre-charge circuit is electrically connected to the bit line through a sensing node of the page buffer;

[0016] The page buffer is configured to apply, through the first pre-charge circuit, the first forced programming voltage higher than the normal programming bit line voltage and lower than the inhibit programming bit line voltage to the bit line corresponding to the storage unit to be subjected to the first bit line forcing operation.

[0017] In an alternative embodiment, further comprising: a second pre-charge circuit for generating the second forced programming voltage, the second pre-charge circuit is electrically connected to the bit line through the sensing node, and the second pre-charge circuit is electrically connected to the dynamic latch and can be controlled by the information stored by the dynamic latch;

[0018] The page buffer is configured to apply a second forced programming voltage, which is higher than the first forced programming voltage and lower than the disabled programming bit line voltage, to the bit line corresponding to the memory cell to which the second bit line forced operation is to be performed, through the second precharge circuit.

[0019] In one alternative implementation, the second precharge circuit includes a first PMOS transistor and a second PMOS transistor connected in series between the power supply voltage and the sensing node, wherein the gate of the first PMOS transistor is electrically connected to the dynamic register, and the second PMOS transistor is controlled by a second bit line forced operation enable signal.

[0020] In one alternative implementation, the control switch includes a single-transistor control switch or a dual-transistor control switch.

[0021] In one alternative implementation, the control switch is a MOS transistor-based transmission gate.

[0022] In one alternative implementation, the second terminal of the control switch is coupled to the sensing node of the page buffer via a circuit node to which it is electrically connected.

[0023] The sensing node is also coupled to the first latch.

[0024] Secondly, embodiments of this disclosure provide a storage device, including: a storage cell array having a plurality of storage cell strings and a plurality of bit lines connected to the plurality of storage cell strings; and peripheral circuitry coupled to the storage cell array via the bit lines and used to operate the storage cell array.

[0025] The peripheral circuit includes multiple page buffers as described in any of the first aspects.

[0026] The page buffer is connected to the corresponding bit line via a sensing node, and is connected to the memory cell string via the bit line.

[0027] In one alternative implementation, the peripheral circuitry is configured to apply a normal programming bit line voltage to a normal programming cell based on programming verification information, a first bit line forced information, and a second bit line forced information, and to apply a programmable prohibition bit line voltage to a memory cell to be prohibited, apply a first forced programming voltage having a higher voltage than the normal programming bit line voltage and a lower voltage than the programmable prohibition bit line voltage to a memory cell to which a first bit line forced operation will be performed, and apply a second forced programming voltage having a higher voltage than the first forced programming voltage and a lower voltage than the programmable prohibition bit line voltage to a memory cell to which a second bit line forced operation will be performed.

[0028] In one alternative implementation, the storage device includes a three-dimensional NAND flash memory.

[0029] In a third aspect, the embodiments of the present disclosure provide a programming operation method of a storage device, the method comprising:

[0030] performing a first sensing operation based on a first forced sensing voltage;

[0031] storing a first sensing operation result to a second latch;

[0032] swapping information stored by the second latch and a dynamic latch;

[0033] performing a second sensing operation based on a second forced sensing voltage different from the first forced sensing voltage;

[0034] storing a second sensing operation result to the second latch;

[0035] performing a third sensing operation based on a verify voltage;

[0036] storing a third sensing operation result to the first latch;

[0037] swapping information stored by the second latch and the dynamic latch.

[0038] In a fourth aspect, the embodiments of the present disclosure provide a memory system, comprising:

[0039] one or more storage devices as in any of the second aspects; and

[0040] a controller coupled to the storage devices and configured to control the storage devices.

[0041] In the technical solutions provided by the present disclosure, a page buffer is provided, which includes a first latch for storing programming verification information, a second latch for storing first bit line forced information, and a dynamic latch for storing second bit line forced information, the dynamic latch including a control switch electrically connected to the second latch, and being configured to latch information through a parasitic capacitor electrically connected to the control switch. In the present disclosure, the dynamic latch is formed by setting the control switch at the output node of the second latch, which borrows the original parasitic capacitor of the circuit node coupled to the control switch to latch information. In this way, in the embodiments of the present disclosure, the increase of the new latch is realized only by introducing the control switch, thereby being able to reduce the number of elements (such as transistors) constituting the page buffer to a certain extent. BRIEF DESCRIPTION OF DRAWINGS

[0042] In the drawings, like reference numerals refer to like elements throughout the various drawings. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating principles of the application. It should be understood that the drawings are merely for purposes of illustration and are not to be construed as limiting the application.

[0043] Figure 1 A schematic diagram of a memory device according to an embodiment of the present disclosure;

[0044] Figure 2 A circuit diagram of a page buffer according to an embodiment of the present disclosure;

[0045] Figure 3 A threshold voltage distribution diagram of a memory cell according to an embodiment of the present disclosure;

[0046] Figure 4 A flowchart of a program verify operation of a memory device according to an embodiment of the present disclosure;

[0047] Figure 5 A flowchart of a bit line force operation of a memory device according to an embodiment of the present disclosure;

[0048] Figure 6 A block diagram of a memory system according to an exemplary embodiment of the present disclosure;

[0049] Figure 7A A schematic diagram of a memory card according to an exemplary embodiment of the present disclosure;

[0050] Figure 7B A schematic diagram of a solid state drive (SSD) according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] Example embodiments of the present application will be described herein below with reference to the accompanying drawings. While example embodiments of the present application are illustrated, it should be understood that the present application can be embodied in many forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will convey the scope of the application to those skilled in the art.

[0052] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the application. However, it will be apparent to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the application. As used herein, the term "exemplary" means "an example of."

[0053] Furthermore, the accompanying drawings are included to provide a thorough understanding of embodiments of the application and are not intended to be in any way limiting. Like reference numerals in the drawings represent the same or similar elements and features.

[0054] The flow diagrams shown in the various figures, which consist of blocks representing steps carried out in the method, are merely illustrative representations of methods. The order of the steps can be changed, some steps can be left out, other steps can be added, and some steps can be performed concurrently without departing from the scope of the present disclosure. For state diagrams, an event can be any occurrence observed in the system and is often caused by one or more of the elements in the system.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0056] Figure 1 A schematic diagram of a memory device is provided for an embodiment of the present disclosure. Referring to Figure 1 , the memory device (Memory Device) can include a page buffer circuit 110, a memory cell array 120, a row decoder 130, and control logic 140, which can be implemented in a peripheral circuit of the memory device. Although the memory device 10 is shown as a flash memory device such as a vertical NAND flash memory as an example, it is understood that the example schemes or techniques of the present disclosure are not limited to application in flash memory devices, and can be applied to other types of non-volatile memory that require different bit line voltages to be applied differentially to different program cells when programming, such as read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), and the like.

[0057] The page buffer circuit 110 can function as a write driver or as a sense amplifier depending on the operation mode. During a program operation, the page buffer circuit 110 can transmit a bit line voltage corresponding to a storage unit (may also be referred to simply as a "program unit") to be programmed to a bit line of the storage unit array 120. During a read operation, the page buffer circuit 110 can sense data stored in a selected storage unit through a bit line. The page buffer circuit 110 can latch the sensed data and output the latched data externally.

[0058] The storage units in the storage unit array 120 can be formed by a plurality of, for example, NAND storage units arranged in rows and columns, with each row of storage units connected to a corresponding word line and each column of storage units connected to a corresponding bit line. The storage unit array 120 can be connected to the row decoder 130 via the word lines WL0 to WLn-1, the cell string select line SSL, and the ground select line GSL. During a program operation, the control logic 140 can control the voltage biased on the word lines WL, for example, a program voltage Vpgm biased on a selected word line, so as to program the storage units on the selected word line to a certain data state. The storage unit array 120 can be connected to the page buffer circuit 110 via the bit lines BL0 to BLm-1. The storage unit array 120 can include a plurality of memory cell strings. Each memory cell string can be connected to a bit line via a cell string select transistor SST. The storage unit array 120 can be formed by a storage plane including a plurality of storage blocks, the plurality of storage blocks can include a plurality of storage pages, and the plurality of storage pages can include a plurality of storage cells.

[0059] The row decoder 130 can select any one of the storage blocks in the storage unit array 120 in response to an address ADDR. The row decoder 130 can select any one of the word lines of the selected storage block. The row decoder 130 can transmit a word line voltage to the selected word line of the selected storage block.

[0060] The control logic 140 can receive a program command CMD and can output various control signals for controlling the page buffer circuit 110 and the row decoder 130 to perform a program operation in response to the program command CMD. The control logic 140 can be implemented by a controller / processing core in a peripheral circuit and a corresponding firmware program.

[0061] Figure 2 A partial circuit diagram of a page buffer is provided for an embodiment of the present disclosure. The page buffer circuit 110 can include one or more page buffers, for example, one page buffer is provided for one bit line. Referring to Figure 2Each page buffer may include a first latch 111, a second latch 112, and a dynamic latch 113. The information latched by the first latch 111, the second latch 112, and the dynamic latch 113 may include the information required by the memory cell on the corresponding bit line during the programming operation.

[0062] In this embodiment of the disclosure, taking the ISPP (Incremental Step-Pulse Programming) programming scheme of a 3D NAND flash memory storage device as an example, in different programming stages of an ISPP programming process, in order to optimize the threshold voltage distribution and make the thresholds of the programming units more concentrated in the threshold voltage region of the corresponding data state, different bit line voltages are biased on the bit lines of programming units of different bit lines, that is, bit line forcing operation is realized. In this way, even if the programming voltage Vpgm of the gate (applied through the word line) of the programming units of different bit lines is the same, the programming effect will be different. The threshold voltage difference of the programming units with large current threshold voltage differences will be reduced after programming and will be relatively closer to the threshold voltage region of the corresponding data state. The first latch 111 can store information about the third sensing operation, and the second latch 112 and the dynamic latch 113 can store information about the bit line forcing operation. The bit line forcing operation information corresponds to the different bit line voltages that need to be applied to the corresponding bit lines during the programming process, controlled by the programming command CMD. In this embodiment of the disclosure, four different bit line voltages can be latched during the programming process by using the second latch 112 and the dynamic latch 113. (The following will refer to...) Figure 2 The following describes its detailed specifications.

[0063] It should be noted that each page buffer may also include a data latch ( Figure 2 (Not shown in the image). Data latches are used to cache data that will be programmed and written to the memory cell array. When the memory cell is a TLC memory cell, it can store 3 bits of data: Low Page (LP) data, Middle Page (MP) data, and Up Page (UP) data. Correspondingly, the data latches can include three data latches: LP lower page latch, MP middle page latch, and UP upper page latch. When the memory cell is a QLC memory cell, it can store 4 bits of data: Lower Page (LP) data, Middle Page (MP) data, Up Page (UP) data, and Extra Page (XP) data. Correspondingly, the data latches can include four data latches: LP lower page latch, MP middle page latch, UP upper page latch, and XP extra page latch.

[0064] The first latch 111 can store information about the third sensing operation during the program operation. In more detail, the first latch 111 can latch information for distinguishing the storage cells to be subjected to the inhibit operation among the storage cells based on the program verify voltage, i.e., distinguishing information for distinguishing the storage cells to be programmed and the storage cells to be inhibited from each other. During the third sensing operation, the page buffer 110 can apply different bit line voltages to the storage cells to be programmed and the storage cells to be inhibited by using the program / inhibit distinguishing information applied to the sensing node SO by the first latch 111. It is noted that the program verify information stored in the first latch is information obtained based on the program verify voltage Vvfy.

[0065] The second latch 112 can store information about the first bit line forcing operation during the program operation. In more detail, the second latch 112 can store information for distinguishing the storage cells to be subjected to the first bit line forcing operation among the storage cells that fail the program verify, i.e., distinguishing information for distinguishing the storage cells to be subjected to the first bit line forcing operation and the storage cells not to be subjected to the first bit line forcing operation from each other. During the first bit line forcing operation, the page buffer can apply the first forced program voltage to the storage cells to be subjected to the first bit line forcing operation by using the first bit line forcing information stored in the second latch 112. Here, the storage cells that fail the program verify are the storage cells to be programmed.

[0066] The dynamic latch 113 includes a control switch 114 electrically connected to the second latch 112, and is configured to store information about the second bit line forcing operation during the program operation by latching the information through the parasitic capacitance electrically connected to the control switch 114. In more detail, the dynamic latch 113 can include distinguishing information for distinguishing the storage cells to be subjected to the second bit line forcing operation and the storage cells not to be subjected to the second bit line forcing operation from each other. During the second bit line forcing operation, the page buffer can apply the second forced program voltage to the storage cells to be subjected to the second bit line forcing operation by using the second bit line forcing information stored in the dynamic latch 113. In the embodiment of the disclosure, the dynamic latch 113 can directly apply the second bit line forcing information to the sensing node SO, wherein the dynamic latch 113 is configured to latch the information from the second latch 112 through the parasitic capacitance when the control switch 114 is turned on. Thus, the second bit line forcing information can be obtained from the dynamic latch 113 when the page buffer performs the second bit line forcing operation during the program operation of the storage cells.

[0067] The second latch 112 is electrically connected with a first end of the control switch 114, and in a case where the control switch 114 is controlled to be open, the information stored in the second latch 112 is transmitted to a second end of the control switch 114 and stored through the parasitic capacitance electrically connected with the second end.

[0068] Here, the second end of the control switch 114 is coupled to a sensing node SO of the page buffer through a circuit node electrically connected therewith; and the sensing node SO is also coupled to the first latch 111.

[0069] Here, the first bit line forced information and the second bit line forced information are different. Specifically, the first bit line forced information and the second bit line forced information are bit line voltage information corresponding to different bit line forced operations, respectively.

[0070] In the embodiment of the present disclosure, the dynamic latch is formed by setting the control switch 114 at the output node of the second latch 112, and the dynamic latch borrows the original parasitic capacitance of the circuit node coupled with the control switch 114 to latch information. Thus, in the embodiment of the present disclosure, the increase of the new latch can be realized only by introducing the control switch, and compared with the first latch 111 or the second latch 112, the structure is simple, thereby being able to reduce the number of elements (such as transistors) constituting the page buffer to a certain extent.

[0071] In addition, in the embodiment of the present disclosure, the programming mode that two kinds of bit line forced operations are adopted for different programming units in a programming process can be realized. Thus, the programming units can be prevented from being over-programmed, thereby reducing the width of the threshold voltage distribution of the plurality of storage units and improving the accuracy of the programming operation.

[0072] In some embodiments, the control switch 114 can be realized by various controllable switch elements, such as MOS transistors. Specifically, the control switch 114 is realized by a single-transistor control switch or a double-transistor control switch, for example, the control switch 114 can be a transmission gate of a single-MOS transistor structure or a transmission gate of a double-MOS transistor structure. It should be noted that the control switch is taken as a single-transistor control switch in the embodiment of the present disclosure for illustration. Here, the single-transistor control switch is composed of one NMOS transistor, which can be turned on or turned off in response to a switch control signal PASS L. In actual application, in order to better control the dynamic latch, a double-transistor control switch can be selected as the control switch. The double-transistor control switch is a control switch formed by a PMOS transistor and an NMOS transistor in parallel, for example, a CMOS transmission gate.

[0073] Continuing as Figure 2As shown, the first end of the control switch 114 is electrically connected to the second latch 112, for example, can be electrically connected to the output node of the second latch 112, and the second end of the control switch 114 is electrically connected to a corresponding node, for example, is electrically connected to the MOS transistor N6, and the node corresponding to the specific circuit structure is not limited, but it will be understood that one or more semiconductor elements (for example, MOS transistor) corresponding to the node will form a corresponding parasitic capacitance. When the control switch 114 is controlled to be in an on or off state, the parasitic capacitance is borrowed to store information, thereby realizing the dynamic latch function.

[0074] Figure 3 The threshold voltage distribution diagram of the storage unit provided by an embodiment of the present disclosure. Referring to Figure 2 and Figure 3 , the first latch 111 can store the first latch information DS corresponding to the sensing obtained by the program verification voltage Vvfy. In an example embodiment of the present disclosure, the storage unit with a threshold voltage greater than the program verification voltage Vvfy can be an inhibiting cell, and the first latch 111 can store "1" as the first latch information DS. In addition, the storage unit with a threshold voltage level less than the program verification voltage Vvfy can be a program cell (PGM Cell), and the first latch 111 can store "0" as the first latch information DS. That is, if a bit line, here, the first latch information DS can be the program verification information.

[0075] The second latch 112 can include second latch information DL corresponding to the first forcing sensing voltage Vfc1 as bit line forcing information for the first bit line forcing operation. The first forcing sensing voltage Vfc1 can be less than the program verify voltage Vvfy. In example embodiments of the present disclosure, a storage unit having a threshold voltage greater than the first forcing sensing voltage Vfc1 and less than the program verify voltage Vvfy can be a storage unit to be subjected to a bit line forcing operation in a subsequent programming process, referred to herein as a first forcing cell. It is noted that the bit line forcing operation in the present embodiments includes a first bit line forcing operation and a second bit line forcing operation. A storage unit having a threshold voltage greater than the first forcing sensing voltage Vfc1 and less than the second forcing sensing voltage Vfc2 can be a storage unit to be subjected to the first bit line forcing operation. The first forcing cell minus the second forcing cell is a storage unit to be subjected to the first bit line forcing operation. In other words, the first forcing cell includes a storage unit to be subjected to the first bit line forcing operation and a storage unit to be subjected to the second bit line forcing operation. When the threshold voltage of the program cell is greater than the first forcing sensing voltage Vfc1, the second latch 112 can store "1" as the second latch information DL. In addition, a storage unit having a threshold voltage less than the first forcing sensing voltage Vfc1 is not a first forcing cell but a normal program cell subjected to a normal programming operation, and the second latch 112 can store "0" as the second latch information DL. Here, the second latch information DL can be first bit line forcing information, and when the first forcing information stored in DM is "0", it indicates that the program cell of the corresponding bit line will not be subjected to the first bit line forcing operation. It is noted that the normal program cell is a storage unit in the program cell that is not subjected to a bit line forcing operation, and thus, in some embodiments, the normal program cell can also be referred to as a program cell that will not be subjected to a forcing operation.

[0076] The dynamic latch 113 can include third latch information DM corresponding to a second forced sensing voltage Vfc2 as bit line forced information for a second bit line forced operation. The second forced sensing voltage Vfc2 can be less than the program verify voltage Vvfy and greater than the first forced sensing voltage Vfc1. In an example embodiment of the present disclosure, a storage unit having a threshold voltage greater than the second forced sensing voltage Vfc2 and less than the program verify voltage Vvfy can be a storage unit to be subjected to a second bit line forced operation, referred to herein as a second forced cell. When the threshold voltage is greater than the second forced sensing voltage Vfc2, the dynamic latch 113 can store "1" as the third latch information DM. In addition, a storage unit having a threshold voltage less than the second forced sensing voltage Vfc2 is not a second forced cell, but is a normal program cell subjected to a normal program operation and a storage unit subjected to a first bit line forced operation, the dynamic latch 113 can store "0" as the third latch information DM. Here, the third latch information DM can be second bit line forced information, and in a case where the second forced information stored by DM is "0", it indicates that the program cell of the corresponding bit line will not be subjected to a second bit line forced operation.

[0077] In a program operation in which a same program voltage Vpgm is applied to storage cells of a certain selected row, the page buffer can use the first latch information DS, the second latch information DL, and the third latch information DM to apply a corresponding bit line voltage to a corresponding storage cell, so that the storage cells can be subjected to bit line forced operations in a differentiated manner. In other words, in an embodiment of the present disclosure, different storage cells are subjected to classification program control, and the storage cells can be classified into a normal program cell, a storage cell to be subjected to a first bit line forced operation, a storage cell to be subjected to a second bit line forced operation, and a forbidden cell, and the four types of storage cells are subjected to classification program control using different bit line voltages.

[0078] In an embodiment of the present disclosure, the page buffer further includes a first precharge circuit 116 for generating a first forced program voltage, and the first precharge circuit 116 is electrically connected to a bit line through a sensing node SO. The page buffer is configured to apply, through the first precharge circuit 116, a first forced program voltage higher than a normal program bit line voltage and lower than a forbidden program bit line voltage to a bit line corresponding to a storage cell to be subjected to a first bit line forced operation. It should be noted that the first precharge circuit 116 is also configured to apply a forbidden program bit line voltage to a bit line corresponding to a storage cell to be forbidden (a forbidden cell).

[0079] In the embodiments of the present disclosure, the page buffer further comprises a second pre-charge circuit 115 for generating a second forced programming voltage; the second pre-charge circuit 115 is connected to the bit line through a sensing node, and is electrically connected to the dynamic latch and can be controlled by the information stored in the dynamic latch; the page buffer is configured to apply, through the second pre-charge circuit 115, a second forced programming voltage higher than the first forced programming voltage and lower than the forbidden programming bit line voltage to the bit line corresponding to the storage unit to be subjected to the second bit line forcing operation.

[0080] In the embodiments of the present disclosure, the second pre-charge circuit 115 comprises two PMOS transistors connected in series between a power supply voltage and the sensing node. Referring to Figure 2 , the second pre-charge circuit 115 comprises a first PMOS transistor P1 and a second PMOS transistor P2, the first PMOS transistor P1 can be turned on or turned off in response to the dynamic latch signal DM_B, and the second PMOS transistor P2 can be turned on or turned off in response to the second forced information EN_4BL_B. It should be noted that the first PMOS transistor P1 is connected to the second end of the control switch 114 through a wire (not shown in the figure), so that the dynamic latch signal DM_B is a signal controlled by the information stored in the dynamic latch 113.

[0081] The page buffer can perform the programming operation including the first bit line forcing operation and the second bit line forcing operation using a three-step sensing method. In the programming operation, in addition to using two kinds of bit line voltages of the forbidden programming bit line voltage Vinh (such as Vdd) and the normal programming bit line voltage Vprog (such as the ground voltage Vgnd), if only one kind of forced programming voltage (which is greater than the normal programming bit line voltage Vprog and less than the forbidden programming bit line voltage Vinh) is added to perform the programming operation on a plurality of programming units, although the programming operation with a certain degree of programming degree distinction can be achieved, the threshold voltage distribution of the plurality of programming units after being programmed can still not be narrow enough. Therefore, in the programming operation of the embodiments of the present disclosure, in addition to using two kinds of bit line voltages of the forbidden programming bit line voltage Vinh (such as VDD) and the normal programming bit line voltage Vprog (such as the ground voltage Vgnd), two kinds of forced programming voltages (which are both greater than the normal programming bit line voltage Vprog and less than the forbidden programming bit line voltage Vinh) are used, so as to perform the programming operation with finer degree of programming degree distinction on a plurality of programming units.

[0082] The page buffer can perform first programming on the normal programming cells with a normal programming bit line voltage Vprog based on the first forced sensing voltage Vfc1 and the second forced sensing voltage Vfc2, and can perform the first bit line forcing operation on the memory cells to be subjected to the first bit line forcing operation with the first forced programming voltage, and can perform the second bit line forcing operation on the memory cells to be subjected to the second bit line forcing operation with the second forced programming voltage. In more detail, the page buffer can perform the bit line forcing operation by applying the first forced programming voltage to the memory cells to be subjected to the first bit line forcing operation and applying the second forced programming voltage to the memory cells to be subjected to the second bit line forcing operation. Herein, the first forced programming voltage is higher than the normal programming bit line voltage Vprog and lower than the inhibit programming bit line voltage Vinh, and the second forced programming voltage is higher than the first forced programming voltage and lower than the inhibit programming bit line voltage Vinh. It is noted that the normal programming bit line voltage Vprog, the first forced programming voltage, the second forced programming voltage, and the inhibit programming bit line voltage Vinh herein are voltages applied to the bit line during programming.

[0083] For example, the normal programming bit line voltage Vprog can be a ground voltage Vgnd, the inhibit programming bit line voltage Vinh can be a power supply voltage VDD, the first forced programming voltage can be a voltage between the power supply voltage VDD and the ground voltage Vgnd, and the second forced programming voltage can be a voltage between the first forced programming voltage and the power supply voltage VDD. Accordingly, the page buffer can distinguish the memory cells to be inhibited (inhibited cells), the first forced cells, the second forced cells, and the programming cells not to be forced (normal programming cells) from each other based on the first latch information DS, the second latch information DL, and the third latch information DM. In more detail, the page buffer can distinguish the programming cells and the inhibited cells from each other using the first latch information DS in the program verify operation, and can distinguish the first forced cells and the programming cells not to be forced (normal programming cells) from each other using the second latch information DL in the first bit line forcing operation, and can distinguish the second forced cells from the first forced cells and the programming cells not to be forced (normal programming cells) using the third latch information DM in the second bit line forcing operation. Accordingly, the page buffer can apply the inhibit programming bit line voltage Vinh to the memory cells to be inhibited, the first forced programming voltage to the memory cells to be subjected to the first bit line forcing operation, the second forced programming voltage to the memory cells to be subjected to the second bit line forcing operation, and the normal programming bit line voltage Vprog to the programming cells not to be forced (normal programming cells).

[0084] Figure 4A flowchart of a program verify operation of a storage device is provided for an embodiment of the present disclosure. The program verify operation is used to verify whether a storage cell is programmed to a corresponding target threshold voltage. The program verify operation of the storage device includes the following steps: Figure 2 to Figure 4 A flow of the program verify operation is described. The program verify operation of the storage device includes the following steps:

[0085] Step 401: Perform a verify state preset.

[0086] The present disclosure does not limit the number of bits stored by each storage cell. The present disclosure takes TLC with 3 storage bits as an example for illustration, and the TLC has 8 states (LV0-LV7). Here, the verify state can be any one of the 8 states. At this time, since the sensing operation is performed, the forbidden cell, the first forced cell, the second forced cell and the normally programmed cell are not determined, and therefore the verify state information is stored in the first latch 111, and the forbidden information is stored in the second latch and the dynamic latch. The verify state information is used to indicate the current verify state. The forbidden information can be formed by logic "1" and logic "0", wherein the logic "1" indicates that the storage cell is not programmed, and the logic "0" indicates that the storage cell is programmed.

[0087] Step 402: Perform a first sensing operation based on the first forced sensing voltage.

[0088] Here, the first forced sensing voltage Vfc1 corresponding to the verify state can be applied to the word line of the storage cell, so as to perform the first sensing operation (3BL sensing) of the verify state on the storage cell. The page buffer includes a sensing node SO used to determine the state (for example, the data stored in the storage cell) of the storage cell therein. The state of the storage cell can be determined by detecting the current flowing through the sensing node SO.

[0089] Step 403: Store the first sensing operation result to the second latch.

[0090] In the embodiment of the present disclosure, the second latch 112 is configured to store information used to distinguish the storage cell to be subjected to the first bit line forced operation among the storage cells that fail the program verify based on the first forced sensing voltage Vfc1, as the first bit line forced information. In other words, after the first sensing operation is performed, the first bit line forced information can be stored to the second latch 112, and the first bit line forced information indicates the first forced cell that passes the verify of the first forced sensing voltage. Here, the first sensing operation result is the first bit line forced information. In actual application, the first forced information can be written to the second latch 112 through the control signal SET_L. The control signal SET_L is the control signal of the NMOS transistor N7, which can be turned on or turned off in response to the control signal SET_L.

[0091] Step 404: Exchange the information stored in the second latch and the dynamic latch.

[0092] In this embodiment of the disclosure, combined with Figure 2 The specific process of switching the information stored in the second latch 112 and the dynamic latch 113 is as follows: The second PMOS transistor P2 is turned off by the second forced signal EN_4BL_B = 1; the NMOS transistor N1 is turned on by the signal RD_L = 1, thus allowing the dynamic latch to output its stored inhibit information to the sensing node SO. The switch control signal PASS_L = 1 is applied, turning on the control switch 114, thereby causing the dynamic latch 113 to latch the first line forced information from the second latch 112 through the parasitic capacitance electrically connected to the control switch. The NMOS transistors N7 and N8 are turned on by the control signals SET_L = 1 and RST_SA_LATCH = 1, thus making the second latched information DL = 1 stored in the second latch 112. The NMOS transistor N9 is turned on by the control signal RST_L = 1, thus allowing the second latch to store the inhibit information at the sensing node SO.

[0093] Step 405: Perform a second sensing operation based on the second forced sensing voltage.

[0094] Here, the second forced sensing voltage Vfc2 corresponding to the verification state can be applied to the word line of the memory cell, thereby performing the second sensing operation (4BL sensing) of the verification state on the memory cell.

[0095] Step 406: Store the result of the second sensing operation into the second latch.

[0096] In this embodiment, after the second sensing operation, the second bit line forced information can be stored in the second latch 112. The second bit line forced information indicates that the second forced unit has passed the verification of the second forced sensing voltage. Here, the result of the second sensing operation is the second bit line forced information. In practical applications, the second bit line forced information can be written to the second latch 112 via the control signal SET_L.

[0097] Step 407: Perform the third sensing operation based on the verification voltage.

[0098] Here, the programming verification voltage Vvfy corresponding to the verification state can be applied to the word line of the memory cell, thereby performing the third sensing operation (Verify sensing) of the verification state on the memory cell.

[0099] It should be noted that the first forced sensing voltage Vfc1 is less than the second forced sensing voltage Vfc2, and the second forced sensing voltage Vfc2 is less than the program verify voltage Vvfy.

[0100] Step 408: store the third sensing operation result to the first latch.

[0101] In the embodiment of the present disclosure, the first latch 111 is configured to store information used to distinguish between the cells to be programmed and the storage cells to be inhibited based on the program verify voltage as the program verify information. After the third sensing operation is performed, the program verify information can be stored to the first latch 111, and the program verify information can indicate the inhibited cells that pass the verification of the program verify voltage. Here, the third sensing operation result is the program verify information. In actual application, the program verify information can be written to the first latch 111 through the control signal RST_S.

[0102] Step 409: verify state verification update.

[0103] After the third sensing operation based on the program verify voltage is completed, the information stored in the corresponding latch is updated according to the verification result of each storage cell. Specifically, the information stored in the second latch is updated according to the first sensing operation result of each storage cell, that is, the first sensing operation result is stored to the second latch; the information stored in the second latch is updated according to the second sensing operation result of each storage cell, that is, the second sensing operation result is stored to the second latch; and the information stored in the first latch is updated according to the third sensing operation result of each storage cell, that is, the third sensing operation result is stored to the first latch.

[0104] Step 410: determine whether the verification state is the highest state.

[0105] Here, taking TLC as an example, determining whether the verification state is the highest state is to determine whether the verification state is LV7. If the verification state is the highest state, step 412 is performed, and if the verification state is not the highest state, step 411 is performed.

[0106] Step 411: exchange the information stored in the second latch and the dynamic latch.

[0107] In the embodiment of the present disclosure, in combination with Figure 2The specific process of exchanging the information stored in the second latch 112 and the dynamic latch 113 is as follows: by applying the second force signal EN_4BL_B=1, the second PMOS transistor P2 is turned off; by applying the signal RD_L=1, the NMOS transistor N1 is turned on, so that the dynamic latch can output the first forced information stored therein to the sensing node SO. By applying the switch control signal PASS_L=1, the control switch 114 is turned on, so that the dynamic latch 113 can latch the second bit line forced information from the second latch 112 through the parasitic capacitor electrically connected by the control switch. By applying the control signal SET_L=1 and the control signal RST_SA_LATCH=1, the NMOS transistor N7 and the NMOS transistor N8 are turned on, so that the second latch information DL=1 stored in the second latch 112 is set to 1. By applying the control signal RST_L=1, the NMOS transistor N9 is turned on, so that the second latch 112 stores the first bit line forced information at the sensing node SO. After step 411 is performed, step 401 is performed, and the programming and verification operation of the next state is continued.

[0108] Step 412: end verification.

[0109] The disclosure also provides a storage device. A schematic diagram of the storage device is shown in FIG. 6. Figure 1 The storage device includes a storage cell array and the page buffer described above; the storage cell array has a plurality of storage cell strings and a plurality of bit lines connected to the plurality of storage cell strings; the page buffer is connected to the bit line via the sensing node SO and connected to the storage cell string via the bit line.

[0110] In the embodiments of the disclosure, the page buffer is configured to apply a normal programming bit line voltage to a programming cell that is not to be forced to operate, apply an inhibited programming bit line voltage to a storage cell that is to be inhibited, apply a first forced programming voltage higher than the normal programming bit line voltage and lower than the inhibited programming bit line voltage to a storage cell that is to be subjected to a first bit line forced operation, and apply a second forced programming voltage higher than the first forced programming voltage and lower than the inhibited programming bit line voltage to a storage cell that is to be subjected to a second bit line forced operation, based on the programming and verification information, the first bit line forced information, and the second bit line forced information. Here, the normal programming bit line voltage Vprog can be a ground voltage Vgnd, the inhibited programming bit line voltage Vinh can be a power supply voltage VDD, the first forced programming voltage can be a voltage between the power supply voltage VDD and the ground voltage Vgnd, and the second forced programming voltage can be a voltage between the first forced programming voltage and the power supply voltage VDD. It should be noted that the normal programming bit line voltage Vprog, the first forced programming voltage, the second forced programming voltage, and the inhibited programming bit line voltage Vinh herein are voltages applied to the bit line.

[0111] In this embodiment of the disclosure, after the third sensing operation is performed based on the verification voltage, the corresponding bit line voltage can be applied to the corresponding memory cell based on the information stored in the first latch, the second latch and the dynamic latch, so that the memory cell can be distinguishably subjected to bit line forced operation. Figure 5 A flowchart illustrating bit-line forced operation of a storage device according to an embodiment of this disclosure. (In conjunction with...) Figure 4 and Figure 5 After the third sensing operation based on the verification voltage, the first latch stores programming verification information, the second latch stores second bit line forcing information, and the dynamic latch stores first bit line forcing information. Here, the programming verification information can indicate the disabled cell that has passed the verification of the programming verification voltage. In other words, the disabled cell can be determined through the programming verification information. In step 501, a disabled programming bit line voltage Vinh (power supply voltage VDD) is applied to the bit line of the memory cell (disabled cell) to be disabled. At this time, a normal programming bit line voltage Vprog (ground voltage Vgnd) can be applied to the bit lines of the memory cell that will undergo bit line forcing operation and the normal programming cell.

[0112] Combination Figure 2 The specific implementation process is as follows: The NMOS transistor N2 is turned on by the bit line bias signal VBLBIAS = V2X; the NMOS transistor N3 is turned on by the sensing node signal VSOBLK = V2X; the NMOS transistor N4 is turned off by the bit line clamp signal VBLCLAMP = 0; and the second forced signal EN_4BL_B = 1, which turns off the second PMOS transistor P2. This allows the application of a programmable disabling bit line voltage Vinh (power supply voltage VDD) to the bit line of the disabling unit based on the programming verification information stored in the first latch 111. Here, V2X can be equal to twice VDD.

[0113] In step 502, the memory cell to which the second bit line forced operation will be performed (i.e., Figure 3 A voltage V is applied to the bit line of the second forced unit shown. 4BL -V 3BL Here, V 4BL For the second forced programming voltage, V 3BL This is the first forced programming voltage. At this time, the memory cell where the first bit line will be forced (i.e.,...) can be programmed. Figure 3The bit line of the first forced unit is applied with the first forced programming voltage Vforce, and the bit line of the normal programming unit which will not be forced is applied with the normal programming bit line voltage Vprog (ground voltage Vgnd). In the embodiment of the present disclosure, since the control switch 114 is arranged at the output node of the second latch 112 to form a dynamic latch, the second latch 112 cannot directly output the information stored therein to the sensing node SO, and therefore, if the second bit line forced information stored in the second latch is to be output to the sensing node SO, the first bit line forced information stored in the dynamic latch needs to be first dumped to the first latch, and then the second bit line forced information stored in the second latch is output to the dynamic latch through the control switch, so as to output the second bit line forced information to the sensing node SO through the dynamic latch.

[0114] In combination Figure 2 The voltage Vforce is applied to the bit line of the second forced unit. 4BL -V 3BL The specific implementation process is as follows: the bit line bias signal VBLBIAS = V2X is used to make the NMOS transistor N2 conduct, the bit line clamp signal VBLCLAMP = 0 is used to make the NMOS transistor N4 cut off, the sensing discharge signal SODISCH = 0 is used to make the NMOS transistor N5 cut off, the control signal RD_L = 1 is used to make the NMOS transistor N1 conduct, so that the dynamic latch can output the second bit line forced information stored therein to the sensing node SO, the second forced signal EN_4BL_B = 0 is used to make the second PMOS transistor P2 conduct, and the sensing node signal VSOBLK = V 4BL -V 3BL + Vt, so that the second pre-charge circuit can output the voltage V 4BL -V 3BL to the bit line of the second forced unit. It should be noted that during this period, the bit line corresponding to the forbidden unit is in a floating state.

[0115] In step 503, the first forced programming voltage Vforce is applied to the bit line corresponding to the first forced unit (including the storage unit to be subjected to the first bit line forced operation and the storage unit to be subjected to the second bit line forced operation). 3BL At this time, the bit line of the normal programming unit which will not be forced can be applied with the normal programming bit line voltage Vprog (ground voltage Vgnd). At this time, the first bit line forced information is stored in the first latch, and the second bit line forced information is stored in the second latch and the dynamic latch.

[0116] In combination Figure 2 The first forced programming voltage Vforce is applied to the bit line of the first forced unit. 3BLThe specific implementation process is: through the bit line bias signal VBLBIAS=V2X, so that the NMOS transistor N2 is turned on, the sensing discharge signal SODISCH=1, so that the NMOS transistor N5 is turned on, the bit line clamp signal VBLCLAMP=V 3BL +Vt, the sensing node signal VSOBLK=V 4BL +Vt, the second forced signal EN_4BL_B=0, so that the second PMOS transistor P2 is turned on, so that the first forced programming voltage V 3BL is applied to the bit line of the storage unit to be subjected to the first bit line forced operation, and the second forced programming voltage V 4BL is applied to the bit line of the storage unit to be subjected to the second bit line forced operation. It should be noted that during this period, the bit line corresponding to the forbidden unit is in a floating state.

[0117] In the process of performing the bit line forced operation of the embodiment of the present disclosure, the voltage V 4BL -V 3BL is first applied to the bit line of the storage unit (second forced unit) to be subjected to the second bit line forced operation, and then the first forced programming voltage V 3BL is applied to the bit line of the first forced unit (including the storage unit to be subjected to the first bit line forced operation and the storage unit to be subjected to the second bit line forced operation). In this way, the bit line voltage of the storage unit to be subjected to the second bit line forced operation is first changed from Vgnd to V 4BL -V 3BL , and then from V 4BL -V 3BL to V 4BL , and at the same time, the bit line voltage of the storage unit to be subjected to the first bit line forced operation is also changed from Vgnd to V 3BL . This two-step voltage application method for performing the second bit line forced operation also has a one-step voltage application method, in which the bit line voltage of the storage unit to be subjected to the second bit line forced operation is directly changed from Vgnd to V 4BL , and the bit line voltage of the storage unit to be subjected to the first bit line forced operation is also changed from Vgnd to V 3BL . When applying voltage to the bit line of the storage unit to be subjected to the first bit line forced operation and the bit line of the storage unit to be subjected to the second bit line forced operation, although in the case of one-step voltage application, the difference between the bit line voltage of the storage unit to be subjected to the first bit line forced operation and the bit line voltage of the storage unit to be subjected to the second bit line forced operation is V 4BL -V 3BLHowever, in the case of applying the voltage in two steps, the bit line voltage of the memory cell to be subjected to the first bit line force operation is maintained at Vgnd when the voltage is applied for the first time, which is less affected by the bit line voltage of the memory cell to be subjected to the second bit line force operation; and the change value of the bit line voltage of the memory cell to be subjected to the second bit line force operation is V 3BL The change value of the bit line voltage of the memory cell to be subjected to the first bit line force operation is also V 3BL And in the case of applying the voltage in one step, the change value of the bit line voltage of the memory cell to be subjected to the second bit line force operation is V 4BL The change value of the bit line voltage of the memory cell to be subjected to the first bit line force operation is also V 3BL Compared with the one-step voltage application mode, the change values of the bit line voltages of the memory cells to be subjected to the first bit line force operation and the second bit line force operation are less different in the two-step voltage application mode, and thus the memory cells are less disturbed. Therefore, the two-step voltage application mode can reduce the disturbance between the memory cells.

[0118] In the technical solutions provided in the present disclosure, a page buffer is provided, which includes a first latch for storing program verification information, a second latch for storing first bit line force information, and a dynamic latch for storing second bit line force information, the second latch and the dynamic latch being connected through a control switch; the dynamic latch is configured to latch information through a parasitic capacitor. In the present disclosure, the dynamic latch is formed by setting a control switch at the output node of the second latch. The dynamic latch borrows the original parasitic capacitor of the circuit node coupled with the control switch to latch information. Thus, in the embodiments of the present disclosure, the increase of the new latch can be realized only by introducing the control switch, and the structure is simple compared with, for example, the first latch 111 or the second latch 112, so that the number of elements (such as transistors) constituting the page buffer can be reduced to a certain extent.

[0119] Figure 6 A block diagram of an example system 600 having storage is shown in accordance with some aspects of the present disclosure. The system 600 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage. As Figure 6As shown in FIG. 6, the system 600 can include a host 608 and a storage system 602 including one or more storage devices 604 including an array of storage cells and a plurality of page buffers and a controller 606. The host 608 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 608 can be configured to send or receive data to or from the storage device 604.

[0120] The storage device 604 can be any memory disclosed in the present disclosure. As disclosed in detail below, the storage device 604 (e.g., a non-volatile memory) can have a reduced leakage current from a drive transistor (e.g., a string driver) coupled to an unselected word line during an erase operation, which allows for further scaling of the drive transistor.

[0121] According to some embodiments, the controller 606 is coupled to the storage device 604 and the host 608 and is configured to control the storage device. The controller 606 can manage data stored in the storage device and communicate with the host 608. In some embodiments, the controller 606 is designed for operation in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 606 is designed for operation in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptops, etc. and enterprise storage devices. The controller 606 can be configured to control operations of the storage device 604, such as read, erase, and program operations. The controller 606 can also be configured to manage various functions related to data stored in or to be stored in the storage device 604, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the controller 606 is also configured to process error correction codes (ECC) related to data read from or written to the storage device 604. The controller 606 can also perform any other suitable functions, such as formatting the storage device 604. The controller 606 can communicate with external devices (e.g., the host 608) according to a particular communication protocol. For example, the controller 606 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0122] The controller 606 and one or more storage devices 604 can be integrated into various types of storage devices, such as included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the storage system 602 can be implemented and packaged into different types of end electronic products. For example, the storage system 602 can be implemented and packaged into a memory card, a solid state drive (SSD), a universal flash storage (UFS) device, an embedded multimedia card (eMMC) device, a USB flash drive, etc. Figure 7AIn one example shown in FIG. 6, the controller 606 and the single storage device 604 can be integrated into a memory card 702. The memory card 702 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 702 can also include a memory card connector 704 that couples the memory card 702 with a host (e.g., the host 608 in FIG. 6). In another example shown in FIG. 6, the controller 606 and the multiple storage chips 604 can be integrated into an SSD 706. The SSD 706 can also include an SSD connector 708 that couples the SSD 706 with a host (e.g., the host 608 in FIG. 6). In some embodiments, the storage capacity and / or the operating speed of the SSD 706 are greater than those of the memory card 702. Figure 6 Figure 7B Figure 6

[0123] The features disclosed in the several apparatus embodiments provided by the present disclosure can be arbitrarily combined, without conflict, to form new apparatus embodiments.

[0124] The above description is merely illustrative of the disclosure and does not limit the scope of the disclosure. Any modifications made within the scope of the disclosure and equivalents thereof should be covered by the scope of the disclosure. Therefore, the scope of the disclosure should be based on the protection scope of the claims.​​​

Claims

1. A page buffer, characterized in that, include: A first latch for storing programming verification information, a second latch for storing the first bit line forced information, and a dynamic latch for storing the second bit line forced information; wherein the first bit line forced information is different from the second bit line forced information; The dynamic latch includes a control switch electrically connected to the second latch, and the second latch is electrically connected to a first terminal of the control switch. When the control switch is turned on, the information stored in the second latch is transmitted to the second terminal of the control switch and stored through the parasitic capacitance electrically connected to the second terminal.

2. The page buffer according to claim 1, characterized in that, During the first sensing operation based on the first forced sensing voltage, the second latch is configured to store information used to distinguish, based on the first forced sensing voltage, the memory cell that will undergo the first line forced operation among the memory cells that have not passed programming verification, as the first line forced information.

3. The page buffer according to claim 2, characterized in that, Before performing the second sensing operation based on the second forced sensing voltage, the dynamic latch is configured such that the control switch is turned on such that the current first bit line forced information from the second latch is latched through the parasitic capacitance.

4. The page buffer according to claim 3, characterized in that, During the second sensing operation based on the second forced sensing voltage, the second latch is configured to store information used to distinguish, based on the second forced sensing voltage, the memory cell to be subjected to the second bit line forced operation among the memory cells that have not passed programming verification, as the second bit line forced information.

5. The page buffer according to claim 4, characterized in that, After the third sensing operation based on the programmed verification voltage, the dynamic latch is configured to output the first bit line forced information stored in the parasitic capacitance to the sensing node of the page buffer, and latch the second bit line forced information from the second latch when the control switch is turned on; the second latch is configured to store the first bit line forced information at the sensing node.

6. The page buffer according to claim 3, characterized in that, The first forced sensing voltage is less than the second forced sensing voltage.

7. The page buffer according to claim 5, characterized in that, The second forced sensing voltage is less than the programming verification voltage.

8. The page buffer according to claim 1, characterized in that, Also includes: A first pre-charge circuit for generating a first forced programming voltage; The first pre-charge circuit is electrically connected to the bit line through the sensing node of the page buffer; The page buffer is configured to apply a first forced programming voltage, which is higher than the normal programming bit line voltage and lower than the disabled programming bit line voltage, to the bit line corresponding to the memory cell to which the first bit line forced operation is to be performed, through the first pre-charge circuit.

9. The page buffer according to claim 8, characterized in that, Also includes: A second pre-charge circuit for generating a second forced programming voltage, the second pre-charge circuit being electrically connected to the bit line via a sensing node, the second pre-charge circuit being electrically connected to the dynamic latch and being controllable by the information stored in the dynamic latch; The page buffer is configured to apply a second forced programming voltage, which is higher than the first forced programming voltage and lower than the disabled programming bit line voltage, to the bit line corresponding to the memory cell to which the second bit line forced operation is to be performed, through the second precharge circuit.

10. The page buffer according to claim 9, characterized in that, The second pre-charge circuit includes a first PMOS transistor and a second PMOS transistor connected in series between the power supply voltage and the sensing node, wherein the gate of the first PMOS transistor is electrically connected to the dynamic latch, and the second PMOS transistor is controlled by a second bit line forced operation enable signal.

11. The page buffer according to claim 1, characterized in that, The control switch includes a single-transistor control switch or a dual-transistor control switch.

12. The page buffer according to claim 1, characterized in that, The control switch is a transmission gate based on a MOS transistor.

13. The page buffer according to claim 1, characterized in that, The second end of the control switch is coupled to the sensing node of the page buffer through a circuit node to which it is electrically connected; The sensing node is also coupled to the first latch.

14. A storage device, characterized in that, include: A storage cell array having a plurality of storage cell strings and a plurality of bit lines connected to the plurality of storage cell strings; and Peripheral circuitry, which is coupled to the memory cell array via the bit lines and is used to operate the memory cell array; The peripheral circuit includes a plurality of page buffers as described in any one of claims 1 to 13. The page buffer is connected to the corresponding bit line via a sensing node, and is connected to the memory cell string via the bit line.

15. The storage device according to claim 14, characterized in that, The peripheral circuitry is configured to apply a normal programming bit line voltage to the normal programming cell based on programming verification information, a first bit line forced information, and a second bit line forced information; apply a programmable prohibition bit line voltage to the memory cell to be prohibited; apply a first forced programming voltage, which is higher than the normal programming bit line voltage and lower than the programmable prohibition bit line voltage, to the memory cell to which the first bit line forced operation is to be performed; and apply a second forced programming voltage, which is higher than the first forced programming voltage and lower than the programmable prohibition bit line voltage, to the memory cell to which the second bit line forced operation is to be performed.

16. The storage device according to claim 14, characterized in that, The storage device includes a three-dimensional NAND flash memory.

17. A method for programming a storage device as described in claim 14, characterized in that, The method includes: The first sensing operation is performed based on the first forced sensing voltage; Store the result of the first sensing operation into the second latch; Exchange the information stored in the second latch and the dynamic latch; A second sensing operation is performed based on a second forced sensing voltage that is different from the first forced sensing voltage; Store the result of the second sensing operation into the second latch; The third sensing operation is performed based on the verification voltage; Store the result of the third sensing operation into the first latch; Exchange the information stored in the second latch and the dynamic latch.

18. A memory system comprising: One or more storage devices as described in any one of claims 14 to 16; as well as A controller coupled to the storage device and configured to control the storage device.

Images