Matrix calculation circuit, method, electronic device and computer readable storage medium

Abstract

The disclosed embodiments disclose a matrix calculation circuit, method, electronic device and computer-readable storage medium. The matrix calculation circuit includes: a first data reading circuit, used to read and cache the first data in the first matrix and the position information of the first data, wherein the first matrix is ​​a compressed matrix of the data matrix; a second data output control signal is generated according to the position information of the first data; a second data reading circuit, used to read and cache the second data in the second matrix; and control the output of the second data according to the second data output control signal; a calculation circuit, used to calculate the third data according to the first data and the second data. The above-mentioned matrix calculation circuit controls the output of multiple second data by reading the position information of multiple first data, which solves the technical problem that only single data calculation can be performed when performing matrix calculation in the prior art and the calculation of the data acquisition address is complicated.

Description

Technical Field

[0001] The present disclosure relates to the field of processors, and in particular to a matrix calculation circuit, method, electronic device, and computer-readable storage medium. Background Art

[0002] With the development of science and technology, human society is rapidly entering the intelligent era. An important feature of the intelligent era is that people obtain more and more types of data, the amount of data obtained is increasing, and the speed of processing data is getting higher and higher. Chips are the cornerstone of task allocation, which fundamentally determines people's ability to process data. From the perspective of application fields, there are two main routes for chips: one is the general chip route, such as CPU (central processing unit), etc., which can provide great flexibility, but the effective computing power is relatively low when processing algorithms in specific fields; the other is the dedicated chip route, such as TPU (tensor processing unit), etc., which can play a higher effective computing power in certain specific fields, but in the face of flexible and changeable more general fields, their processing capabilities are relatively poor or even unable to process. Due to the wide variety and huge amount of data in the intelligent era, chips are required to have both extremely high flexibility, able to process algorithms in different fields and changing with each passing day, and extremely strong processing capabilities, able to quickly process huge and rapidly growing amounts of data.

[0003] In neural network calculations, convolution calculations account for the majority of the total computational workload, and convolution calculations can be converted into matrix multiplication calculations. Therefore, in order to increase the throughput in neural network tasks, reduce latency, and increase the effective computing power of the chip, the focus is on increasing the speed of matrix multiplication calculations.

[0004] The matrix composed of data in many neural networks (the data here includes parameter data and input data in the neural network) is a sparse matrix, that is, a large number of elements in the matrix have values ​​of 0. In order to reduce the storage volume and bandwidth usage of data in neural network calculations, sparse matrices are compressed for storage; in order to increase the speed of matrix operations, sparse matrix operations are optimized.

[0005] Figure 1a This is a schematic diagram of matrix multiplication calculation in a neural network. Figure 1a As shown, M1 is the data matrix, M2 is the parameter matrix, and M is the output matrix. Each row of data in M1 and each column of parameters in M2 are multiplied and added to obtain a data in M. Figure 1a The two matrices M1 and M2 in may have one or both sparse matrices.

[0006] like Figure 1bThe figure shows a schematic diagram of matrix compression. For storage in sparse matrices, a general compression method can be used: only non-zero elements are stored. While storing the value of this non-zero element, its position information in the matrix is ​​also stored, that is, the relative coordinates X and Y of the element in the matrix. Among them, X represents the matrix row number, and Y represents the matrix column number. This method treats data and coordinates as a data structure and stores them in units of this data structure. Figure 1b As shown, taking an MxN matrix as an example, the MxN matrix on the left is compressed into a compressed matrix on the right, and each data structure in the compressed matrix represents the non-zero data in the left matrix and the coordinates of the non-zero data in the matrix.

[0007] In a sparse matrix, since some elements in the matrix have a value of 0 and these 0 elements do not need to be stored, this compression method can effectively reduce the storage capacity of the matrix. Figure 1c The figure shows an example of compressing a matrix using the above compression method. For a 16x16 sparse matrix, only a, b, c and d are non-zero elements. After compression and storage, only the values ​​and coordinates of these elements need to be stored, thereby saving storage space.

[0008] When performing M1xM2 matrix operations, the compressed matrix is ​​used as the matrix used for actual data acquisition. However, the above technical solution has the following disadvantages: 1. When performing matrix operations, the data utilization rate is low, and usually only independent operation units can be used to calculate single data; 2. According to the data coordinates of the compressed matrix, the calculation of the data acquisition address is complex, which affects the performance. Summary of the invention

[0009] This summary is provided to introduce concepts in a brief form that will be described in detail in the detailed description below. This summary is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0010] In order to solve the above technical problems in the prior art, the present disclosure proposes the following technical solutions:

[0011] In a first aspect, an embodiment of the present disclosure provides a matrix calculation circuit, comprising:

[0012] A first data reading circuit is used to read and cache first data and position information of the first data in a first matrix, wherein the first matrix is ​​a compressed matrix of a data matrix; and generate a second data output control signal according to the position information of the first data;

[0013] A second data reading circuit is used for reading and caching the second data in the second matrix; and controlling the output of the second data according to the second data output control signal;

[0014] A calculation circuit is used to calculate third data according to the first data and the second data.

[0015] Furthermore, the first data reading circuit further includes:

[0016] A first data cache circuit, a first data sorting circuit, and a first control circuit;

[0017] Wherein, the first control circuit is used to generate a first data reading address according to the first address of the first matrix;

[0018] The first data cache circuit is used to cache the first data read out according to the first data read address and the position information of the first data;

[0019] The first data sorting circuit is used to reorder the position information of the first data and the first data in a one-to-one position correspondence according to the first data position information in the first data cache circuit, wherein the reordering result is that the data in the same row in the data matrix are still in the same row after reordering.

[0020] Furthermore, the second data reading circuit further includes:

[0021] A second data cache circuit, a data selection circuit, and a second control circuit;

[0022] Wherein, the second control circuit is used to generate a second data reading address according to the first address of the second matrix;

[0023] The second data cache circuit is used to cache the second data read out according to the second data read address;

[0024] The data selection circuit is used to select and output the second data from the second data cache circuit according to the second data output control signal.

[0025] Further, generating a second data output control signal according to the position information of the first data includes:

[0026] The first data sorting circuit is used to generate the second data output control signal according to the column information in the first data position information.

[0027] Furthermore, the data selection circuit is used to select and output the second data from the second data cache circuit according to the second data output control signal, including:

[0028] The data selection circuit is used for selecting and outputting second data corresponding to the column information from the second data buffer circuit according to the column information in the second data output control signal.

[0029] Furthermore, the first data are K columns of first data in the data matrix, and the second data are K rows of second data in the second matrix corresponding to the K columns of first data in the matrix calculation.

[0030] Furthermore, the computing circuit comprises:

[0031] A computing unit array, wherein the computing unit array includes a plurality of computing units;

[0032] A row of computing units in the computing unit array receives a row of second data in the second data;

[0033] A row of computing units in the computing unit array receives one first data among the first data.

[0034] Further, the calculation circuit is used to calculate the third data according to the first data and the second data, including:

[0035] The calculation circuit receives a column of first data output by the first data sorting circuit; receives at least one row of second data selected and output by the data selection circuit; and calculates third data based on the column of first data and the at least one row of second data.

[0036] Furthermore, the location information of the first data includes: row coordinates and column coordinates of the first data in the data matrix.

[0037] In a second aspect, an embodiment of the present disclosure provides a matrix calculation method, including:

[0038] Reading and buffering first data and position information of the first data in a first matrix, wherein the first matrix is ​​a compressed matrix of a data matrix;

[0039] generating a second data output control signal according to the position information of the first data;

[0040] Reading and buffering second data in the second matrix;

[0041] Controlling output of the second data according to the second data output control signal;

[0042] The third data is calculated according to the first data and the second data.

[0043] In a third aspect, an embodiment of the present disclosure provides a processing core, comprising the matrix calculation circuit, decoding unit, and storage device described in any one of the first aspects.

[0044] In a fourth aspect, an embodiment of the present disclosure further provides a chip, comprising at least one processing core according to the third aspect.

[0045] In a fifth aspect, an embodiment of the present disclosure provides an electronic device, comprising: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, so that when the processor is executed, the matrix calculation method described in any one of the first aspects is implemented.

[0046] In a sixth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable a computer to execute any matrix calculation method described in the first aspect.

[0047] In a seventh aspect, an embodiment of the present disclosure provides a computer program product, comprising computer instructions. When the computer instructions are executed by a computing device, the computing device can execute any matrix calculation method described in the first aspect.

[0048] In an eighth aspect, an embodiment of the present disclosure provides a computing device, comprising one or more chips described in the fourth aspect.

[0049] The disclosed embodiments disclose a matrix calculation circuit, method, electronic device and computer-readable storage medium. The matrix calculation circuit includes: a first data reading circuit, used to read and cache the first data in the first matrix and the position information of the first data, wherein the first matrix is ​​a compressed matrix of the data matrix; a second data output control signal is generated according to the position information of the first data; a second data reading circuit, used to read and cache the second data in the second matrix; and control the output of the second data according to the second data output control signal; a calculation circuit, used to calculate the third data according to the first data and the second data. The above-mentioned matrix calculation circuit controls the output of multiple second data by reading the position information of multiple first data, which solves the technical problem that only single data calculation can be performed when performing matrix calculation in the prior art and the calculation of the data acquisition address is complicated.

[0050] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0052] Figure 1a-1c It is a schematic diagram of the prior art of the present disclosure;

[0053] Figure 2 A schematic diagram of the structure of a matrix calculation circuit provided in an embodiment of the present disclosure;

[0054] Figure 3 A schematic diagram of the structure of a first data reading circuit provided in an embodiment of the present disclosure;

[0055] Figure 4 An example schematic diagram of reordering of a first data reading circuit provided by an embodiment of the present disclosure;

[0056] Figure 5 A schematic diagram of the structure of a second data reading circuit provided in an embodiment of the present disclosure;

[0057] Figure 6a-6e A schematic diagram of an application example of an embodiment of the present disclosure;

[0058] Figure 7 A flowchart of a matrix calculation method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0060] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0061] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0062] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0063] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0064] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0065] Figure 2 Schematic diagram of a matrix calculation circuit provided in an embodiment of the present disclosure. The matrix calculation circuit (EU) 200 provided in this embodiment includes:

[0066] A first data reading circuit (LD_M1) 201, the first data reading circuit is used to read and cache first data and position information of the first data in a first matrix, wherein the first matrix is ​​a compressed matrix of a data matrix; and generate a second data output control signal according to the position information of the first data;

[0067] A second data reading circuit (LD_M2) 202, the second data reading circuit is used to read and cache the second data in the second matrix; and control the output of the second data according to the second data output control signal;

[0068] The calculation circuit 203 is used for calculating the third data according to the first data and the second data.

[0069] Exemplarily, the first data reading circuit reads and caches the first data in the first matrix according to the read address of the first data, and the read address of the first data is generated according to the storage first address of the first matrix; the second data reading circuit reads and caches the second data in the second matrix according to the read address of the second data, and the read address of the second data is generated according to the storage first address of the second matrix. The storage first address of the first matrix and the storage first address of the second matrix are obtained through the instruction decoding circuit ID (Instruction Decoder), and the instruction decoding circuit is used to decode the matrix calculation instruction to obtain the storage first address of the first matrix, the storage first address of the second matrix, and the size of the first matrix and the second matrix and other parameters.

[0070] Exemplarily, the matrix calculation instruction includes an instruction type, a storage start address of a first matrix, a storage start address of a second matrix, and size parameters of the first matrix and the second matrix. In one embodiment, the instruction type is a matrix multiplication instruction, the first matrix is ​​a compressed matrix of a data matrix in a neural network convolution calculation, and the second matrix is ​​a parameter matrix in a neural network convolution calculation; wherein the data matrix and / or the second matrix is ​​a sparse matrix, and a large number of elements in the sparse matrix have a value of 0. It can be understood that the storage start address of the matrix and the size parameters of the matrix (such as the number of rows and columns of the matrix) in the matrix calculation instruction can be expressed in the form of a register address, and the instruction decoding circuit shown obtains the corresponding data from the corresponding register address.

[0071] In the disclosed embodiment, the first data reading circuit 201 receives the first address of the first matrix decoded by the instruction decoding circuit, and generates a read address of the first data according to the first address; optionally, multiple first data in the first matrix are read out at one time according to the read address of the first data. Exemplarily, the maximum number of first data read out at one time is preset to be K columns, where the K columns are K columns in the data matrix, then the first data reading circuit generates the read address of the first data according to the first address of the first matrix and K, reads out and caches multiple first data representing the K columns and the position information of the multiple first data from the first matrix at one time. After obtaining the position information of the multiple first data, the first data reading circuit generates a control signal of the second data according to the position information of the multiple first data, so as to control the output of the multiple second data cached by the second data reading circuit.

[0072] In the disclosed embodiment, the second data reading circuit 202 receives the first address of the second matrix decoded by the instruction decoding circuit, and generates the read address of the second data according to the first address; multiple second data in the second matrix are read out at one time according to the read address of the second data. Exemplarily, the maximum number of second data read out at one time is preset to be K rows, and exemplary, the second matrix is ​​not a compressed matrix, then the K rows are the K rows in the second matrix; the second data reading circuit generates the read address of the second data according to the first address of the second matrix and K, and reads out and caches K rows of second data from the second matrix at one time. Afterwards, according to the control signal of the received second data, the output of the multiple second data is controlled to output all or part of the multiple second data.

[0073] In an embodiment of the present disclosure, the calculation circuit receives a plurality of first data transmitted from the first data reading circuit and a plurality of second data transmitted from the second data reading circuit, and calculates to obtain third data, wherein the third data is one or more.

[0074] like Figure 3 As shown, in order to realize the function of the first data reading circuit, optionally, the first data reading circuit further includes:

[0075] A first data buffer circuit 301, a first data sorting circuit 302 and a first control circuit 303;

[0076] Wherein, the first control circuit 303 is used to generate a first data reading address according to the first address of the first matrix;

[0077] The first data cache circuit 301 is used to cache the first data read out according to the first data read address and the position information of the first data;

[0078] The first data sorting circuit 302 is used to reorder the position information of the first data and the first data in a one-to-one position correspondence according to the first data position information in the first data cache circuit, wherein the reordering result is that the same row of data in the data matrix is ​​still in the same row.

[0079] Optionally, the first control circuit 303 receives the first address of the first matrix obtained by decoding the instruction decoding circuit, the preset parameter K, and the size parameter of the first matrix, such as the first matrix includes data in N columns of the data matrix. Optionally, the first control circuit includes a first read control circuit CL1 and a first address generation circuit AG1, and the first read control circuit CL1 receives the first address of the first matrix obtained by decoding the instruction decoding circuit, the preset parameter K, and the size parameter of the first matrix, and controls AG1 to generate a first data read address Addr1, so that the first data read circuit can read the K columns of first data in the data matrix in the first matrix at one time according to Addr1.

[0080] Optionally, the first data cache circuit 301 further includes a first memory or a first storage area DB11 for caching multiple first data, and a second memory or a second storage area DB10 for caching location information of multiple first data. After reading out the multiple first data and the location information of the multiple first data from the first matrix, the multiple first data are cached in DB11, and the location information of the multiple first data is cached in DB10.

[0081] Optionally, the first data sorting circuit 302 further includes a reordering position information cache circuit IRDB and a reordering first data cache circuit DRDB. The IRDB is used to cache the position information of the multiple first data after reordering, and the DRDB is used to cache the multiple first data after reordering. Optionally, the position information of the multiple first data includes the row coordinates and column coordinates of the first data in the data matrix, the row coordinates are represented by the X coordinate, and the column coordinates are represented by the Y coordinate. Exemplarily, the reordering is performed in the order of columns first and rows later, that is, first in order from small to large according to the Y coordinate, and then in order from small to large according to the X coordinate to ensure that the first data in the same row in the data matrix are still in the same row, and the first data in different rows are still not in the same row. The XY coordinates after reordering are cached in the IRDB, and the first data after reordering are cached in the DRDB. Figure 4 is a schematic diagram of a reordering example, such as Figure 4 As shown, the data matrix M1_O is a sparse matrix, the first matrix is ​​a compressed matrix M1 of the data matrix, M1 includes the first data Data in the data matrix and the position information (X, Y) of the first data in the data matrix, the first data reading circuit reads the 3 columns of data in M1, and the position information therein is arranged in the order of first arranging the Y coordinate from small to large, and then rearranged in the order of arranging the X coordinate from small to large, and the position information with the same X coordinate is located in the same row, and the position information with different X coordinates is located in different rows, as shown in FIG. Figure 4As shown in , (0,0) and (0,1) are located in row 0, and (1,2) is located in row 1; the first data is reordered according to the position corresponding to the position information, such as Figure 4 As shown, the first data 1 and 2 are located in the 0th row, and the first data 3 is located in the second row. Since the number of non-zero data in each row of the data matrix may be different, the length of each row of data may be different after reordering, such as Figure 4 The 0th row has two data, while the 1st row has only one data.

[0082] After reordering, the first data reading circuit outputs the position information DO0 and the first data DO1, wherein DO1 is part or all of the first data among the plurality of first data, and the position information DO0 is the position information corresponding to DO1.

[0083] In one embodiment, the first data reading circuit and the second data reading circuit read out and cache all the first data in the first matrix and all the second data in the second matrix once according to the configuration, and at this time the position information DO0 can be directly used as the control information of the second data; optionally, the first data reading circuit and the second data reading circuit read and cache part of the first data and the second data once according to the configuration, and at this time the control information of the second data can be generated through the position information DO0, and exemplarily, the relative column information in the cache is generated through the position information D00 as the control information of the second data.

[0084] like Figure 5 As shown, in order to realize the function of the second data reading circuit, optionally, the second data reading circuit further includes:

[0085] A second data buffer circuit 501, a data selection circuit 502 and a second control circuit 503;

[0086] Wherein, the second control circuit 503 is used to generate a second data reading address according to the first address of the second matrix;

[0087] The second data cache circuit 501 is used to cache the second data read out according to the second data read address;

[0088] The data selection circuit 502 is used to select and output the second data from the second data cache circuit according to the second data output control signal.

[0089] Optionally, the second control circuit 503 receives the first address of the second matrix obtained by decoding the instruction decoding circuit, the preset parameter K, and the size parameter of the second matrix, such as the second matrix includes N rows of second data. Optionally, the second control circuit includes a second read control circuit CL2 and a second address generation circuit AG2, and the second read control circuit CL2 receives the first address of the first matrix obtained by decoding the instruction decoding circuit, the preset parameter K, and the size parameter of the first matrix, etc., and controls AG2 to generate a second data read address Addr2, so that the second data read circuit can read K rows of second data in the second matrix at a time according to Addr2.

[0090] Optionally, the second data cache circuit 501 includes a second data memory or a second data storage area, whose size is the size of K rows of second data, and the read multiple second data are cached row by row in the second data cache circuit according to their positions in the second matrix.

[0091] Optionally, the data selection circuit 502 includes a switch signal generating circuit DEC and a gate circuit SW, wherein the switch signal generating circuit is used to receive the second data output control signal to generate a switch signal of the gate circuit, and after receiving the switch signal, the gate circuit SW controls the switch corresponding to the switch signal to open to output the corresponding second data.

[0092] Optionally, the second control signal includes column information in the position information of the plurality of first data, and the data selection circuit selects and outputs the second data corresponding to the column information from the second data buffer circuit according to the column information in the second data output control signal. Specifically, after receiving the second data output control signal, the switch signal generation circuit DEC obtains the column information therein, generates row switch information corresponding to the column information, turns on the switch circuit, and outputs a row of second data among the plurality of second data corresponding to the switch circuit.

[0093] like Figure 2 As shown, the calculation circuit 203 includes:

[0094] A computing unit array PUA, wherein the computing unit array includes a plurality of computing units PU 1,1 ,PU 1,2 ,……PU M,N ;

[0095] A row of computing units in the computing unit array receives a row of second data in the second data;

[0096] A row of computing units in the computing unit array receives one first data among the first data.

[0097] Optionally, the calculation circuit 203 receives a reordered column of first data output by the first data sorting circuit; receives at least one row of second data selected and output by the data selection circuit; and calculates third data based on the reordered column of first data and the at least one row of second data.

[0098] Specifically, one first data in a column of first data output by the first data sorting circuit is output to a row of computing units in the computing circuit. If a column of first data includes two first data, the first data in row 0 is output to each computing unit in row 0, and the first data in row 1 is output to each computing unit in row 1; the data selection circuit selects and outputs one or more rows of second data corresponding to a column of first data output by the first data sorting circuit; if a column of first data includes one first data, the second data selected and output by the data selection circuit is one row of second data. Thus, the computing units participating in the calculation will obtain two data inputs, one first data and one second data, and the computing unit calculates the calculation results of the first data and the second data by the calculation type specified by the type of the calculation instruction to obtain the third data, and multiple computing units obtain multiple third data and output them. The above calculation process is repeated, and each computing unit accumulates its calculation results until all the first data and the second data are read to obtain an output matrix, wherein the value of each element in the output matrix is ​​the accumulated result of the computing units participating in the calculation.

[0099] Figure 6a-6e is an example of the calculation process of the matrix calculation circuit in the above embodiment. Figure 6a As shown, it is the matrix multiplication calculation that the matrix calculation circuit needs to perform, M1_O is the data matrix, M2 is the second matrix, and M is the third matrix obtained by multiplying the M1_O and M2 matrices.

[0100] Among them, M1_O is stored in the form of a compressed matrix, such as Figure 6b As shown, M1_0 is compressed to generate the first matrix M1 and saved. Assume K=4, that is, during the calculation process, 4 columns of first data in the data matrix M1_O are read each time, and 4 rows of second data in the second matrix are read each time. For the example, all the data in M1 and M2 are read and cached at once. Figure 6b As shown, the first data reading circuit of the matrix calculation circuit reads the first data in the entire first matrix M1 into the data cache circuit at one time, and reorders it through the first data sorting circuit to obtain the following Figure 6b The storage order in IRDB and DRDB is shown in .

[0101] like Figure 6cThe figure shows an overall schematic diagram of using the matrix calculation circuit to perform matrix calculation. The 4 columns of first data of M1 are read in units of K=4 columns, that is, the columns with column numbers 0-3 in the data matrix. Since in this example, the total number of columns of the data matrix M1_O is 4, the entire M1 will be read and cached in the first data reading circuit LD_M1 at one time; after reading, reordering is performed, the position information is stored in the IRDB of LD_M1, and the first data is stored in the DRDB of LD_M1. The 4 rows of data of M2 are read in units of K=4 rows and cached in the second data reading circuit LD_M2. Since in this example, the total number of rows of M2 is 4, the entire M2 will be read and cached in LD_M2 at one time. After that, after calculation by the 4 calculation units in the calculation array, a 4*4 output matrix M is output, where each element in M ​​corresponds to the output data of a calculation unit.

[0102] like Figure 6d The diagram is a schematic diagram of the first calculation. The calculation circuit obtains the first column of first data from DRDB of LD_M1, wherein the first column of first data includes 1 in row 0 and 2 in row 1, wherein 1 in row 0 is input to the calculation unit PU in row 0 in the calculation circuit. 0,0 and PU 0,1 2 in row 1 is input to the calculation unit PU in row 1 of the calculation circuit 1,0 and PU 1,1 LD_M1 sends the column coordinates 0 and 1 of the first column of the first data cached in IRDB to LD_M2, and the data selection circuit of LD_M2 selects and outputs the second data of the 0th and 1st rows corresponding to the column coordinates of the first data cached in LD_M2 according to the column coordinates 0 and 1, wherein the second data of the 0th row is input to the calculation unit PU of the 0th row 0,0 and PU 0,1 In the example, the second data of row 0 includes 1 and 2, wherein the second data 1 is input to the computing unit PU. 0,0 The second data 2 is input to the computing unit PU 0,1 wherein the second data of row 1 is input to the calculation unit PU of row 1 1,0 and PU 1,1 In the example, the second data of row 1 includes 1 and 2, wherein the second data 1 is input to the computing unit PU. 1,0 The second data 2 is input to the computing unit PU 1,1 After that, each computing unit performs multiplication and accumulation calculations independently to obtain PU 0,0 The calculation result 1, PU 0,1 The calculation result 2, PU 1,0 The calculation results 2 and PU 1,1 The calculation result 4; since the first data and the second data have not been calculated, the third data obtained is the intermediate data M_temp.

[0103] like Figure 6e The diagram shows the second calculation. The calculation circuit obtains the first data of the second column from the DRDB of LD_M1, where the first data of the second column includes 3 of the 0th row and 4 of the 1st row, where 3 of the 0th row is input to the calculation unit PU of the 0th row in the calculation circuit. 0,0 and PU 0,1 The 4 in row 1 are input to the calculation unit PU in row 1 of the calculation circuit. 1,0 and PU 1,1 LD_M1 sends the column coordinates 2 and 3 of the first column of the first data cached in IRDB to LD_M2, and the data selection circuit of LD_M2 selects and outputs the second data of the second and third rows corresponding to the column coordinates of the first data cached in LD_M2 according to the column coordinates 2 and 3, wherein the second data of the second row is respectively input into the corresponding calculation unit PU of the 0th row 0,0 and PU 0,1 In the example, the second data of row 0 includes 1 and 2, wherein the second data 1 is input to the computing unit PU. 0,0 The second data 2 is input to the computing unit PU 0,1 wherein the second data of the third row is input to the calculation unit PU of the first row 1,0 and PU 1,1 In the example, the second data of the third row includes 1 and 2, wherein the second data 1 is input to the computing unit PU 1,0 The second data 2 is input to the computing unit PU 1,1 After that, each computing unit performs multiplication and accumulation calculations independently to obtain PU 0,0 The calculation result 4, PU 0,1 The calculation result 8, PU 1,0 The calculation results of 6 and PU 1,1 The calculation result is 12; since the first data and the second data are calculated, the third data obtained is the value of the element in the output matrix M.

[0104] It can be seen from the calculation process of the above example that using the matrix calculation circuit in the present invention to perform matrix multiplication operations only requires two calculations to complete the multiplication of a 2*4 matrix and a 4*2 matrix, which greatly improves the calculation speed and saves calculation time.

[0105] Through the above-mentioned technical scheme disclosed in the present invention, the compressed sparse matrix is ​​directly calculated, which effectively saves storage space and data bandwidth; using a computing unit array, all computing units perform data processing synchronously, which greatly improves data utilization, and multiple computing units can share the same data; directly calculating the compressed sparse matrix, skipping the calculation of some 0 elements, thereby improving the calculation speed and enhancing the effective computing power of the chip.

[0106] Figure 7 Flow chart of the matrix calculation method provided by the embodiment of the present disclosure. Figure 7 As shown, the method comprises the following steps:

[0107] Step S701, reading and caching first data and position information of the first data in a first matrix, wherein the first matrix is ​​a compressed matrix of a data matrix;

[0108] Step S702, generating a second data output control signal according to the first data position information;

[0109] Step S703, reading and caching the second data in the second matrix;

[0110] Step S704, controlling the output of the second data according to the second data output control signal;

[0111] Step S705: Calculate and obtain third data based on the first data and the second data.

[0112] Further, the reading and caching the first data in the first matrix and the position information of the first data includes:

[0113] Generate a first data reading address according to the first address of the first matrix;

[0114] Buffering the first data read out according to the first data read address and the location information of the first data;

[0115] The first data position information and the first data are reordered in a one-to-one correspondence according to the position information of the first data, wherein the reordering result is that the data in the same row in the data matrix are still in the same row.

[0116] Further, the reading and caching the second data in the second matrix includes:

[0117] generating a second data reading address according to the first address of the second matrix;

[0118] The second data read out according to the second data read address is cached.

[0119] Further, generating a second data output control signal according to the first data position information includes:

[0120] The second data output control signal is generated according to the column information in the first data position information.

[0121] Further, controlling the output of the second data according to the second data output control signal includes:

[0122] According to the column information in the second data output control signal, second data corresponding to the column information is selected from the second data and outputted.

[0123] Furthermore, the first data are K columns of first data in the data matrix, and the second data are K rows of second data in the second matrix corresponding to the K columns of first data in the matrix calculation.

[0124] Further, calculating the third data according to the first data and the second data includes:

[0125] A column of first data is received; at least one row of second data is received; and third data is calculated based on the column of first data and the at least one row of second data.

[0126] Furthermore, the location information of the first data includes: row coordinates and column coordinates of the first data in the data matrix.

[0127] In the above, although the various steps in the above method embodiment are described in the above order, those skilled in the art should be aware that the steps in the embodiments of the present disclosure are not necessarily executed in the above order, and they may also be executed in other orders such as reverse order, parallel order, and cross order. Moreover, on the basis of the above steps, those skilled in the art may also add other steps. These obvious variations or equivalent replacement methods should also be included in the protection scope of the present disclosure and will not be repeated here.

[0128] The disclosed embodiment further provides a processing core, which includes at least one matrix calculation circuit, a decoding unit, and a storage device in the above embodiments.

[0129] The present disclosure also provides a chip, which includes at least one processing core in the above embodiment.

[0130] An embodiment of the present disclosure provides an electronic device, comprising: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, so that when the processors are executed, any matrix calculation method described in the embodiments is implemented.

[0131] The embodiments of the present disclosure also provide a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute any matrix calculation method described in the aforementioned embodiments.

[0132] The embodiments of the present disclosure also provide a computer program product, which is characterized in that it includes computer instructions. When the computer instructions are executed by a computing device, the computing device can execute any matrix calculation method described in the aforementioned embodiments.

[0133] The disclosed embodiments further provide a computing device, characterized in that it comprises any chip described in the embodiments.

[0134] The flowcharts and block diagrams in the accompanying drawings of the present disclosure illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, task segment, or a part of the code, which contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0135] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, limit the unit itself.

[0136] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0137] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Claims

1. A matrix calculation circuit, characterized in that: include: A first data reading circuit is used to read and cache first data in a first matrix and position information of the first data, wherein the first matrix is ​​a compressed matrix of a data matrix, and the compressed matrix includes non-zero data in the first matrix and positions of the non-zero data in the first matrix; generating a second data output control signal according to the position information of the first data; A second data reading circuit, used for reading and caching second data in the second matrix; Controlling output of the second data according to the second data output control signal; A calculation circuit is used to calculate third data according to the first data and the second data.

2. The matrix calculation circuit according to claim 1, characterized in that: The first data reading circuit further includes: A first data cache circuit, a first data sorting circuit, and a first control circuit; Wherein, the first control circuit is used to generate a first data reading address according to the first address of the first matrix; The first data cache circuit is used to cache the first data read out according to the first data read address and the position information of the first data; The first data sorting circuit is used to reorder the position information of the first data and the first data in a one-to-one position correspondence according to the first data position information in the first data cache circuit, wherein the reordering result is that the data in the same row in the data matrix are still in the same row after reordering.

3. The matrix calculation circuit according to claim 1 or 2, wherein: The second data reading circuit further includes: A second data cache circuit, a data selection circuit, and a second control circuit; Wherein, the second control circuit is used to generate a second data reading address according to the first address of the second matrix; The second data cache circuit is used to cache the second data read out according to the second data read address; The data selection circuit is used to select and output the second data from the second data cache circuit according to the second data output control signal.

4. The matrix calculation circuit according to claim 3, wherein the step of generating the second data output control signal according to the position information of the first data comprises: The first data sorting circuit is used to generate the second data output control signal according to the column information in the first data position information.

5. The matrix calculation circuit according to claim 4, wherein the data selection circuit is used to select and output the second data from the second data buffer circuit according to the second data output control signal, comprising: The data selection circuit is used for selecting and outputting the second data corresponding to the column information from the second data buffer circuit according to the column information in the second data output control signal.

6. The matrix calculation circuit according to claim 1, wherein the calculation circuit comprises: A computing unit array, wherein the computing unit array includes a plurality of computing units; A row of computing units in the computing unit array receives a row of second data in the second data; A row of computing units in the computing unit array receives one first data among the first data.

7. The matrix calculation circuit according to claim 3, wherein the calculation circuit is used to calculate the third data according to the first data and the second data, comprising: The calculation circuit receives a reordered column of first data output by the first data sorting circuit; receiving at least one row of second data selected and output by the data selection circuit; The third data is calculated based on the reordered column of first data and the at least one row of second data.

8. The matrix calculation circuit according to claim 1, wherein the position information of the first data comprises: The row coordinates and column coordinates of the first data in the data matrix.

9. A matrix calculation method, characterized in that: include: Reading and caching first data in a first matrix and position information of the first data, wherein the first matrix is ​​a compressed matrix of a data matrix, and the compressed matrix includes non-zero data in the first matrix and positions of the non-zero data in the first matrix; generating a second data output control signal according to the position information of the first data; Reading and buffering the second data in the second matrix; Controlling output of the second data according to the second data output control signal; The third data is calculated according to the first data and the second data.

10. A processing core comprising the matrix calculation circuit according to any one of claims 1 to 8.

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