A LVS layout inspection method for photosensitive array of CCD image sensor

Abstract

The present invention discloses an LVS layout inspection method for a CCD image sensor photosensitive array, comprising the steps of: completing the layout drawing of photosensitive units according to the process processing requirements, and laying out the photosensitive units according to the pixel arrangement required by the product according to the circuit design requirements to form a layout array; drawing the circuit schematic diagram of the layout array according to the process level definition and the direction of electron flow; writing the code for device extraction according to the device characteristics of the photosensitive units; completing the writing of the LVS rule file according to the code writing; and inspecting the photosensitive unit array area of ​​the circuit schematic diagram. The present invention effectively solves the problem that the layout inspection work needs to be manually inspected, improves the accuracy of the layout inspection and the efficiency of the inspection work, and innovatively provides ideas for this type of inspection method of reversely extracting the circuit diagram from the layout.

Description

Technical Field

[0001] The invention relates to the field of EDA design, and in particular to an LVS layout inspection method for a CCD image sensor photosensitive array. Background Art

[0002] The electrical connection relationship check of the layout is usually carried out using Calibre's LVS check tool. LVS is Calibre's verification tool, which is used to verify whether the layout and logic diagram match. LVS compares the connectivity of the layout and logic diagram at the transistor level and outputs all inconsistencies. LVS inspection requires the netlist generated by the circuit schematic and the LVS check file.

[0003] The schematic diagram of the CCD type sensor is provided by the front-end circuit personnel. However, since the photosensitive unit needs to be designed in accordance with the process requirements of the process manufacturer, some circuit diagrams such as the pixel array are often represented by black boxes and cannot be directly used for layout LVS inspection. Due to the particularity of the photosensitive unit, the input of the circuit is provided by external photons, which brings difficulties to the preparation of inspection files and the drawing of circuit schematics. Therefore, manual inspection is often used for this part of the layout inspection. The current inspection method is to manually check the connection relationship of the photosensitive unit electrodes line by line, and then check the array layout connection after the unit is spliced. This inspection method is time-consuming and labor-intensive, and manual inspection is prone to omissions, and the accuracy of the inspection cannot be guaranteed. Summary of the invention

[0004] The purpose of the present invention is to provide a method for LVS layout inspection of a CCD image sensor photosensitive array to solve the problems of large workload and insufficient inspection in existing manual inspection methods.

[0005] The technical solution of the present invention is:

[0006] A LVS layout inspection method for a CCD image sensor photosensitive array, wherein the CCD image sensor photosensitive array is composed of photosensitive units of a plurality of CCD type devices arranged in sequence, and the method comprises the following steps:

[0007] S1. Complete the photosensitive unit layout drawing according to the process requirements, and arrange the photosensitive units according to the pixel arrangement required by the product according to the circuit design requirements to form a layout array;

[0008] S2. Draw the circuit schematic diagram of the layout array according to the process level definition and the direction of electron flow;

[0009] S3. Writing code for device extraction based on the device characteristics of the photosensitive unit;

[0010] S4. Complete the writing of LVS rule files according to the code;

[0011] S5. Check the photosensitive unit array area of ​​the circuit schematic.

[0012] Preferably, the photosensitive unit of the CCD type device includes polysilicon, a buried channel and a channel resistance, wherein the polysilicon is arranged in 2 to 4 overlapping layers; in step 1, the buried channel is implanted with phosphorus at a certain implantation dose according to the electron capacity parameter requirements to form a channel for electron flow; the channel resistance uses high-concentration boron implantation to form a potential barrier to prevent electron flow.

[0013] Preferably, in step 2, a circuit diagram designed for inspection is extracted by reverse extraction of the layout, the layout repetitive units of the CCD device are arranged in an array, the connection relationship of the pixel itself only considers the signal line input, and the CCD photosensitive unit is represented by a gate-level circuit.

[0014] Preferably, the photosensitive unit includes several capacitors, some of which constitute the connection relationship of the multi-phase input signal on the polysilicon, simulating the flow process during electron transfer; the remaining capacitors simulate the capacitance formed between the polysilicon and the buried channel, and these capacitors do not reflect the connection relationship in the flow during electron transfer.

[0015] Preferably, in step 3, according to the characteristics of the capacitor device, the device extraction code is written according to the circuit diagram and the requirements of the process level, wherein the overlap of polysilicon and polysilicon and the combination of polysilicon and buried trench are represented by the upper and lower plates of the capacitor, and the overlap of polysilicon and polysilicon will produce resistance, or the connection relationship is reflected in the circuit diagram by resistance and capacitor.

[0016] Preferably, in step 4, the inspection file is written according to the Standard Verification Rule Format (SVRF) Manual, and the LVS inspection file includes the code displayed in the device extraction part.

[0017] Preferably, in step 5, the method for exporting the netlist and running the LVS check is: exporting the drawn circuit schematic into a netlist in the Virtuoso software, matching the layout array GDS in Calibre-nmLVS and running the LVS check to check the array area; if the electrode connection sequence and the circuit relationship are correct, it passes; if the electrode connection sequence and the circuit relationship are wrong, an error message is fed back.

[0018] The advantages of the present invention are:

[0019] The LVS layout inspection method of the CCD image sensor photosensitive array proposed in the present invention effectively solves the problem that the previous layout inspection work needs to be manually inspected, improves the accuracy of the layout inspection and the efficiency of the inspection work, and innovatively provides ideas for this type of inspection method of reversely extracting the circuit diagram from the layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0021] Figure 1 It is a flow chart of the LVS layout inspection method of the CCD image sensor photosensitive array of the present invention;

[0022] Figure 2 Schematic diagram of the structure of the CCD photosensitive unit in the embodiment;

[0023] Figure 3 It is a gate level circuit schematic diagram of the CCD photosensitive unit in the embodiment;

[0024] Figure 4 The following are the relevant codes extracted from the device in the embodiment. DETAILED DESCRIPTION

[0025] like Figure 1 FIG. 1 is a flow chart of the LVS layout inspection method of the CCD image sensor photosensitive array of the present invention. The CCD image sensor photosensitive array is composed of photosensitive units of a plurality of CCD type devices arranged in sequence. The method comprises the following steps:

[0026] S1. Complete the photosensitive unit layout drawing according to the process requirements, and arrange the photosensitive units according to the pixel arrangement required by the product according to the circuit design requirements to form a layout array;

[0027] S2. Draw the circuit schematic diagram of the layout array according to the process level definition and the direction of electron flow;

[0028] S3. Writing code for device extraction based on the device characteristics of the photosensitive unit;

[0029] S4. Complete the writing of LVS rule files according to the code;

[0030] S5. Check the photosensitive unit array area of ​​the circuit schematic diagram: if the electrode connection sequence and the circuit relationship are correct, it passes; if the electrode connection sequence and the circuit relationship are wrong, an error message is fed back.

[0031] like Figure 2 As shown, the photosensitive unit of the CCD type device includes polysilicon 1, buried channel 2 and channel resistance 3, wherein the polysilicon 1 is arranged in 2 to 4 layers in an overlapping manner; the buried channel 2 is implanted with phosphorus at a certain implantation dose according to the electron capacity parameter requirements to form a channel for electron flow; the channel resistance 3 is implanted with high-concentration boron to form a potential barrier to prevent electron flow. In step 1, the photosensitive unit layout drawn according to the process requirements is as follows Figure 2 shown.

[0032] Since the photosensitive part of the CCD is composed of an array, checking only a single unit cannot guarantee that the array connection relationship is correct. Checking the overall layout circuit connection relationship requires providing a circuit netlist corresponding to the layout. In step 2, the circuit diagram designed for inspection is extracted by reverse extraction from the layout. The layout repeating units of the CCD device are arranged in an array. The connection relationship of the pixel itself only considers the signal line input, and the gate-level circuit is used to represent the CCD photosensitive unit. In summary, in step 2, the gate-level circuit is used to represent the CCD photosensitive unit. The circuit diagram is as follows: Figure 3 shown.

[0033] The photosensitive unit includes 8 capacitors, of which 4 capacitors constitute the connection relationship of the multi-phase input signal on the polysilicon, simulating the flow process during electron transfer; the remaining 4 capacitors simulate the capacitance formed between the polysilicon and the buried channel. These capacitors do not reflect the connection relationship in the flow during electron transfer, but in order to simplify device extraction and batch layout inspection, these 4 capacitors cannot be omitted.

[0034] In step 3, according to the characteristics of capacitor devices, the device extraction code is written based on the requirements of the circuit diagram and process level, in which the overlap of polysilicon and polysilicon and the combination of polysilicon and buried trench are represented by the upper and lower plates of the capacitor. At the same time, the overlap of polysilicon and polysilicon will produce resistance, or the connection relationship is reflected in the circuit diagram by resistance and capacitance. The relevant code for device extraction is as follows: Figure 4 shown.

[0035] In step 4, based on the commonly used processes for CCD type devices in the industry, the inspection file is written in accordance with the Standard Verification Rule Format (SVRF) Manual provided by Calibre. The LVS inspection file includes the code displayed in the device extraction part.

[0036] In step 5, the method of exporting the netlist and running the LVS check is as follows: in the Virtuoso software, the drawn circuit schematic is exported into a netlist, and in Calibre-nmLVS, the layout array GDS is matched and the LVS check is run to check the array area; if the electrode connection sequence and the circuit relationship are correct, it passes; if the electrode connection sequence and the circuit relationship are incorrect, an error message is fed back.

[0037] The LVS layout inspection method of the CCD image sensor photosensitive array of the present invention effectively solves the problem that the previous layout inspection work needs to be manually inspected, improves the accuracy of the layout inspection and the efficiency of the inspection work, and innovatively provides ideas for this type of inspection method of reversely extracting the circuit diagram from the layout.

[0038] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any modifications made according to the spirit of the main technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A LVS layout inspection method for a CCD image sensor photosensitive array, wherein the CCD image sensor photosensitive array is composed of photosensitive units of a plurality of CCD type devices arranged in sequence, characterized in that: The following steps are involved: S1. Complete the photosensitive unit layout drawing according to the process requirements, and arrange the photosensitive units according to the pixel arrangement required by the product according to the circuit design requirements to form a layout array; S2. Draw the circuit schematic diagram of the layout array according to the process level definition and the direction of electron flow; In step S2, the circuit schematic is designed by reverse extraction from the layout, the layout repeating units of the CCD device are arranged in an array form, the connection relationship of the pixel itself only considers the signal line input, and the CCD photosensitive unit is represented by a gate-level circuit; S3. Writing code for device extraction based on the device characteristics of the photosensitive unit; S4. Complete the writing of LVS rule files according to the code; S5. Check the photosensitive unit array area of ​​the circuit schematic.

2. The LVS layout inspection method of the CCD image sensor photosensitive array according to claim 1, characterized in that: The photosensitive unit of the CCD type device includes polysilicon, buried channel and channel resistance, wherein the polysilicon is arranged in 2 to 4 overlapping layers; in step S1, the buried channel is implanted with phosphorus at a certain implantation dose according to the electron capacity parameter requirements to form a channel for electron flow; the channel resistance is implanted with high concentration boron to form a potential barrier to prevent electron flow.

3. The LVS layout inspection method of the CCD image sensor photosensitive array according to claim 2, characterized in that: The photosensitive unit includes several capacitors, some of which constitute the connection relationship of the multi-phase input signal on the polysilicon, simulating the flow process during electron transfer; the remaining capacitors simulate the capacitance formed between the polysilicon and the buried channel, and these capacitors do not reflect the connection relationship in the flow during electron transfer.

4. The LVS layout inspection method of the CCD image sensor photosensitive array according to claim 3, characterized in that: In step S3, according to the characteristics of the capacitor device, the device extraction code is written according to the requirements of the circuit diagram and the process level, wherein the overlap of polysilicon and polysilicon and the combination of polysilicon and buried trench are represented by the upper and lower plates of the capacitor. At the same time, the overlap of polysilicon and polysilicon will produce resistance, and the connection relationship is reflected in the circuit diagram by resistance and capacitor.

5. The LVS layout inspection method of the CCD image sensor photosensitive array according to claim 4, characterized in that: In step S4, the inspection file is written according to the Standard Verification Rule Format (SVRF) Manual, and the LVS inspection file includes the code displayed in the device extraction part.

6. The LVS layout inspection method of the CCD image sensor photosensitive array according to claim 5, characterized in that: In step S5, the method of exporting the netlist and running the LVS check is as follows: in the Virtuoso software, the drawn circuit schematic is exported into a netlist, the layout array GDS is matched in Calibre-nmLVS, and the LVS check is run to check the array area; if the electrode connection sequence and the circuit relationship are correct, it passes; if the electrode connection sequence and the circuit relationship are wrong, an error message is fed back.

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