Chip failure point location method

Abstract

Disclosed is a method for locating chip failure points. The method removes the edge structure of the chip to expose portions of multiple metal layers on the chip's cross section. Current is supplied to the chip through the exposed metal layers, and an EBAC (E-Beam Absorbance Current) technique is used to obtain a cross-sectional image of the chip under current drive. The depth position of the failure point can be directly located based on the intersection of the light and dark areas of the cross-sectional image. This method eliminates the need for multiple chip layer removals, gradually exposing the underlying metal at different depths for multiple tests. This effectively speeds up the analysis and testing of the failure point's depth position, facilitating chip research and development.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for locating a failure point of a chip. Background Art

[0002] NAND flash memory is a superior storage device to hard disk drives. As people pursue low-power, lightweight, and high-performance non-volatile storage products, it has gained widespread application in electronic products. Currently, planar NAND flash memory has reached its practical expansion limit. To further increase storage capacity and reduce the storage cost per bit, 3D NAND memory has been proposed.

[0003] During the 3D NAND product development and manufacturing stages, many chip edge failures occur. Chip edge failure modes typically include open circuits and high resistance. For complete open circuit failures, 3D NAND memory includes a large number of gate structures stacked in its depth direction. The failure point may exist in any of these gate structures, making it difficult to locate and detect the depth of the failure point within the memory chip. Summary of the Invention

[0004] The present invention provides a method for locating a failure point of a chip, wherein the chip includes a plurality of stacked metal layers, including:

[0005] removing an edge structure of the chip to obtain a cross section of the chip;

[0006] providing a current on at least one of the plurality of metal layers in the chip;

[0007] Obtaining a cross-sectional image of the chip under current driving under an electron microscope; wherein,

[0008] The junction of the light and dark areas of the cross-sectional image is the location of the failure point.

[0009] Optionally, before the step of removing the edge structure of the chip, the method further includes:

[0010] A protective base layer is provided on the upper surface of the chip.

[0011] Optionally, the protective substrate layer is a glass layer.

[0012] Optionally, in the step of obtaining a cross-sectional image of the chip under current driving under an electron microscope, the chip is further fixed by a fixing table, and the cross section of the chip is directed toward the nanoprobe station.

[0013] Optionally, the step of providing current on at least one of the plurality of metal layers in the chip includes:

[0014] The metal layers corresponding to the input end and the output end of the plurality of metal layers are connected to the current channel and the ground channel respectively through the nanoprobe.

[0015] Optionally, the step of removing the edge structure of the chip includes:

[0016] The cross-section is prepared until the side of the top metal layer of the chip is exposed, and the cross-section of the chip at least exposes the top metal layer at the edge position of the chip.

[0017] Optionally, the step of obtaining a cross-sectional image of the chip under current driving under an electron microscope includes:

[0018] Adjust the acceleration voltage and electron beam current of the scanning electron microscope to obtain a cross-sectional image of the chip. The intersection of the light and dark areas of the cross-sectional image is the location of the failure point, wherein:

[0019] At least part of the bright area of the cross-sectional image is not directly exposed on the cross section of the chip.

[0020] Optionally, before the step of removing the edge structure of the chip, the method further includes:

[0021] Performing a de-layering operation to peel off the upper surface structure of the chip until the top metal layer of the chip is exposed;

[0022] providing current to the chip through the top metal layer;

[0023] Obtaining a planar image of the upper surface of the chip under current driving under an electron microscope;

[0024] The plane position of the failure point on the top view of the chip is obtained according to the position of the boundary between the light and dark areas of the plane image.

[0025] Optionally, the step of providing current on at least one of the plurality of metal layers in the chip further comprises:

[0026] According to the planar position of the failure point on the top view of the chip, a top metal layer close to the failure point is selected to connect the current channel and the ground channel.

[0027] Optionally, the position of the boundary between the light and dark areas of the cross-sectional image includes a planar position of the failure point on the top view of the chip and a depth position of the failure point in the depth direction of the chip.

[0028] The chip failure point locating method provided by the present invention removes the edge structure of the chip to expose parts of multiple metal layers on the cross section of the chip, provides current to the chip through the exposed metal layer, and obtains a cross-sectional image of the chip cross section under current drive through EBAC (E-Beam Absorbance Current) technology. The depth position of the failure point is directly located according to the position of the intersection of the light and dark areas of the cross-sectional image. There is no need to remove the chip layers multiple times, and the bottom layers at different depths are gradually exposed for multiple tests. This effectively improves the analysis and testing speed of the depth position of the failure point, providing convenience for chip research and development. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0030] Figure 1 FIG. 1 shows a schematic diagram of a chip failure point test according to an embodiment;

[0031] Figure 2 A flow chart of a chip failure point location method according to an embodiment is shown;

[0032] Figure 3 A schematic cross-sectional view of a method for locating a chip failure point according to an embodiment is shown;

[0033] Figure 4 A schematic cross-sectional view showing an edge structure of a chip according to an embodiment;

[0034] Figure 5 A schematic structural diagram of a chip fixing device according to an embodiment is shown;

[0035] Figure 6A and Figure 6B A schematic diagram of a test state of a sample cross section of a chip failure point location method according to an embodiment is shown. DETAILED DESCRIPTION

[0036] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0037] The specific implementation of the present invention is further described in detail below with reference to the accompanying drawings and examples.

[0038] Figure 1 A schematic diagram of a chip failure point test according to an embodiment is shown.

[0039] like Figure 1As shown in the figure, the approximate failure address (failure point location) is confirmed based on the brightness difference of the SEM VC (Scanning Electron Microscope Voltage Contrast) image, and then a delayer analysis is performed to gradually find the specific failure address. The test content mainly includes:

[0040] A nanoprobe P connected to a current channel CUR and a ground channel GND is used to supply current to an edge loop of a chip 100 (e.g., a 3D memory chip). Under a scanning electron microscope (SEM), the top metal exhibits a difference in light and dark areas. Based on the location of the difference, it can be preliminarily confirmed that the failure point is located in the electrical loop between the first top metal 101 and the second top metal 102 at the junction of the light and dark areas.

[0041] When the SEM VC cannot directly find the failure address (i.e., the depth of the failure point in the chip 100 cannot be confirmed), a nanoprober is used to perform a dichotomy check step by step until the failure address is found. The first top metal layer 101 and the second top metal layer 102 are accurately located, and then layer stripping and test positioning are performed to obtain the depth position of the failure point in the chip 100.

[0042] Figure 2 A flow chart of a chip failure point location method according to an embodiment is shown.

[0043] Reference Figure 2 The chip failure point location method of this embodiment includes:

[0044] Step S01: obtaining the plane position of the failure point of the chip using the EBAC technology.

[0045] That is, the upper surface of the chip is de-layered to expose the top metal layer, and the de-layered chip is placed in a scanning electron microscope. Current is passed through the top metal layer of the chip through a nanoprobe, and a planar image of the upper surface of the chip under current drive is obtained through the scanning electron microscope. According to the position of the first top metal layer 101 and the second top metal layer 102 at the junction of the light and dark areas of the planar image, it is confirmed that the failure point is located in the electrical circuit between the first top metal layer 101 and the second top metal layer 102 (the chip is stacked with multiple metal layers, and the electrical circuit corresponds to the connection circuit of the multiple metal layers), so as to obtain the planar position of the failure point.

[0046] Among them, EBAC (E-Beam Absorbance Current) technology includes: exposing the chip electrical circuit and providing current to the chip electrical circuit. If there is an open circuit (or high resistance) point in the chip electrical circuit, charge is injected into the upstream electrical circuit of the open circuit point according to the current, and the downstream electrical circuit of the open circuit point is in a grounded state and has no charge. The electrical circuit with charge injection generates feedback under the action of the electron beam of an electron microscope (scanning electron microscope, SEM, scanning electron microscope, but the implementation of the present invention does not specifically limit the type of electron microscope). The electron microscope images this part as a highlighted image and images other areas without charge injection as dark images, so as to confirm whether the corresponding electrical circuit is open and the location of the open circuit point based on the light and dark states of the image obtained by the electron microscope and the boundary between the light and dark areas.

[0047] Step S02: removing the edge structure of the chip to obtain a cross section of the chip.

[0048] This involves cutting and removing the chip's edge structure through cross-section sampling until the side edges of the top metal layer are exposed. The top metal layer of a chip is generally slightly larger than the bottom metal layer, and cross-section sampling is stopped when the side edges of the top metal layer are exposed. The bottom metal layer is still covered with a small amount of insulating material and is not directly exposed on the sample cross-section. This ensures the integrity of the bottom metal's electrical circuit (original connection state), prevents cross-section sampling from damaging the circuit at the failure point, and ensures the reliability of the analysis and test.

[0049] Step S03: providing current on at least one metal layer in the chip.

[0050] In step S03, the current provided to the chip is provided by the nanoprobe of the nanoprobe station, the nanoprobe is connected to the current channel and the ground channel respectively, and the nanoprobe is connected to the top metal exposed in the sample cross section (corresponding to the input and output ends in the connection loop of the metal layer of the chip), and the current is provided to the electrical circuit described at the failure point through the top metal.

[0051] In this embodiment, the cross section of the chip only exposes the top metal, and current is supplied to the chip through the top metal. In an optional embodiment, the cross section of the chip may also expose other bottom metals, and current may also be supplied to the chip through the bottom metal.

[0052] EBAC (E-Beam Absorbance Current) technology is used to supply current to the exposed electrical circuit, amplify the failure point signal, and improve the light and dark contrast between the part that is subsequently connected to the current and the part that is not connected to the current under the electron microscope, thereby improving positioning efficiency.

[0053] Step S04: obtaining a cross-sectional image of the chip under current driving under an electron microscope.

[0054] Step S05: confirming the depth position of the failure point according to the position of the boundary between the light and dark areas of the cross-sectional image.

[0055] In step S05 , the bright area of the cross-sectional image corresponds to the metal layer connected to the current, and the dark area corresponds to the grounded metal layer not connected to the current. The junction is the open circuit position of the metal layer, corresponding to the failure point.

[0056] In this embodiment, the failure point is first located in the chip's plane, and the plane location of the failure point is determined first. This allows the first top metal layer 101 and the second top metal layer 102 near the failure point to be directly selected in step S03 to connect the current and ground paths based on the plane location of the failure point. This reduces the supply current demand and energy consumption of step S03, facilitates direct positioning of the scanning position in step S03, and eliminates the need to scan the entire AA cross-section of chip 100, further reducing overall power consumption during the analysis. Furthermore, direct positioning is faster.

[0057] In an optional embodiment, the plane positioning step of step S01 is removed, and current is provided to all the electrical circuits of the AA section (i.e., current is provided to the top metals at both ends of the multiple top metals exposed in the section of the chip (refer to Figure 1 The current supply method is used to provide the chip cross section with the corresponding overall drive of the electrical circuit, and a cross-sectional image of all parts of the AA cross section under current drive is obtained by scanning with an electron microscope. The plane position and depth position of the failure point in the chip 100 are confirmed based on the overall cross-sectional image.

[0058] In this embodiment, a 3D memory chip is used as an example. However, the chip failure point location method of the present invention is applicable to the analysis and testing of internal open circuit failure points of various chips with stacked metal layer designs. The specific testable chips are not described in detail here.

[0059] Figure 3 A schematic cross-sectional view of a chip failure point location method according to an embodiment is shown.

[0060] Reference Figure 3 In one embodiment, a chip failure point location method first supplies current to the edge circuit of the chip 100 based on the EBAC technology, confirms the positions of the first top metal layer 101 and the second top metal layer 102 based on the image of the light and dark difference, then intercepts the chip 100 along the AA line, removes part of the edge structure of the chip 100, and exposes the electrical circuit of the outermost circuit (the electrical circuit where the failure point at the edge is located).

[0061] Figure 4FIG. 1 is a schematic cross-sectional view of an edge structure of a chip according to an embodiment.

[0062] Reference Figure 4 The electrical circuit 20 where the failure point is located is stacked in the depth direction of the chip 100, and is located on the structural layer 120 on the substrate 110 of the chip 100. The other parts of the structural layer 120 are insulating materials, and the first top metal 101 and the second top metal 102 are exposed on the top of the structural layer 120.

[0063] On the AA cross section (sample cross section), at least the first top metal 101 and the second top metal 102 are directly exposed so that the nanoprobe P can directly communicate with the first top metal 101 and the second top metal 102, so that the communication current channel CUR can communicate with the first top metal 101, and the communication ground channel GND can communicate with the second top metal 102, thereby providing current to the electrical circuit 20 (composed of multiple stacked and connected metal layers) where the failure point is located.

[0064] In this embodiment, a protective base layer 40 is also provided on the top layer of the chip 100 to protect the top surface structure of the chip 100, reduce damage to the surface structure of the chip 100 during the slicing operation, and ensure the reliability of subsequent testing. The protective base layer 40 is, for example, an insulating material such as a glass layer or a resin layer.

[0065] Figure 5 A schematic structural diagram of a chip fixing device according to an embodiment is shown.

[0066] like Figure 5 As shown, the chip 100 after the edge structure is removed is further fixed by the fixing platform 200, so that the AA cross section faces the nano-probe platform and corresponds to the nano-probe P.

[0067] Figure 6A and Figure 6B A schematic diagram of a test state of a sample cross section of a chip failure point location method according to an embodiment is shown.

[0068] Reference Figure 6A and Figure 6B In this embodiment, only the first top metal 101 and the second top metal 102 are directly exposed on the AA section, and the other bottom metals are covered by the insulating material of the structural layer 120 and are not directly exposed, which can ensure the structural integrity of the electrical circuit where the failure point is located and the reliability of detection and analysis.

[0069] like Figure 6A As shown, when the scanning electron microscope is in a low-voltage working state, only the first top metal layer 101 can be observed to be in a bright state, while the second top metal layer 102 and other electrical circuits covered by insulating materials are in a dark state.

[0070] By adjusting the acceleration voltage, electron beam current and other parameters of the scanning electron microscope, such as Figure 6B As shown, by increasing the output power of the scanning electron microscope, the light and dark metal winding image on the AA section can be observed through the insulating material. The depth position of the failure point can be confirmed based on the intersection 23 of the bright first electrical circuit 21 and the dark second electrical circuit 22.

[0071] Among them, by further referring to the circuit structure layout of chip 100, the process steps corresponding to the open circuit position can be confirmed according to the obtained depth position, and the specific parameters of the corresponding process steps can be adjusted to optimize the performance of chip 100 and improve the production yield of the chip.

[0072] The chip failure point locating method provided by the present invention removes the edge structure of the chip to expose parts of multiple metal layers on the cross section of the chip, provides current to the chip through the exposed metal layer, and obtains a cross-sectional image of the chip cross section under current drive through EBAC (E-Beam Absorbance Current) technology. The depth position of the failure point is directly located according to the position of the intersection of the light and dark areas of the cross-sectional image. There is no need to remove the chip layers multiple times, and the bottom metal at different depths is gradually exposed for multiple tests. This effectively improves the analysis and testing speed of the depth position of the failure point, providing convenience for chip research and development.

[0073] Furthermore, a protective substrate is provided on the upper surface of the chip to reduce the risk of chip breakage during the operation of removing edge structures during cross-section sampling, thereby ensuring the structural reliability of the chip after cross-section sampling, reducing interference factors in analysis and testing, and ensuring test efficiency.

[0074] Furthermore, the cross-sectional sampling is performed to expose the side of the top metal layer of the chip, so that the chip exposes at least part of its multiple stacked metal layers, and keeps the other metal layers from being damaged by the cross-sectional sampling, thereby ensuring the original connection relationship of the metal layers and ensuring the reliability of the failure point location obtained by analysis and testing.

[0075] Furthermore, before performing deep position location, planar location is also performed using the same EBAC technology, eliminating the need for combining other location technologies. This reduces hardware requirements and costs for analysis and testing. Combining the planar and depth locations of the failure point allows for convenient confirmation of the failure point's three-dimensional location. Furthermore, for good chips confirmed to have no failure points after planar location, depth location is no longer necessary, saving analysis and testing resources.

[0076] Furthermore, by selecting a portion of the chip cross section for EBAC technology testing based on the planar position of the failure point, the driving area of the EBAC and the scanning area of the electron microscope can be reduced, the driving power consumption and the scanning time can be reduced, the analysis and testing costs can be reduced, the test cycle can be shortened, and the analysis and testing efficiency can be improved.

[0077] Furthermore, the plane position and depth position of the failure point can be directly obtained based on the overall image of the chip's cross-sectional image in combination with the overall design layout of the chip, which can reduce the overall number of operations and simplify the analysis and testing process.

[0078] While embodiments of the present invention have been described above, these embodiments do not exhaustively describe all details and do not limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for locating a failure point of a chip, wherein the chip comprises a plurality of stacked metal layers, comprising: removing an edge structure of the chip to obtain a cross section of the chip; providing a current on at least one of the plurality of metal layers in the chip; Obtaining a cross-sectional image of the chip under current driving under an electron microscope; wherein, The junction of the light and dark areas of the cross-sectional image is the location of the failure point. The step of removing the edge structure of the chip comprises: The cross-section is prepared until the side of the top metal layer of the chip is exposed, and the cross-section of the chip at least exposes the top metal layer at the edge position of the chip.

2. The chip failure point location method according to claim 1, wherein: Before the step of removing the edge structure of the chip, the method further includes: A protective base layer is provided on the upper surface of the chip.

3. The chip failure point location method according to claim 2, wherein: The protective substrate layer is a glass layer.

4. The chip failure point location method according to claim 1, wherein: In the step of obtaining a cross-sectional image of the chip under current driving under an electron microscope, the chip is further fixed by a fixing table, and the cross section of the chip is directed toward the nanoprobe station.

5. The chip failure point location method according to claim 1, wherein: The step of providing current on at least one of the plurality of metal layers in the chip comprises: The metal layers corresponding to the input end and the output end of the plurality of metal layers are connected to the current channel and the ground channel respectively through the nanoprobe.

6. The chip failure point location method according to claim 1, wherein: The step of obtaining a cross-sectional image of the chip under current driving under an electron microscope comprises: Adjust the acceleration voltage and electron beam current of the scanning electron microscope to obtain a cross-sectional image of the chip. The intersection of the light and dark areas of the cross-sectional image is the location of the failure point, wherein: At least part of the bright area of the cross-sectional image is not directly exposed on the cross section of the chip.

7. The chip failure location method according to claim 1, wherein: Before the step of removing the edge structure of the chip, the method further includes: Performing a de-layering operation to peel off the upper surface structure of the chip until the top metal layer of the chip is exposed; providing current to the chip through the top metal layer; Obtaining a planar image of the upper surface of the chip under current driving under an electron microscope; The plane position of the failure point on the top view of the chip is obtained according to the position of the boundary between the light and dark areas of the plane image.

8. The chip failure point location method according to claim 7, wherein: The step of providing current on at least one of the plurality of metal layers in the chip further comprises: According to the planar position of the failure point on the top view of the chip, a top metal layer close to the failure point is selected to connect the current channel and the ground channel.

9. The chip failure point location method according to claim 1, wherein: The position of the boundary between the light and dark areas of the cross-sectional image includes the plane position of the failure point on the top view of the chip and the depth position of the failure point in the depth direction of the chip.

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