Semiconductor memory device

Abstract

The semiconductor memory device according to the embodiment has: a memory cell array having a plurality of nonvolatile memory cells; a sequencer that controls the sequence of a read operation for reading data from the memory cell array; and a column decoder; and the sequencer controls the following sequence: after receiving a read instruction and an address signal, changing the ready / busy signal from ready to busy, after changing the ready / busy signal to busy, reading data from the memory cell array using a sense amplifier, after storing the data in a data latch circuit, changing the ready / busy signal from busy to ready, after changing the ready / busy signal to ready, receiving a data output instruction, and when a first condition occurs, writing log data including the data stored in the data latch circuit to a storage area of the memory cell array.

Description

[0001] Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2020-152510 (filing date: September 11, 2020). This application incorporates all the contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Art

[0004] Since it is impossible to obtain sufficient data for defect analysis of a semiconductor memory device, defect analysis is sometimes difficult. Summary of the Invention

[0005] Embodiments provide a semiconductor memory device capable of storing data for defect analysis.

[0006] The semiconductor memory device according to the embodiment includes: a memory cell array including a plurality of blocks and capable of storing first data; a sequencer that controls a sequence based on a read operation, the read operation being to read the first data from the memory cell array based on a read command received from a memory controller; and a column decoder including a sense amplifier and a data latch circuit, the sense amplifier performing a sensing operation required for reading the first data from the memory cell array, and the data latch circuit storing the first data; and at least one of the plurality of blocks has first and second selection transistors and a plurality of non-volatile memory cells connected in series between the first and second selection transistors, and the sequencer controls the following sequence: receiving the read command and an address signal, after receiving the read command and the address signal, changing a ready / busy signal from ready to busy, after changing the ready / busy signal to the busy, reading the first data from the memory cell array using the sense amplifier, storing the first data in the data latch circuit, after storing the first data in the data latch circuit, changing the ready / busy signal from the busy to the ready, after changing the ready / busy signal to the ready, receiving a data output command, after receiving the data output command, outputting the first data stored in the data latch circuit to the memory controller, and when a first condition occurs, writing log data including the first data stored in the data latch circuit to a storage area of the memory cell array. Brief Description of the Drawings

[0007] Figure 1 It is a block diagram showing the configuration of a memory system according to the first embodiment.

[0008] Figure 2 This is a circuit diagram showing the configuration of the memory cell array of the first embodiment.

[0009] Figure 3 This is a memory map showing the storage area of the memory cell array of the NAND (Negative AND) type flash memory of the first embodiment.

[0010] Figure 4 This is a memory map showing an example of a specific storage area in which a plurality of log data storage areas are arranged separately in the first embodiment.

[0011] Figure 5 This is a timing diagram showing the timing of data transmission and reception between the memory controller and the NAND type flash memory when executing data readout in the first embodiment.

[0012] Figure 6 This is a diagram showing the read instruction sequence of data in the first embodiment.

[0013] Figure 7 This is a flowchart showing an example of the log data saving process performed by the sequencer when an ECC (Error Check and Correction) error occurrence information is received in the first embodiment.

[0014] Figure 8 This is a diagram showing the process of saving log data to a specific storage area when a read error occurs in the first embodiment.

[0015] Figure 9 This is a timing diagram showing the timing of data transmission and reception between the controller and the NAND type flash memory when executing data write in the second embodiment.

[0016] Figure 10 This is a diagram showing the write instruction sequence of data in the second embodiment.

[0017] Figure 11 This is a flowchart showing an example of the log data saving process performed by the sequencer when a write error occurs in the second embodiment.

[0018] Figure 12 This is a diagram showing the process of saving log data to a specific storage area when a write error occurs in the second embodiment.

[0019] Figure 13 This is a timing diagram showing the timing of data transmission and reception between the controller and the NAND type flash memory when executing data write in a modified example of the second embodiment.

[0020] Figure 14 This is a flowchart showing an example of the log data saving process performed by the sequencer when a write error occurs in a modified example of the second embodiment.

[0021] Figure 15 This is a flowchart showing an example of the log data saving process performed by the sequencer when an error occurs in the third embodiment.

[0022] Figure 16 This is a diagram showing the process of saving log data to a specific storage area when certain errors occur in the third embodiment. Detailed implementation manners

[0023] Hereinafter, the embodiments will be described with reference to the drawings.

[0024] (First Embodiment)

[0025] The memory system of the first embodiment will be described. Hereinafter, a memory system including a NAND type flash memory will be described as an example.

[0026] [Overall Configuration of Memory System]

[0027] First, use Figure 1 to describe the general overall configuration of the memory system of this embodiment.

[0028] Figure 1 This is a block diagram showing the configuration of the memory system of this embodiment. As shown in the figure, the memory system 1 includes a NAND type flash memory (hereinafter referred to as a NAND memory) 100 and a memory controller (hereinafter also simply referred to as a controller) 200. The NAND memory 100 and the controller 200 are formed on, for example, one substrate. The memory system 1 is used for, for example, a memory card such as an SD (Secure Digital) card or an SSD (Solid State Drive).

[0029] The NAND memory 100 is a non-volatile memory. The NAND memory 100 includes a plurality of memory cells and stores data non-volatily. The controller 200 is connected to the NAND memory 100 through a NAND bus. The controller 200 is connected to a host machine 300 (shown by a dotted line) through a host bus. Moreover, the controller 200 is a memory controller that controls the NAND memory 100 and accesses the NAND memory 100 in response to a request received from the host machine 300. The host machine 300 is, for example, a digital camera or a personal computer, and the host bus is a bus that conforms to, for example, the SD interface. The NAND bus is a bus for signal transmission and reception that conforms to the NAND interface.

[0030] Various signals are transmitted and received between the NAND memory 100 and the controller 200 via the NAND interface (I / F) circuit 250. A chip enable signal CEn, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and a write protect signal WPn are supplied from the controller 200 to the NAND memory 100. A ready / busy signal RBn is supplied from the NAND memory 100 to the controller 200. Input / output signals I / O and data strobe signals DQS / DQSn are transmitted and received between the controller 200 and the NAND memory 100.

[0031] The chip enable signal CEn is a signal for enabling the NAND memory 100 and is effective at a low level. The instruction latch enable signal CLE and the address latch enable signal ALE are signals for notifying the NAND memory 100 that the input / output signals I / O are an instruction and an address, respectively. The write enable signal WEn is effective at a low level and is a signal for notifying the NAND memory 100 that the input / output signal I / O is to be written to the NAND memory 100. The read enable signal REn is also effective at a low level and is a signal for enabling the read data from the NAND memory 100 to be output to the input / output signal I / O. The write protect signal WPn is a signal for instructing the NAND memory 100 to prohibit data writing and erasing. The data strobe signals DQS / DQSn are signals for controlling the input / output timing of the input / output signals I / O.

[0032] The ready / busy signal RBn is a signal indicating that the NAND memory 100 is in a ready state (a state capable of receiving commands from the controller 200) or a busy state (a state unable to receive commands from the controller 200), and a low level indicates the busy state. The input / output signal I / O is, for example, an 8-bit signal. Moreover, the input / output signal I / O is the entity of the data transmitted and received between the NAND memory 100 and the controller 200 and is an instruction, an address, write data, read data, etc.

[0033] [Configuration of the controller)

[0034] Next, the detailed configuration of the controller 200 will be described. As Figure 1 shown, the controller 200 is a circuit including a host interface (I / F) circuit 210, a random access memory (hereinafter referred to as RAM) 220, a processor 230 having a central processing unit (CPU), a buffer memory 240, a NAND interface circuit 250, and an ECC (Error Checking and Correcting) circuit 260.

[0035] The host interface circuit 210 is connected to the host machine 300 via the host bus, and transmits the requests and data received from the host machine 300 to the processor 230 and the buffer memory 240 respectively. In addition, in response to the instructions of the processor 230, the data in the buffer memory 240 is transmitted to the host machine 300.

[0036] The RAM 220 is a semiconductor memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), for example. The RAM 220 is used as the working area of the processor 230. Also, the RAM 220 stores the firmware for managing the NAND memory 100 or the management information MI. The management information MI is a look-up table (LUT), conversion table information (TBL), etc. The conversion table information TBL includes conversion information. The conversion information is information for converting the data read level when the controller 200 performs the data read process.

[0037] The processor 230 controls the overall operation of the controller 200. For example, when the processor 230 receives a data read request from the host machine 300, it issues a read instruction to the NAND interface circuit 250 in response to the data read request. When receiving a data write request and a data erase request from the host machine 300, the processor 230 similarly issues an instruction corresponding to the received request to the NAND interface circuit 250. In addition, the processor 230 executes various processes for managing the NAND memory 100, such as wear leveling.

[0038] The buffer memory 240 temporarily stores the write data or the read data.

[0039] The NAND interface circuit 250 is connected to the NAND memory 100 via the NAND bus and manages the communication with the NAND memory 100. Also, the NAND interface circuit 250 sends various signals including instructions and data to the NAND memory 100 based on the instructions received from the processor 230, and receives various signals and data from the NAND memory 100.

[0040] Based on the instructions received from the processor 230, the NAND interface circuit 250 outputs the chip enable signal CEn, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn to the NAND memory 100. Additionally, when writing data, the NAND interface circuit 250 transmits the write instruction issued by the processor 230 and the write data in the buffer memory 240 to the NAND memory 100 in the form of input / output signals I / O. Further, when reading data, the NAND interface circuit 250 transmits the read instruction issued by the processor 230 to the NAND memory 100 in the form of input / output signals I / O, and then receives the data read from the NAND memory 100 in the form of input / output signals I / O and transmits it to the buffer memory 240.

[0041] The ECC circuit 260 performs error detection and error correction processing related to the data stored in the NAND memory 100. That is, the ECC circuit 260 generates error correction symbols when writing data and assigns them to the written data. When reading data, it corrects errors and decodes the data at the same time. When the ECC circuit 260 fails to decode the read data, it notifies the processor 230 of the ECC error.

[0042] [Configuration of NAND Flash Memory]

[0043] Next, the configuration of the NAND memory 100 will be described. As Figure 1 shown, the NAND memory 100 includes a memory cell array 110, a row decoder 120, a driver circuit 130, a column decoder 140, an address register 150, an instruction register 160, a sequencer 170, a register unit 180, and a temperature sensor 190.

[0044] The memory cell array 110 includes a plurality of blocks BLK, and the plurality of blocks BLK include a plurality of non-volatile memory cells corresponding to rows and columns. The block BLK is used as, for example, an erasure unit of data. In Figure 1 it, four blocks BLK0 to BLK3 are shown as an example. Moreover, the memory cell array 110 stores the data provided by the controller 200 non-volatily.

[0045] Based on the block address BA in the address register 150, the row decoder 120 selects any one of the blocks BLK0 to BLK3, and further selects the word line WL in the selected block BLK.

[0046] Based on the page address PA in the address register 150, the driver circuit 130 supplies voltage to the selected block BLK via the row decoder 120.

[0047] The column decoder 140 includes a data latch circuit XDL and sense amplifiers SA. The sense amplifiers SA include a plurality of sense amplifier circuits. When reading out data, the sense amplifiers SA perform a sensing operation. The sensing operation senses the data read out from the memory cell array 110 and performs necessary operations. The data latch circuit XDL includes a plurality of latch circuits for input / output of data. Moreover, the column decoder 140 outputs the read data DAT to the controller 200 via its data latch circuit XDL. When writing data, after the data latch circuit XDL has received the write data DAT from the controller 200, the column decoder 140 performs a write operation on the memory cell array 110.

[0048] The read data and the write data are user data. The data latch circuit XDL has a user data storage section. The user data storage section is a circuit part capable of storing user data. The data latch circuit XDL also has a redundant section that can also store the following address information, etc. That is, the data latch circuit XDL can store the read data, the write data, and the address information, etc.

[0049] In addition, in the present embodiment and other embodiments, an example in which the user data storage section and the redundant section are provided in the data latch circuit XDL is described, but they may also be provided in other data latch circuits, such as the data latch circuits ADL and BDL. That is, the data latch circuits ADL, BDL, or CDL may also be used as the data latch circuit for temporarily storing the following log data.

[0050] The address register 150 stores the address ADD received from the controller 200. The address ADD includes the block address BA and the page address PA. That is, the address register 150 stores address information. The instruction register 160 stores the instruction CMD received from the controller 200.

[0051] The sequencer 170 is a control circuit that controls the overall operation of the NAND memory 100 based on the instruction CMD stored in the instruction register 160.

[0052] Based on the instruction CMD from the controller 200, the sequencer 170 performs data readout, data write, and data erase.

[0053] Furthermore, the sequencer 170 performs a log data saving process in the following manner. Therefore, the sequencer 170 can obtain the address from the address register 150. Furthermore, the sequencer 170 can transfer data to the column decoder 140.

[0054] The register unit 180 includes a plurality of registers. Temperature codes of the temperature sensor 190, etc. can be stored in the register unit 180.

[0055] The temperature sensor 190 generates a temperature code representing the temperature of the NAND memory 100. The sequencer 170 periodically (e.g., for each operation) acquires the temperature code. The temperature code is temperature information of the NAND memory 100. The temperature code is usage status data of the NAND memory 100.

[0056] Next, the configuration of the block BLK will be described using Figure 2 FIG. Figure 2 is a circuit diagram showing the configuration of the memory cell array of the present embodiment. As shown in the figure, one block BLK includes, for example, four string units SU (SU0 to SU3). In addition, each string unit SU includes a plurality of NAND strings 6.

[0057] Each NAND string 6 includes, for example, eight memory cell transistors MT (MT0 to MT7) and two select transistors ST1, ST2. Each memory cell transistor MT has a control gate and a charge storage layer, and stores data non-volatilely. Moreover, a plurality of (e.g., eight) memory cell transistors MT are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2.

[0058] The gates of the select transistors ST1 in each of the string units SU0 to SU3 are respectively connected to the select gate lines SGD0 to SGD3. In contrast, the gates of the select transistors ST2 in each of the string units SU0 to SU3 are commonly connected to, for example, the select gate line SGS. Of course, the gates of the select transistors ST2 in each of the string units SU0 to SU3 may also be connected to different select gate lines SGS0 to SGS3 in units of string units. In addition, the control gates of the memory cell transistors MT0 to MT7 located within the same block BLK are commonly connected to the word lines WL0 to WL7, respectively.

[0059] In addition, the drains of the select transistors ST1 of the plurality of NAND strings 6 located in the same column within the memory cell array 110 are commonly connected to the bit line BL (BL0 to BL(K−1), where K is a natural number of 2 or more). That is, the bit line BL commonly connects the plurality of NAND strings 6 between the plurality of blocks BLK. Further, the sources of the plurality of select transistors ST2 are commonly connected to the source line SL.

[0060] That is, each string unit SU includes a plurality of NAND strings 6 connected to a plurality of different bit lines BL and connected to the same select gate line SGD. In addition, each block BLK includes a plurality of string units SU. Moreover, the memory cell array 110 is an aggregate of a plurality of blocks BLK to which each bit line BL is commonly connected.

[0061] Figure 3 is a memory map of the storage area of the memory cell array 110 of the NAND memory 100.

[0062] In the memory cell array 110, in addition to the storage area for storing user data, there is a specific storage area PMA that does not write user data. The specific storage area PMA is a storage area different from the storage area for storing user data. Thus, user data is not written to the specific storage area PMA.

[0063] The specific storage area PMA includes a plurality of log data storage areas PMAp. Each log data storage area PMAp has a data size capable of storing a plurality of log data LD.

[0064] The log data LD has a data part DP including the following error occurrence data and a redundant part RP including address information (including information including a block address BA and a page address PA). The data part DP including the error occurrence data corresponds to the user data storage part of the data latch circuit XDL, and the redundant part RP including the address information (block address BA and page address PA) corresponds to the redundant part of the data latch circuit XDL.

[0065] In Figure 3 the specific storage area PMA has a plurality of log data storage areas PMAp. Each log data storage area PMAp includes at least one block BLK. Each block BLK includes a plurality of pages. Reading data from the memory cell array 110 and writing data to the memory cell array 110 are performed in units of pages, which are a set of multi-bit data. Each page can be specified by a page address PA. One log data LD can be stored in each page. Thus, one log data LD is stored in one page in one block BLK in the specific storage area PMA. Within one block BLK, the log data LD is sequentially stored in a plurality of consecutive pages. When each log data storage area PMAp includes a plurality of blocks BLK, if the log data LD is stored in all pages within one block BLK, the log data LD is stored in the next block BLK within the specific storage area PMA. Thus, by incrementing, for example, the page address PA in the specific storage area PMA one by one after saving the log data LD, the saved log data LD can be saved while storing the next log data LD. The address for storing the next log data LD is specified by an address index managed by the sequencer 170. Here, after saving one log data LD, the page address PA indicated by the address index is incremented one by one, but it is also possible to increment the page address PA indicated by the address index in units of a specific number such as two or three, and change the page address PA indicating the address for storing the next log data LD.

[0066] Figure 4 is a memory map showing an example of the specific storage area PMA in which a plurality of log data storage areas PMAp are arranged separately.

[0067] InFigure 4 Among them, two log data storage areas PMAp are arranged at intervals. In each block BLK of the log data storage area PMAp, a page address PA is incremented each time log data LD is stored, so that the saved log data LD can be saved while the next log data LD is stored. If the log data LD is stored in all pages within a block BLK, after saving the log data LD, the block number is incremented one by one, for example, so that the saved log data LD can be saved while the next log data LD is stored in the next block BLK. If the log data LD is stored in all pages of all blocks BLK within a log data storage area PMAp, the block address BA and page address PA of another log data storage area PMAp are specified, and the log data LD is stored in the other log data storage area PMAp.

[0068] [Log data saving process when read error occurs]

[0069] As described above, the sequencer 170 performs data reading, data writing, and data erasing based on the instruction CMD from the controller 200. This embodiment relates to the saving of the log data LD when a read error occurs.

[0070] Figure 5 It is a timing chart showing the timing of data transmission and reception between the controller 200 and the NAND memory 100 when data reading is performed.

[0071] After the read instruction is issued from the controller 200 to the NAND memory 100, the sequencer 170 performs a read operation (P1). That is, the sequencer 170 reads data from the NAND memory 100 according to the read instruction and stores the read data in the data latch circuit XDL. During the read operation (P1), the ready / busy signal becomes busy, and the status register in the register unit 180 is also set to a state indicating busy. After the read operation ends, the ready / busy signal becomes the ready state (P1a), and the status register is also set to a state indicating ready. The controller 200 can confirm the state of the status register by issuing a status read instruction. The controller 200 determines that the read operation has been completed based on the ready / busy signal or the state of the status register.

[0072] The controller 200 issues a data output instruction to the NAND memory 100. The sequencer 170 outputs the data in the data latch circuit XDL to the controller 200 according to the data output instruction. That is, the sequencer 170 outputs the read data to the memory controller 200.

[0073] In the controller 200, the received data is subjected to error detection and error correction by the ECC circuit 260. When an error is detected in the received data and the error correction fails, the processor 230 sends an ECC error occurrence message to the NAND memory 100.

[0074] When an ECC error occurs, the processor 230 performs a process of setting the block where the ECC error has occurred as a bad block (defective block).

[0075] If the sequencer 170 receives an ECC error occurrence message, it executes a prohibition process (P2) of prohibiting the acceptance of a specific instruction. Here, the specific instruction is an instruction accompanied by a situation where the data stored in the data latch circuit XDL is updated by the memory controller 200. After executing the prohibition process P2, the read data remains stored in the data latch circuit XDL. The sequencer 170 executes a log data storage process (P3).

[0076] As described above, when the sequencer 170 receives a notification of a read error, after performing a process of prohibiting the update of the data in the data latch circuit XDL, it writes specific data to a specific storage area PMA.

[0077] Figure 6 It is a diagram showing a read instruction sequence of data. In the read instruction sequence, the sequencer 170 first outputs a reservation instruction "c01". After outputting the reservation instruction "c01", it outputs an instruction "c02". The instruction "c02" notifies the execution of a read operation. When the instructions "c01" and "c02" are output, the instruction latch enable signal CLE becomes high. After the output of the instructions "c01" and "c02" ends, the instruction latch enable signal CLE becomes low. After outputting the instruction "c02", it outputs address data including two column addresses "CA1", "CA2" and three row addresses "RA1", "RA2", "RA3". When the address data "CA1", "CA2", "RA1", "RA2", "RA3" is output, the address latch enable signal ALE becomes high. After the output of the address data ends, the address latch enable signal ALE becomes low. Following the address data, it outputs an instruction "c03" indicating the execution of a read operation. When the instruction "c03" is output, the instruction latch enable signal CLE becomes high. After the output of the instruction "c03" ends, the instruction latch enable signal CLE becomes low. After outputting the instruction "c03", the ready / busy signal RBn becomes low.

[0078] After the ready / busy signal RBn goes high, the controller 200 outputs a data output instruction. First, the instruction "c04" is output. The instruction "c04" notifies the execution of the data output operation. When the instruction "c04" is output, the instruction latch enable signal CLE goes high. After the output of the instruction "c04" ends, the instruction latch enable signal CLE goes low. After outputting the instruction "c04", five address data are output. When the address data are output, the address latch enable signal ALE goes high. After the output of the address data ends, the address latch enable signal ALE goes low. Following the address data, the instruction "c05" indicating the execution of the data output operation is output. When the instruction "c05" is output, the instruction latch enable signal CLE goes high. After the output of the instruction "c05" ends, the instruction latch enable signal CLE goes low. After outputting the instruction "c05", the sequencer 170 outputs the data of the data latch circuit XDL.

[0079] By executing the read instruction in the above-described manner, the controller 200 can read data from the NAND memory 100.

[0080] Figure 7 It is a flowchart showing an example of the log data saving process of the sequencer 170 when an ECC error occurrence message is received.

[0081] The sequencer 170 determines whether an ECC error occurrence message is received (S1). If an ECC error occurrence message is received, the sequencer 170 executes the processes from S2 and below. If an ECC error occurrence message is not received (S1: No), the sequencer 170 does not execute the processes from S2 and below.

[0082] If an ECC error occurrence message is received (S1: Yes), the sequencer 170 executes a specific prohibition process P2 (S2). The specific prohibition process P2 is a prohibition process for prohibiting acceptance of an instruction accompanied by an update of the data latch circuit XDL.

[0083] For example, the prohibition process P2 makes the ready / busy signal RBn go low and supplies it from the NAND memory 100 to the controller 200. When the ready / busy signal RBn is low, the controller 200 does not output an instruction to the NAND memory 100.

[0084] After S2, the sequencer 170 writes the address information where the ECC error occurred into the redundant part of the data latch circuit XDL (S3).

[0085] After S3, sequencer 170 transfers the data with an ECC error (i.e., error-occurred data) and the address information from data latch circuit XDL to a data storage area of a specific storage area PMA (S4). That is, after receiving the notification of a read error from memory controller 200, sequencer 170 writes specific data to the specific storage area PMA. The specific data includes the read data and the address information related to the read instruction. Specifically, sequencer 170 writes the data of data latch circuit XDL as log data LD to a data storage area of the specific storage area PMA.

[0086] Sequencer 170 increments the address of the address index of the specific storage area PMA (S5). The address information of the address index is stored in the specific storage area PMA.

[0087] As described above, the specific storage area PMA has a plurality of log data storage areas PMAp. Sequencer 170 manages the address index. The address index indicates the address of the log data storage area PMAp in the specific storage area PMA where the next log data LD is to be stored. After sequencer 170 writes the log data LD to the log data storage area PMAp, it increments the address of the log data storage area PMAp. The value (address) of the address index is changed by incrementing by 1, and in the log data storage area PMAp where the log data LD has been written once, the data is not overwritten. As a result, the log data LD is saved.

[0088] As described above, after sequencer 170 writes specific data to the specific storage area PMA, it performs a process of protecting the specific data written to the specific storage area PMA.

[0089] The error-occurred data and the address information (block address BA and page address PA) are stored in the log data storage area PMAp.

[0090] Figure 8 It is a diagram showing the process of saving log data to the specific storage area PMA when a read error occurs.

[0091] When controller 200 cannot correct the ECC of the read data, it outputs the ECC error-occurred information to NAND memory 100. Sequencer 170 saves the log data LD of data latch circuit XDL to the specific storage area PMA in storage cell array 110.

[0092] The log data LD is stored in the storage area at the address indicated by the address index in the storage area PMA.

[0093] As described above, according to the first embodiment, in the memory system 1, when a read error occurs, the sequencer 170 autonomously stores the log data LD in a specific storage area PMA of the NAND memory 100. The log data LD includes error occurrence data related to the read error and its address information (block address BA and page address PA). Thus, it is possible to perform defect analysis using the log data LD in the NAND memory 100.

[0094] (Second Embodiment)

[0095] In the first embodiment, when a read error occurs, the log data LD is saved. However, in the second embodiment, when a write error occurs, the log data LD is saved in the specific storage area PMA.

[0096] The configuration of the memory system according to the second embodiment is the same as the configuration of the memory system 1 according to the first embodiment. The configurations of the NAND memory 100 and the memory controller 200 are also the same as the configurations of the NAND memory 100 and the memory controller 200 according to the first embodiment, respectively. Thus, the same components are denoted by the same reference numerals and their descriptions are omitted.

[0097] [Log Data Saving Process When a Write Error Occurs]

[0098] Figure 9 It is a timing diagram showing the timing of data transmission and reception between the controller 200 and the NAND memory 100 when data writing is performed.

[0099] After a write command is issued from the controller 200 to the NAND memory 100, the sequencer 170 performs a write operation (P11). The write operation includes a programming operation and a verification operation. The programming operation is an operation of increasing the threshold (or prohibiting injection to maintain the threshold) by injecting electrons into the charge storage layer. The verification operation is an operation of determining whether the threshold of the memory cell transistor MT has reached the target level by reading data after the programming operation.

[0100] During the write operation (P11), the ready / busy signal becomes busy, and the status register in the register unit 180 is also set to a status indicating busy. After the write operation ends, the ready / busy signal becomes ready (P11a), and the status register is also set to a status indicating ready. The controller 200 issues a status read command to the NAND memory 100. The sequencer 170 performs a status read process (P12) according to the status read command. The status read process is a process of reading status data indicating whether the write operation was successful or failed.

[0101] When the sequencer 170 fails in a write operation (i.e., a write error occurs), it executes a prohibition process (P13) to prohibit accepting specific instructions. Here, the specific instructions are those accompanied by a situation where the data stored in the data latch circuit XDL is updated by the memory controller 200. After the prohibition process P13, the written data (expected value), i.e., the data with a write error, remains unchanged in the data latch circuit XDL.

[0102] The sequencer 170 outputs status data to the controller 200.

[0103] When the sequencer 170 fails in a write operation, after outputting the status data, it executes a log data saving process (P14).

[0104] As described above, when a write error occurs, the sequencer 170, after performing a process to prohibit data update in the data latch circuit XDL, writes specific data to a specific storage area PMA.

[0105] Figure 10 It is a diagram showing a write instruction sequence of data. In the write instruction sequence, the sequencer 170 first outputs a reservation instruction "c01". After outputting the reservation instruction "c01", it outputs an instruction "c11". The instruction "c11" notifies the execution of a write operation. When the instructions "c01" and "c11" are output, the instruction latch enable signal CLE becomes high. After the output of the instructions "c01" and "c11" ends, the instruction latch enable signal CLE becomes low. After outputting the instruction "c11", it outputs address data including two column addresses "CA1", "CA2" and three row addresses "RA1", "RA2", "RA3". When the address data "CA1", "CA2", "RA1", "RA2", "RA3" is output, the address latch enable signal ALE becomes high. After the output of the address data ends, the address latch enable signal ALE becomes low. Following the address data, it outputs the write data. The sequencer 170 saves the data written to the data latch circuit XDL. Following the write data, it outputs an instruction "c12" indicating the execution of a write operation. When the instruction "c12" is output, the instruction latch enable signal CLE becomes high. After the output of the instruction "c12" ends, the instruction latch enable signal CLE becomes low. After outputting the instruction "c12", the ready / busy signal RBn becomes low until the write ends.

[0106] By executing the write instruction in the above-described manner, the controller 200 can write data to the NAND memory 100.

[0107] Figure 11 It is a flowchart showing an example of the log data saving process of the sequencer 170 when a write error occurs.

[0108] The sequencer 170 determines whether a write error has occurred (S11). Based on the status data, it determines whether a write error has occurred. During the write operation, in the verification operation after the programming operation, when it is determined that the threshold of the memory cell transistor MT has not reached the target level, a write error has occurred.

[0109] If a write error occurs, the sequencer 170 performs the processing below S12. If no write error occurs, the sequencer 170 does not perform the processing below S12.

[0110] If a write error occurs (S11: Yes), the sequencer 170 performs a specific prohibition process P13 (S12). The specific prohibition process P13 is a process of prohibiting acceptance of an instruction accompanied by an update of the data latch circuit XDL.

[0111] For example, the prohibition process P13 makes the ready / busy signal RBn go low and supplies it from the NAND memory 100 to the controller 200. When the ready / busy signal RBn is low, the controller 200 does not output an instruction to the NAND memory 100.

[0112] After S12, the sequencer 170 writes the address information of the occurrence of the write error to the redundant part of the data latch circuit XDL (S13).

[0113] After S13, the sequencer 170 transfers the data where the write error occurred (i.e., the error-occurring data) and the address information from the data latch circuit XDL to one data storage area of the specific storage area PMA (S14). That is, the sequencer 170 writes data to the NAND memory 100 according to the write instruction. When a data write error occurs in the sequencer 170, specific data is written to the specific storage area PMA. This specific data includes the write data and the address information related to the write instruction. Specifically, the sequencer 170 writes the data of the data latch circuit XDL as log data LD to one data storage area of the specific storage area PMA.

[0114] The sequencer 170 increases the address of the address index of the specific storage area PMA (S15).

[0115] As described above, the specific storage area PMA has a plurality of log data storage areas PMAp. The sequencer 170 manages an address index indicating the address of the log data storage area PMAp in the specific storage area PMA where the next log data LD is stored. After the log data LD is written to the log data storage area PMAp, the address of the log data storage area PMAp is increased. By increasing the address by 1, in the log data storage area PMAp where the log data LD has been written once, the data is not overwritten. As a result, the log data LD is saved.

[0116] As described above, after the sequencer 170 writes specific data to a specific storage area PMA, it performs a process of protecting the specific data written to the specific storage area PMA.

[0117] Error occurrence data and address information (block address BA and page address PA) are stored in the log data storage area PMAp.

[0118] Figure 12 It is a diagram showing the process of saving log data LD to a specific storage area PMA when a write error occurs.

[0119] When there is a write error, the sequencer 170 saves the log data LD of the data latch circuit XDL to a specific storage area PMA in the memory cell array 110.

[0120] The log data LD is stored in the storage area PMA at the address indicated by the address pointer.

[0121] Thus, in the NAND memory 100, when a write error occurs, the sequencer 170 autonomously stores the log data LD in a specific storage area PMA. The log data LD includes error occurrence data related to the write error and its address information (block address BA and page address PA). Thus, it is possible to perform defect analysis using the log data LD in the NAND memory 100.

[0122] Next, a modified example will be described.

[0123] In the second embodiment, when a write error occurs, the error occurrence data and its address information are stored in a specific storage area PMA. However, the error occurrence data and its address information may be stored in a specific storage area PMA each time a write is performed, and the data in the specific storage area PMA may be made unupdatable when a write error occurs.

[0124] Figure 13 It is a timing diagram showing the timing of data transmission and reception between the controller 200 and the NAND memory 100 when executing data writing in the modified example.

[0125] After a write command is issued from the controller 200 to the NAND memory 100, the sequencer 170 performs a write operation (P21) to the address specified by the controller 200.

[0126] The sequencer 170 performs a log data saving process (P22). The log data saving process (P22) is the same as the log data saving process (P14).

[0127] During the write operation (P22), the ready / busy signal becomes busy, and the status register in the register unit 180 is also set to a status indicating busy. After the write operation ends, the ready / busy signal becomes the ready state (P22a), and the status register is also set to a status indicating ready. The controller 200 issues a status read instruction to the NAND memory 100. The sequencer 170 determines whether a write error has occurred based on the status data.

[0128] If a status failure (P23) occurs, status data indicating a write failure is output to the controller 200.

[0129] If a status failure (P23) occurs, after the sequencer 170 outputs the status data, it performs overwrite prohibition processing (P24). In the overwrite prohibition processing (P24), the address index of a specific storage area PMA is incremented. Overwrite prohibition also includes cases where overwriting is restricted for a certain period or a certain number of times.

[0130] Figure 14 It is a flowchart showing an example of the log data saving process of the sequencer 170 when a write error occurs.

[0131] The sequencer 170 performs a write operation (S21) to the address specified by the controller 200.

[0132] After S21, the sequencer 170 writes the address information to the redundant part of the data latch circuit XDL (S22).

[0133] After S22, the sequencer 170 transfers the error occurrence data and the address information from the data latch circuit XDL to a data storage area in a specific storage area PMA (S23).

[0134] The sequencer 170 determines whether a write error has occurred during the execution of the write operation in S21 (S24). If a write error occurs, the sequencer 170 increments the address index of the specific storage area PMA (S25). If no write error occurs, the sequencer 170 proceeds to the process of S21.

[0135] Each time a write operation is continuously executed, if no write error occurs (S24: No), new data (write data) and address information are overwritten to the specific storage area PMA. If a write error occurs (S24: Yes), the sequencer 170 increments the address of the specific storage area PMA (S25). Thus, the log data storage area PMAp storing the data (i.e., the error occurrence data) and the address information is not overwritten.

[0136] As described above, according to the second embodiment and the modification example, in the NAND memory 100, when a write error occurs, log data LD is stored in the specific storage area PMA. The log data LD includes error occurrence data related to the write error and its address information (block address BA and page address PA). Thus, defective analysis can be performed using the log data LD.

[0137] In addition, when the memory cell transistor MT is a TLC (Triple Level Cell, three-level cell) capable of storing 3 bits of data, a QLC (Quad Level Cell, four-level cell) capable of storing 4 bits of data, etc., the specific storage area PMA is preferably a pSLC (pseudo Single Level Cell) area. The pSLC area is an area where data is written in the SLC mode. The SLC mode is a mode in which data is stored in the form of 1-bit data in a memory cell transistor MT capable of storing multi-value data such as TLC or QLC. When writing the log data LD to the pSLC area, the sequencer 170 writes the data in the SLC mode.

[0138] For example, in the case of TLC, as Figure 2 shown by the single-dot chain line in, multiple memory cell transistors MT of each word line WL can store 3 pages of data. When upper-page data is written, it is stored in the first log data storage area of the pSLC. When middle-page data is written, it is stored in the second log data storage area of the pSLC. When lower-page data is written, it is stored in the third log data storage area of the pSLC.

[0139] (Third Embodiment)

[0140] In the first embodiment, when a read error occurs, log data LD is saved. In the second embodiment, log data is saved when a write error occurs. However, in the third embodiment, when certain errors occur, log data LD related to the usage state or operation state of the NAND memory 100 is saved to the specific storage area PMA.

[0141] The configuration of the memory system of the third embodiment is the same as the configuration of the memory system 1 of the first embodiment. The configurations of the NAND memory 100 and the memory controller 200 are also the same as the configurations of the NAND memory 100 and the memory controller 200 of the first embodiment, respectively. Thus, the same reference numerals are used for the same components and the description is omitted.

[0142] Figure 15It is a flowchart showing an example of the save process of the log data LD of the sequencer 170 when an error occurs. In the present embodiment, the temperature code of the temperature sensor 190 is included in the log data LD. The temperature code is acquired by the sequencer 170 and stored as temperature information in the temperature code register of the register unit 180.

[0143] When a read error occurs, the sequencer 170 receives ECC error information from the controller 200. A write error or an erase error is detected in the sequencer 170.

[0144] The sequencer 170 determines whether a certain error such as a read error has occurred (S31).

[0145] If a certain error is detected (S31: Yes), the sequencer 170 executes the processes after S32. If no certain error is detected (S31: No), the sequencer 170 does not execute the processes after S32.

[0146] If a certain error is detected (S31: Yes), the sequencer 170 prohibits accepting a specific instruction (P32). Here, the specific instruction is an instruction accompanied by a case where the data stored in the data latch circuit XDL is updated by the memory controller 200.

[0147] After S32, the sequencer 170 writes the temperature information of the temperature sensor 190 as usage status data to the redundant part of the data latch circuit XDL (S33).

[0148] After S33, the sequencer 170 transfers the temperature information from the data latch circuit XDL to a specific storage area PMA (S34). The error occurrence data and the temperature information are stored in the data latch circuit XDL. The sequencer 170 writes the data of the data latch circuit XDL to the specific storage area PMA.

[0149] As described above, the sequencer 170 writes the temperature information of the temperature sensor 190 to the specific storage area PMA.

[0150] After S34, the sequencer 170 increments the address of the address index of the specific storage area PMA (S35).

[0151] As described above, according to the third embodiment, in the memory system 1, if a certain error occurs, the temperature information is stored as log data LD in the specific storage area PMA. Thus, it is possible to perform defect analysis using the log data LD.

[0152] In addition, in the above-described embodiment, if certain errors occur, log data LD including temperature information is saved, but information other than temperature information may also be included in the log data LD. For example, information on the number of erasures or the number of reads may be included in the log data LD as operation status information of the NAND memory 100 together with the temperature information. The information on the number of erasures or the number of reads is the cumulative number from after factory to the point in time when certain errors occur.

[0153] Moreover, in addition, information related to operation conditions such as the shift amount included in the Set Feature instruction may be included in the log data LD as operation status information.

[0154] That is, the sequencer 170 may also write information on the operation status of the NAND memory 100 to a specific storage area PMA.

[0155] The number of erasures is the number of times of the erase operation executed by the sequencer 170 according to the received instruction. The number of erasures is counted by the sequencer 170 for each block every time an erase instruction is executed and stored in the erase count register in the register unit 180. The counting of the number of erasures may also include the number of erasures in the operation test implemented by the customer.

[0156] The number of reads is the number of times of the read operation executed by the sequencer 170 according to the received instruction. The number of reads is counted by the sequencer 170 for each block every time a read instruction is executed and stored in the read count register in the register unit 180. The counting of the number of reads may also include the number of reads in the operation test implemented by the customer.

[0157] The information related to operation conditions such as the shift amount is information for setting the operation conditions for executing the received instruction. The information related to the operation conditions is stored in the register unit 180. For example, every time a Set Feature instruction is received, the data related to operation conditions such as the shift amount related to the Set Feature instruction is retrieved and stored in the Feature register.

[0158] Figure 16 It is a diagram showing the process of saving log data to a specific storage area PMA when certain errors occur.

[0159] When certain errors occur, the sequencer 170 writes the data stored in at least one of the temperature code register, the erase count register, the read count register, and the Feature register to the redundant part of the data latch circuit XDL.

[0160] The log data LD of the data latch circuit XDL is saved in a specific storage area PMA in the memory cell array 110.

[0161] In addition, error code information indicating that the error that has occurred is a read error, a write error, or an erase error may also be included in the log data LD.

[0162] As described above, according to the third embodiment, in the memory system 1, when a certain error occurs, the sequencer 170 autonomously stores data in the use state or the operation state as the log data LD in the specific storage area PMA. Thus, defective analysis can be performed using the log data LD.

[0163] (Fourth Embodiment)

[0164] In the third embodiment, in the memory system 1, when a certain error occurs, regardless of the type of the error, the log data LD related to the use state or the operation state is stored in the specific storage area PMA. In the fourth embodiment, when a read error occurs, the log data LD including the error occurrence data, the address information (block address BA and page address PA), and information related to at least one of the use state and the operation state is stored in the specific storage area PMA.

[0165] The configuration of the memory system according to the fourth embodiment is the same as the configuration of the memory system 1 according to the first embodiment, and the configurations of the NAND memory 100 and the memory controller 200 are also the same as the configurations of the NAND memory 100 and the memory controller 200 according to the first embodiment, respectively. Thus, the same reference numerals are used for the same components and the description thereof is omitted.

[0166] In the first embodiment, when a read error occurs, the error occurrence data and the address information (block address BA and page address PA) are included in the log data LD. The error occurrence data is stored in the data part DP in the log data LD.

[0167] In contrast, in the fourth embodiment, when a read error occurs, the address information (block address BA and page address PA) and the information in the use state or the operation state are written to the redundant part of the data latch circuit XDL. As a result, the information in the use state or the operation state such as the address information and the temperature information is included in the redundant part RP in the log data LD.

[0168] That is, the instruction received by sequencer 170 is a read instruction from memory controller 200 that controls NAND memory 100. Sequencer 170 reads data from NAND memory 100 according to the read instruction. Sequencer 170 outputs the read data as read data to memory controller 200. After sequencer 170 receives a notification of a read error from memory controller 200, it writes specific data to specific storage area PMA. This specific data includes the read data, address information related to the read instruction, and information on the usage status or operation status of NAND memory 100.

[0169] As described above, according to the fourth embodiment, in memory system 1, when a read error occurs, sequencer 170 autonomously stores log data LD in specific storage area PMA of NAND memory 100. This log data LD includes error occurrence data related to the read error, its address information (block address BA and page address PA), and information on the usage status or operation status. Thus, it is possible to perform defect analysis using log data LD in NAND memory 100.

[0170] (Fifth Embodiment)

[0171] In the third embodiment, in memory system 1, if certain errors occur, regardless of the type of error, log data LD related to the usage status or operation status is stored in specific storage area PMA. In this fifth embodiment, when a write error occurs, log data LD including error occurrence data, address information (block address BA and page address PA), and information related to at least one of the usage status and operation status is stored in specific storage area PMA.

[0172] The configuration of the memory system of the fifth embodiment is the same as the configuration of memory system 1 of the first embodiment, and the configurations of NAND memory 100 and memory controller 200 are also the same as the configurations of NAND memory 100 and memory controller 200 of the first embodiment, respectively. Thus, the same constituent elements are denoted by the same reference numerals and their description is omitted.

[0173] In the second embodiment, when a write error occurs, the log data LD includes error occurrence data and address information. The error occurrence data is stored in data part DP in the log data LD.

[0174] In contrast, in the fifth embodiment, when a write error occurs, address information (block address BA and page address PA) and information on the usage status or operation status are written to the redundant part of data latch circuit XDL. As a result, information on the usage status such as address information and temperature information is included in redundant part RP in the log data LD.

[0175] As described above, according to the fifth embodiment, in the memory system 1, when a write error occurs, the sequencer 170 autonomously stores the log data LD in a specific storage area PMA of the NAND memory 100. The log data LD includes error occurrence data related to the write error, its address information (block address BA and page address PA), and information on the usage status or operation status. Thus, it is possible to perform defect analysis using the log data LD in the NAND memory 100.

[0176] That is, the instruction received by the sequencer 170 is a write instruction from the memory controller 200 that controls the NAND memory 100. The sequencer 170 writes data into the NAND memory 100 according to the write instruction. When a write error of the data occurs, the sequencer 170 writes specific data into the specific storage area PMA. The specific data includes the written data, the address information related to the write instruction, and information on the usage status or operation status of the NAND memory 100.

[0177] In addition, the variation of the second embodiment can also be applied to the fifth embodiment. That is, it is also possible to store the log data LD including error occurrence data, address information, and information related to at least one of the usage status or operation status in the specific storage area PMA every time data is written, and make the data in the specific storage area PMA unable to be updated when a write error occurs.

[0178] As described above, according to each of the embodiments, the sequencer 170 can receive an instruction from the memory controller 200 that controls the data read operation and write operation for the NAND memory 100. When an error occurs in an operation (read operation, write operation, erase operation) corresponding to the received instruction, the sequencer 170 writes specific data into a specific storage area PMA of the NAND memory 100.

[0179] Thus, according to each of the embodiments, it is possible to provide a semiconductor memory device capable of storing data for defect analysis.

[0180] The above-described embodiments and variations can also be combined with each other within the possible range. For example, the variation of the second embodiment can be combined with the third embodiment.

[0181] Several embodiments of the present invention have been described, but these embodiments are illustrated as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or their variations are included in the scope or gist of the invention, and are included in the invention described in the claims and its equivalents.

Claims

1. A semiconductor memory device, characterized in that comprising: a memory cell array including a plurality of blocks capable of storing first data; an sequencer controlling a sequence based on a read operation, the read operation being to read the first data from the memory cell array based on a read instruction received from a memory controller; and a column decoder including: a sense amplifier and a data latch circuit, the sense amplifier performing a sensing operation required for reading the first data from the memory cell array, the data latch circuit storing the first data; and at least one of the plurality of blocks has: a first and a second select transistor, and a plurality of non-volatile memory cells connected in series between the first and the second select transistors; the sequencer controls the following sequence: receiving the read instruction and an address signal, after receiving the read instruction and the address signal, changing a ready / busy signal from ready to busy, after changing the ready / busy signal to busy, reading the first data from the memory cell array using the sense amplifier and storing the first data in the data latch circuit, after storing the first data in the data latch circuit, changing the ready / busy signal from busy to ready, after changing the ready / busy signal to ready, receiving a data output instruction, after receiving the data output instruction, outputting the first data stored in the data latch circuit to the memory controller, when receiving a notification of a read error, writing log data including the first data stored in the data latch circuit to a storage area of the memory cell array; the data latch circuit is capable of storing the first data and address information related to the address signal.

2. The semiconductor memory device according to claim 1, wherein: when receiving the read instruction and the address signal, the sequencer controls the following sequence: receiving an instruction latch enable signal and the read instruction, after receiving the read instruction, receiving an address latch enable signal and the address signal.

3. The semiconductor memory device according to claim 1, wherein: the sequencer controls the following sequence: if receiving the notification of the read error from the memory controller, prohibiting data update of the data latch circuit, after prohibiting the data update, writing the log data to the storage area.

4. The semiconductor memory device according to claim 3, wherein: the sequencer controls the following sequence: after writing the log data to a first area of the storage area, restricting writing to the first area.

5. The semiconductor memory device according to claim 1, wherein: the sequencer manages an address index for controlling an address of the storage area to which the log data should be written, and controls the following sequence: if receiving the notification of the read error from the memory controller, writing the log data to a first area of the storage area based on the address index, after writing to the first area, changing a value of the address index, If the notification of the read error is received again from the memory controller, the log data is written to the second area of the storage area based on the changed address index.

6. The semiconductor memory device according to claim 1, wherein It further includes: a temperature sensor; and a register that stores the temperature information obtained using the temperature sensor; and the log data includes the temperature information stored in the register.

7. The semiconductor memory device according to claim 1, wherein: the log data further includes information on the operation state of the semiconductor memory device, the information on the operation state includes at least one of the following information: information related to the number of executions of the read operation performed by the sequencer, information related to the number of executions of the erase operation performed by the sequencer, and information related to the conditions used in the operations performed by the sequencer.

8. A semiconductor memory device, characterized in that It has: a memory cell array including a plurality of blocks and capable of storing first data; a sequencer that controls a sequence based on a write operation, the write operation being to write the first data to the memory cell array based on a write instruction received from a memory controller; and a column decoder including: a sense amplifier and a data latch circuit, the sense amplifier performing an operation required for writing the first data to the memory cell array, and the data latch circuit storing the first data; and at least one of the plurality of blocks has: a first and a second selection transistor, and a plurality of non-volatile memory cells connected in series between the first and the second selection transistors; the sequencer controls the following sequence: receiving the write instruction, an address signal, and the first data, after receiving the write instruction, the address signal, and the first data, changing the ready / busy signal from ready to busy, storing the received first data in the data latch circuit, after changing the ready / busy signal from ready to busy, using the sense amplifier to write the first data stored in the data latch circuit to the memory cell array, after writing the first data to the memory cell array, changing the ready / busy signal from busy to ready, when a write error occurs, writing log data including the first data stored in the data latch circuit to a storage area of the memory cell array; the data latch circuit can store the first data and address information related to the address signal.

9. The semiconductor memory device according to claim 8, wherein: when the sequencer receives the write instruction, the address signal, and the first data, the sequencer controls the following sequence: receiving an instruction latch enable signal and the write instruction, after receiving the write instruction, receiving an address latch enable signal and the address signal.

10. The semiconductor memory device according to claim 8, wherein: the sequencer controls the following sequence: when the write error occurs, prohibiting data update of the data latch circuit, after prohibiting the data update, writing the log data to the storage area.

11. The semiconductor memory device according to claim 10, wherein: The sequencer controls the following sequence: After writing the log data to the first area of the storage area, writing to the first area is restricted.

12. The semiconductor memory device according to claim 8, wherein: The sequencer Manages an address index for controlling the address of the storage area to which the log data should be written, and controls the following sequence: If the write error occurs, based on the address index, the log data is written to the first area of the storage area, After writing to the first area, the value of the address index is changed, If the write error occurs again, based on the changed address index, the log data is written to the second area of the storage area.

13. The semiconductor memory device according to claim 8, wherein It further has: A temperature sensor; and A register that stores temperature information obtained using the temperature sensor; and The log data includes the temperature information stored in the register.

14. The semiconductor memory device according to claim 8, wherein: The log data further includes information on the operation state of the semiconductor memory device, The information on the operation state includes at least one of the following information: Information related to the number of execution times of the read operation performed by the sequencer, Information related to the number of execution times of the erase operation performed by the sequencer, and Information related to the conditions used in the operations performed by the sequencer.

15. A semiconductor memory device, characterized in that It has: A memory cell array including a plurality of blocks capable of storing first data; A sequencer that controls a sequence based on a write operation, the write operation being to write the first data to the memory cell array based on a write instruction received from a memory controller; And A column decoder including: a sense amplifier and a data latch circuit, the sense amplifier performing an operation required for writing the first data to the memory cell array, and the data latch circuit storing the first data; and At least one of the plurality of blocks has: a first and a second selection transistor, and a plurality of non-volatile memory cells connected in series between the first and the second selection transistors; The sequencer Manages an address index for controlling the address of the storage area of the memory cell array, and Controls the following sequence: Receives the write instruction, an address signal, and the first data, After receiving the write instruction, the address signal, and the first data, changes the ready / busy signal from ready to busy, Stores the received first data in the data latch circuit, After changing the ready / busy signal to the busy state, uses the sense amplifier to write the first data stored in the data latch circuit to the memory cell array, After writing the first data to the memory cell array, based on the address index, writes log data including the first data stored in the data latch circuit to the storage area, After writing the log data to the storage area, changes the ready / busy signal from the busy state to the ready state, When a write error occurs, change the value of the address pointer; The data latch circuit can store the first data and address information related to the address signal.

16. The semiconductor memory device according to claim 15, wherein It further includes: a temperature sensor; and a register that stores the temperature information obtained using the temperature sensor; and the log data includes the temperature information stored in the register.

17. The semiconductor memory device according to claim 15, wherein: the log data further includes information on the operation state of the semiconductor memory device, and the information on the operation state includes at least one of the following information: information related to the number of execution times of the read operation performed by the sequencer, information related to the number of execution times of the erase operation performed by the sequencer, and information related to the conditions used in the operations performed by the sequencer.

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