Resistive memory device, operation method thereof and memory cell array thereof

Abstract

The present invention provides a resistive memory device including a memory cell array, at least one dummy transistor and a control circuit. The memory cell array includes a plurality of memory cells. Each memory cell includes a resistance conversion element. The dummy transistor is electrically insulated from the resistance conversion element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is used to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor so that the dummy transistor outputs a saturation current. The control circuit is used to determine the size of the second bit line voltage driving the memory cell according to the saturation current. In addition, an operating method of a resistive memory device and a memory cell array are also proposed.

Description

Technical Field

[0001] The present invention relates to a memory device and an operating method of the memory device, and more particularly to a resistive memory device, an operating method of the resistive memory device and a memory cell array thereof. Background Art

[0002] The memory cell of the current resistive random access memory (RRAM) generally includes a resistance conversion element and a transistor. The resistance conversion element includes an upper electrode and a lower electrode arranged opposite to each other and a resistance conversion layer located between the upper electrode and the lower electrode. The transistor has a gate connected to a word line, a source connected to a source line, and a drain connected to a first end of the resistance conversion element. Before the resistance conversion element can be repeatedly switched between high and low resistance states to store data, a channel forming process must first be performed. The forming process includes providing a bias voltage, such as a positive bias voltage, to the resistance conversion element through a transistor, so that a current flows from the upper electrode to the lower electrode, so that oxygen vacancies (oxygen vacancy) and oxygen ions (oxygen ions) are generated in the resistance conversion layer to form a current path, so that the resistance conversion element changes from a high resistance state (HRS) to a low resistance state (LRS) to form a conductive filament. Usually, in the formed filament, the diameter of the portion adjacent to the upper electrode is smaller than the diameter of the portion adjacent to the lower electrode. Afterwards, the RRAM can be reset or set so that the resistance conversion element is switched to a high resistance state and a low resistance state, respectively, to complete the data storage. In addition, when resetting the current RRAM, it includes providing a reverse bias voltage with a polarity opposite to that when setting to the resistance conversion element through a transistor, so that the current flows from the lower electrode to the upper electrode. At this time, the oxygen vacancies adjacent to the upper electrode combine with part of the oxygen ions to interrupt the current path, so that the filament is disconnected at the adjacent upper electrode. When setting the current RRAM, it includes providing a bias voltage with the same polarity as when forming the program to the resistance conversion element through a transistor, so that the current flows from the upper electrode to the lower electrode. At this time, the oxygen ions adjacent to the upper electrode are detached, and oxygen vacancies are reformed, so that the filament is reformed at the adjacent upper electrode.

[0003] Generally speaking, the driving capability of transistors will affect the current read from the memory cell (referred to as the cell current). However, before the filament is formed, the driving capability of the transistors in each memory cell cannot be known. As a result, the bit line voltage required to write the resistance conversion element to a specific resistance state cannot be accurately provided, resulting in the current RRAM having to adjust the bit line voltage multiple times during the formation process and each write operation (including reset and set) to ensure that the RRAM is written to a specific resistance state, and the bit line voltage needs to be readjusted during each write operation, thereby reducing the operation speed. In addition, since multiple transistors in the memory array often have process variations, the driving capabilities of these transistors are not consistent, so additional circuits need to be configured to avoid the problem of excessive variation in the cell current under the same operation, which is not conducive to the miniaturization of RRAM. Summary of the invention

[0004] The present invention provides a resistive memory device, an operating method of the resistive memory device and a memory cell array, which are used to improve the above-mentioned problems of low operating speed and disadvantage of miniaturization of the existing RRAM.

[0005] The resistive memory device of the present invention includes a memory cell array, a dummy transistor and a control circuit. The memory cell array includes a plurality of memory cells. Each memory cell includes a resistance conversion element. The dummy transistor is electrically insulated from the resistance conversion element of the memory cell. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is used to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor so that the dummy transistor outputs a saturation current. The control circuit is used to determine the size of a second bit line voltage for driving the memory cell according to the saturation current.

[0006] The operating method of the resistive memory device of the present invention includes: providing a first bit line voltage, a source line voltage and a word line voltage to a dummy transistor to determine the size of a saturation current of the dummy transistor; determining the size of a second bit line voltage provided to a memory cell according to the size of the saturation current; and driving the memory cell according to the determined second bit line voltage so that the cell current of the memory cell is greater than a target current value.

[0007] The memory cell array of the resistive memory device of the present invention includes a plurality of memory cells, each memory cell includes: a lower electrode layer, a resistance conversion layer and an upper electrode layer. The resistance conversion layer is arranged on the lower electrode layer and includes a plurality of regions with different conduction conditions. The upper electrode layer is arranged on the resistance conversion layer and is used to receive a bit line voltage.

[0008] In an embodiment of the present invention, the control circuit can know the characteristics of the transistor element to be electrically connected to the memory cell through the dummy transistor that is not electrically connected to the memory cell, so as to accurately apply the bit line voltage to the memory cell to speed up the operation. In addition, in an embodiment of the present invention, the memory cell array of the resistive memory device can be composed of a plurality of resistance conversion elements. Compared with the existing RRAM memory cell array, which needs to be configured with a plurality of transistors respectively connected in series with the resistance conversion elements, the embodiment of the present invention is conducive to the miniaturization of the resistive memory device.

[0009] In order that the foregoing may be better understood, several embodiments are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0011] Figure 1 A schematic diagram showing a resistive memory device according to an embodiment of the present invention;

[0012] Figure 2 Show Figure 1 A schematic diagram of a memory cell array and a dummy transistor array according to an embodiment;

[0013] Figure 3 Show Figure 2 A schematic diagram of the internal structure of a memory cell and a dummy transistor of an embodiment;

[0014] Figure 4 A schematic diagram showing a resistance conversion element according to an embodiment of the present invention;

[0015] Figure 5 Show Figure 4 A schematic diagram of a conductive region of a resistance switching layer of an embodiment;

[0016] Fig. 6A and Figure 6B A schematic flow chart showing a manufacturing process of a resistance conversion layer according to an embodiment of the present invention;

[0017] Figure 7 A flowchart showing a method for operating a resistive memory device according to an embodiment of the present invention;

[0018] Figure 8 A flowchart showing a method for operating a resistive memory device according to another embodiment of the present invention;

[0019] Fig. 9 FIG. 4 is a schematic diagram showing a waveform of a ramp voltage according to an embodiment of the present invention.

[0020] Description of Figure Numbers

[0021] 100: resistive memory device;

[0022] 110: control circuit;

[0023] 120: memory cell array;

[0024] 130: sensing circuit;

[0025] 140: voltage generating circuit;

[0026] 210: memory cell;

[0027] 212: resistance conversion element;

[0028] 214: Transistor;

[0029] 220: dummy transistor;

[0030] 230: dummy transistor column;

[0031] 310: upper electrode layer;

[0032] 320: resistance conversion layer;

[0033] 330: lower electrode layer;

[0034] 410, 420, 430, 440: area;

[0035] 900: ramp voltage;

[0036] Is: saturation current;

[0037] Ic: unit cell current;

[0038] S100, S110, S120, S201, S202, S203, S204, S205, S206, S207, S208, S610, S620: method steps;

[0039] S810, S820, S830: stage;

[0040] VBL, VBLn: bit line voltage;

[0041] VSL, VSLn: source line voltage;

[0042] VWLn: word line voltage;

[0043] WL: Word line. DETAILED DESCRIPTION

[0044] Figure 1A schematic diagram showing a resistive memory device according to an embodiment of the present invention is shown. Figure 2 Show Figure 1 A schematic diagram of a memory cell array and dummy transistor columns according to an embodiment. Figure 3 Show Figure 2 Schematic diagram of the internal structure of the memory cell and the dummy transistor of the embodiment. Figures 1 to 3 The resistive memory device 100 of the present embodiment includes a control circuit 110, a memory cell array 120, a dummy transistor 220, a sensing circuit 130, and a voltage generating circuit 140. The control circuit 110 is coupled to the memory cell array 120 and the dummy transistor 220. The sensing circuit 130 and the voltage generating circuit 140 are coupled to the control circuit 110 and the memory cell array 120. The memory cell array 120 is composed of a plurality of memory cells 210. The dummy transistor 220 is electrically insulated from the resistance conversion element of the memory cell 210. The number of the dummy transistors 220 is less than the number of the memory cells 210. In the present embodiment, the resistive memory device 100 includes a plurality of dummy transistors 220, and the dummy transistors 220 are arranged in a column to form a dummy transistor column 230. The dummy transistor column 230 can be adjacently disposed outside the memory cell array 120, and arranged in an array with the plurality of memory cells 210. However, the number and position of the dummy transistors are not limited thereto. In another embodiment, the resistive memory device 100 has only one dummy transistor 220. In yet another embodiment, a plurality of dummy transistors 220 are arranged in a plurality of columns and a plurality of rows to form a dummy transistor array. In one embodiment, the dummy transistors 220 may not be disposed adjacent to the memory cell 210, so as not to be arranged in an array with the memory cell 210.

[0045] In the present embodiment, the memory cell 210 is composed of a resistance conversion element 212, and its implementation can be sufficiently taught, suggested and implemented by the common knowledge in the technical field. The two ends of the memory cell 210 are respectively coupled to the bit line voltage (second bit line voltage) VBL and the source line voltage VSL. In the present embodiment, the memory cell 210 is coupled to the source line voltage VSL via an external transistor 214 coupled to the word line WL. The external transistor 214 is disposed outside the resistive memory device 100. In one embodiment, the source line voltage VSL is, for example, a ground voltage. The two ends of the dummy transistor 220 are respectively coupled to the bit line voltage (first bit line voltage) VBLn and the source line voltage VSLn, and the gate is coupled to the word line voltage VWLn. The dummy transistor 220 is used to simulate the external transistor 214, and its process conditions or characteristics are the same or similar to those of the external transistor 214. The control circuit 110 is used to provide a suitable bit line voltage VBLn, a source line voltage VSLn and a word line voltage VWLn to the dummy transistor 220, so that the dummy transistor 220 outputs a saturation current Is. The sensing circuit 130 is used to sense the saturation current Is of the dummy transistor 220 and provide the saturation current Is to the control circuit 110. The control circuit 110 determines the size of the bit line voltage VBL driving the memory cell 210 according to the saturation current Is, so that the memory cell 210 outputs a cell current Ic. The sensing circuit 130 is used to sense the cell current Ic and provide the cell current Ic to the control circuit 110 to verify whether the formation process or the write operation is successful. In one embodiment, the control circuit 110 determines the bit line voltage VBL applied to the memory cell 210 according to the lookup table shown in Table 1 below. The lookup table may be stored by a plurality of control bits. For example, the bit line voltage VBL_1 corresponding to the saturation current interval ">800" may be stored in an option bit among the plurality of control bits, and so on.

[0046] Table 1

[0047] Saturation current range (μA / μm) Bit line voltage VBL (V) >800 VBL_1 600～800 VBL_2 400～600 VBL_3 200～400 VBL_4

[0048] Table 1 lists the relationship between the saturation current interval and the bit line voltage VBL. In Table 1, the bit line voltage VBL_4>VBL_3>VBL_2>VBL_1. In detail, the control circuit 110 determines which of the saturation current intervals illustrated in Table 1 the saturation current Is of the dummy transistor 220 falls within, so as to correspondingly find out the bit line voltage VBL required to drive the memory cell 210. For example, if the control circuit 110 determines that the saturation current Is of the dummy transistor 220 falls within the maximum saturation current interval “>800”, it means that the driving capability of the dummy transistor 220 is stronger. Correspondingly, when the external transistor 214 used to drive the memory cell 210 is similar to the above-mentioned dummy transistor 220, it can be predicted by reading the saturation current Is of the dummy transistor 220 that the number of filament paths that need to be opened to complete the formation process or setting of the memory cell 210 is relatively small. Therefore, during the programming or writing operation, when the memory cell 210 is driven by an external transistor similar to the dummy transistor 220, the initial bit line voltage applied to the memory cell 210 is set to VBL_1. On the contrary, if the control circuit 110 determines that the saturation current Is of the dummy transistor 220 falls within the minimum current range "200-400", it means that the driving capability of the dummy transistor 220 is weak. Correspondingly, when the external transistor used to drive the memory cell 210 is similar to the above-mentioned dummy transistor 220, the number of filament paths required to be opened when completing the programming or setting of the memory cell 210 can be predicted by reading the saturation current Is of the dummy transistor 220. Therefore, during the programming or writing operation, when the memory cell 210 is driven by an external transistor similar to the dummy transistor 220, the initial bit line voltage applied to the memory cell 210 is set to VBL_4. In this way, the present embodiment can dynamically adjust the initial bit line voltage according to the saturation current Is read from the dummy transistor 220, so that the write operation of the memory cell 210 (for example, setting the memory cell 210 so that the cell current Ic is greater than the default target current value (for example, 30 microamperes)) can be performed efficiently and save power consumption. In addition, through the resistance conversion layer provided by the present embodiment, the dynamically adjusted initial bit line voltage can change the number of filament paths opened, which can reduce the limitation on the transistor saturation current. The specific content and manufacturing method of the resistance conversion layer of the present embodiment will be described in detail later.

[0049] In this embodiment, the voltage generating circuit 140 is used to generate the bit line voltage VBL and other voltages required for operation to the memory cell array 120 and the dummy transistor 220. Table 1 above records that when the saturation current Is output by the dummy transistor 220 is larger, the initial bit line voltage VBL is smaller. However, the values ​​​​exemplified in Table 1 above are not used to limit the present invention, and the lookup table is not limited to the form of Table 1.

[0050] In this embodiment, the control circuit 110 may be a processor with computing capabilities. Alternatively, the control circuit 110 may be a hardware circuit designed by a hardware description language (HDL) or any other digital circuit design method known to those skilled in the art, and implemented by a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC).

[0051] In another embodiment not shown, the memory cell 210 has a structure of a transistor element and a resistance conversion element (1T1R) connected in series, wherein the transistor element is the same as the dummy transistor 220. The word line voltage VWLn is provided to the transistor element in the memory cell 210 via the word line WL, and the resistance conversion element is coupled to the source line voltage VSL via the transistor element. The transistor elements and the dummy transistor 220 in a plurality of memory cells 210 located in the same row are respectively coupled to the same word line WL. However, in the case where the dummy transistor 220 is not arranged in an array with the memory cell 210, the transistor element in the memory cell 210 and any dummy transistor 220 are coupled to different word lines WL.

[0052] In this embodiment, the circuit structures and implementations of the sensing circuit 130 and the voltage generating circuit 140 can be sufficiently taught, suggested, and implemented based on the common knowledge in the technical field.

[0053] Figure 4 A schematic diagram showing a resistance conversion element according to an embodiment of the present invention. Figure 5 Show Figure 4 A schematic diagram of a resistance conversion layer of an embodiment. Figure 4 and Figure 5, the resistance conversion element 212 of this embodiment includes an upper electrode layer 310, a resistance conversion layer 320 and a lower electrode layer 330. The resistance conversion layer 320 is arranged between the upper electrode layer 310 and the lower electrode layer 330. The upper electrode layer 310 is coupled to the bit line voltage VBL. The lower electrode layer 330 is coupled to the source line voltage VSL. The resistance conversion layer 320 may include a plurality of regions with different conduction conditions. In this embodiment, the resistance conversion layer 320 includes a plurality of regions 410, 420, 430, 440 with different doping concentrations, and the doping elements may be oxygen, hydrogen, nitrogen, argon or aluminum plasma. The resistance conversion element 212 may also include a barrier layer and an oxygen ion storage layer, and the present invention is not limited to Figure 4 The material of the barrier layer may include aluminum oxide (Al x O y ), titanium oxide (Ti x O y ), Tantalum Oxide (Ta x O y ), Hafnium Oxide (Hf x O y ), nickel oxide (Ni x O y )、Zirconium oxide (Zr x O y ) or a combination thereof. In some embodiments, the material of the barrier layer is aluminum oxide. The oxygen ion storage layer can be used to store oxygen ions from the resistance conversion layer 320. The material of the oxygen ion storage layer may include titanium (Ti), tantalum (Ta), hafnium (Hf), zirconium (Zr). In some embodiments, the material of the oxygen ion storage layer is titanium. In an embodiment not shown, the resistance conversion element includes a first barrier layer and a second barrier layer, and the first barrier layer is, for example, configured on the resistance conversion layer to prevent oxygen ion diffusion. The oxygen ion storage layer is, for example, configured on the first barrier layer. The second barrier layer is, for example, configured on the oxygen ion storage layer. The upper electrode layer is, for example, configured on the second barrier layer.

[0054] The upper electrode layer 310 and the lower electrode layer 330 are good conductors, and the materials of the two can be the same or different. The materials of the upper electrode layer 310 and the lower electrode layer 330 can include titanium, tantalum, titanium nitride, tantalum nitride, other suitable conductive materials or combinations thereof. The material of the resistance conversion layer 320 includes, for example, transition metal oxide (TMO). By applying different voltages to the upper electrode layer 310 and the lower electrode layer 330, the resistance state of the resistance conversion element 212 can be changed to provide a function of storing data. That is, the memory cell 210 has at least two resistance states.

[0055] The operation of the control circuit 110 driving the memory cell 210 may include but is not limited to a formation procedure, a reset operation, and a setting operation. In the present embodiment, the control circuit 110 may perform a formation procedure on the memory cell 210. During this process, the electrodes at both ends of the memory cell 210 are continuously biased (i.e., a formation voltage) to generate an external electric field on the resistance conversion layer 320. For example, according to Table 1, the control circuit 110 may determine the magnitude of the bit line voltage VBL applied to the upper electrode layer 310. The external electric field will separate the oxygen atoms in the resistance conversion layer 320 into oxygen ions and oxygen vacancies. The oxygen vacancies form filaments in the resistance conversion layer 320 as a current transfer path. When the external electric field exceeds the critical value, the resistance conversion layer 320 will produce a dielectric collapse phenomenon, thereby changing from a high resistance state to a low resistance state. This collapse is not permanent, and its resistance value can still be changed. In this embodiment, since the resistance conversion layer 320 includes four regions 410, 420, 430, and 440 with different doping concentrations, the conduction conditions of these regions are different. Therefore, the number of conductive channels formed can be determined according to the size of the bit line voltage VBL applied to the upper electrode layer 310. In one embodiment, the doping concentration of region 440 is greater than the doping concentration of region 430, the doping concentration of region 430 is greater than the doping concentration of region 420, and the doping concentration of region 420 is greater than the doping concentration of region 410. In addition, the bit line voltage VBL_1 can drive region 440 to conduct, the bit line voltage VBL_2 can drive regions 430 and 440 to conduct, the bit line voltage VBL_3 can drive regions 420, 430, and 440 to conduct, and the bit line voltage VBL_4 can drive regions 410, 420, 430, and 440 to conduct.

[0056] Fig. 6A and Figure 6B A schematic flow chart of manufacturing a resistance conversion layer according to an embodiment of the present invention is shown. Fig. 6A and Figure 6B In the present embodiment, for example, an ion implantation process is performed on the resistance conversion layer 320, so that the resistance conversion layer 320 has regions 410, 420, 430, 440 with different doping concentrations. In the ion implantation process, only one or two masks may be used to form the regions 410, 420, 430, 440. In step S610, a first mask is used to shield the region 410 so as to perform a first ion implantation process on the region 420. In step S620, a second mask is used or the first mask is rotated 90 degrees to shield the regions 410 and 420 so as to perform a second ion implantation process on the regions 430 and 440. In this way, the doping concentrations of the regions 410, 420, 430, 440 are different.

[0057] Figure 7 A flowchart showing the operation method of a resistive memory device according to an embodiment of the present invention is shown. Figure 1and Figure 7 The operating method of the resistive memory device of this embodiment is at least applicable to Figure 1 The resistive memory device 100 is provided, but the present invention is not limited thereto. In step S100, the control circuit 110 provides a suitable bit line voltage, a source line voltage, and a word line voltage to the dummy transistor 220 to determine the size of the saturation current Is of the dummy transistor 220. In step S110, the control circuit 110 determines the size of the bit line voltage VBL provided to the memory cell 210 according to the size of the saturation current Is. For example, the control circuit 110 determines the size of the bit line voltage VBL provided to the memory cell 210 according to the lookup table as shown in Table 1, and controls the voltage generating circuit 140 to generate and output the bit line voltage VBL to the memory cell array 120 according to the determined size of the bit line voltage VBL. Next, in step S120, the control circuit 110 drives the memory cell 210 according to the determined bit line voltage VBL so that the cell current Ic of the memory cell 210 is greater than the target current value.

[0058] In addition, the specific details of the operation method of the resistive memory device according to the embodiment of the present invention can be obtained by Figures 1 to 6B Sufficient teachings, suggestions and implementation instructions are obtained from the description of the embodiments.

[0059] Figure 8 A flowchart showing the steps of operating a resistive memory device according to another embodiment of the present invention. Figure 1 , Figure 5 and Figure 8 , the operation method of this embodiment can be roughly divided into three stages, such as the detection stage S810, the determination stage S820 and the actuation stage S830. The above three stages are only used for illustrative purposes and are not used to limit the present invention. In the detection stage S810, the control circuit 110 can detect or test the performance of the virtual transistor 220, such as detecting the size of the saturation current Is of the virtual transistor 220 to generate a detection result. In the determination stage S820, the control circuit 110 determines how many regions in the resistance conversion element 212 need to be turned on or off based on the detection result and the lookup table such as Table 1 to make the cell current Ic of the memory cell 210 greater than or less than the target current value. In the actuation stage S830, the control circuit 110 ensures that the number of regions turned on can make the cell current Ic of the memory cell 210 greater than the target current value.

[0060] Specifically, in step S201, the control circuit 110 applies an initial voltage to the dummy transistor column 230. The initial voltage includes a word line voltage, a bit line voltage and / or a source line voltage. In step S202, the sensing circuit 130 reads multiple saturation currents Is of multiple dummy transistors 220 from the dummy transistor column 230. In step S203, the control circuit 110 determines and calculates the saturation current of each dummy transistor 220 to generate the median of the saturation current Is of the dummy transistor column 230 as a detection result. In another embodiment, the control circuit 110 may calculate these saturation currents Is to obtain an average value or majority value of these saturation currents Is as a detection result. Then, in the decision stage S820, the control circuit 110 determines the bit line voltage VBL for driving the memory cell 210 based on the detection result and the lookup table.

[0061] In step S204, the control circuit 110 determines the bit line voltage VBL applied to the memory cell 210 in the forming operation according to the lookup table shown in Table 1. In step S205, the control circuit 110 controls the voltage generating circuit 140 to generate and output the bit line voltage VBL to the memory cell 210 according to the magnitude of the bit line voltage VBL determined in step S204, so that the memory cell 210 outputs the cell current Ic. In step S206, the sensing circuit 130 senses the cell current Ic and provides the cell current Ic to the control circuit 110.

[0062] Taking the forming operation as an example, in step S207, the control circuit 110 determines whether the cell current Ic of the memory cell 210 read out is greater than the target current value. If so, the operation ends. If not, in step S208, the control circuit 110 increases the bit line voltage VBL by a predetermined value and returns to step S205 to apply the increased bit line voltage VBL to the memory cell 210. Fig. 9 As shown, if the result of step S207 is no, the next bit line voltage VBL is greater than the previous bit line voltage VBL, that is, the ramp voltage 900, whose waveform is only used for illustrative purposes and is not used to limit the present invention. Among them, the source line voltage VSL is also included between the square waves of the bit line voltage VBL, and the level of the source line voltage VSL does not change with the number of times it is applied. In the ramp voltage 900, the initial level of the bit line voltage VBL can be determined according to Table 1. The control circuit 110 repeatedly executes steps S205 to S208 until the cell current Ic is greater than the target current value. Therefore, in the activation stage S830, the control circuit 110 can ensure that the one or more conductive channels formed can make the cell current Ic of the memory cell 210 greater than the target current value.

[0063] In one embodiment, the control circuit 110 also includes an automatic stop circuit of a ramp voltage, which is configured to determine whether the increased cell current Ic is greater than an automatic stop threshold. If so, it outputs a write termination result. Otherwise, it continues to increase the bit line voltage until the cell current reaches the automatic stop threshold.

[0064] In summary, in the embodiment of the present invention, when a program or write operation is formed, when the memory cell is driven by a transistor similar to a dummy transistor, the control circuit can detect or test the device performance of the dummy transistor, and determine the magnitude of the bit line voltage used to drive the memory cell based on the detection result and the lookup table, so that the cell current of the memory cell is greater than the target current value. Therefore, the control circuit can know the characteristics of the transistor used to drive the memory cell, so that the bit line voltage can be accurately applied to the memory cell, which can speed up the operation speed of the memory cell and save power consumption. On the other hand, it also reduces the limitation on the transistor saturation current.

[0065] Those skilled in the art will appreciate that various modifications and variations of the disclosed embodiments may be made without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure encompass modifications and variations of the present disclosure that fall within the scope of the appended claims and their equivalents.

Claims

1. A resistive memory device, comprising: A memory cell array, comprising a plurality of memory cells, each of the memory cells comprising a resistance conversion element; at least one dummy transistor electrically insulated from the resistance conversion element; as well as The control circuit is coupled to the memory cell array and the at least one dummy transistor, and is used to provide a first bit line voltage, a source line voltage and a word line voltage to the at least one dummy transistor so that the at least one dummy transistor outputs a saturation current, and determines the size of a second bit line voltage for driving the memory cell according to the saturation current.

2. The resistive memory device according to claim 1, wherein the control circuit determines which of a plurality of saturation current intervals the saturation current of the at least one dummy transistor is in, so as to drive the memory cell according to the second bit line voltage corresponding to the saturation current interval. 3 . The resistive memory device according to claim 2 , wherein the control circuit drives the memory cell according to the determined second bit line voltage so that a cell current of the memory cell is greater than a target current value. 4 . The resistive memory device according to claim 1 , wherein the resistance conversion element comprises a plurality of regions with different conduction conditions, and the second bit line voltage is used to drive at least one of the regions with different conduction conditions to conduct.

5. The resistive memory device according to claim 4, wherein the resistance conversion element comprises a lower electrode layer, a resistance conversion layer, a first barrier layer, an oxygen ion storage layer, a second barrier layer and an upper electrode layer, the resistance conversion layer is arranged between the first barrier layer and the lower electrode layer, the oxygen ion storage layer is arranged on the first barrier layer, and the upper electrode layer is arranged on the second barrier layer. 6 . The resistive memory device according to claim 4 , wherein the regions with different conduction conditions have different doping concentrations. 7 . The resistive memory device of claim 4 , wherein the second bit line voltage decreases as the saturation current increases.

8. The resistive memory device according to claim 1, further comprising: a sensing circuit, coupled to the control circuit and the at least one dummy transistor, for sensing the saturation current of the at least one dummy transistor and outputting the saturation current to the control circuit; as well as The voltage generating circuit is coupled to the control circuit and the memory cell array, and is used for generating and outputting the second bit line voltage to the memory cell array.

9. An operating method of a resistive memory device, wherein the resistive memory device comprises a memory cell array and at least one dummy transistor, the memory cell array comprises a plurality of memory cells, each of the memory cells comprises a resistance conversion element, the operating method comprising: Providing a first bit line voltage, a source line voltage and a word line voltage to the at least one dummy transistor to determine the magnitude of a saturation current of the at least one dummy transistor, wherein the at least one dummy transistor is electrically insulated from the resistance conversion element; Determining the magnitude of a second bit line voltage provided to the memory cell according to the magnitude of the saturation current; as well as The memory cell is driven according to the determined bit line voltage so that a cell current of the memory cell is greater than a target current value.

10. The operating method of the resistive memory device according to claim 9, wherein the step of determining the magnitude of the second bit line voltage provided to the memory cell according to the magnitude of the saturation current comprises: Determining the magnitude of the second bit line voltage according to a lookup table; as well as The second bit line voltage is generated and output according to the determined magnitude of the second bit line voltage. 11 . The operating method of the resistive memory device according to claim 10 , wherein the lookup table comprises a relationship between a plurality of saturation current intervals and the second bit line voltage corresponding to each of the saturation current intervals.

12. The operating method of a resistive memory device according to claim 9, wherein each of the memory cells comprises a resistance conversion element, the resistance conversion element comprises a plurality of regions with different conduction conditions, and the second bit line voltage is used to drive at least one of the regions with different conduction conditions to conduct. 13 . The operating method of the resistive memory device according to claim 12 , wherein the second bit line voltage decreases as the saturation current increases.

14. A memory cell array of a resistive memory device, comprising a plurality of memory cells, each of the memory cells comprising: Lower electrode layer; A resistance conversion layer, disposed on the lower electrode layer, including a plurality of regions with different conduction conditions; as well as The upper electrode layer is arranged on the resistance conversion layer and is used to receive a bit line voltage, wherein the number of regions with different conduction conditions that are turned on increases with the increase of the bit line voltage. 15 . The memory cell array of the resistive memory device according to claim 14 , wherein the regions with different conduction conditions have different doping concentrations. 16 . The memory cell array of the resistive memory device according to claim 14 , wherein as the bit line voltage decreases, the doping concentration of the regions with different conduction conditions that are turned on becomes larger.

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