Method for manufacturing semiconductor device and substrate processing apparatus using plasma

Abstract

Provided is a method for manufacturing a semiconductor device with improved electrical characteristics and reliability. The method for manufacturing a semiconductor device includes: providing a substrate on which a first oxide film, a nitride film, and a second oxide film are sequentially stacked, and a trench is formed that penetrates through the first oxide film, the nitride film, and the second oxide film; using a first plasma process to remove a portion of the nitride film exposed by the trench while chamfering the oxide film exposed by the trench; and using a second plasma process to remove the nitride film remaining after the first plasma process.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device and a substrate processing apparatus utilizing plasma. Background Technology

[0002] To meet consumer demands for both high performance and low cost, the integration level of semiconductor devices is increasing. Therefore, three-dimensional semiconductor devices with multiple memory cells arranged in a three-dimensional (stereoscopic) manner are being developed. Conversely, due to the high integration level, defects such as voids or seams may occur when metal is filled into specific spaces. These defects can degrade the electrical characteristics and reliability of the semiconductor device. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device with improved electrical characteristics and reliability.

[0004] Another technical problem to be solved by the present invention is to provide a substrate processing apparatus utilizing plasma for implementing the above-described semiconductor device manufacturing method.

[0005] The technical problems of this invention are not limited to those mentioned above. Those skilled in the art can clearly understand other technical problems not mentioned through the following description.

[0006] An aspect of a method for manufacturing a semiconductor device according to the present invention for solving the above-mentioned technical problems includes the following steps: providing a substrate on which a first oxide film, a nitride film, and a second oxide film are sequentially stacked, and forming a trench penetrating the first oxide film, the nitride film, and the second oxide film; removing a portion of the nitride film exposed by the trench using a first plasma process while chamfering the oxide film exposed by the trench; and removing the nitride film remaining after the first plasma process using a second plasma process.

[0007] The first plasma process can utilize fluorine-containing free radicals.

[0008] The second plasma process can utilize nitrogen-containing free radicals and oxygen-containing free radicals.

[0009] In the first plasma process, the selectivity ratio of the nitride film to the oxide film can be a first selectivity ratio, and in the second plasma process, the selectivity ratio of the nitride film to the oxide film can be a second selectivity ratio greater than the first selectivity ratio.

[0010] The method may also include a step of filling the space where the nitride film is removed with metal.

[0011] The first plasma process and the second plasma process can be performed in situ.

[0012] Another aspect of the method for manufacturing a semiconductor device according to the present invention for solving the above-mentioned technical problems includes the following steps: providing a substrate on which are formed: an insulating film structure having alternating stacks of a plurality of oxide films and a plurality of nitride films, a vertical structure penetrating the insulating film structure and including a charge storage film for storing data, and a trench penetrating the insulating film structure; removing a portion of the plurality of nitride films exposed by the trench using a first plasma process while chamfering the plurality of oxide films exposed by the trench; removing the plurality of nitride films remaining after the first plasma process using a second plasma process to form a gate forming region exposing a portion of the vertical structure; and filling the gate forming region with metal for electrical connection to the vertical structure.

[0013] The first plasma process can utilize fluorine-containing free radicals.

[0014] The second plasma process can utilize nitrogen-containing free radicals and oxygen-containing free radicals.

[0015] In the first plasma process, the selectivity ratio of the nitride film to the oxide film can be a first selectivity ratio, and in the second plasma process, the selectivity ratio of the nitride film to the oxide film can be a second selectivity ratio greater than the first selectivity ratio.

[0016] One aspect of the substrate processing apparatus of the present invention for solving the aforementioned other technical problem includes: a first space disposed between an electrode and an ion blocker; a second space disposed between the ion blocker and a nozzle; a processing space below the nozzle and for processing a substrate; and a support module disposed in the processing space and supporting the substrate, wherein a substrate is placed on the support module, a first oxide film, a nitride film and a second oxide film are sequentially stacked on the substrate, and a trench is formed penetrating the first oxide film, the nitride film and the second oxide film; a fluorine-containing gas is supplied to the first space to generate a first plasma, and the first plasma is supplied to the processing space via the ion blocker and the nozzle to chamfer the exposed plurality of oxide films while removing a portion of the plurality of nitride films exposed by the trench.

[0017] The processing space can be supplied with nitrogen and hydrogen gas, the first plasma can be filtered by the ion blocker and supplied to the processing space through the nozzle, and may also include mixing with the nitrogen and hydrogen gas to generate a first etchant, and a portion of the plurality of nitride films exposed by the trench can be removed while beveling the exposed plurality of oxide films with the first etchant.

[0018] The nitrogen- and hydrogen-containing gas can be supplied through the ion blocker or the nozzle.

[0019] The substrate processing apparatus may further include: after chamfering the plurality of oxide films, providing a nitrogen-containing gas and a first oxygen-containing gas to the first space to generate a second plasma, and removing the remaining portion of the nitride film by means of the second plasma.

[0020] A second oxygen-containing gas may be provided to the processing space, the second plasma being filtered by the ion blocker and provided to the processing space through the nozzle, and may also include mixing with the second oxygen-containing gas to generate a second etchant, and removing the remaining portion of the nitride film by the second etchant.

[0021] The temperature of the processing space can be 10 to 100°C, and the pressure can be 650 to 850 mTorr.

[0022] Specific details of other embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0023] Figure 1 This is a block diagram illustrating a semiconductor device for some embodiments of the present invention.

[0024] Figure 2 It is used for explanation Figure 1 A view of a portion of the storage block of a semiconductor device.

[0025] Figure 3 It is magnification Figure 2 The view of area A.

[0026] Figures 4 to 9 This is a view illustrating intermediate steps in a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0027] Figure 10 This is a conceptual diagram illustrating a substrate processing apparatus according to some embodiments of the present invention.

[0028] Figure 11 yes Figure 10 Another example of an ion barrier and nozzle in a substrate processing device.

[0029] Figure 12 yes Figure 10 Another example of an ion barrier and nozzle for a substrate processing device. Detailed Implementation

[0030] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The advantages and features of the present invention, as well as methods for achieving these advantages and features, will be explained by referring to the following description in conjunction with the accompanying drawings. Figure 1 The invention becomes clear from the detailed description of the embodiments. However, the invention is not limited to the embodiments disclosed below, but can be implemented in many different forms. These embodiments are provided only to make the disclosure of the invention complete and to fully inform those skilled in the art of the scope of the invention, which is defined only by the scope of the claims. Throughout the specification, the same reference numerals refer to the same constituent elements.

[0031] When a component or layer is referred to as "on" or "above" another component or layer, it includes not only that it is directly above another component or layer, but also that other layers or other components are in between. Conversely, when a component is referred to as "directly" on or directly above another component, it indicates that there are no other components or layers in between.

[0032] To readily describe the relationship between one element or component and another, as shown in the figure, spatial relative terms such as "below," "below," "lower," "above," and "upper" can be used. It should be understood that, in addition to the orientation shown in the figure, spatial relative terms also include terms indicating the different orientations of the elements during use or operation. For example, when the element shown in the figure is flipped, an element described as "below" or "below" of another element may be located "above" of that element. Therefore, the exemplary term "below" can include both "below" and "above" orientations. An element may also be oriented in another direction, thus allowing the spatial relative terms to be interpreted according to orientation.

[0033] Although the terms "first," "second," etc., are used to describe various elements, constituent elements, and / or parts, these elements, constituent elements, and / or parts are obviously not limited by these terms. These terms are only used to distinguish one element, constituent element, and / or part from another element, constituent element, and / or part. Therefore, the first element, first constituent element, or first part mentioned below can obviously also be a second element, second constituent element, or second part within the technical concept of the present invention.

[0034] The terminology used in this specification is for illustrative purposes and is not intended to limit the invention. In this specification, the singular form includes the plural form unless specifically stated otherwise. The terms "comprises" and / or "comprising" as used in this specification do not exclude the presence or addition of one or more other constituent elements, steps, operations, and / or components besides those mentioned.

[0035] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) may be used in the sense that can be commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries are not to be ideally or excessively interpreted unless explicitly defined otherwise.

[0036] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing the invention with reference to the drawings, the same or corresponding constituent elements are given the same reference numerals regardless of the reference numerals, and repeated descriptions thereof are omitted.

[0037] Figure 1 This is a block diagram illustrating a semiconductor device for some embodiments of the present invention. Figure 2 It is used for explanation Figure 1 A view of a portion of the storage block of a semiconductor device. Figure 3 It is magnification Figure 2 A view of area A. Figures 1 to 3 In this context, semiconductor devices are exemplified by vertical NAND flash memory devices, but are not limited to this.

[0038] First refer to Figure 1 According to some embodiments of the present invention, the storage cell array of the non-volatile storage device 1 may include a plurality of storage blocks BLK1 to BLKn (where n is a natural number).

[0039] Reference Figure 2 Multiple electrode structures ST can be arranged on the substrate 1010. The electrode structures ST can extend parallel to each other in a first direction D1. Here, the first direction D1 and the second direction D2 can be parallel to the upper surface of the substrate 1010.

[0040] The substrate 1010 can be one of the following: a material with semiconductor properties (e.g., a silicon wafer), an insulating material (e.g., glass), a semiconductor covered by an insulating material, or a conductor. For example, the substrate 1010 can be a silicon wafer. The buffer insulating film 1101 can be located between the electrode structure ST and the substrate 1010, and can include a silicon oxide film.

[0041] Each of the electrode structures ST may include multiple gate electrodes GE and multiple insulating films ILD, which are alternately stacked along a third direction D3 perpendicular to the first direction D1 and the second direction D2. The three-dimensional semiconductor memory device may be a vertical NAND flash memory device, and the gate electrode GE of each electrode structure ST may be used as the gate electrode of the string select transistor, memory cell transistor and ground select transistor of the NAND cell string.

[0042] The thickness of the insulating film ILD can vary depending on the characteristics of the semiconductor memory element. For example, the insulating film ILD may include a silicon oxide film or a low-dielectric film.

[0043] The gate electrode GE may include at least one selected from metals (e.g., tungsten, copper, aluminum, etc.), doped semiconductors (e.g., doped silicon, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), or transition metals (e.g., titanium, tantalum, etc.). Reference numeral GEa indicates a gate electrode disposed on one side of the vertical structure VS, and reference numeral GEb indicates a gate electrode disposed on the other side of the vertical structure VS.

[0044] Multiple vertical structures VS can extend along a third direction D3 perpendicular to the upper surface of the substrate 1010, and can penetrate each electrode structure ST. In the plane, the vertical structures VS can be arranged in a Z-shape along the first direction D1 and the second direction D2.

[0045] Each of the vertical structures VS may include a vertical semiconductor pattern LSP, USP connected to the substrate 1010, and a data storage pattern (i.e., a charge storage film) DS between the vertical semiconductor patterns LSP, USP and the electrode structure ST. Further, each of the vertical structures VS may have a bit line conductive pad BCP formed of a conductive material at its upper end. For example, the bit line conductive pad BCP may be formed of a semiconductor material doped with impurities.

[0046] Vertical semiconductor pattern LSPs and USPs can include semiconductor materials such as silicon (Si), germanium (Ge), or mixtures thereof. Vertical semiconductor pattern LSPs and USPs can be used as channels for ground select transistors, string select transistors, and memory cell transistors in vertical NAND flash memory devices. Vertical semiconductor pattern LSPs and USPs can include a lower semiconductor pattern LSP that passes through the lower portion of the electrode structure ST and contacts the substrate 1010, and an upper semiconductor pattern USP that passes through the upper portion of the electrode structure ST and contacts the lower semiconductor pattern LSP. The lower semiconductor pattern LSP can be an epitaxial pattern and can have a pillar shape. The upper semiconductor pattern USP can have a U-shape defining an internal empty space, a tube shape with a closed lower end, or a macaroni shape, and the interior of the upper semiconductor pattern USP can be filled with a buried insulating pattern.

[0047] Data storage pattern (i.e., charge storage film) DS, as the data storage film of a vertical NAND flash memory device, may include tunnel insulating film (TIL), charge storage film (CIL), and barrier insulating film (BLK) (see Figure 3 ).

[0048] Here is a reference Figure 3 The contact groove T portion of the insulating film ILD1 may have a first width W1, and the contact vertical structure VS portion of the insulating film ILD1 may have a second width W2. The first width W1 is smaller than the second width W2.

[0049] On the other hand, a gate electrode GE1 is formed in the region between adjacent stacked insulating films ILD1 and ILD2 (i.e., the gate formation region). In the gate electrode GE1 disposed between the lower insulating film ILD1 and the upper insulating film ILD2, a portion of the contact trench T may have a first thickness T1, and a portion of the contact vertical structure VS may have a second thickness T2. The first thickness T1 is thicker than the second thickness T2.

[0050] In other words, it is known that the entry points between adjacent stacked insulating films ILD1 and ILD2 are relatively wide (refer to T1). When the region between adjacent stacked insulating films ILD1 and ILD2 (i.e., the gate formation region) is filled with metal (e.g., tungsten) to form the gate electrode GE1, the metal can easily fill the region between adjacent stacked insulating films ILD1 and ILD2 due to the wide entry points. Therefore, defects such as voids or cracks are not easily generated in the gate electrode GE1. This prevents degradation of electrical characteristics and reliability caused by voids or cracks.

[0051] The following is for reference Figures 4 to 9 To illustrate a method for manufacturing a semiconductor device according to some embodiments of the present invention. Figures 4 to 9 This is a view illustrating intermediate steps in a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0052] First, refer to Figure 4 An insulating film structure 1110 can be formed by alternately depositing a sacrificial film SL and an insulating film ILD on a substrate 1010. In the insulating film structure 1110, the sacrificial film SL can be formed of a material that has etch selectivity relative to the insulating film ILD. For example, the sacrificial film SL and the insulating film ILD can be formed of insulating materials and can have etch selectivity relative to each other. The sacrificial film SL and the insulating film ILD can be selected from silicon films, silicon oxide films, silicon carbide films, silicon germanium films, silicon oxynitride films, or silicon nitride films. For example, the sacrificial film SL can be formed of a silicon nitride film, and the insulating film ILD can be formed of a silicon oxide film. Before forming the insulating film structure 1110, a buffer insulating film 1101 made of a thermally oxidized film can be formed on the upper surface of the substrate.

[0053] Next, a vertical structure VS can be formed that penetrates the insulating film structure 1110 and is connected to the substrate 1010. The vertical structure VS can be formed by forming vertical holes in the substrate 1010 through the insulating film structure 1110 and the buffer insulating film 1101, and forming a lower semiconductor pattern LSP, an upper semiconductor pattern USP, and a data storage pattern DS in each vertical hole.

[0054] Specifically, the lower semiconductor pattern LSP can be an epitaxial pattern formed by performing a selective epitaxial growth (SEG) process that uses a substrate 1010 exposed in a vertical via as a seed layer. The lower semiconductor pattern LSP can be formed as a pillar shape that fills the lower portion of the vertical via. As another example, the formation of the lower semiconductor pattern LSP can be omitted.

[0055] A top semiconductor pattern USP can be formed in a vertical via on which a bottom semiconductor pattern LSP is formed. The top semiconductor pattern USP can be formed by depositing a semiconductor layer of uniform thickness in the vertical via. Here, the semiconductor layer can be formed with a thickness that does not completely fill the vertical via. Therefore, the top semiconductor pattern USP can define an empty space (or gap region) in the vertical via, and the empty space can be filled by an insulating pattern VI (see reference). Figure 7 and Figure 8 Alternatively, air filling can be used. Furthermore, a bit line conductive pad (BCP) can be formed at the upper end of the upper semiconductor pattern (USP). The bit line conductive pad (BCP) can be an impurity region doped with impurities, or it can be formed of a conductive material.

[0056] Reference Figure 5A first interlayer insulating film 1050 can be formed covering the upper surface of the vertical structure VS. After forming the first interlayer insulating film 1050, a trench T can be formed penetrating the first interlayer insulating film 1050 and the insulating film structure 1110 and exposing the substrate 1010. The trench T can be formed to be separated from the vertical structure VS and to expose the sidewalls of the sacrificial film SL and the insulating film ILD. The trench T can be formed by performing an anisotropic etching process on the insulating film structure 1110, and during the anisotropic etching process, the insulating film ILD and the sacrificial film SL can have a low etch selectivity.

[0057] By forming trenches T, multiple mold structures 1110m can be formed on the substrate 1010. A portion of the substrate 1010 can be exposed by the trenches T between the mold structures 1110m, and multiple vertical structures VS can penetrate each mold structure 1110m.

[0058] Reference Figure 6 By removing the sacrificial film SL exposed by the trench T, a gate formation region GR can be formed between the insulating films ILD. The gate formation region GR can be formed by isotropically etching the sacrificial film SL using an etching formulation that has etch selectivity for the insulating film ILD, the vertical structure VS, and the substrate 1010. Here, the sacrificial film SL can be completely removed by an isotropic etching process.

[0059] The process for removing the sacrificial film SL will be described in detail below. The case in which the sacrificial film SL is a nitride film (e.g., a silicon nitride film) and the insulating film ILD is an oxide film (e.g., a silicon oxide film) will be described.

[0060] The removal process of the sacrificial membrane SL can be performed by multiple (e.g., two) plasma processes that are different from each other.

[0061] Specifically, such as Figure 7 As shown, a portion of the sacrificial film SL (nitride film) exposed by the trench is removed by a first plasma process, while the insulating films ILD1 and ILD2 (oxide film) exposed by the trench T are chamfered. That is, the thickness of the outer portion of the insulating films ILD1 and ILD2 in contact with the trench T can be less than the thickness of the inner portion in contact with the vertical structure VS (W2>W1).

[0062] Next, as Figure 8 As shown, the sacrificial film SL (nitride film) left after the first plasma process is removed by a second plasma process. As a result, the gate formation region GR is formed. That is, the width of the outer portion of the gate formation region GR that contacts the trench T can be greater than the width of the inner portion that contacts the vertical structure VS (D1>D2).

[0063] In the first plasma process and the second plasma process, the selectivity of the nitride film (i.e., the sacrificial film SL) with respect to the oxide film (i.e., the insulating films ILD1, ILD2) can be controlled differently. The higher the selectivity, the greater the etching amount of the nitride film compared to the etching amount of the oxide film.

[0064] In the first plasma process, the selectivity of the nitride film with respect to the oxide film can be a first selectivity, and in the second plasma process, the selectivity of the nitride film with respect to the oxide film can be a second selectivity greater than the first selectivity. That is, since the selectivity of the first plasma process is low, the oxide film is removed together with the nitride film, so the edge of the oxide film can be rounded (i.e., chamfered). In contrast, since the selectivity of the second plasma process is high, mainly the nitride film is removed.

[0065] Since this first plasma process requires an HF source, fluorine radicals (F * ) are utilized in the first plasma process. NF3 gas (with additional H2 gas) can be used as the gas for generating the first plasma.

[0066] In addition, since this second plasma process requires a NO source, nitrogen radicals (N * ) and oxygen radicals (O * ) are utilized in the second plasma process. N2, O2 gases can be used as the gases for generating the second plasma.

[0067] In addition, the first plasma process and the second plasma process can be performed in-situ. That is, the first plasma process and the second plasma process can be continuously performed in one chamber.

[0068] Refer to Figure 9 for a specific description of a substrate processing apparatus capable of performing the first plasma process and the second plasma process.

[0069] Next, refer to Figure 9 , a horizontal insulating film (not shown) and a gate conductive film . A horizontal insulating film can be formed on the surface of the mold structure with a substantially uniform thickness in the gate formation region GR. The gate conductive film can partially fill the trench T or completely fill the trench T.

[0070] The gate conductive film can be deposited by supplying a deposition gas from the trench T to the gate formation region GR. Since the interval between the insulating films ILD increases as it approaches the trench T (i.e., D2 < D1 in reference to Figure 8 ), the generation of voids and cracks can be suppressed during the filling of the gate formation region GR with the gate conductive film .

[0071] For example, forming the gate conductive film 1150 may include sequentially depositing a barrier metal film and a metal film. The barrier metal film may be formed from a metal nitride film such as TiN, TaN, or WN. Furthermore, the metal film may be formed from a metallic material such as W, Al, Ti, Ta, Co, or Cu. For example, the gate conductive film 1150 may be formed using a chemical vapor deposition (CVD) method using tungsten hexafluoride (WF6), silane (SiH4), or hydrogen (H2).

[0072] Refer again Figure 2 Separate gate electrodes GE in each cell are formed by separating the gate conductive films 1150 that are connected to each other.

[0073] Figure 10 This is a conceptual diagram illustrating a substrate processing apparatus according to some embodiments of the present invention. Figure 10 The device can be used to perform Figure 7 First plasma process and / or Figure 8 The substrate processing apparatus for the second plasma process.

[0074] Reference Figure 10 According to some embodiments of the present invention, the substrate processing apparatus 10 includes a process chamber 100, a support module 200, an electrode module 300, a gas supply module 500, and a control module 600.

[0075] The process chamber 100 provides a processing space 101 for processing the substrate W. The process chamber 100 may be cylindrical in shape. The process chamber 100 is formed of a metallic material. For example, the process chamber 100 may be formed of aluminum. An opening 130 is formed on one side wall of the process chamber 100. The opening 130 serves as an inlet / outlet for loading and unloading the substrate W. The inlet / outlet can be opened or closed by a door. An exhaust port (not shown) is provided on the bottom surface of the process chamber 100. The exhaust port serves as a discharge outlet for byproducts generated in the processing space 101 to be discharged to the outside of the process chamber 100. The exhaust operation is performed by a pump.

[0076] A support module 200 is disposed in the processing space 101 and supports the substrate W. The support module 200 may be an electrostatic chuck that supports the substrate W using electrostatic force, but is not limited thereto. The electrostatic chuck may include: a dielectric plate on which the substrate W is placed, electrodes disposed in the dielectric plate and providing electrostatic force to attract the substrate W to the dielectric plate, a heater disposed in the dielectric plate and heating the substrate W to control the temperature of the substrate W, etc.

[0077] The electrode module 300 includes an electrode (or upper electrode) 330, an ion blocker 340, a nozzle 350, etc., and functions as a capacitively coupled plasma source. The gas supply module 500 includes a first gas supply module 510 or GSM1, a second gas supply module 520 or GSM2, and a third gas supply module 530 or GSM3. The control module 600 or CM controls the gas supply to the gas supply modules 510, 520, and 530.

[0078] The first space 301 is arranged between the electrode 330 and the ion blocker 340, and the second space 302 is arranged between the ion blocker 340 and the nozzle 350. The processing space 101 is located below the nozzle 350.

[0079] Electrode 330 can be connected to a high-frequency power supply 311, and ion blocker 340 can be connected to a constant voltage (e.g., ground voltage). Electrode 330 includes a plurality of first supply holes. First gas supply module 510 supplies first gas G1 to first space 301 through electrode 330 (i.e., the first supply holes of electrode 330). The electromagnetic field generated between electrode 330 and ion blocker 340 excites first gas G1 into a plasma state. The first gas excited into a plasma state (i.e., plasma effluent) includes free radicals, ions, and / or electrons.

[0080] The ion blocker 340 can be formed of a conductive material; for example, the ion blocker 340 can be in the shape of a plate such as a disk. The ion blocker 340 can be connected to a constant voltage. The ion blocker 340 includes a plurality of first through holes formed in the vertical direction. In the plasma effluent, free radicals or uncharged neutral species can pass through the first through holes of the ion blocker 340. Conversely, charged substances (i.e., ions) have difficulty passing through the first through holes of the ion blocker 340.

[0081] The nozzle 350 may be formed of a conductive material; for example, the nozzle 350 may be in the shape of a plate, such as a disk. The nozzle 350 may be connected to a constant voltage. The nozzle 350 includes a plurality of second through holes formed in the vertical direction. Plasma effluent from the ion barrier 340 is provided to the processing space 101 via the second space 302 and the second through holes of the nozzle 350.

[0082] In addition, additional process gases (i.e., second gas G2 and third gas G3) are provided to ion blocker 340 and / or nozzle 350, and the process gases react / mix with plasma effluent to form an etchant.

[0083] When process gas is supplied through ion blocker 340, the process gas can be supplied to processing space 101 through second space 302 and nozzle 350. Or, as Figure 10 As shown, process gas can be supplied to the processing space 101 through nozzle 350.

[0084] When performing the aforementioned first plasma process, since an HF source is required, the first gas G1 supplied to the first space 301 via electrode 330 can be a fluorine-containing gas (e.g., NF3 gas). In addition to NF3 gas, the first gas G1 may also include H2 gas. Furthermore, the second gas G2 can be NH3 gas.

[0085] Furthermore, a nitrogen-containing gas (e.g., N2 gas) can be added as the third gas G3. Nitrogen (N2) plays a role in adjusting the uniformity of etching. If the nitrogen flow rate is increased, the etching rate decreases while the uniformity increases. Conversely, if the nitrogen flow rate is decreased, the etching rate increases while the uniformity decreases. By controlling the nitrogen flow rate independently relative to the ammonia flow rate, uniformity can be precisely controlled.

[0086] Furthermore, since a NO source is required in the second plasma process, the first gas G1 supplied to the first space 301 through electrode 330 can be N2 or O2. The second gas G2 can be O2. In the second plasma process, a gas capable of adjusting the etching uniformity can also be used as the third gas G3.

[0087] Next, the first plasma process and the second plasma process will be explained in detail.

[0088] Fluorine-containing gas (i.e., NF3) is supplied to the first space 301 to generate the first plasma. Nitrogen- and hydrogen-containing gas (i.e., NH3) is supplied to the processing space 101.

[0089] A first plasma is provided into the processing space 101 via an ion barrier 340 and a nozzle 350. Specifically, the first plasma is filtered by the ion barrier 340 and provided into the processing space 101 via the nozzle 350, where it is mixed with a nitrogen- and hydrogen-containing gas (i.e., NH3) to generate a first etchant. The first etchant is used to etch multiple exposed oxide films (refer to...) Figure 7 The ILD1 and ILD2 are chamfered, and the multiple nitride films exposed by the trench T are removed (see reference). Figure 7 It is part of SL.

[0090] The first plasma environment can be vented, and the second plasma process can be performed in situ. The second plasma process can be performed in the same chamber where the first plasma process is performed.

[0091] A nitrogen-containing gas (i.e., N2) and a first oxygen-containing gas (i.e., O2) are supplied to the first space 301 to generate a second plasma. A second oxygen-containing gas (i.e., O2) may be supplied to the processing space 101.

[0092] The second plasma is filtered by the ion blocker 340 and supplied to the processing space 101 through the nozzle 350, and mixes with the second oxygen-containing gas (i.e., O2) to generate a second etchant. The remaining portion of the nitride film is removed by the second etchant (see reference). Figure 8 ).

[0093] During the first and second plasma processes, the temperature of the processing space 101 can be 10–100°C, and the pressure can be 650–850 mTorr. In the first plasma process, NF3 gas and H2 gas for plasma generation can be supplied at flow rates of 10–40 sccm and 0–20 sccm, respectively. In the second plasma process, N2 gas and O2 gas for plasma generation can be supplied at flow rates of 100–1000 sccm and 100–2000 sccm, respectively.

[0094] Figure 11 yes Figure 10 Another example of an ion barrier and nozzle in a substrate processing device.

[0095] Figure 12 yes Figure 10 Another example of an ion barrier and nozzle for a substrate processing device.

[0096] The second gas G2 and the third gas G3 can be supplied from only a portion of the ion blocker 340 and the nozzle 350.

[0097] Specifically, refer to Figure 11 The ion blocker 340 includes a first filtration region 341S and a second filtration region 341E disposed outside the first filtration region 341S. The first filtration region 341S may be disposed in the central region of the ion blocker 340, and the second filtration region 341E may be disposed in the edge region of the ion blocker 340.

[0098] The nozzle 350 includes a first spray area 351S and a second spray area 351E disposed outside the first spray area 351S. The first spray area 351S may be disposed in the central area of ​​the nozzle 350, and the second spray area 351E may be disposed in the edge area of ​​the nozzle 350.

[0099] Specifically, the first filtration region 341S of the ion blocker 340 may have supply holes 3411a and 3412a, while the second filtration region 341E may have a 3413 but no supply holes. Conversely, the first spray region 351S of the nozzle 350 does not have supply holes, while the second spray region 351E has supply holes 3511b and 3512b. A through hole 3513 is formed on the entire surface of the nozzle 350.

[0100] In this structure, a second gas G2 and a third gas G3 can be supplied through a first filtration zone 341S and a second spray zone 351E. The second gas G2 is supplied through a supply hole 3411a in the first filtration zone 341S and a supply hole 3511b in the second spray zone 351E. The third gas G3 is supplied through a supply hole 3412a in the first filtration zone 341S and a third supply hole 3512b in the second spray zone 351E. The second gas G2 and the third gas G3 supplied through the first filtration zone 341S are provided to the processing space 101 through a through hole 3513.

[0101] Furthermore, the flow rate of the third gas G3 supplied through the first filtration zone 341S and the flow rate of the third gas G3 supplied through the second spray zone 351E can be controlled differently.

[0102] If the flow rate of the third gas G3 supplied through the first filtration region 341S is greater than the flow rate of the third gas G3 supplied through the second spray region 351E, the amount of the third gas G3 will increase in the central region of the substrate W corresponding to the first filtration region 341S. Therefore, the etching rate in the central region of the substrate W decreases, while the uniformity increases.

[0103] Conversely, if the flow rate of the third gas G3 supplied through the second spray region 351E is greater than the flow rate of the third gas G3 supplied through the first filter region 341S, the third gas G3 will increase in the edge region of the substrate W corresponding to the second spray region 351E. Therefore, the etching rate of the edge region of the substrate W decreases, while the uniformity increases.

[0104] Reference Figure 12 In the first filtration region 341S of the ion blocker 340, supply holes 3411a and 3412a may be formed, while in the second filtration region 341E, a 3413 may be formed without supply holes. Conversely, in the first spray region 351S of the nozzle 350, no supply holes are formed, while in the second spray region 351E, a supply hole 3512b is formed. A through hole 3513 is formed on the entire surface of the nozzle 350.

[0105] In the above structure, the second gas G2 can be supplied only from the first filtration zone 341S, and the third gas G3 can be supplied through the first filtration zone 341S and the second spray zone 351E.

[0106] The second gas G2 is supplied through the supply hole 3411a of the first filtration region 341S. The third gas G3 is supplied through the supply hole 3412a of the first filtration region 341S and the third supply hole 3512b of the second spray region 351E. The second gas G2 supplied through the first filtration region 341S is provided to the processing space 101 through the through hole 3513. In this case, the third gas G3 is relatively increased compared to the second gas G2 at the edge region of the substrate W. Therefore, the etching rate at the edge region of the substrate W is reduced, while the uniformity is improved.

[0107] Furthermore, although not illustrated in separate figures, the second gas G2 can be supplied from the first filtration zone 341S and the second spray zone 351E, and the third gas G3 can be supplied through the first filtration zone 341S.

[0108] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art should understand that the present invention can be implemented in other specific forms without changing its technical concept or essential features. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: A substrate is provided, on which a first oxide film, a nitride film and a second oxide film are stacked in sequence, and a trench is formed that penetrates the first oxide film, the nitride film and the second oxide film; While removing a portion of the nitride film exposed by the trench using a first plasma process, the first oxide film and the second oxide film exposed by the trench are chamfered; as well as The nitride film left after the first plasma process is removed using a second plasma process. In the first plasma process, the selectivity ratio of the nitride film to the first oxide film or the second oxide film is a first selectivity ratio, and In the second plasma process, the selectivity of the nitride film relative to the first oxide film or the second oxide film is a second selectivity greater than the first selectivity.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, The first plasma process utilizes fluorine-containing free radicals.

3. The method for manufacturing a semiconductor device according to claim 1, wherein, The second plasma process utilizes nitrogen-containing free radicals and oxygen-containing free radicals.

4. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of filling the space in which the nitride film is removed with metal.

5. The method for manufacturing a semiconductor device according to claim 1, wherein, The first plasma process and the second plasma process are performed in situ.

6. A method for manufacturing a semiconductor device, comprising the following steps: A substrate is provided on which are formed: an insulating film structure consisting of alternating stacks of multiple oxide films and multiple nitride films, a vertical structure penetrating the insulating film structure and including a charge storage film for storing data, and a trench penetrating the insulating film structure. While removing a portion of the plurality of nitride films exposed by the trenches using a first plasma process, the plurality of oxide films exposed by the trenches are chamfered. A second plasma process is used to remove multiple nitride films left after the first plasma process to form a gate formation region that exposes a portion of the vertical structure; as well as Metal is filled in the gate forming region to electrically connect it to the vertical structure. In the first plasma process, the selectivity ratio of the nitride film to the oxide film is a first selectivity ratio, and In the second plasma process, the selectivity of the nitride film relative to the oxide film is a second selectivity that is greater than the first selectivity.

7. The method for manufacturing a semiconductor device according to claim 6, wherein, The first plasma process utilizes fluorine-containing free radicals.

8. The method for manufacturing a semiconductor device according to claim 6, wherein, The second plasma process utilizes nitrogen-containing free radicals and oxygen-containing free radicals.

9. A substrate processing apparatus, comprising: The first space is arranged between the electrodes and the ion blocker; The second space is arranged between the ion blocker and the nozzle; The processing space is located below the nozzle and is used for processing the substrate; as well as A support module is arranged in the processing space and supports the substrate. A substrate is placed on the support module, and multiple oxide films and multiple nitride films are alternately stacked on the substrate, with trenches forming through the multiple oxide films and multiple nitride films. Fluorine-containing gas is supplied to the first space to generate a first plasma. The first plasma is provided to the processing space via the ion blocker and the nozzle to chamfer the exposed plurality of oxide films while removing a portion of the plurality of nitride films exposed by the trenches, such that the selectivity of the nitride film relative to the oxide film is a first selectivity. After beveling the plurality of oxide films, nitrogen-containing gas and oxygen-containing gas are supplied to the first space to generate a second plasma, and the remaining portion of the plurality of nitride films is removed by the second plasma, such that the selectivity of the nitride film relative to the oxide film is a second selectivity greater than the first selectivity.

10. The substrate processing apparatus according to claim 9, wherein, Nitrogen and hydrogen gas is supplied to the processing space. The first plasma is filtered by the ion barrier and provided to the processing space through the nozzle, and also includes a first etchant generated by mixing with the nitrogen- and hydrogen-containing gas. While chamfering the exposed plurality of oxide films with the first etchant, a portion of the plurality of nitride films exposed by the trenches is removed.

11. The substrate processing apparatus according to claim 10, wherein, The nitrogen- and hydrogen-containing gas is provided through the ion blocker or the nozzle.

12. The substrate processing apparatus according to claim 9, wherein, A second oxygen-containing gas is provided to the processing space. The second plasma is filtered by the ion blocker and supplied to the processing space through the nozzle, and also includes a second etchant generated by mixing with the second oxygen-containing gas. The remaining portions of the plurality of nitride films are removed by the second etchant.

13. The substrate processing apparatus according to claim 9, wherein, The temperature of the processing space is 10~100℃ and the pressure is 650~850mTorr.

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