Method for manufacturing semiconductor device, semiconductor device, memory, and storage system

Abstract

Embodiments of the present invention disclose a method for manufacturing a semiconductor device, a semiconductor device, a memory, and a storage system. The method includes: providing a first semiconductor structure and a dielectric layer covering the first semiconductor structure; the first semiconductor structure includes a first gate structure, and a first source region and a first drain region located on opposite sides of the first gate structure; forming a sacrificial layer on the dielectric layer, and the surface of the sacrificial layer facing away from the dielectric layer is flush; forming a mask layer on the sacrificial layer, and the mask layer has a first mask opening; through the first mask opening, etching the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure to expose a part of the first gate structure, a part of the first source region, and a part of the first drain region as the first ohmic contact region of the first semiconductor structure. Embodiments of the present invention can reduce the ohmic contact region of the semiconductor structure and reduce the leakage risk.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and particularly to a method for manufacturing a semiconductor device, a semiconductor device, a memory, and a storage system. Background Art

[0002] In a semiconductor device, the ohmic contact region of a transistor (especially a high-voltage transistor) cannot be too large. However, affected by the thickness of the photoresist layer, the size of the opening in the photoresist layer cannot be reduced to the target size, resulting in the ohmic contact region formed on the transistor through the opening in the photoresist layer not being able to be reduced to the required size. After forming an ohmic contact layer on the ohmic contact region, there may be a risk of leakage. Summary of the Invention

[0003] Embodiments of the present invention provide a method for manufacturing a semiconductor device, a semiconductor device, a memory, and a storage system, which can reduce the ohmic contact region of a semiconductor structure and reduce the risk of leakage.

[0004] Embodiments of the present invention provide a method for manufacturing a semiconductor device, including:

[0005] Providing a first semiconductor structure and a dielectric layer covering the first semiconductor structure; the first semiconductor structure includes a first gate structure, and a first source region and a first drain region located on opposite sides of the first gate structure;

[0006] Forming a sacrificial layer on the dielectric layer, and the surface of the sacrificial layer facing away from the dielectric layer is flush;

[0007] Forming a mask layer on the sacrificial layer, and the mask layer has a first mask opening;

[0008] Through the first mask opening, etching the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure to expose a part of the first gate structure, a part of the first source region, and a part of the first drain region as the first ohmic contact region of the first semiconductor structure.

[0009] Further, the mask layer includes a photoresist layer and an anti-reflection layer, and the first mask opening includes a first opening and a second opening;

[0010] The step of forming the mask layer on the sacrificial layer includes:

[0011] Sequentially forming the anti-reflection layer and the photoresist layer on the sacrificial layer, and the photoresist layer has the first opening;

[0012] Through the first opening, forming the second opening in the anti-reflection layer, and the size of the second opening is smaller than the size of the first opening.

[0013] Further, the step of etching the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure through the first mask opening to expose a part of the first gate structure, a part of the first source region, and a part of the first drain region includes:

[0014] Through the second opening, a third opening is formed in the sacrificial layer, and the photoresist layer is removed. The size of the third opening is smaller than the size of the second opening;

[0015] Through the third opening, the dielectric layer is etched to expose a part of the first gate structure, a part of the first source region, and a part of the first drain region.

[0016] Further, the dielectric layer includes a stop layer covering the first semiconductor structure and an insulating layer located on the stop layer. The sacrificial layer is located on the insulating layer;

[0017] The step of etching the dielectric layer through the third opening to expose a part of the first gate structure, a part of the first source region, and a part of the first drain region includes:

[0018] Through the third opening, a fourth opening is formed in the insulating layer, and the anti-reflection layer is removed. The fourth opening includes a first sub-opening, a second sub-opening, and a third sub-opening. The orthographic projection of the first sub-opening on the first gate structure is located within the first gate structure. The orthographic projection of the second sub-opening on the first source region is located within the first source region. The orthographic projection of the third sub-opening on the first drain region is located within the first drain region;

[0019] Remove the sacrificial layer;

[0020] Through the fourth opening, a fifth opening is formed in the stop layer to expose a part of the first gate structure, a part of the first source region, and a part of the first drain region.

[0021] Further, the sacrificial layer includes any one of an organic bottom layer and a carbon coating, and the anti-reflection layer includes any one of a silicon oxy hard mask layer and a silicon oxynitride layer.

[0022] Further, the mask layer further includes a second mask opening;

[0023] The method further includes:

[0024] Providing a second semiconductor structure, the second semiconductor structure including a second gate structure, and a second source region and a second drain region located on opposite sides of the second gate structure; the dielectric layer also covers the second semiconductor structure;

[0025] The sacrificial layer and the dielectric layer corresponding to the second semiconductor structure are etched through the second mask opening to expose the second semiconductor structure, so that the second gate structure, the second source region and the second drain region in the second semiconductor structure serve as the second ohmic contact region of the second semiconductor structure.

[0026] Furthermore, the method further comprises:

[0027] An ohmic contact layer is formed in the first ohmic contact region and the second ohmic contact region.

[0028] Furthermore, the first semiconductor structure includes a high-voltage transistor, and the second semiconductor structure includes any one of a low-voltage transistor and an ultra-low-voltage transistor.

[0029] The present invention further provides a semiconductor device, which is formed by the above-mentioned method for manufacturing a semiconductor device, and the semiconductor device comprises:

[0030] A first semiconductor structure, comprising a first gate structure, and a first source region and a first drain region located on opposite sides of the first gate structure; the first semiconductor structure has a first ohmic contact region, and the first ohmic contact region covers a portion of the first gate structure, a portion of the first source region, and a portion of the first drain region;

[0031] The ohmic contact layer is located on the first ohmic contact region.

[0032] An embodiment of the present invention further provides a memory, comprising a memory array structure, and a peripheral structure connected to the memory array structure;

[0033] The peripheral structure includes the above-mentioned semiconductor device.

[0034] An embodiment of the present invention further provides a storage system, comprising the above-mentioned memory and a controller connected to the memory.

[0035] The beneficial effects of the embodiments of the present invention are as follows: a dielectric layer is covered on the first semiconductor structure, a sacrificial layer is formed on the dielectric layer, a surface of the sacrificial layer facing away from the dielectric layer is made flush, a mask layer is formed on the sacrificial layer, and the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure are etched through a first mask opening in the mask layer to expose a portion of the first gate structure, a portion of the first source region, and a portion of the first drain region as the ohmic contact region of the first semiconductor structure, thereby reducing the thickness of the mask layer by forming the sacrificial layer in the dielectric layer and the mask layer, reducing the size of the first mask opening in the mask layer, and further reducing the ohmic contact region of the first semiconductor structure, so as to reduce the risk of leakage after the ohmic contact layer is formed on the ohmic contact region. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] To more clearly illustrate the technical solutions in the embodiments or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0037] Figure 1 It is a schematic structural diagram corresponding to the manufacturing method of semiconductor devices in some embodiments;

[0038] Figure 2 It is a schematic flow diagram of the manufacturing method of the semiconductor device provided by the embodiment of the present invention;

[0039] Figures 3a to 3i It is a schematic structural diagram corresponding to the manufacturing method of the semiconductor device provided by the embodiment of the present invention;

[0040] Figure 4 It is a schematic structural diagram of a semiconductor device provided by the embodiment of the present invention;

[0041] Figure 5 It is a schematic structural diagram of a memory provided by the embodiment of the present invention;

[0042] Figure 6 It is a schematic structural diagram of a storage system provided by the embodiment of the present invention. Detailed Embodiments

[0043] The specific structures and functional details disclosed herein are only representative and are for the purpose of describing the exemplary embodiments of the present invention. However, the present invention can be specifically implemented in many alternative forms and should not be construed as being limited only to the embodiments set forth herein.

[0044] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0045] In the description of the present invention, it should be noted that, unless otherwise clearly defined and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0046] The terms used herein are merely for describing specific embodiments and are not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "a" and "an" used herein are also intended to include the plural. It should also be understood that the terms "comprises" and / or "comprising" specify the presence of the stated features, integers, steps, operations, units, and / or components, and do not preclude the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0047] As Figure 1 shown, in some embodiments, in order to reduce the ohmic contact area of a transistor (especially a high-voltage transistor), a dielectric layer 200a is first formed on the transistor 100a, and then a photoresist layer 300a is formed on the dielectric layer 200a. The photoresist layer 300a has an opening 301a to etch an opening 201a in the dielectric layer 200a through the opening 301a, exposing the ohmic contact area 101a of the transistor 100a. However, due to the height difference between the gate structure 102a of the transistor 100a and the source region 103a and the drain region 104a, the thickness of the photoresist layer 300a is relatively large, so that the size of the opening 301a in the photoresist layer 300a cannot be reduced to the target size. And the lateral etching force of the dielectric layer 200a is relatively large, resulting in the size of the opening 201a in the dielectric layer 200a being larger than the size of the opening 301a in the photoresist layer 300a, so that the transistor area exposed by the opening 201a may be larger than the area where the gate structure 102a, the source region 103a, and the drain region 104a are located, thereby resulting in a relatively large ohmic contact area 101a of the transistor 100a. After forming an ohmic contact layer on the ohmic contact area 101a of the transistor 100a, there may be a risk of leakage.

[0048] Based on this, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Refer to Figure 2 , which is a schematic flow chart of the method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0049] As Figure 2As shown, the manufacturing method of the semiconductor device provided by the embodiment of the present invention includes steps 101 to 104, which are specifically as follows:

[0050] Step 101: Provide a first semiconductor structure and a dielectric layer covering the first semiconductor structure; the first semiconductor structure includes a first gate structure, and a first source region and a first drain region located on opposite sides of the first gate structure.

[0051] In the embodiment of the present invention, as Figure 3a shown, the first semiconductor structure 1a may be formed on the substrate 1. The substrate 1 may be a silicon substrate, a germanium substrate, or a semiconductor substrate including other elements. The substrate 1 may be doped with a trace amount of trivalent elements such as boron, indium, gallium, aluminum, etc. to form a P-type semiconductor substrate; the substrate 1 may also be doped with a trace amount of pentavalent elements such as phosphorus, antimony, arsenic, etc. to form an N-type semiconductor substrate.

[0052] A first active region (not shown in the figure) may be formed in the substrate 1. The first active region is close to the upper surface of the substrate 1 (i.e., the surface of the substrate 1 on the side where the first semiconductor structure 1a is subsequently formed). By ion implantation (IMP), P-type doping or N-type doping is injected into the first active region, so that a P-type active region or an N-type active region can be formed in the substrate. Then, through ion implantation, a specific region in the first active region of the substrate 1 can be doped to form a first source region 11a and a first drain region 12a of the first semiconductor structure 1a in the first active region of the substrate 1. The first source region 11a and the first drain region 12a are close to the upper surface of the substrate 1, and the first source region 11a and the first drain region 12a are arranged at intervals. The first source region 11a and the first drain region 12a can form a P-type doped region or an N-type doped region by injecting P-type doping or N-type doping. The doping types of the first source region 11a and the first drain region 12a are the same. If the first semiconductor structure 1a is an N-type transistor, N-type doping is injected into the first source region 11a and the first drain region 12a; if the first semiconductor structure 1a is a P-type transistor, P-type doping is injected into the first source region 11a and the first drain region 12a.

[0053] Through ion implantation, specific regions in the first active region of the substrate 1 can also be doped to form a first doped region and a second doped region in the first active region of the substrate. The first doped region and the second doped region are close to the upper surface of the substrate. The first doped region and the second doped region are spaced apart, and the first doped region is located on the side of the first source region 11a away from the first drain region 12a, and the second doped region is located on the side of the first drain region 12a away from the first source region 11a. By implanting P-type doping or N-type doping, the first doped region and the second doped region can form a P-type doped region or an N-type doped region. The doping types of the first doped region and the second doped region are the same. The first doped region and the second doped region are used to lead out the first active region, so that an external bias voltage is applied to the first active region to provide different substrate bias voltages for the first semiconductor structure 1a.

[0054] A first gate structure 13a of the first semiconductor structure 1a can be formed on the first active region between the first source region 11a and the first drain region 12a. There is a height difference between the first gate structure 13a and the first source region 11a and the first drain region 12a, that is, the upper surface of the first gate structure 13a (the surface of the first gate structure 13a away from the substrate 1) is higher than the upper surfaces of the first source region 11a and the first drain region 12a. The first gate structure 13a can include a first gate insulating layer 131a and a first gate layer 132a. The first gate insulating layer 131a is located on the first active region between the first source region 11a and the first drain region 12a, and the first gate layer 132a is located on the first gate insulating layer 131a. In some embodiments, as Figure 3a shown, the first gate insulating layer 131a can also extend onto the first source region 11a and the first drain region 12a, that is, the first gate insulating layer 131a covers the first active region, and the first gate layer 132a is located on the first gate insulating layer 131a between the first source region 11a and the first drain region 12a. The first gate insulating layer 131a is used to isolate the first gate layer 132a from the first active region. The first gate insulating layer 131a includes but is not limited to silicon oxide, etc., and the first gate layer 132a includes but is not limited to polysilicon, etc.

[0055] The first gate structure 13a may further include a first sidewall 133a located on the sidewalls of the first gate layer 132a. The first sidewall 133a may be an ONON (silicon oxide - silicon nitride - silicon oxide - silicon nitride) structure (not shown in the figure), that is, the first sidewall 133a may include a first silicon oxide layer located on the sidewalls of the first gate layer 132a, a first silicon nitride layer located on the surface of the first silicon oxide layer, a second silicon oxide layer located on the surface of the first silicon nitride layer, and a second silicon nitride layer located on the surface of the second silicon oxide layer. The first sidewall 133a is used to protect the sidewalls of the first gate layer 132a, and increase the spacing between the first gate layer 132a and the first source region 11a and the first drain region 12a, reducing the leakage risk.

[0056] On the periphery of the first active region in the substrate 1, there may also be a first shallow trench isolation structure (not shown in the figure). The first shallow trench isolation structure is used to isolate the first semiconductor structure from other semiconductor structures. The first shallow trench isolation structure includes but is not limited to silicon oxide, etc.

[0057] The dielectric layer 2 covers the surface of the first semiconductor structure 1a. When the first gate insulating layer 131a in the first gate structure 13a is only located on the first active region between the first source region 11a and the first drain region 12a, the dielectric layer 2 covers the upper surface of the first source region 11a, the upper surface of the first drain region 12a, and the sidewalls and upper surface of the first gate structure 13a. When the first gate insulating layer 131a in the first gate structure 13a also covers the first source region 11a and the first drain region 12a, as Figure 3a shown, the dielectric layer 2 covers the first gate insulating layer 131a on the first source region 11a and the first drain region 12a and the sidewalls and upper surface of the first gate structure 13a.

[0058] The dielectric layer 2 may include a stop layer 21 and an insulating layer 22. The stop layer 21 covers the surface of the first semiconductor structure 1a, and the insulating layer 22 covers the stop layer 21. The stop layer 21 is used to avoid over - etching of the subsequent insulating layer 22, thereby avoiding damage to the first source region 11a, the first drain region 12a, and the first gate structure 13a. The stop layer 21 includes but is not limited to silicon oxide, etc., and the insulating layer 22 includes but is not limited to silicon nitride, etc.

[0059] On the substrate 1, there may also be a second semiconductor structure. Specifically, the method further includes:

[0060] Providing a second semiconductor structure, the second semiconductor structure including a second gate structure, and a second source region and a second drain region located on opposite sides of the second gate structure; the dielectric layer also covers the second semiconductor structure.

[0061] As Figure 3aAs shown, the second semiconductor structure 1b is located on the substrate 1, and the second semiconductor structure 1b is spaced apart from the first semiconductor structure 1a. A second active region (not shown in the figure) may be formed in the substrate 1, and a second source region 11b and a second drain region 12b of the second semiconductor structure 1b may be formed in the second active region, and the second source region 11b and the second drain region 12b are spaced apart. The formation methods of the second active region, the second source region 11b, and the second drain region 12b in the second semiconductor structure 1b are similar to those of the first active region, the first source region 11a, and the first drain region 12a in the first semiconductor structure 1a, and will not be described in detail herein.

[0062] A second gate structure 13b of the second semiconductor structure 1b may be formed on the second active region between the second source region 11b and the second drain region 12b. There is a height difference between the second gate structure 13b and the second source region 11b and the second drain region 12b, that is, the upper surface of the second gate structure 13b is higher than the upper surfaces of the second source region 11b and the second drain region 12b. The second gate structure 13b may include a second gate insulating layer 131b and a second gate layer 132b. The second gate insulating layer 131b is located on the second active region between the second source region 11b and the second drain region 12b, and the second gate layer 132b is located on the second gate insulating layer 131b. In some embodiments, as Figure 3a shown, the second gate insulating layer 131b may further extend onto the second source region 11b and the second drain region 12b, that is, the second gate insulating layer 131b covers the second active region, and the second gate layer 132b is located on the second gate insulating layer 131b between the second source region 11b and the second drain region 12b. The second gate insulating layer 131b is used to isolate the second gate layer 132b from the second active region. The second gate insulating layer 131b includes, but is not limited to, silicon oxide, etc., and the second gate layer 132b includes, but is not limited to, polysilicon, etc.

[0063] The second gate structure 13b may further include a second spacer 133b located on the sidewalls of the second gate layer 132b. The second spacer 133b may be an ONON (oxide-nitride-oxide-nitride) structure (not shown in the figure). The structure of the second spacer 133b is the same as that of the first spacer 133a, and will not be described in detail herein. The second spacer 133b is used to protect the sidewalls of the second gate layer 132b, and increases the spacing between the second gate layer 132b and the second source region 11b and the second drain region 12b, reducing the risk of leakage.

[0064] A second shallow trench isolation structure (not shown in the figure) may also be provided on the periphery of the second active region in the substrate 1. The second shallow trench isolation structure is used to isolate the second semiconductor structure 1b from other semiconductor structures. The second shallow trench isolation structure includes, but is not limited to, silicon oxide, etc.

[0065] The dielectric layer 2 may also cover the surface of the second semiconductor structure 1b. When the second gate insulating layer 131b in the second gate structure 13b is only located on the second active region between the second source region 11b and the second drain region 12b, the dielectric layer 2 also covers the upper surface of the second source region 11b, the upper surface of the second drain region 12b, and the sidewalls and the upper surface of the second gate structure 13b. When the second gate insulating layer 131b in the second gate structure 13b also covers the second source region 11b and the second drain region 12b, as Figure 3a shown, the dielectric layer 2 also covers the second gate insulating layer 131b on the second source region 11b and the second drain region 12b and the sidewalls and the upper surface of the second gate structure 13b. When the dielectric layer 2 includes a stop layer 21 and an insulating layer 22, the stop layer 21 also covers the surface of the second semiconductor structure 1b, and the insulating layer 22 covers the stop layer 21.

[0066] In an embodiment of the present invention, the first semiconductor structure 1a may be a high-voltage transistor, and the second semiconductor structure 1b may be a low-voltage transistor or an ultra-low-voltage transistor. Among them, ultra-low voltage, low voltage, and high voltage are relative concepts. The operating voltage of the ultra-low-voltage transistor (i.e., the voltage applied to the gate layer in the gate structure) is relatively small, the operating voltage of the high-voltage transistor is relatively large, and the operating voltage of the low-voltage transistor is between the operating voltage of the ultra-low-voltage transistor and the operating voltage of the high-voltage transistor. Among the ultra-low-voltage transistor, the low-voltage transistor, and the high-voltage transistor, the active region of the high-voltage transistor is the largest, the active region of the ultra-low-voltage transistor is the smallest, and the size of the active region of the low-voltage transistor is between the two; the channel depth of the high-voltage transistor is the largest, the channel depth of the ultra-low-voltage transistor is the smallest, and the channel depth of the low-voltage transistor is between the two; the thickness of the gate insulating layer in the high-voltage transistor is the largest, the thickness of the gate insulating layer in the ultra-low-voltage transistor is the smallest, and the thickness of the gate insulating layer in the low-voltage transistor is between the two. As Figure 3a shown, the thickness of the first gate insulating layer 131a in the first semiconductor structure 1a is greater than the thickness of the second gate insulating layer 131b in the second semiconductor structure 1b.

[0067] Step 102: Form a sacrificial layer on the dielectric layer, and the surface of the sacrificial layer facing away from the dielectric layer is flush.

[0068] Since there is a height difference between the first gate structure 13a in the first semiconductor structure 1a and the first source region 11a and the first drain region 12a, after the dielectric layer 2 is covered on the first semiconductor structure 1a, there is still a height difference between the dielectric layer 2 on the first gate structure 13a and the dielectric layer 2 on the first source region 11a and the first drain region 12a. Therefore, it is necessary to form a sacrificial layer on the dielectric layer 2 to make the surface of the sacrificial layer facing away from the dielectric layer 2 flush to eliminate this height difference.

[0069] AsFigure 3b As shown, when the dielectric layer 2 covers the surface of the first semiconductor structure 1a, a sacrificial layer 3 is deposited on the dielectric layer 2. The upper surface height of the sacrificial layer 3 is greater than the upper surface height of the first gate structure 13a to fill the height difference between the first gate structure 13a and the first source region 11a and the first drain region 12a in the first semiconductor structure 1a, that is, the upper surface of the sacrificial layer 3 corresponding to the first gate structure 13a is flush with the upper surface of the sacrificial layer 3 corresponding to the first source region 11a and the first drain region 12a. When the dielectric layer 2 also covers the surface of the second semiconductor structure 1b, the upper surface height of the sacrificial layer 3 is greater than the upper surface height of the second gate structure 13b to fill the height difference between the second gate structure 13b and the second source region 11b and the second drain region 12b in the second semiconductor structure 1b, that is, the upper surface of the sacrificial layer 3 corresponding to the second gate structure 13b is flush with the upper surface of the sacrificial layer 3 corresponding to the second source region 11b and the second drain region 12b. The sacrificial layer 3 is made of a material with good fluidity. The sacrificial layer 3 includes, but is not limited to, an organic under layer (ODL) and a spin-on-carbon (SOC).

[0070] Step 103: Form a mask layer on the sacrificial layer, and the mask layer has a first mask opening.

[0071] Since the upper surfaces of the sacrificial layer 3 are flush, the mask layer does not need to fill the height difference between the first gate structure 13a and the first source region 11a and the first drain region 12a in the first semiconductor structure 1a anymore, that is, the thickness of the mask layer can be thinner, so that the size of the first mask opening in the mask layer can be smaller.

[0072] The mask layer may include a photoresist layer and an anti-reflection layer, and the first mask opening may include a first opening and a second opening. Specifically, the forming the mask layer on the sacrificial layer in step 103 includes:

[0073] Form the anti-reflection layer and the photoresist layer on the sacrificial layer in sequence, and the photoresist layer has the first opening;

[0074] Through the first opening, form the second opening in the anti-reflection layer, and the size of the second opening is smaller than the size of the first opening.

[0075] As Figure 3c shown, form an anti-reflection layer 41 on the sacrificial layer 3. Since the upper surfaces of the sacrificial layer 3 are flush, the thickness of the anti-reflection layer 41 can be very thin, and the upper surfaces of the anti-reflection layer 41 are flush. Then, form a photoresist layer 42 on the anti-reflection layer 41. Since the upper surfaces of the anti-reflection layer 41 are flush, the thickness of the photoresist layer 42 can be very thin, and the thickness of the photoresist layer 42 is less than Figure 1The thickness of the photoresist layer 300a. When the sacrificial layer 3 is an organic bottom layer, the anti-reflection layer 41 can be a silicon-oxy-based hard mask layer (SHB); when the sacrificial layer 3 is a carbon coating, the anti-reflection layer 41 can be a silicon oxynitride layer (SiON). The anti-reflection layer 41 and the photoresist layer 42 constitute the mask layer 4.

[0076] The photoresist layer 42 has a first opening 43 corresponding to the position of the first semiconductor structure 1a. The first opening 43 can include three sub-openings, and the three sub-openings respectively correspond to the positions of the first source region 11a, the first drain region 12a, and the first gate layer 132a, and the three sub-openings all penetrate through the photoresist layer 42. Since the thickness of the photoresist layer 42 is very thin, the size of the first opening 43 (i.e., the size of the three sub-openings) can be very small, and the size of the first opening 43 is less than Figure 1 the size of the opening 301a in the photoresist layer 300a. The size of the first opening 43 refers to the lateral length of the first opening 43, and the lateral direction refers to the direction parallel to the upper surface of the substrate 1.

[0077] When there is also a second semiconductor structure 1b on the substrate 1, the photoresist layer 42 also has a sixth opening 45 corresponding to the position of the second semiconductor structure 1b, and the sixth opening 45 penetrates through the photoresist layer 42. The orthographic projection of the sixth opening 45 on the substrate 1 completely covers the second semiconductor structure 1b.

[0078] Then, as Figure 3d shown, through the first opening 43 in the photoresist layer 42, the anti-reflection layer 41 is etched to form a second opening 44 corresponding to the position of the first semiconductor structure 1a in the anti-reflection layer 41. Since the first opening 43 in the photoresist layer 42 includes three sub-openings, the second opening 44 in the photoresist layer 42 includes three sub-openings, and the three sub-openings in the first opening 43 and the three sub-openings in the second opening 44 are in one-to-one correspondence and communicate with each other, that is, the three sub-openings in the second opening 44 respectively correspond to the positions of the first source region 11a, the first drain region 12a, and the first gate layer 132a, and the three sub-openings in the second opening 44 all penetrate through the anti-reflection layer 41. The size of the second opening 44 can be smaller than the size of the first opening 43, that is, the size of each sub-opening in the second opening 44 is smaller than the size of the corresponding sub-opening in the first opening 43. The sidewall of the second opening 44 can be inclined, that is, the size of the bottom of the second opening 44 (the end of the second opening 44 close to the sacrificial layer 3) can be smaller than the size of the top (the end of the second opening 44 close to the photoresist layer 42). The size of the second opening 44 can refer to the bottom size of the second opening 44, that is, the lateral length of the bottom of the second opening 44. The first opening 43 and the second opening 44 together constitute the first mask opening of the mask layer 4.

[0079] In this embodiment, by providing an anti-reflection layer 41, the lithography effect can be improved, and the size of the second opening 44 is smaller than that of the first opening 43, and the size of the first opening 43 is smaller than Figure 1 the opening 301a in the photoresist layer 300a in Figure 1 to further reduce the opening size, which is beneficial to reducing the ohmic contact area of the first semiconductor structure 1a subsequently.

[0080] When forming the second opening 44 in the anti-reflection layer 41, the anti-reflection layer 41 corresponding to the second semiconductor structure 1b can also be etched through the sixth opening 45 in the photoresist layer 42 to form a seventh opening 46 in the anti-reflection layer 41. The orthographic projection of the seventh opening 46 on the substrate 1 completely covers the second active region to expose the corresponding sacrificial layer 3 on the second semiconductor structure 1b. The sixth opening 45 and the seventh opening 46 together constitute the second mask opening of the mask layer 4.

[0081] Step 104: Through the first mask opening, etch the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure to expose part of the first gate structure, part of the first source region, and part of the first drain region as the first ohmic contact region of the first semiconductor structure.

[0082] Through the first mask opening, the sacrificial layer 3 can be etched first, and then the dielectric layer 2 can be etched to expose the ohmic contact region of the first semiconductor structure 1a. Since the size of the first mask opening is reduced, the ohmic contact region of the first semiconductor structure 1a is reduced, that is, the ohmic contact region of the first semiconductor structure 1a is smaller than the regions where the first source region 11a, the first drain region 12a, and the first gate layer 132a are located.

[0083] Specifically, the step 104 of "through the first mask opening, etch the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure to expose part of the first gate structure, part of the first source region, and part of the first drain region" includes:

[0084] Through the second opening, form a third opening in the sacrificial layer and remove the photoresist layer. The size of the third opening is smaller than that of the second opening;

[0085] Through the third opening, etch the dielectric layer to expose part of the first gate structure, part of the first source region, and part of the first drain region.

[0086] When there is also a second mask opening on the mask layer 4, the method further includes:

[0087] Through the second mask opening, etch the sacrificial layer and the dielectric layer corresponding to the second semiconductor structure to expose the second semiconductor structure, so that the second gate structure, the second source region, and the second drain region in the second semiconductor structure serve as the second ohmic contact region of the second semiconductor structure.

[0088] As Figure 3e shown, through the second opening 44 in the anti-reflection layer 41, etch the sacrificial layer 3 to form a third opening 30 in the sacrificial layer 3 corresponding to the position of the first semiconductor structure 1a. Since the second opening 44 in the anti-reflection layer 41 includes three sub-openings, the third opening 30 in the sacrificial layer 3 includes three sub-openings, and the three sub-openings in the third opening 30 correspond to and communicate with the three sub-openings in the second opening 44 one by one, that is, the three sub-openings in the third opening 30 respectively correspond to the positions of the first source region 11a, the first drain region 12a, and the first gate layer 132a, and the three sub-openings in the third opening 30 penetrate through the sacrificial layer 3. The size of the third opening 30 can be smaller than the size of the second opening 44, that is, the size of each sub-opening in the third opening 30 is smaller than the size of the corresponding sub-opening in the second opening 44. The side wall of the third opening 30 can be inclined, that is, the size of the bottom of the third opening 30 (the end of the third opening 30 away from the anti-reflection layer 41) can be smaller than the size of the top (the end of the third opening 30 close to the anti-reflection layer 41). The size of the third opening 30 can refer to the bottom size of the third opening 30, that is, the lateral length of the bottom of the third opening 30.

[0089] In this embodiment, by providing the sacrificial layer 3, the thickness of the mask layer 4 can be reduced, thereby reducing the size of the first mask opening. Moreover, the size of the third opening 30 is smaller than the size of the second opening 44, the size of the second opening 44 is smaller than the size of the first opening 43, and the size of the first opening 43 is smaller than Figure 1 the opening 301a in the photoresist layer 300a in

[0090] order to further reduce the opening size, which is beneficial to reducing the ohmic contact region of the first semiconductor structure 1a subsequently. In addition, in order to ensure that the size of the third opening 30 in the sacrificial layer 3 is more controllable, the sacrificial layer 3 can be made of a carbon coating in this embodiment.

[0091] Since the material of the sacrificial layer 3 is similar to that of the photoresist layer 42, when etching the sacrificial layer 3, the photoresist layer 42 can be etched simultaneously to remove the photoresist layer 42, simplifying the manufacturing process and avoiding excessive overall thickness of the photoresist layer 42, the anti-reflection layer 41, and the sacrificial layer 3, which may affect the subsequent etching of the dielectric layer 2.

[0092] When the dielectric layer 2 includes a stop layer 21 and an insulating layer 22, the step of etching the dielectric layer through the third opening to expose a part of the first gate structure, a part of the first source region, and a part of the first drain region includes:

[0093] Through the third opening, a fourth opening is formed in the insulating layer, and the anti-reflection layer is removed; the fourth opening includes a first sub-opening, a second sub-opening, and a third sub-opening. The orthographic projection of the first sub-opening on the first gate structure is located within the first gate structure, the orthographic projection of the second sub-opening on the first source region is located within the first source region, and the orthographic projection of the third sub-opening on the first drain region is located within the first drain region;

[0094] The sacrificial layer is removed;

[0095] Through the fourth opening, a fifth opening is formed in the stop layer to expose a part of the first gate structure, a part of the first source region, and a part of the first drain region.

[0096] As Figure 3f shown, through the third opening 30 in the sacrificial layer 3, the insulating layer 22 is etched to form a fourth opening 220 corresponding to the position of the first semiconductor structure 1a in the insulating layer 22. Since the third opening 30 in the sacrificial layer 3 includes three sub-openings, the fourth opening 220 in the insulating layer 22 includes three sub-openings, namely, a first sub-opening 221, a second sub-opening 222, and a third sub-opening 223. The first sub-opening 221, the second sub-opening 222, and the third sub-opening 223 correspond to and communicate with the three sub-openings in the sacrificial layer 3 one by one. That is, the first sub-opening 221 corresponds to the position of the first gate structure 13a, the second sub-opening 222 corresponds to the position of the first source region 11a, and the third sub-opening 223 corresponds to the position of the first drain region 12a.

[0097] When forming the fourth opening 220 in the insulating layer 22, the corresponding insulating layer 22 on the second semiconductor structure 1b can also be etched to completely remove the corresponding insulating layer 22 on the second semiconductor structure 1b (including the insulating layer 22 corresponding to the sidewalls and the upper surface of the second source region 11b, the second drain region 12b, and the second gate structure 13b), exposing the stop layer 21 on the second semiconductor structure 1b.

[0098] Since it is necessary to remove the insulating layer 22 corresponding to the sidewall of the second gate structure 13b, the lateral etching force of the insulating layer 22 will be increased, resulting in the size of the fourth opening 220 in the insulating layer 22 may be larger than the bottom size of the third opening 30. However, due to the small bottom size of the third opening 30, the size of the fourth opening 220 is still smaller than Figure 1 the size of the opening 201a in the dielectric layer 200a of Figure 1 . The positive projection of the first sub-opening 221 on the first gate structure 13a is located within the first gate layer 132a, the positive projection of the second sub-opening 222 on the first source region 11a is located within the first source region 11a, and the positive projection of the third sub-opening 223 on the first drain region 12a is located within the first drain region 12a.

[0099] Since the anti-reflection layer 41 is made of a material similar to that of the insulating layer 22, when etching the insulating layer 22, the anti-reflection layer 41 can be etched simultaneously to remove the anti-reflection layer 41, thus simplifying the manufacturing process. Since the thickness of the insulating layer 22 is relatively thin, in order to avoid the anti-reflection layer 41 remaining after the etching of the insulating layer 22 is completed and affecting the subsequent etching of the sacrificial layer 3, the anti-reflection layer 41 in this embodiment can adopt a silicon oxy hard mask layer to ensure that the anti-reflection layer 41 can be completely removed.

[0100] As Figure 3g shown, after removing the anti-reflection layer 41, the sacrificial layer 3 is etched to remove the sacrificial layer 3.

[0101] Then, as Figure 3h shown, through the fourth opening 220 in the insulating layer 22, the stop layer 21 is etched to form a fifth opening 210 in the stop layer 21 corresponding to the position of the first semiconductor structure 1a. Since the fourth opening 220 includes the first sub-opening 221, the second sub-opening 222, and the third sub-opening 223, the fifth opening 210 in the stop layer 21 includes three sub-openings, and the three sub-openings in the fifth opening 210 correspond to and communicate with the first sub-opening 221, the second sub-opening 222, and the third sub-opening 223 one by one, that is, the three sub-openings in the fifth opening 210 respectively correspond to the positions of the first source region 11a, the first drain region 12a, and the first gate layer 132a, and the three sub-openings in the fifth opening 210 all penetrate the stop layer 21. The size of the fifth opening 210 is the same as that of the fourth opening 220, so that the positive projection of the fifth opening 210 on the first source region 11a, the first drain region 12a, and the first gate layer 132a is located within the first source region 11a, the first drain region 12a, and the first gate layer 132a.

[0102] When the first gate insulating layer 131a in the first semiconductor structure 1a is only located on the first active region between the first source region 11a and the first drain region 12a, the fifth opening 210 can expose a part of the upper surface of the first source region 11a, a part of the upper surface of the first drain region 12a, and a part of the upper surface of the first gate layer 132a. The exposed part of the upper surface of the first source region 11a, the exposed part of the upper surface of the first drain region 12a, and the exposed part of the upper surface of the first gate layer 132a constitute the first ohmic contact region 15a of the first semiconductor structure 1a, that is, the first ohmic contact region 15a does not exceed the regions where the first source region 11a, the first drain region 12a, and the first gate layer 132a are located, thereby reducing the ohmic contact region of the first semiconductor structure 1a.

[0103] When the first gate insulating layer 131a in the first semiconductor structure 1a also covers the first source region 11a and the first drain region 12a, the fifth opening 210 can expose a part of the upper surface of the first gate layer 132a and a part of the first gate insulating layer 131a on the first source region 11a and the first drain region 12a. By continuously etching the part of the first gate insulating layer 131a on the first source region 11a and the first drain region 12a through the fifth opening 210, a part of the upper surface of the first source region 11a and a part of the upper surface of the first drain region 12a are exposed. The exposed part of the upper surface of the first source region 11a, the exposed part of the upper surface of the first drain region 12a, and the exposed part of the upper surface of the first gate layer 132a constitute the first ohmic contact region 15a of the first semiconductor structure 1a, so that the first ohmic contact region 15a of the first semiconductor structure 1a can be reduced.

[0104] When forming the fifth opening 210 in the stop layer 21, the stop layer 21 on the second semiconductor structure 1b can also be etched to completely remove the stop layer 21 on the second semiconductor structure 1b (including the stop layer 21 located on the sidewalls and upper surfaces of the second source region 11b, the second drain region 12b, and the second gate structure 13b).

[0105] When the second gate insulating layer 131b in the second semiconductor structure 1b is only located on the second active region between the second source region 11b and the second drain region 12b, the stop layer 21 on the second semiconductor structure 1b is removed to completely expose the second semiconductor structure 1b, that is, the entire upper surfaces of the second source region 11b, the second drain region 12b, and the second gate layer 132b are exposed. The entire upper surfaces of the second source region 11b, the second drain region 12b, and the second gate layer 132b constitute the second ohmic contact region 15b of the second semiconductor structure 1b.

[0106] When the second gate insulating layer 131b in the second semiconductor structure 1b also covers the second source region 11b and the second drain region 12b, the stop layer 21 on the second semiconductor structure 1b is removed, exposing the entire upper surface of the second gate layer 132b and the second gate insulating layer 131b on the second source region 11b and the second drain region 12b. The etching of the second gate insulating layer 131b on the second source region 11b and the second drain region 12b is continued to completely remove the second gate insulating layer 131b on the second source region 11b and the second drain region 12b, so as to expose the entire upper surfaces of the second source region 11b and the second drain region 12b. The entire upper surfaces of the second source region 11b, the second drain region 12b, and the second gate layer 132b constitute the second ohmic contact region 15b of the second semiconductor structure 1b.

[0107] Further, the method further includes:

[0108] Forming an ohmic contact layer in the first ohmic contact region and the second ohmic contact region.

[0109] As Figure 3i shown, after forming the first ohmic contact region 15a of the first semiconductor structure 1a and the second ohmic contact region 15b of the second semiconductor structure 1b, the remaining insulating layer 22 can be removed. Then, an ohmic contact layer 5 is formed in the first ohmic contact region 15a of the first semiconductor structure 1a and the second ohmic contact region 15b of the second semiconductor structure 1b. The ohmic contact layer 5 covers a partial upper surface of the first source region 11a, a partial upper surface of the first drain region 12a, and a partial upper surface of the first gate layer 132a in the first semiconductor structure 1a. The first semiconductor structure is a high-voltage transistor, and the working voltage of the high-voltage transistor is relatively large, so that the distance between the first source region 11a and the first drain region 12a and the first gate structure 13a cannot be too small. In this embodiment, the first ohmic contact region 15a is reduced, and further the coverage area of the ohmic contact layer 5 on the first semiconductor structure 1a is reduced, which can reduce the leakage risk of the first semiconductor structure 1a. The ohmic contact layer 5 also covers the entire upper surfaces of the second source region 11b, the second drain region 12b, and the second gate layer 132b in the second semiconductor structure 1b. The second semiconductor structure 1b is a low-voltage transistor or an ultra-low-voltage transistor, and its working voltage is relatively small, so that the ohmic contact layer 5 can completely cover the upper surfaces of the second source region 11b, the second drain region 12b, and the second gate layer 132b, without affecting the electrical performance of the second semiconductor structure 1b.

[0110] After forming the ohmic contact layer 5, a plurality of contact structures (not shown in the figure) can be formed on the ohmic contact layer 5. The plurality of contact structures are respectively connected to the first source region 11a, the first drain region 12a, the first gate layer 132a, the second source region 11b, the second drain region 12b, and the second gate layer 132b through the ohmic contact layer 5. The ohmic contact layer 5 is used to reduce the contact resistance between the source region, the drain region, and the gate layer and the corresponding contact structures. The ohmic contact layer 5 forms an ohmic contact with the source region, the drain region, and the gate layer, so that the voltage drop at the contact is small enough when a voltage is applied to the source region, the drain region, and the gate layer, reducing the impact on the electrical performance of the device. Among them, the material of the ohmic contact layer 5 can be nickel silicide NiSi.

[0111] The manufacturing method of the semiconductor device provided by the embodiment of the present invention can cover a dielectric layer on the first semiconductor structure, form a sacrificial layer on the dielectric layer, make the surface of the sacrificial layer facing away from the dielectric layer flat, form a mask layer on the sacrificial layer, and etch the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure through the first mask opening in the mask layer to expose part of the first gate structure, part of the first source region, and part of the first drain region as the ohmic contact region of the first semiconductor structure. Thus, by forming a sacrificial layer in the dielectric layer and the mask layer, the thickness of the mask layer is reduced, the size of the first mask opening in the mask layer is reduced, and further the ohmic contact region of the first semiconductor structure is reduced. After forming an ohmic contact layer on the ohmic contact region, the leakage risk is reduced.

[0112] Correspondingly, the embodiment of the present invention further provides a semiconductor device formed by the manufacturing method of the semiconductor device in the above embodiment.

[0113] As Figure 4 shown, the semiconductor device provided by the embodiment of the present invention includes a substrate 1, a first semiconductor structure 1a, and an ohmic contact layer 5.

[0114] The first semiconductor structure 1a includes a first source region 11a, a first drain region 12a, and a first gate structure 13a. The substrate 1 includes a first active region (not shown in the figure). The first source region 11a and the first drain region 12a are located in the first active region, and the first source region 11a and the first drain region 12a are arranged at intervals. The first gate structure 13a is located on the first active region between the first source region 11a and the first drain region 12a, so that there is a height difference between the first gate structure 13a and the first source region 11a and the first drain region 12a, that is, the upper surface of the first gate structure 13a is higher than the upper surfaces of the first source region 11a and the first drain region 12a.

[0115] The first gate structure 13a may include a first gate insulating layer 131a and a first gate layer 132a. The first gate insulating layer 131a is located on the first active region between the first source region 11a and the first drain region 12a, and the first gate layer 132a is located on the first gate insulating layer 131a. The first gate insulating layer 131a is used to isolate the first gate layer 132a from the first active region. The first gate insulating layer 131a includes, but is not limited to, silicon oxide, etc., and the first gate layer 132a includes, but is not limited to, polysilicon, etc.

[0116] The first gate structure 13a may further include a first spacer 133a located on the sidewalls of the first gate layer 132a. The first spacer 133a may have an ONON (oxide-nitride-oxide-nitride) structure (not shown in the figure). The first spacer 133a is used to protect the sidewalls of the first gate layer 132a, and increase the spacing between the first gate layer 132a and the first source region 11a and the first drain region 12a, reducing the leakage risk.

[0117] The first semiconductor structure 1a has a first ohmic contact region 15a, and the first ohmic contact region 15a covers a part of the first source region 11a, a part of the first drain region 12a, and a part of the first gate structure 13a. Specifically, the first ohmic contact region 15a covers a part of the upper surface of the first source region 11a, a part of the upper surface of the first drain region 12a, and a part of the upper surface of the first gate layer 132a.

[0118] The ohmic contact layer 5 is located on the first ohmic contact region 15a, that is, the ohmic contact layer 5 covers a part of the upper surface of the first source region 11a, a part of the upper surface of the first drain region 12a, and a part of the upper surface of the first gate layer 132a, to reduce the leakage risk of the first semiconductor structure 1a. There are also contact structures (not shown in the figure) corresponding to the first source region 11a, the first drain region 12a, and the first gate layer 132a on the ohmic contact layer 5. The ohmic contact layer 5 is used to reduce the contact resistance between the first source region 11a, the first drain region 12a, and the first gate layer 132a and the corresponding contact structures. The ohmic contact layer 5 forms an ohmic contact with the first source region 11a, the first drain region 12a, and the first gate layer 132a, so that when a voltage is applied to the first source region 11a, the first drain region 12a, and the first gate layer 132a, the voltage drop at the contact is small enough, reducing the impact on the electrical performance of the device. Among them, the material of the ohmic contact layer 5 may be nickel silicide NiSi.

[0119] The semiconductor device may further include a stop layer 21, and the stop layer 21 covers the non-ohmic contact region of the first semiconductor structure 1a. The non-ohmic contact region of the first semiconductor structure 1a refers to other regions of the first semiconductor structure 1a except the first ohmic contact region 15a.

[0120] In some embodiments, such as Figure 3i shown, the first gate insulating layer 131a may further extend to the non-ohmic contact regions of the first source region 11a and the first drain region 12a, and the first gate insulating layer 131a on the first source region 11a and the first drain region 12a is located between the substrate 1 and the stop layer 21. The non-ohmic contact regions of the first source region 11a and the first drain region 12a refer to the other regions of the first source region 11a and the first drain region 12a except for the first ohmic contact region 15a.

[0121] The semiconductor device may further include a second semiconductor structure 1b, and the second semiconductor structure 1b includes a second source region 11b, a second drain region 12b, and a second gate structure 13b. The substrate 1 includes a second active region (not shown in the figure), the second source region 11b and the second drain region 12b are located in the second active region, and the second source region 11b and the second drain region 12b are arranged at intervals. The second gate structure 13b is located on the second active region between the second source region 11b and the second drain region 12b, such that there is a height difference between the second gate structure 13b and the second source region 11b and the second drain region 12b, that is, the upper surface of the second gate structure 13b is higher than the upper surfaces of the second source region 11b and the second drain region 12b.

[0122] The second gate structure 13b may include a second gate insulating layer 131b and a second gate layer 132b. The second gate insulating layer 131b is located on the second active region between the second source region 11b and the second drain region 12b, and the second gate layer 132b is located on the second gate insulating layer 131b. The second gate insulating layer 131b is used to isolate the second gate layer 132b from the second active region. The second gate insulating layer 131b includes, but is not limited to, silicon oxide, etc., and the second gate layer 132b includes, but is not limited to, polysilicon, etc.

[0123] The second gate structure 13b may further include a second sidewall 133b located on the sidewalls of the second gate layer 132b. The second sidewall 133b may be an ONON (oxide-nitride-oxide-nitride) structure (not shown in the figure). The second sidewall 133b is used to protect the sidewalls of the second gate layer 132b, and increase the spacing between the second gate layer 132b and the second source region 11b and the second drain region 12b, reducing the leakage risk.

[0124] The second semiconductor structure 1b has a second ohmic contact region 15b, and the second ohmic contact region 15b covers the entire upper surface of the second source region 11b, the entire upper surface of the second drain region 12b, and the entire upper surface of the second gate layer 132b.

[0125] The ohmic contact layer 5 is also located on the second ohmic contact region 15b, that is, the ohmic contact layer 5 also covers the entire upper surface of the second source region 11b, the entire upper surface of the second drain region 12b, and the entire upper surface of the second gate layer 132b. There are also contact structures (not shown in the figure) corresponding to the second source region 11b, the second drain region 12b, and the second gate layer 132b on the ohmic contact layer 5. The ohmic contact layer 5 is used to reduce the contact resistance between the second source region 11b, the second drain region 12b, and the second gate layer 132b and the corresponding contact structures. The ohmic contact layer 5 forms an ohmic contact with the second source region 11b, the second drain region 12b, and the second gate layer 132b, so that the voltage drop at the contact is small enough when a voltage is applied to the second source region 11b, the second drain region 12b, and the second gate layer 132b, reducing the impact on the electrical performance of the device.

[0126] Among them, the first semiconductor structure 1a can be a high-voltage transistor. The operating voltage of the high-voltage transistor is relatively large, so that the distances between the first source region 11a and the first drain region 12a and the first gate structure 13a cannot be too small. In this embodiment, the first ohmic contact region 15a is reduced, and then the coverage area of the ohmic contact layer 5 on the first semiconductor structure 1a is reduced, which can reduce the leakage risk of the first semiconductor structure 1a. The second semiconductor structure 1b can be a low-voltage transistor or an ultra-low-voltage transistor, and the operating voltage is relatively small, so that the ohmic contact layer 5 can completely cover the upper surfaces of the second source region 11b, the second drain region 12b, and the second gate layer 132b, without affecting the electrical performance of the second semiconductor structure 1b.

[0127] The semiconductor device provided by the embodiment of the present invention can enable the ohmic contact layer to only cover part of the first source region, part of the first drain region, and part of the first gate structure in the first semiconductor structure, reduce the coverage area of the ohmic contact layer, and reduce the leakage risk of the first semiconductor structure.

[0128] See Figure 5 , which is a schematic structural diagram of a memory provided by an embodiment of the present invention.

[0129] As Figure 5 shown, the memory includes a memory array structure 100 and a peripheral structure 200. Among them, the memory array structure 100 can be a non-volatile memory array structure. For example, the memory array structure 100 can be a NAND flash memory, a NOR flash memory, etc. The peripheral structure 200 can include devices such as CMOS (Complementary Metal Oxide Semiconductor), SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), and Xpoint chip.

[0130] Specifically, the peripheral structure 200 can be located on the storage array structure 100, and the peripheral structure 200 is connected to the storage array structure 100. The peripheral structure 200 can include the semiconductor devices in the above embodiments, which will not be elaborated here in detail.

[0131] Other architectural forms can also be adopted for the storage array structure 100 and the peripheral structure 200. For example, the peripheral structure 200 is located below the storage array structure 100, that is, the PUC (periphery under core array) architecture, or the peripheral structure 200 and the storage array structure 100 are arranged side by side, that is, the PNC (periphery near core array) architecture, etc. No specific limitation is made here.

[0132] The memory provided by the embodiment of the present invention can reduce the leakage risk of the peripheral structure in the memory.

[0133] See Figure 6 , which is a schematic structural diagram of the storage system provided by the embodiment of the present invention.

[0134] As Figure 6 shown, the embodiment of the present invention also provides a storage system. The storage system includes a memory 300 and a controller 400. The memory 300 is electrically connected to the controller 400, and the controller 400 is used to control the memory 300 to store data. The memory 300 is the memory in the above embodiments, which will not be elaborated here in detail. The controller 400 can be a controller well known to those skilled in the art, which will not be elaborated here in detail.

[0135] The storage system can be applied to terminal products such as computers, televisions, set-top boxes, vehicles, etc.

[0136] In summary, although the present invention has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention is subject to the scope defined by the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a first semiconductor structure and a dielectric layer covering the first semiconductor structure; The first semiconductor structure includes a first gate structure, and a first source region and a first drain region located on opposite sides of the first gate structure; Forming a sacrificial layer on the dielectric layer, and the surface of the sacrificial layer facing away from the dielectric layer is flush; Forming a mask layer on the sacrificial layer, and the mask layer has a first mask opening; Through the first mask opening, etching the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure to expose a part of the first gate structure, a part of the first source region, and a part of the first drain region as the first ohmic contact region of the first semiconductor structure.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The mask layer includes a photoresist layer and an anti-reflection layer, and the first mask opening includes a first opening and a second opening; The step of forming the mask layer on the sacrificial layer includes: Sequentially forming the anti-reflection layer and the photoresist layer on the sacrificial layer, and the photoresist layer has the first opening; Through the first opening, forming the second opening in the anti-reflection layer, and the lateral length of the second opening is less than the lateral length of the first opening.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The step of etching the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure through the first mask opening to expose a part of the first gate structure, a part of the first source region, and a part of the first drain region includes: Through the second opening, forming a third opening in the sacrificial layer and removing the photoresist layer, and the lateral length of the third opening is less than the lateral length of the second opening; Through the third opening, etching the dielectric layer to expose the part of the first gate structure, the part of the first source region, and the part of the first drain region.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The dielectric layer includes a stop layer covering the first semiconductor structure and an insulating layer located on the stop layer, and the sacrificial layer is located on the insulating layer; The step of etching the dielectric layer through the third opening to expose the part of the first gate structure, the part of the first source region, and the part of the first drain region includes: Through the third opening, forming a fourth opening in the insulating layer and removing the anti-reflection layer; the fourth opening includes a first sub-opening, a second sub-opening, and a third sub-opening, and the orthographic projection of the first sub-opening on the first gate structure is located within the first gate structure, the orthographic projection of the second sub-opening on the first source region is located within the first source region, and the orthographic projection of the third sub-opening on the first drain region is located within the first drain region; Removing the sacrificial layer; Through the fourth opening, forming a fifth opening in the stop layer to expose the part of the first gate structure, the part of the first source region, and the part of the first drain region.

5. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The sacrificial layer includes any one of an organic bottom layer and a carbon coating, and the anti-reflection layer includes any one of a silicon oxy hard mask layer and a silicon oxynitride layer.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The mask layer further includes a second mask opening; The method further includes: A second semiconductor structure is provided, the second semiconductor structure including a second gate structure, and a second source region and a second drain region located on opposite sides of the second gate structure; the dielectric layer also covers the second semiconductor structure; Through the second mask opening, the sacrificial layer and the dielectric layer corresponding to the second semiconductor structure are etched to expose the second semiconductor structure, so that the second gate structure, the second source region and the second drain region in the second semiconductor structure serve as second ohmic contact regions of the second semiconductor structure.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The method further includes: Forming an ohmic contact layer in the first ohmic contact region and the second ohmic contact region.

8. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The first semiconductor structure includes a high-voltage transistor, and the second semiconductor structure includes any one of a low-voltage transistor and an ultra-low-voltage transistor.

9. A semiconductor device, characterized in that, Formed by the manufacturing method of the semiconductor device according to any one of claims 1 to 8, the semiconductor device includes: A first semiconductor structure, including a first gate structure, and a first source region and a first drain region located on opposite sides of the first gate structure; the first semiconductor structure has a first ohmic contact region, and the first ohmic contact region covers a part of the first gate structure, a part of the first source region, and a part of the first drain region; An ohmic contact layer, located on the first ohmic contact region.

10. A memory, characterized in that,Including a memory array structure and a peripheral structure connected to the memory array structure; The peripheral structure includes the semiconductor device according to claim 9.

11. A storage system, characterized in that, Including the memory according to claim 10 and a controller connected to the memory.

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