A tunneling efficiency adjustable semi-floating gate transistor and a preparation method thereof

Abstract

The application discloses a semi-floating gate transistor with adjustable tunneling efficiency and a preparation method thereof. The preparation method of the semi-floating gate transistor with adjustable tunneling efficiency comprises the following steps: forming a P-well region, performing first light-doped N-type ion implantation to form an N-well region, so as to form a channel impurity distribution of the semi-floating gate transistor, and the N-well region is located above the P-well region; etching to form a U-shaped groove, so that the U-shaped groove penetrates through the N-well region; forming a first gate oxide layer, forming a window on the surface of the N-well region, forming a semi-floating gate, and making the semi-floating gate contact with the N-well region at the window; then performing edge etching, so that the surface of a part of the N-well region adjacent to one side of the window is exposed, performing second heavy-doped N-type ion implantation, forming an N + doped region in the N-well region, so as to adjust the tunneling efficiency of the tunneling transistor; forming a control gate dielectric layer, so that the control gate dielectric layer covers the semi-floating gate and extends to cover a part of the N + doped region, then forming a control gate, so that the control gate covers the control gate dielectric layer; and forming a source region and a drain region on two sides of the control gate.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor memory, and particularly relates to a semi-floating gate transistor with adjustable tunneling efficiency and a preparation method thereof. BACKGROUND

[0002] With the device size getting smaller and smaller, current DRAM devices are facing more and more problems. For example, the DRAM device requires refreshing once every 64 ms, so the capacitance value of the capacitor must be kept above a certain value to ensure a long enough charge holding time. However, with the shrinking of the feature size of integrated circuits, the manufacture of large capacitors has become increasingly difficult, and has already accounted for more than 30% of the manufacturing cost. The semi-floating gate transistor, as a new type of memory device, is different from the usual 1T1C structure of the DRAM device. It is composed of a floating gate transistor and an embedded tunneling transistor (TFET). The programming of the charge carriers is completed by the band-to-band tunneling of the charge carriers when the tunneling transistor is turned on. The erasing of the charge is completed by the positive bias of the PN junction formed by the semi-floating gate and the N well region. As can be seen from its working principle, the doping concentration of the N well region will affect the tunneling efficiency of the tunneling transistor, and further affect the programming efficiency of the semi-floating gate transistor and the readout current.

[0003] On the other hand, the doping concentration of the N well region is also related to the impurity distribution and concentration of the channel of the semi-floating gate transistor, and affects the threshold voltage of the semi-floating gate device. Therefore, how to obtain the appropriate TFET tunneling efficiency and threshold voltage of the semi-floating gate transistor through appropriate N well ion implantation process is the key to realizing good performance of the device. SUMMARY

[0004] The present application discloses a preparation method of a semi-floating gate transistor with adjustable tunneling efficiency, comprising the following steps: forming a P well region in the device manufacturing area of a substrate, then performing first light doping N-type ion implantation to form an N well region, so as to form the channel impurity distribution of the semi-floating gate transistor, wherein the N well region is located above the P well region; etching to form a U-shaped groove, so that the U-shaped groove penetrates through the N well region; depositing a first gate oxide layer, then etching to form a window on the surface of the N well region, then forming a semi-floating gate, so that the semi-floating gate covers the first gate oxide layer and completely fills the U-shaped groove, and is in contact with the N well region at the window; then performing edge etching, so that the surface of part of the N well region adjacent to one side of the window is exposed, performing second heavy doping N-type ion implantation to form an N + doped region in the N well region, so as to adjust the tunneling efficiency of the tunneling transistor; forming a control gate dielectric, so that the control gate dielectric covers the semi-floating gate and extends to cover part of the N + doped region, then forming a control gate, so that the control gate covers the control gate dielectric; forming a source region and a drain region on both sides of the control gate.

[0005] In the method for fabricating a semi-floating gate transistor with adjustable tunneling efficiency of the present invention, preferably, the semi-floating gate is P-type polysilicon and the control gate is N-type polysilicon.

[0006] In the method for fabricating a semi-floating gate transistor with adjustable tunneling efficiency of the present invention, preferably, the dose range of the first lightly doped N-type ion implantation is 8e. 12 cm -2 ~8e 13 cm -2 The dose range of the second heavily doped N-type ion implantation is 1e. 14 cm -2 ~5e 14 cm -2 .

[0007] The present invention also discloses a semi-floating gate transistor with adjustable tunneling efficiency, comprising: a substrate having a P-well region, an N-well region, and a U-shaped trench formed thereon, wherein the N-well region is located above the P-well region, the U-shaped trench penetrates the N-well region, and an N-shaped trench is formed on the upper part of one side of the N-well region. + Doped region; a first gate oxide layer formed on the surface of the U-shaped trench and extending to cover a portion of the surface of the N-well region, and having a window formed on one side; a semi-floating gate covering the first gate oxide layer and completely filling the U-shaped trench, and contacting the N-well region at the window; a control gate dielectric covering the semi-floating gate and extending to cover a portion of the N-well region. + Doped region; control gate, covering the control gate dielectric; source region and drain region, respectively formed on both sides of the control gate, the N-well region and the N-well region. + In the doped region.

[0008] In the semi-floating gate transistor with adjustable tunneling efficiency of the present invention, preferably, the semi-floating gate is P-type polysilicon and the control gate is N-type polysilicon.

[0009] In the semi-floating gate transistor with adjustable tunneling efficiency of the present invention, preferably, the semi-floating gate is P-type polysilicon and the control gate is N-type polysilicon.

[0010] In the semi-floating gate transistor with adjustable tunneling efficiency of the present invention, preferably, the control gate dielectric comprises a silicon oxide layer and a silicon nitride layer.

[0011] This invention balances the threshold voltage of the semi-floating gate transistor and the tunneling efficiency of the tunneling transistor through two N-well region ion implantations, thereby optimizing the device performance. Attached Figure Description

[0012] Figure 1 This is a flowchart of a method for fabricating a semi-floating gate transistor with adjustable tunneling efficiency.

[0013] Figures 2 to 9This is a schematic diagram of the stage structure of each step in the fabrication method of a semi-floating gate transistor with adjustable tunneling efficiency. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining this invention and are not intended to limit this invention. The described embodiments are merely some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0015] In the description of this invention, it should be noted that the terms "upper," "lower," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0016] Furthermore, many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details. Unless specifically indicated below, various parts of the device may be made of materials known to those skilled in the art, or may employ materials with similar functionality developed in the future.

[0017] Figure 1 This is a flowchart of a method for fabricating a semi-floating gate transistor with adjustable tunneling efficiency. (Example:) Figure 1 As shown, it includes the following steps:

[0018] Step S1: A hard mask 200 is formed by depositing a pad oxide layer and a nitride layer in the device fabrication area of ​​the substrate. Then, P-type ion implantation and related annealing are performed to form a P-well region 100. Following this, a first dose range of 8e is applied. 12 cm -2 ~8e 13 cm -2 Lighter N-type ion implantation and annealing between the layers form an N-well region 102, resulting in the structure shown below. Figure 2 As shown. The relatively lightly doped N-well region ion implantation was mainly used to form the channel impurity distribution of the semi-floating gate transistor.

[0019] Step S2, then etching to form a U-shaped groove, making the U-shaped groove penetrate the N-well region 102, and then removing the hard mask layer 104, the resulting structure is as follows. Figure 3 As shown.

[0020] Step S3: Deposit the first gate oxide layer 103, followed by etching to form a semi-floating gate window on the surface of the N-well region 102, resulting in the structure shown below. Figure 4 As shown. Next, a P-type first polysilicon layer 104 of a certain thickness is deposited as a semi-floating gate, and then chemically mechanically polished (CMP) is performed to cover the first gate oxide layer 103 and completely fill the U-shaped trench, and to contact the N-well region 102 at the window. The resulting structure is as shown. Figure 5 As shown.

[0021] Step S4: After depositing a silicon nitride mask, edge etching is performed to remove a portion of the first polysilicon layer 104 and a portion of the first gate oxide layer 103 adjacent to the half-floating gate window, exposing a portion of the surface of the N-well region 102. The resulting structure is as follows: Figure 6 As shown. A sacrificial oxide layer is deposited, followed by a second dose range of 1e. 14 cm -2 ~5e 14 cm -2 The implantation and annealing of heavily doped N-type ions resulted in the formation of N-type ions in the N-well region 102. + The doped region is 105, and then the sacrificial oxide layer is removed, resulting in the structure shown below. Figure 7 As shown, the second, more heavily doped N-well ion implantation is mainly used to control the tunneling efficiency of the tunneling transistor. By performing two N-well ion implantations, the difficult trade-off between the threshold voltage of the semi-floating gate transistor and the tunneling efficiency of the tunneling transistor is balanced from the process flow perspective, thus optimizing the device performance in terms of the process flow.

[0022] Step S5: A silicon oxide layer 106 and a silicon nitride layer 107 of a certain thickness are deposited to form a control gate dielectric, which covers the first polysilicon layer 104 and extends to cover a portion of the N-type silicon. + Doped region 105. Next, a second polysilicon layer 108 is deposited to cover the control gate dielectric. Edge etching is performed to expose the substrate surfaces on both sides of the control gate, resulting in the structure shown below. Figure 8 As shown.

[0023] Step S6: Sidewalls 109 are formed on both sides of the control gate. Then, N-type ion implantation is performed to form the source region 110 and drain region 111, and the second polysilicon layer 108 is N-type doped to serve as the control gate, completing the fabrication of a semi-floating gate transistor with adjustable tunneling efficiency. The resulting structure is shown below. Figure 9 As shown. Of course, the present invention is not limited to this, and the source region, drain region and control gate can also be formed by epitaxy or other means.

[0024] likeFigure 9 As shown, the semi-floating gate transistor with adjustable tunneling efficiency includes: a substrate having a P-well region 100, an N-well region 102, and a U-shaped trench, wherein the N-well region 102 is located above the P-well region 100, the U-shaped trench penetrates the N-well region 102, and an N-well is formed on the upper part of one side of the N-well region 102. + Doped region 105; First gate oxide layer 103, formed on the surface of the U-shaped trench and extending to cover a portion of the surface of the N-well region 102, and having a window formed on one side; Semi-floating gate 104, covering the first gate oxide layer 103 and completely filling the U-shaped trench, and contacting the N-well region 102 at the window; Control gate dielectric including silicon oxide 106 and silicon nitride 107, covering the semi-floating gate 104 and extending to cover a portion of the N-well region 102. + Doped region 105; control gate 108, covering the control gate dielectric; source region 110 and drain region 111, respectively formed on both sides of the control gate N-well region 102 and N-well region 103. + In doped region 105.

[0025] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semi-floating gate transistor with adjustable tunneling efficiency, characterized in that, Includes the following steps: A P-well region is formed in the device fabrication area of ​​the substrate, followed by a first light doping N-type ion implantation to form an N-well region, thereby forming the channel impurity distribution of the semi-floating gate transistor. The N-well region is located above the P-well region. Etching forms a U-shaped groove that penetrates the N-well region; A first gate oxide layer is deposited to cover the surface of the U-shaped groove and the surface of the N-well region. Then, etching is performed to form a window on the surface of the N-well region near the drain region. Next, a semi-floating gate is formed to cover the first gate oxide layer and completely fill the U-shaped groove, and to contact the N-well region at the window. Edge etching is performed to expose a portion of the N-well region's surface adjacent to the window, followed by a second heavy-doped N-type ion implantation to form N-type ions within the N-well region. + Doped regions are used to regulate the tunneling efficiency of tunneling transistors; Form a control gate medium that covers the semi-floating gate and extends to cover a portion of the N. + The doped region is then formed, and a control gate is formed to cover the control gate dielectric. A source region and a drain region are formed on both sides of the control gate, wherein the source region is formed on the upper part of the N-well region and the drain region is formed on the N-well region. + The upper part of the doped region.

2. The method for fabricating a semi-floating gate transistor with adjustable tunneling efficiency according to claim 1, characterized in that, The semi-floating gate is P-type polysilicon, and the control gate is N-type polysilicon.

3. The method for fabricating a semi-floating gate transistor with adjustable tunneling efficiency according to claim 1, characterized in that, The dose range of the first lightly doped N-type ion implantation is 8e. 12 cm -2 ~8e 13 cm -2 ; The dose range of the second heavily doped N-type ion implantation is 1e. 14 cm -2 ~5e 14 cm -2 .

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