Semiconductor packaging method and carrier plate for semiconductor packaging method

Abstract

The application provides a semiconductor packaging method and a carrier plate used in the semiconductor packaging method. The semiconductor packaging method comprises the following steps: mounting at least one chip to be packaged on a carrier plate; the carrier plate comprises a body and an auxiliary structure arranged on the surface of the body, the surface of the body comprises a first region and a second region, the at least one chip to be packaged is arranged on the second region, the auxiliary structure is arranged on the first region, the auxiliary structure is integrally formed with the carrier plate, or the auxiliary structure is an integral structure; forming an encapsulation layer on the carrier plate, the encapsulation layer encapsulates the at least one chip to be packaged, and an encapsulation structure comprising the at least one chip to be packaged and the encapsulation layer is obtained; the auxiliary structure makes the encapsulation structure form a positioning structure close to the surface of the body; when the auxiliary structure is integrally formed with the body, the carrier plate is peeled off to expose the positioning structure and the chip to be packaged; when the auxiliary structure is an integral structure, the body is peeled off to expose the positioning structure and the chip to be packaged.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor packaging method and a carrier board for the semiconductor packaging method. Background Technology

[0002] Common semiconductor packaging technologies, such as chip packaging, mainly involve the following processes: For the front-side processing of the chip, the front side of the chip is first mounted on a carrier substrate, then thermo-pressed and encapsulated. The carrier substrate is then peeled off, and a redistribution structure is formed on the front side of the chip before encapsulation. Exposure is required during the formation of the redistribution layer; the locations to be exposed must be determined before exposure. For the back-side processing of the chip, the back side of the chip is mounted on a carrier substrate.

[0003] Current chip packaging technology involves mounting multiple target chips simultaneously with the chip on a carrier board, using these target chips to locate the exposure position. However, placement errors exist during the target chip mounting process, and the target chips are subject to lateral impact from the molding material during thermoforming, causing them to shift. This alters the relative positions of the multiple target chips, resulting in inaccurate exposure positions and reduced exposure accuracy. Summary of the Invention

[0004] This application provides a semiconductor packaging method and a carrier board for the semiconductor packaging method.

[0005] According to a first aspect of the embodiments of this application, a semiconductor packaging method is provided, the semiconductor packaging method comprising:

[0006] At least one chip to be packaged is mounted on a carrier board; the carrier board includes a body and an auxiliary structure disposed on the surface of the body, the surface of the body includes a first region and a second region, the at least one chip to be packaged is mounted on the second region of the body; the auxiliary structure is disposed on the first region of the body, the auxiliary structure is integrally formed with the body, or the auxiliary structure is an integral structure.

[0007] An encapsulation layer is formed on the carrier board, and the encapsulation layer encapsulates the at least one chip to be packaged, resulting in an encapsulation structure including the at least one chip to be packaged and the encapsulation layer; the auxiliary structure forms a positioning structure close to the surface of the body of the encapsulation structure.

[0008] When the auxiliary structure is integrally formed with the main body, the carrier board is peeled off to expose the positioning structure and the chip to be packaged; when the auxiliary structure is an integral structure, the main body is peeled off to expose the positioning structure and the chip to be packaged.

[0009] In one embodiment, when the auxiliary structure is integrally formed with the body, the auxiliary structure includes a plurality of protrusions formed on the surface of the body, and the positioning structure includes encapsulation structure grooves formed on the surface of the encapsulation structure corresponding to each of the protrusions; or...

[0010] When the auxiliary structure is integrally formed with the main body, the auxiliary structure includes a plurality of groove structures formed on the surface of the main body, and the positioning structure includes encapsulation structure protrusions formed on the surface of the encapsulation structure corresponding to each of the groove structures; or...

[0011] When the auxiliary structure is integrally formed with the main body, the auxiliary structure includes at least one protrusion structure and at least one groove structure formed on the surface of the main body. The positioning structure includes a groove portion of the encapsulation structure corresponding to the protrusion structure formed on the surface of the encapsulation structure and a protrusion portion of the encapsulation structure corresponding to the groove structure formed on the surface of the encapsulation structure.

[0012] In one embodiment, when the auxiliary structure is an integral structure, the auxiliary structure includes a frame body, the frame body including opposing first surfaces and second surfaces;

[0013] Before mounting at least one chip to be packaged onto the carrier board, the semiconductor packaging method further includes: attaching the first surface of the frame to the first region of the body;

[0014] The encapsulation layer further encapsulates the frame body, and the encapsulation structure further includes the frame body; the positioning structure includes the frame body; the first surface of the frame body includes a plurality of positioning areas, and the positioning areas are provided with frame body recesses.

[0015] In one embodiment, the number of chips to be packaged is multiple, and the auxiliary structure further includes multiple rods located within the frame body and connected to the frame body. The multiple rods divide the area enclosed by the frame body into multiple hollow areas, and the chips to be packaged are located in the hollow areas.

[0016] In one embodiment, the front side of the chip and the positioning structure are located on the same side; when the auxiliary structure is an integral structure, after peeling off the main body to expose the positioning structure and the chip to be packaged, or when the auxiliary structure is integrally formed with the main body, after peeling off the carrier board to expose the positioning structure and the chip to be packaged, the semiconductor packaging method further includes:

[0017] A conductive layer is formed on the front side of the chip;

[0018] A photoresist film layer is formed on the conductive layer, and the position of the photoresist film layer to be exposed is determined according to the positioning structure.

[0019] The photoresist film is exposed according to the position to be exposed in order to pattern the photoresist film and obtain the photoresist layer.

[0020] The area of ​​the conductive layer not blocked by the photoresist layer is etched to obtain a redistribution layer.

[0021] According to a second aspect of the present application, a carrier board for a semiconductor packaging method is provided. The carrier board includes a body and an auxiliary structure. The surface of the carrier board includes a first region and a second region. The auxiliary structure is disposed in the first region, and the second region is used to mount a chip to be packaged. The auxiliary structure is integrally formed with the body, or the auxiliary structure is an integral structure.

[0022] In one embodiment, when the auxiliary structure is integrally formed with the body, the auxiliary structure includes at least one protrusion structure and / or at least one groove structure formed on the surface of the body.

[0023] In one embodiment, the thickness of the protrusion structure is greater than or equal to 10 μm; the depth of the groove structure is greater than or equal to 10 μm.

[0024] In one embodiment, when the auxiliary structure is an integral structure, the auxiliary structure includes a frame body; the frame body includes a first surface and a second surface facing each other, the first surface facing the main body;

[0025] The first surface of the frame includes multiple positioning areas, and each positioning area has a recess.

[0026] In one embodiment, when the auxiliary structure is an integral structure, the auxiliary structure further includes a plurality of rods located within the frame body and connected to the frame body, the plurality of rods dividing the area enclosed by the frame body into a plurality of hollow areas.

[0027] The main technical effects achieved by the embodiments of this application are:

[0028] The semiconductor packaging method provided in this application is used for a carrier board in a semiconductor packaging method. The carrier board includes a body and an auxiliary structure. The auxiliary structure forms a positioning structure near the surface of the carrier board by the encapsulation structure. When the auxiliary structure is an integral structure, the positioning structure is exposed after the body is peeled off. When the auxiliary structure is integrally formed with the body, the positioning structure is exposed after the carrier board is peeled off. Subsequently, the position to be exposed is determined according to the positioning structure when the redistribution layer is formed. When the auxiliary structure is integrally formed with the body, the positioning structure formed during the encapsulation layer formation process will not be offset relative to the body. When the auxiliary structure is an integral structure, the relative positions of different regions of the positioning structure formed during the encapsulation layer formation process will not change. Therefore, the accuracy of the exposure position determined according to the positioning structure is high, which helps to improve the exposure accuracy. Attached Figure Description

[0029] Figure 1 This is a flowchart of a semiconductor packaging method provided in an exemplary embodiment of this application;

[0030] Figure 2 This is a top view of the carrier provided in an exemplary embodiment of this application;

[0031] Figure 3 This is a cross-sectional view of a carrier provided in an exemplary embodiment of this application;

[0032] Figure 4 This is a cross-sectional view of the first intermediate structure of the semiconductor packaging structure provided in another exemplary embodiment of this application;

[0033] Figure 5 This is a cross-sectional view of a carrier provided in another exemplary embodiment of this application;

[0034] Figure 6 This is a cross-sectional view of the first intermediate structure of the semiconductor packaging structure provided in another exemplary embodiment of this application;

[0035] Figure 7 This is a top view of the carrier provided in yet another exemplary embodiment of this application;

[0036] Figure 8 yes Figure 7 A cross-sectional view of the carrier shown;

[0037] Figure 9 This is a top view of the first intermediate structure of the semiconductor packaging structure provided in another exemplary embodiment of this application;

[0038] Figure 10 yes Figure 9 The cross-sectional view of the first intermediate structure shown;

[0039] Figure 11This is a cross-sectional view of the second intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0040] Figure 12 This is a cross-sectional view of a second intermediate structure of a semiconductor packaging structure provided in another exemplary embodiment of this application;

[0041] Figure 13 This is a cross-sectional view of the second intermediate structure of the semiconductor packaging structure provided in another exemplary embodiment of this application;

[0042] Figure 14 This is a cross-sectional view of the third intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0043] Figure 15 This is a cross-sectional view of the third intermediate structure of the semiconductor packaging structure provided in another exemplary embodiment of this application;

[0044] Figure 16 This is a cross-sectional view of the third intermediate structure of the semiconductor packaging structure provided in another exemplary embodiment of this application;

[0045] Figure 17 This is a flowchart of a semiconductor packaging method provided in another exemplary embodiment of this application;

[0046] Figure 18 This is a cross-sectional view of the fourth intermediate structure of the semiconductor packaging structure provided in an exemplary embodiment of this application;

[0047] Figure 19 This is a cross-sectional view of the fourth intermediate structure of the semiconductor packaging structure provided in another exemplary embodiment of this application;

[0048] Figure 20 This is a cross-sectional view of the fourth intermediate structure of the semiconductor packaging structure provided in another exemplary embodiment of this application. Specific Implementation

[0049] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0050] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0051] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0052] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0053] This application provides a semiconductor packaging method. See also... Figure 1 The semiconductor packaging method includes the following steps 110 to 130.

[0054] In step 110, at least one chip to be packaged is mounted on a carrier board; the carrier board includes a body and an auxiliary structure disposed on the surface of the body, the surface of the body includes a first region and a second region, the at least one chip to be packaged is mounted on the second region of the body, the auxiliary structure is disposed on the first region of the body, the auxiliary structure is integrally formed with the body, or the auxiliary structure is an integral structure.

[0055] In step 120, an encapsulation layer is formed on the carrier board, the encapsulation layer encapsulates the at least one chip to be encapsulated, resulting in an encapsulation structure including the at least one chip to be encapsulated and the encapsulation layer; the auxiliary structure forms a positioning structure close to the surface of the body of the encapsulation structure.

[0056] In step 130, when the auxiliary structure is integrally formed with the main body, the carrier board is peeled off to expose the positioning structure and the chip to be packaged; when the auxiliary structure is an integral structure, the main body is peeled off to expose the positioning structure and the chip to be packaged.

[0057] The semiconductor packaging method provided in this application includes a substrate and an auxiliary structure. The auxiliary structure forms a positioning structure near the surface of the substrate by the encapsulation structure. When the auxiliary structure is an integral structure, the chip side facing the substrate and the positioning structure are exposed after the substrate is peeled off. When the auxiliary structure is integrally formed with the substrate, the chip side facing the substrate and the positioning structure are exposed after the substrate is peeled off. Subsequently, the position to be exposed is determined according to the positioning structure when the redistribution layer is formed. When the auxiliary structure is integrally formed with the substrate, the positioning structure formed during the encapsulation layer formation process will not shift relative to the substrate. When the auxiliary structure is an integral structure, the relative positions of different regions of the positioning structure formed during the encapsulation layer formation process will not change. Therefore, the accuracy of the exposure position determined according to the positioning structure is high, which helps to improve the exposure accuracy.

[0058] The following will describe in detail each step of the semiconductor packaging method provided in the embodiments of this application.

[0059] In step 110, at least one chip to be packaged is mounted on a carrier board; the carrier board includes a body and an auxiliary structure disposed on the surface of the body, the surface of the body includes a first region and a second region, the at least one chip to be packaged is mounted on the second region of the body, the auxiliary structure is disposed on the first region of the body, the auxiliary structure is integrally formed with the carrier board, or the auxiliary structure is an integral structure.

[0060] In one embodiment, see Figure 2 The carrier board 10 includes a body 12 and an auxiliary structure 11. The body 12 includes a first region 101 and a second region 102 for mounting the chip to be packaged. The auxiliary structure is disposed in the first region 101. All areas of the surface of the body 12 except for the second region 102 can be the first region 101. The shape of the second region 102 is designed according to the layout of the chip to be packaged on the entire carrier board 10, and the shape of the second region 102 can include a circle, a rectangle, or other shapes. The first region 101 includes the edge region of the body 12 and the region located between adjacent second regions 102.

[0061] In one embodiment, after the chip 20 to be packaged is mounted on the body 12, the front side of the chip to be packaged can face the body 12. The front side of the chip to be packaged has solder pads that can bring out the internal circuitry of the chip. In one embodiment, it can be obtained by cutting a silicon wafer. The silicon wafer has an active surface, and the active surface of the silicon wafer has solder pads. The silicon wafer can be cut by mechanical cutting or laser cutting. Optionally, before cutting the silicon wafer, a grinding machine can be used to grind the back side of the silicon wafer opposite the active surface to achieve a specified thickness.

[0062] The bonding pads of the chip to be packaged consist of conductive electrodes led from the internal circuitry of the chip to the chip surface. Multiple bonding pads may be provided on the front side of the chip. These pads are placed on the conductive electrodes of the chip, leading them out.

[0063] In one embodiment, the body 12 may be circular, rectangular, or other shapes. The carrier plate 10 may be made of an iron-nickel constant expansion alloy, or the body 12 may be made of stainless steel, polymer, etc.

[0064] In one embodiment, the chip 20 to be packaged can be attached to the body 12 by an adhesive layer, and the adhesive layer can be made of an easy-to-peel material so that the chip 20 to be packaged can be peeled off from the body 12 in the future. For example, the adhesive layer can be made of a heat-removing material that can lose its stickiness by heating.

[0065] In one embodiment, see Figure 3 The auxiliary structure 11 includes a plurality of protrusions 111 formed on the surface of the body 12, which are obtained through step 110 as follows. Figure 4 The first intermediate structure is shown. The protruding structure 111 can be formed by protruding from the surface of the body 12 and is integrally formed with the body 12.

[0066] In another embodiment, see Figure 5 The auxiliary structure 11 includes a plurality of grooves 112 formed on the surface of the body 12, which are obtained through step 110. Figure 6 The first intermediate structure is shown. The groove 112 can be formed by recessing the surface of the body 12 and is integrally formed with the body 12.

[0067] In yet another embodiment, see Figure 7 and Figure 8 The auxiliary structure 11 includes a frame body 113. The semiconductor packaging method further includes attaching the frame body to a first region of the body. In some embodiments, the frame body 113 may be attached to the first region 101 of the body 12 firstly, and then at least one chip 20 to be packaged may be attached to a second region 102 of the body 12. After attaching the frame body to the first region of the body 12, the following can be obtained: Figure 7 and Figure 8 The structure is shown. In other embodiments, the chip 20 to be packaged may be mounted on the second region 102 of the body 12 first, and then the auxiliary structure 11 may be mounted on the first region 101 of the body 12. Alternatively, the chip 20 to be packaged and the auxiliary structure 11 may be mounted on the body 12 simultaneously.

[0068] The frame 113 can be disposed in the edge region of the body 12, and the placement of the frame 113 does not affect the mounting of the chip 20 to be packaged. Step 110 yields the following result: Figure 9 and Figure 10 The first intermediate structure shown has the chip 20 to be packaged located within the area enclosed by the frame body 113.

[0069] In some embodiments, the frame 113 may be attached to the body 12 by an adhesive layer, and the adhesive layer may be made of an easily peelable material so that the frame 113 may be subsequently peeled off from the body 12. For example, the adhesive layer may be made of a heat-removing material that can be de-adhesive by heating.

[0070] Figure 4 , Figure 6 and Figure 10 In the illustrated embodiment, a plurality of chips 20 to be packaged are mounted on the body 12. In other embodiments, the number of chips 20 to be packaged mounted on the body 12 may be one.

[0071] In step 120, an encapsulation layer is formed on the carrier board, the encapsulation layer encapsulates the at least one chip to be encapsulated, resulting in an encapsulation structure including the at least one chip to be encapsulated and the encapsulation layer; the auxiliary structure forms a positioning structure close to the surface of the body of the encapsulation structure.

[0072] Step 120 yields the following result: Figure 11 , Figure 12 or Figure 13 The second intermediate structure is shown. During the subsequent formation of the redistribution layer, an exposure process is required. The positioning structure is used to determine the location to be exposed before the exposure process. Specifically, before the exposure process, an image can be captured by a camera device. The controller can identify the positioning structure in the image and determine its position information. Based on the relative positional relationship between the positioning structure and the location to be exposed, the location to be exposed is determined.

[0073] In some embodiments, the number of positioning structures is multiple, meaning two or more. In some embodiments, the number of positioning structures is at least three, and these at least three positioning structures are arranged at intervals on the surface of the encapsulation structure. The distance between the position to be exposed and each positioning structure is a corresponding design distance. When there are three or more positioning structures, the position to be exposed at the corresponding set distance is unique, making the determined position to be exposed more accurate. In the illustrated embodiment, the body 12 is roughly rectangular, and the number of positioning structures is four, with the four positioning structures located at the four corners of the body 12. In other embodiments, the number of positioning structures can be three, five, six, etc.

[0074] In one embodiment, step 120 of forming the encapsulation layer may include the following steps:

[0075] First, an encapsulation material layer is formed, which covers the carrier board and encapsulates at least one chip to be encapsulated. The distance from the surface of the encapsulation material layer away from the body 12 is greater than a preset distance. In this step, the thickness of the encapsulation material layer is greater than the thickness of the chip 20 to be encapsulated, so that the encapsulation material layer completely encapsulates the chip 20 to be encapsulated, and the back side of the chip 20 to be encapsulated is not exposed.

[0076] Next, the encapsulation material layer is thinned on the side facing away from the carrier substrate to obtain the encapsulation layer. The distance from the surface of the encapsulation layer facing away from the body 12 to the body 12 is equal to a preset distance. In this step, the encapsulation material layer can be thinned using a grinding process. When the distance from the surface of the encapsulation layer facing away from the body 12 to the body 12 is equal to the preset distance, the chip to be encapsulated may or may not be exposed on the surface facing away from the body 12.

[0077] See Figure 11 , Figure 12 or Figure 13 The encapsulation layer 31 covers the body 12, encapsulating the chip 20 and the exposed surface of the body 12, and is used to encapsulate the chip 20 to be packaged in order to reconstruct a flat plate structure. That is, the encapsulation structure 30 is flush with the surface of the body 12 so that after the carrier board 10 is peeled off, rewiring and packaging can continue on the reconstructed flat plate structure.

[0078] In one embodiment, before forming the encapsulation layer 31, some pretreatment steps, such as chemical cleaning or plasma cleaning, can be performed to remove impurities from the surface of the chip 20 and the carrier 10, so that the encapsulation layer 31 can be more closely connected to the surface of the chip 20 to be encapsulated and the carrier 10, and delamination or cracking will not occur.

[0079] In one embodiment, the encapsulation layer 31 can be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding of an epoxy resin compound.

[0080] In one embodiment, see Figure 11 The auxiliary structure 11 includes a plurality of protrusions 111 formed on the surface of the body 12, and the positioning structure 21 includes encapsulation structure grooves 211 formed on the surface of the encapsulation structure 30 corresponding to each of the protrusions 111. When forming the encapsulation layer 31, the encapsulation layer 31 covers each chip 20 to be encapsulated and the protrusions 111, thereby forming encapsulation structure grooves 211 at positions corresponding to the protrusions 111.

[0081] In some embodiments, the thickness of the protrusion 111 is greater than or equal to 10 μm. The depth range of the formed encapsulation structure groove 211 is the same as the thickness range of the protrusion 111, that is, the depth of the encapsulation structure groove 211 is greater than or equal to 10 μm. This avoids the encapsulation structure groove 211 being too shallow, resulting in low contrast between the encapsulation structure groove 211 and other areas in the image captured by the camera device, making it difficult to identify the encapsulation structure groove 211.

[0082] Furthermore, the thickness of the protrusion structure 111 is less than or equal to 20 μm. This avoids the encapsulation structure groove 211 being too deep, which would cause the encapsulation structure groove 211 to penetrate the encapsulation structure 30, resulting in electrolyte leakage through the encapsulation structure groove 211 during the subsequent electroplating process to form the redistribution layer. The thickness of the protrusion structure 111 can be, for example, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, etc. Figure 2 In the illustrated embodiment, the cross-section of the protrusion structure 111 is circular only as an example. In other embodiments, the cross-section of the protrusion structure 111 may also be rectangular, annular, or other shapes.

[0083] In another embodiment, see Figure 12 The auxiliary structure 11 includes a plurality of groove structures 112 formed on the surface of the body 12, and the positioning structure 21 includes encapsulation structure protrusions 212 formed on the surface of the encapsulation structure 30 corresponding to each of the groove structures 112. When forming the encapsulation layer 31, the encapsulation layer 31 covers each chip 20 to be encapsulated and fills the groove structures 112, thereby forming encapsulation structure protrusions 212 at positions corresponding to the groove structures 112 in the encapsulation layer 31.

[0084] In some embodiments, the depth of the groove structure 112 is greater than or equal to 10 μm. The depth range of the formed encapsulation structure protrusion 212 is the same as the thickness range of the groove structure 112, that is, the thickness of the encapsulation structure protrusion 212 is greater than or equal to 10 μm. This setting avoids the encapsulation structure protrusion 212 being too thin, resulting in low contrast between the brightness and darkness of the encapsulation structure protrusion 212 and other areas in the image acquired by the imaging device, which would make the encapsulation structure protrusion 212 difficult to identify.

[0085] Furthermore, the depth of the groove structure 112 is less than or equal to 20 μm. In subsequent steps, during the formation of the redistribution layer, it is necessary to ensure that the surface of the formed dielectric layer is flat. This design avoids the encapsulation structure protrusion 212 being too thick, which would result in an excessively thick dielectric layer to be formed in subsequent steps, making the process difficult to implement. The depth of the groove structure 112 can be, for example, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, etc. Figure 2 In the illustrated embodiment, the cross-section of the groove structure 112 is circular only as an example. In other embodiments, the cross-section of the groove structure 112 may also be rectangular, annular, or other shapes.

[0086] In another embodiment, when the auxiliary structure 11 is integrally formed with the body 12, the auxiliary structure 11 includes at least one protrusion and at least one groove formed on the surface of the body 12, and the positioning structure 21 includes a groove portion of the encapsulation structure corresponding to the protrusion formed on the surface of the encapsulation structure 30 and a protrusion portion of the encapsulation structure corresponding to the groove formed on the surface of the encapsulation structure. For example, the auxiliary structure 11 on the surface of the body 12 includes two protrusions and two grooves, and the positioning structure includes two recesses and two protrusions of the encapsulation structure formed on the surface of the encapsulation structure 30.

[0087] In the three embodiments described above, the auxiliary structure 11 is integrally formed with the body 12. Therefore, during the formation of the encapsulation layer, the auxiliary structure 11 will not be displaced relative to the body 12, and the position of the positioning structure 21 formed on the encapsulation structure will not be shifted. Furthermore, the positioning structure 21 is integrally formed with the encapsulation layer 31. When the encapsulation layer 31 shrinks after the encapsulation structure 30 is subsequently peeled off from the body 12, the positioning structure 21 shrinks as well, and the distance between different positioning structures 21 will change. The deviation between the actual distance between different positioning structures 21 and the design distance (the distance between different positioning structures 21 before the encapsulation structure 30 is peeled off from the body 12 is the design distance) can be calculated. The position to be exposed is determined based on the actual distance between different positioning structures 21 and the corresponding deviation, ensuring the accuracy of the determined position to be exposed.

[0088] In another embodiment, the encapsulation layer 31 covers the frame body 113, which is a one-piece structure, meaning it is an integral structure independent of the main body 12. The encapsulation structure 30 also includes the frame body 113. See also Figure 7 and Figure 13The frame body 113 includes a first surface 1131 and a second surface 1132 facing each other. The first surface 1131 is located on the same side as the front side of the chip 20 to be packaged. The positioning structure 21 includes the frame body 113. With this configuration, when the encapsulation layer 31 is formed, it encapsulates the frame body 113. After the encapsulation structure 30 is subsequently peeled off from the body 12, the frame body 113 separates from the body 12, exposing the first surface 1131 of the frame body 113. The position to be exposed can be determined through the frame body 113. Since the frame body 113 is an independent component, the position of the positioning structure is not affected by the encapsulation material when the encapsulation layer 31 is formed; that is, the position of the positioning structure does not change. In subsequent steps, after peeling the encapsulation structure 30 from the body 12, the exposure position determined based on the position of the positioning structure can be highly accurate, which helps to improve the exposure accuracy.

[0089] In one embodiment, the first surface 1131 includes positioning areas 1133, and there may be multiple positioning areas 1133. Each positioning area 1133 has a frame recess 1134. This arrangement allows the positioning area 1133 to have a different contrast between its brightness and darkness and other areas of the first surface 1131 in the image acquired by the camera device, facilitating the identification of the positioning area 1133. In some embodiments, the frame recess 1134 of the positioning area 1133 may have a specific pattern.

[0090] In one embodiment, the number of chips 20 to be packaged is multiple, and the auxiliary structure 11 further includes multiple rods 114 located within and connected to the frame body 113. The multiple rods 114 divide the area enclosed by the frame body 113 into multiple cutout areas, and the chips 20 to be packaged are located in the cutout areas. The number of cutout areas may be the same as the number of chips 20 to be packaged and may correspond one-to-one, with each chip 20 to be packaged located in a corresponding cutout area. By providing the rod portion 114, the auxiliary structure 11 can be made stronger, preventing deformation of the frame body 113 during the process of mounting the auxiliary structure 11 onto the body 12 or during the formation of the encapsulation layer 31, which would cause changes in the relative positions of different positioning areas 1133 and help improve exposure accuracy. Furthermore, the rod portion 114 divides the frame body 113 into multiple cutout areas, each containing a chip 20 to be encapsulated. Therefore, the rod portion 114 can act as an alignment point when mounting the chip 20 to be encapsulated, helping to improve the accuracy of mounting the chip 20. In some embodiments, the frame body 113 and the rod portion 114 can be made of metal.

[0091] In step 130, when the auxiliary structure is integrally formed with the main body, the carrier board is peeled off to expose the positioning structure and the chip to be packaged; when the auxiliary structure is an integral structure, the main body is peeled off to expose the positioning structure and the chip to be packaged.

[0092] Step 130 yields the following result: Figure 14 , Figure 15 or Figure 16 The third intermediate structure shown.

[0093] In one embodiment, the carrier plate 10 or the body 12 can be directly and mechanically peeled off from the encapsulation structure 30. In another embodiment, when the chip 20 to be encapsulated is bonded to the body 12 by an adhesive layer, and the adhesive layer is made of a heat-removing material, heating can be used to reduce the adhesiveness of the adhesive layer, thereby peeling off the body 12 or the carrier plate 10. If the chip 20 to be encapsulated is mounted on the body 12 with its front side facing the body 12, peeling off the body 12 or the carrier plate 10 will expose the front side of each chip 20 to be encapsulated. When the auxiliary structure includes a frame body 113, the frame body 113 is bonded to the body 12 by an adhesive layer, and the adhesive layer is made of a heat-removing material, heating can be used to reduce the adhesiveness of the adhesive layer, thereby peeling off the body 12 and exposing the first surface of the frame body.

[0094] In one embodiment, see Figure 17 If the front side of the chip is located on the same side as the positioning structure, then after peeling off the body 12, the front side of the chip is exposed. After step 130 of peeling off the body, the semiconductor packaging method further includes steps 140 to 170.

[0095] In step 140, a conductive layer is formed on the front side of the chip.

[0096] Before this step, the third intermediate structure is first flipped so that the front side of the chip 20 is facing up, and the third intermediate structure is fixed on the support plate to facilitate the subsequent formation of a conductive layer on the front side of the chip.

[0097] When forming a conductive layer, a seed layer can be formed first, followed by an electroplating process to form a metal layer on the seed layer. The conductive layer includes both the seed layer and the metal layer. The seed layer and the metal layer can cover the front side of the chip and the packaging layer.

[0098] In step 150, a photoresist film is formed on the conductive layer, and the position of the photoresist film to be exposed is determined according to the positioning structure.

[0099] In step 160, the photoresist film is exposed according to the position to be exposed in order to pattern the photoresist film and obtain the photoresist layer.

[0100] In this step, after exposing the area to be exposed, the photoresist film layer can be patterned using a development process.

[0101] In step 170, the area of ​​the conductive layer not blocked by the photoresist layer is etched to obtain a redistribution layer.

[0102] Step 170 yields the following result: Figure 18 , Figure 19 and Figure 20 The fourth intermediate structure is shown. The redistribution layer includes conductive structures 50 for bringing out the pads on the front side of the chip.

[0103] Since the positioning structure in the third intermediate structure is relatively accurate, the position of the photoresist film layer to be exposed, determined by the positioning structure, is relatively accurate, the pattern of the photoresist layer is relatively accurate, and thus the reliability of the rewiring layer in the fourth intermediate structure is relatively high.

[0104] In one embodiment, after etching the area of ​​the conductive layer not blocked by the photoresist layer, the resulting structure is a semiconductor package structure. The semiconductor packaging method further includes: removing the photoresist layer; cutting the semiconductor package structure to remove the positioning structure.

[0105] When cutting semiconductor package structures, one can follow... Figure 18 , Figure 19 and Figure 20 The packaged chip is obtained by cutting along the dashed lines shown. Furthermore, the positioning structure is removed during the cutting process of the semiconductor package structure; when the positioning structure includes a frame, the connecting rods are also removed.

[0106] In this embodiment of the application, the positioning structure can also be used to position the cutting position when cutting the semiconductor package structure, or to position the printing position when printing product information onto the surface of the chip.

[0107] This application also provides a carrier board for a semiconductor packaging method. See [link to relevant documentation]. Figure 2 , Figure 3 , Figure 5 , Figure 7 and Figure 8 The carrier board 10 includes a body 12 and an auxiliary structure 11. The surface of the body 12 includes a first region 101 and a second region 102. The auxiliary structure 12 is disposed in the first region 101, and the second region 102 is used to mount the chip to be packaged. The auxiliary structure 11 is integrally formed with the body 12, or the auxiliary structure 11 is an integral structure.

[0108] In one embodiment, the auxiliary structure 11 is integrally formed with the body 12, and the auxiliary structure 11 includes a plurality of protrusions 111 and / or at least one groove structure 112 formed on the surface of the body 12.

[0109] In some embodiments, the thickness of the protrusion structure 111 is greater than or equal to 10 μm, and the depth of the groove structure 112 is greater than or equal to 10 μm.

[0110] Figure 3 In the embodiment shown, the auxiliary structure 11 includes a plurality of protrusions 111. Figure 5 In the embodiment shown, the auxiliary structure 11 includes a plurality of grooves 112.

[0111] In one embodiment, see Figure 7 and Figure 8 When the auxiliary structure 11 is an integral structure, the auxiliary structure 11 includes a frame body 113; the frame body 113 includes a first surface 1131 and a second surface 1132 facing each other, with the first surface 1131 facing the main body.

[0112] In some embodiments, the first surface 1131 includes a positioning area 1133, and the positioning area 1133 is provided with a frame body recess 1134.

[0113] In one embodiment, the auxiliary structure 11 further includes a plurality of rods 114 located within and connected to the frame body 113, the plurality of rods 114 dividing the area enclosed by the frame body 113 into a plurality of hollow areas.

[0114] The carrier board for semiconductor packaging method provided in this application belongs to the same inventive concept as the above-described semiconductor packaging method. The relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0115] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0116] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0117] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A semiconductor packaging method, characterized by, The application relates to a semiconductor packaging method. The method comprises the following steps: mounting at least one chip to be packaged on a carrier plate; the carrier plate comprises a body and an auxiliary structure arranged on the surface of the body; the surface of the body comprises a first region and a second region; the at least one chip to be packaged is mounted on the second region of the body; the auxiliary structure is arranged on the first region of the body; the auxiliary structure is integrally formed with the body, or the auxiliary structure is an integral structure; when the auxiliary structure is an integral structure, the auxiliary structure comprises a frame body and a plurality of rod parts arranged in the frame body and connected with the frame body; the plurality of rod parts divide the region surrounded by the frame body into a plurality of hollow regions; forming an encapsulation layer on the carrier plate, so as to encapsulate the at least one chip to be packaged, and obtaining an encapsulation structure comprising the at least one chip to be packaged and the encapsulation layer; the auxiliary structure makes the encapsulation structure form a plurality of positioning structures close to the surface of the body; the number of the chips to be packaged is plural, and each chip to be packaged is located in the hollow region; when the auxiliary structure is integrally formed with the body, the carrier plate is peeled off to expose the positioning structures and the chips to be packaged; when the auxiliary structure is an integral structure, the body is peeled off to expose the positioning structures and the chips to be packaged; forming a conductive layer on the front surface of the chip; forming a photoresist film layer on the conductive layer, and determining the position to be exposed of the photoresist film layer according to the positioning structures; exposing the photoresist film layer according to the position to be exposed, so as to perform a patterning treatment on the photoresist film layer, and obtaining a photoresist layer; performing etching on the region of the conductive layer which is not shielded by the photoresist layer, and obtaining a redistribution layer.

2. The semiconductor packaging method of claim 1, wherein, when the auxiliary structure is integrally formed with the body, the auxiliary structure comprises a plurality of protruding structures formed on the surface of the body, and the positioning structures comprise encapsulation structure groove parts corresponding to the protruding structures and formed on the surface of the encapsulation structure; or, when the auxiliary structure is integrally formed with the body, the auxiliary structure comprises a plurality of groove structures formed on the surface of the body, and the positioning structures comprise encapsulation structure protruding parts corresponding to the groove structures and formed on the surface of the encapsulation structure; or, when the auxiliary structure is integrally formed with the body, the auxiliary structure comprises at least one protruding structure and at least one groove structure formed on the surface of the body, and the positioning structures comprise encapsulation structure groove parts corresponding to the protruding structures and formed on the surface of the encapsulation structure, and encapsulation structure protruding parts corresponding to the groove structures and formed on the surface of the encapsulation structure.

3. The semiconductor packaging method of claim 1, wherein, the frame body comprises opposite first and second surfaces; before the step of mounting the at least one chip to be packaged on the carrier plate, the semiconductor packaging method further comprises the step of mounting the first surface of the frame body on the first region of the body. The encapsulation layer also encapsulates the frame body, and the encapsulation structure also comprises the frame body; the positioning structure comprises the frame body; the first surface of the frame body comprises a plurality of positioning areas, and the positioning areas are provided with frame body recesses.

4. A carrier for a semiconductor packaging method, characterized by, The semiconductor packaging method of any one of claims 1 to 3; the carrier plate comprises a main body and an auxiliary structure, a surface of the carrier plate comprises a first area and a second area; the auxiliary structure is arranged on the first area, and the second area is used for attaching a chip to be packaged; the auxiliary structure is integrally formed with the main body, or the auxiliary structure is an integral structure; when the auxiliary structure is an integral structure, the auxiliary structure comprises a frame body and a plurality of rod portions located in the frame body and connected with the frame body, and the plurality of rod portions divide an area surrounded by the frame body into a plurality of hollow areas.

5. The carrier plate for a semiconductor packaging method according to claim 4, wherein When the auxiliary structure is integrally formed with the main body, the auxiliary structure comprises at least one protruding structure and / or at least one recess structure formed on a surface of the main body.

6. The carrier plate for a semiconductor packaging method according to claim 5, wherein The thickness of the protruding structure is greater than or equal to 10 μm; and the depth of the recess structure is greater than or equal to 10 μm.

7. The carrier plate for a semiconductor packaging method according to claim 4, wherein The frame body comprises opposite first and second surfaces, and the first surface faces the main body. The first surface of the frame body comprises a plurality of positioning areas, and the positioning areas are provided with recesses.

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