Fan-out packaging method and packaging structure

Abstract

The present invention provides a fan-out packaging method and packaging structure, comprising: fixing the front faces of multiple groups of functional chips on the surface of a wafer carrier in the form of a first array, forming a first plastic encapsulation layer on the back faces of the multiple groups of functional chips; removing the wafer carrier, forming a high-density interconnection wiring layer on the front faces of the multiple groups of functional chips; cutting the multiple groups of functional chips, and fixing the side with the high-density interconnection wiring layer on the surface of a panel carrier in the form of a second array; fixing the first surfaces of multiple first chips and multiple passive components on the surface of the panel carrier; forming a second plastic encapsulation layer on the side of the multiple groups of functional chips facing away from the high-density interconnection wiring layer, and on the second surfaces of the multiple first chips and multiple passive components; removing the panel carrier, and forming a low-density interconnection wiring layer on the high-density interconnection wiring layer. The packaging method of the present invention can effectively meet the requirements of high-density interconnection, while being low-cost and having a high output rate.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a fan-out packaging method and packaging structure. Background Art

[0002] With the advancement of semiconductor technology, packaging technology is moving towards higher density and higher integration. Currently, fan-out technology has become a key development direction for high-density interconnects. By using redistribution layers to connect single and multiple chips, it significantly increases the flexibility of packaging integration. Fan-out technology has been applied in fields such as high-performance computing (HPC) and mobile phone processors.

[0003] Currently, there are two main development directions for fan-out technology: fan-out wafer-level packaging (FOWLP) based on wafer technology, and fan-out panel-level packaging (FOPLP) based on panel technology. Fan-out wafer-level packaging can achieve higher wiring density, and currently has achieved mass production of line widths of 2 microns, but the yield rate is low and the cost is high. Fan-out panel-level packaging has high yield rate and low cost, but due to the large panel size, fine line widths are difficult to achieve. Currently, the line widths that can be mass-produced are all above 5μm.

[0004] For multi-chip system-level packaging, such as Figure 1 As shown, there are multiple chips in the middle, and the wiring density requirements of each chip are different, but the same process is currently used. It needs to follow the most stringent technical standards and the manufacturing cost is high.

[0005] In view of the above problems, it is necessary to propose a fan-out packaging method and packaging structure that is reasonably designed and can effectively solve the above problems. Summary of the Invention

[0006] The present invention aims to solve at least one of the technical problems existing in the prior art and provide a fan-out packaging method and packaging structure.

[0007] One aspect of the present invention provides a fan-out packaging method, the method comprising:

[0008] Provide wafer carriers and panel carriers;

[0009] Fixing the front sides of the plurality of functional chips in a first array on the surface of the wafer carrier, and forming a first plastic sealing layer on the back sides of the plurality of functional chips;

[0010] Separating the plurality of functional chips from the wafer carrier, and forming a high-density interconnection wiring layer on the front surface of the plurality of functional chips;

[0011] Cutting the plurality of functional chips and fixing the side having the high-density interconnection wiring layer formed thereon on the surface of the panel carrier in the form of a second array;

[0012] Fixing the first surfaces of a plurality of first chips and a plurality of passive components on the surface of the panel carrier;

[0013] forming a second plastic encapsulation layer on a side of the plurality of groups of functional chips away from the high-density interconnect wiring layer, and on a second surface of the plurality of first chips and the plurality of passive components;

[0014] The plurality of groups of functional chips, the plurality of first chips, and the plurality of passive components are separated from the panel carrier, and a low-density interconnection wiring layer is formed on the high-density interconnection wiring layer.

[0015] Optionally, the dielectric materials of the first dielectric layer and the second dielectric layer are different.

[0016] Optionally, forming a high-density interconnection wiring layer on the front surface of the plurality of groups of functional chips includes:

[0017] forming a first dielectric layer on the front surface of the first plastic packaging layer and the plurality of groups of functional chips;

[0018] patterning the first dielectric layer to form a plurality of first openings;

[0019] forming a first metal interconnection layer on the surface of the patterned first dielectric layer;

[0020] The first metal interconnection layer is patterned to form the high-density interconnection wiring layer.

[0021] Optionally, forming a low-density interconnect wiring layer on the surface of the high-density interconnect wiring layer includes:

[0022] forming a second dielectric layer on a surface of the high-density interconnect wiring layer, the plurality of first chips, and the first surfaces of the plurality of passive devices;

[0023] patterning the second dielectric layer to form a plurality of second openings;

[0024] forming a second metal interconnection layer on the surface of the patterned second dielectric layer;

[0025] The second metal interconnection layer is patterned to form the low-density interconnection wiring layer.

[0026] Optionally, the dielectric materials of the first dielectric layer and the second dielectric layer are different.

[0027] Optionally, after forming the low-density interconnect wiring layer, the method further includes:

[0028] forming a third dielectric layer on the surface of the patterned second metal interconnection layer;

[0029] patterning the third dielectric layer to form a plurality of third openings;

[0030] Ball planting is performed at the plurality of third openings to form a plurality of solder balls.

[0031] Optionally, each group of functional chips includes at least two different types of chips.

[0032] Another aspect of the present invention provides a fan-out packaging structure, comprising a functional chipset, a first chip, a passive device, a high-density interconnect wiring layer, a low-density interconnect wiring layer, a first plastic packaging layer, and a second plastic packaging layer;

[0033] The high-density interconnect wiring layer is arranged on the front of the first plastic packaging layer and the functional chip in the functional chipset;

[0034] The low-density interconnect wiring layer is disposed above the high-density interconnect wiring layer and the first surface of the first chip and the passive device;

[0035] The first plastic packaging layer wraps the functional chipset;

[0036] The second plastic packaging layer wraps the functional chipset, the first chip and the passive components.

[0037] Optionally, the high-density interconnect wiring layer includes a first dielectric layer provided on the front side of the functional chip in the functional chipset, and a first metal interconnect layer provided on the first dielectric layer;

[0038] The low-density interconnect wiring layer includes a second dielectric layer disposed on the first metal interconnect layer, the first chip and the first surface of the passive device, and a second metal interconnect layer disposed on the second dielectric layer.

[0039] Optionally, the first chip and the passive component are respectively arranged on both sides of the functional chipset.

[0040] Optionally, the functional chipset includes at least two chips of different types.

[0041] The fan-out packaging method and packaging structure of the present invention adopt high-density interconnection in multiple groups of functional chips, which can well meet the high-density interconnection requirements; the first chip and passive components adopt low-density interconnection, which can improve the output rate and reduce the manufacturing cost. By integrating wafer-level fan-out technology and panel-level fan-out technology, different levels of interconnection are integrated into one package. Compared with the current traditional fan-out wafer-level packaging, the fan-out packaging method of the present invention can provide lower cost and higher output rate under the conditions of equal interconnection density. Compared with the current traditional fan-out panel-level packaging, the fan-out packaging method of the present invention can provide higher interconnection density to meet the needs of high-performance devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic flow chart of a fan-out packaging method according to an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of a chip placement area in a wafer carrier according to another embodiment of the present invention;

[0044] Figure 3 Schematic diagram of a second array B on a panel carrier according to another embodiment of the present invention;

[0045] Figure 4 Schematic diagram of a first array A on a wafer carrier according to another embodiment of the present invention;

[0046] Figures 5 to 18 This is a schematic diagram of a packaging process for a fan-out packaging structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0048] like Figure 1 As shown, one aspect of the present invention provides a packaging method S100 of a fan-out packaging structure, the packaging method S100 comprising:

[0049] S110, providing wafer carrier and panel carrier.

[0050] Specifically, if Figure 2 、 Figure 3 and Figure 4 As shown, a wafer carrier 110 and a panel carrier 120 are provided. The wafer carrier 110 is primarily made of glass, silicon wafer, or metal. The panel carrier 120 is primarily made of glass, metal, or a glass fiber resin sheet. The materials of the wafer carrier 110 and the panel carrier 120 are not specifically limited in this embodiment and can be selected as needed.

[0051] The passive device 140 may be at least one of a resistor, a capacitor, an inductor, a converter, a gradienter, a matching network, a resonator, a filter, a mixer, a switch, etc., which is not specifically limited in this embodiment.

[0052] S120, fixing the front sides of the plurality of functional chips in a first array on the surface of the wafer carrier, and forming a first plastic packaging layer on the back sides of the plurality of functional chips.

[0053] It should be noted that each group of functional chips includes at least two chips of different types. Figure 5 As shown, in this embodiment, each group of functional chips includes a second chip 150 and a third chip 160. The second chip 150 and the third chip 160 are two different types of chips, and the second chip 150 and the third chip 160 are high-performance chips, such as processors. Of course, each group of functional chips can also include other functional chips, which is not specifically limited in this embodiment.

[0054] Specifically, if Figure 5 As shown, in this embodiment, the front sides of the second chip 150 and the third chip 160 in the plurality of functional chips are fixed to the surface of the wafer carrier 110 by the first patch adhesive 111, and the wafer level packaging technology is used to well meet the high density interconnection requirements. Figure 3 As shown, after the multiple groups of functional chips are attached, they form a first array A, which is a square array. Figure 6 As shown, a molding compound is used to mold the backsides of the functional chips in the plurality of functional chip groups. That is, a first molding layer 170 is formed on the backsides of the second chip 150 and the third chip 160 in the plurality of functional chip groups. The molding method can be vacuum lamination or a conventional molding process, which is not specifically limited in this embodiment.

[0055] S130, separating the multiple groups of functional chips from the wafer carrier, and forming a high-density interconnection wiring layer on the front side of the multiple groups of functional chips.

[0056] Specifically, if Figure 7 As shown, the multiple functional chips are separated from the wafer carrier 110, that is, the wafer carrier 110 is removed. The separation method can be thermal separation, laser separation, ultraviolet light separation, mechanical separation, etc. These methods are all commonly used temporary bonding separation methods. The separation method is not specifically limited in this embodiment and can be selected according to actual needs.

[0057] A high-density interconnection wiring layer is formed on the front surface of the plurality of functional chips, comprising:

[0058] First, a first dielectric layer is formed on the front surface of the first plastic packaging layer and the plurality of groups of functional chips.

[0059] Specifically, if Figure 8 As shown, a first dielectric layer 151 is applied to the front surface of the first plastic encapsulation layer 170 and the functional chips in the plurality of functional chips. In other words, the first dielectric layer 151 is applied to the surfaces of the first plastic encapsulation layer 170, the plurality of second chips 150, and the plurality of third chips 160. The material of the first dielectric layer 151 is polyimide (PI), polybenzoxazole (PBO), etc., and the coating method is typically wafer spin coating, which is not specifically limited in this embodiment. The first dielectric layer 151 protects the plurality of functional chips.

[0060] Next, the first dielectric layer is patterned to form a plurality of first openings.

[0061] like Figure 8 As shown, the first dielectric layer 151 is patterned by a photolithography process to form a plurality of first openings 152 .

[0062] Next, a first metal interconnection layer is formed on the surface of the patterned first dielectric layer.

[0063] Specifically, if Figure 9 As shown, a first metal interconnect layer 153 is deposited on the surface of the patterned first dielectric layer 151. The deposition method can be electroplating, sputtering, thermal evaporation, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition. The metal material of the first metal interconnect layer 153 is typically titanium or copper. The deposition method and metal material are not specifically limited in this embodiment.

[0064] Finally, the first metal interconnection layer is patterned to form the high-density interconnection wiring layer.

[0065] Specifically, if Figure 9 As shown, the first metal interconnect layer 153 is patterned by photolithography and etching processes to form a high-density interconnect wiring layer. The etching process can be wet etching or dry etching, which is not specifically limited in this embodiment.

[0066] In this embodiment, multiple groups of functional chips are high-performance chips of different types, such as processor chips. In system-level packaging design, high-performance chips usually have high wiring requirements, so multiple groups of functional chips are packaged using fan-out wafer-level packaging to form the above-mentioned high-density interconnection wiring layer, which can provide higher interconnection density and meet the needs of high-performance devices.

[0067] S140, cutting the plurality of functional chips, and fixing the side having the high-density interconnection wiring layer formed thereon on the surface of the panel carrier in the form of a second array.

[0068] Specifically, multiple groups of functional chips are cut according to the area size of the panel carrier 120 and Figure 4The second array B shown is fixed on the surface of the panel carrier 120, and the panel level packaging technology is used to improve the yield and reduce the manufacturing cost. Figure 10 As shown, the side where the high-density interconnection wiring layer is formed is fixed on the panel carrier 120 by the second patch adhesive 121 , that is, the first metal interconnection layer 153 is attached to the second patch adhesive 121 .

[0069] S150, fixing the first surfaces of a plurality of first chips and a plurality of passive components on the surface of the panel carrier.

[0070] It should be noted that in this embodiment, the first chip 130 is a low-performance chip, but may also be other types of chips, which are not specifically limited in this embodiment. The passive component 140 may be at least one of a resistor, a capacitor, an inductor, a converter, a gradienter, a matching network, a resonator, a filter, a mixer, and a switch, which are not specifically limited in this embodiment.

[0071] Specifically, if Figure 11 As shown, multiple first chips 130 and multiple passive components 140 are also fixed to the panel carrier 120 via the second adhesive 121. Furthermore, in this embodiment, the first chips 130 and the passive components 140 are respectively arranged on both sides of each group of functional chips. The first chips 130 and the passive components 140 may also be distributed in other ways, which are not specifically limited in this embodiment.

[0072] S160 , forming a second plastic encapsulation layer on a side of the multiple groups of functional chips away from the high-density interconnection wiring layer, and on a second surface of the multiple third chips and the multiple passive components.

[0073] Specifically, if Figure 12 As shown, multiple groups of functional chips are fixed to the panel carrier 120 in a second array B on a side facing away from the high-density interconnect wiring layer, and a second plastic encapsulation layer is formed on the second surface of the multiple first chips 130 and the multiple passive components 140. In other words, the second plastic encapsulation layer 180 encapsulates the multiple first chips 130, the multiple passive components 140, the multiple second chips 150, and the multiple third chips 160. The plastic encapsulation method can be film vacuum lamination or a traditional plastic encapsulation process, which is not specifically limited in this embodiment.

[0074] S170, separating the multiple groups of functional chips, the multiple first chips, and the multiple passive components from the panel carrier, and forming a low-density interconnection wiring layer on the high-density interconnection wiring layer.

[0075] Specifically, if Figure 13As shown, multiple groups of functional chips, multiple first chips 130, and multiple passive components 140 are separated 120 from the panel carrier, that is, the panel carrier 120 is removed. The separation method can be thermal separation, laser separation, ultraviolet light separation, mechanical separation, etc. These methods are all currently commonly used temporary bonding separation methods. The separation method is not specifically limited in this embodiment and can be selected according to actual needs.

[0076] Forming a low-density interconnection wiring layer on the high-density interconnection wiring layer, comprising:

[0077] First, a second dielectric layer is formed on a surface of the high-density interconnect wiring layer, the plurality of first chips, and first surfaces of the plurality of passive devices.

[0078] Specifically, if Figure 14 As shown, a second dielectric layer 131 is formed on the first metal interconnect layer 153, the first surfaces of the plurality of first chips 130, and the first surfaces of the plurality of passive devices 140. The second dielectric layer 131 protects the first metal interconnect layer 153. The material of the second dielectric layer 131 can be a photosensitive dielectric layer (PID) or an Ajinomoto laminated film (ABF), etc., which is not specifically limited in this embodiment. The process of covering the first metal interconnect layer 153, the first surfaces of the plurality of first chips 130, and the first surfaces of the plurality of passive devices 140 with the second dielectric layer 131 can be a vacuum lamination process or a printing process, which is not specifically limited in this embodiment.

[0079] Next, the second dielectric layer is patterned to form a plurality of second openings.

[0080] Specifically, if Figure 14 As shown, the second dielectric layer 131 is patterned using a photolithography process to form a plurality of second openings 132 on the second dielectric layer 131 .

[0081] Next, a second metal interconnection layer is formed on the surface of the patterned second dielectric layer.

[0082] Specifically, if Figure 15 As shown, a second metal interconnect layer 133 is deposited on the surface of the patterned second dielectric layer 131. The deposition method can be electroplating, sputtering, thermal evaporation, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition. The metal material of the second metal interconnect layer 133 is typically titanium or copper. The deposition method and metal material are not specifically limited in this embodiment.

[0083] Finally, the second metal interconnection layer is patterned to form the low-density interconnection wiring layer.

[0084] Specifically, if Figure 15As shown, the second metal interconnection layer 133 is patterned by photolithography and etching processes to form a low-density interconnection wiring layer. The etching process can be wet etching or dry etching, which is not specifically limited in this embodiment.

[0085] In this embodiment, the first chip is a low-performance chip, such as a power device. In the system-level packaging design, the wiring requirements of the low-performance chip are usually low, so multiple first chips and multiple passive devices are packaged in a fan-out panel level to form the above-mentioned low-density interconnection wiring layer, which can improve the output rate and reduce the manufacturing cost.

[0086] Exemplarily, the dielectric materials of the first dielectric layer 151 and the second dielectric layer 131 are different. The material of the first dielectric layer 151 is polyimide (PI), polybenzoxazole (PBO), etc., and the material of the second dielectric layer 131 is a photosensitive dielectric layer (PID) or ajinomoto laminated film (ABF), etc. This is because the first dielectric layer 151 is made on a wafer-level process, and the second dielectric layer 131 is made on a panel-level process. The preferred dielectric layer is selected according to different processes, and the two dielectric layers are close in material and there will be no problems such as poor contact or inability to implement the process.

[0087] Exemplarily, after forming the low-density interconnect wiring layer, the method further includes:

[0088] First, a third dielectric layer is formed on the surface of the patterned second metal interconnection layer.

[0089] Specifically, if Figure 16 As shown, the third dielectric layer 134 is covered on the surface of the patterned second metal interconnect layer 133. The material of the third dielectric layer 134 can be a photosensitive solder resist (PSR), etc., and is not specifically limited in this embodiment. The process of covering the third dielectric layer 134 on the second metal interconnect layer 133 can be a vacuum lamination process or a printing process, and the process of covering the third dielectric layer 134 on the second metal interconnect layer 133 is not specifically limited in this embodiment.

[0090] Next, the third dielectric layer is patterned to form a plurality of third openings.

[0091] Specifically, if Figure 16 As shown, the third dielectric layer 134 is patterned by a photolithography process to form a plurality of third openings 135 on the third dielectric layer 134 .

[0092] Finally, ball planting is performed at the plurality of third openings to form a plurality of solder balls.

[0093] Specifically, if Figure 17 As shown, ball planting is performed at the plurality of third openings 135 to form a plurality of solder balls 136 , and the plurality of solder balls 136 are electrically connected to the outside.

[0094] For example, Figure 18 As shown, after forming a plurality of solder balls 136, the plurality of functional chips and the first chip 130 and passive components 140 located on both sides of each functional chip group are cut to form a single chip package structure. Each chip package structure includes a second chip 150 and a third chip 160 located in the middle region, and a first chip 130 and passive components 140 located in the edge region.

[0095] It should be noted that if the thickness of the second plastic encapsulation layer 180 is very thick, the side of the second plastic encapsulation layer facing away from the multiple groups of functional chips can be polished after forming the solder balls 136 to reduce the package thickness. Alternatively, the side of the second plastic encapsulation layer facing away from the multiple groups of functional chips can be polished after forming the second plastic encapsulation layer 180 to reduce the package thickness, ultimately forming an optimal package structure.

[0096] The fan-out packaging method and packaging structure of the present invention adopt high-density interconnection in multiple groups of functional chips, which can well meet the high-density interconnection requirements; the first chip and passive components adopt low-density interconnection, which can improve the output rate and reduce the manufacturing cost. By integrating wafer-level fan-out technology and panel-level fan-out technology, different levels of interconnection are integrated into one package. Compared with the current traditional fan-out wafer-level packaging, the fan-out packaging method of the present invention can provide lower cost and higher output rate under the conditions of equal interconnection density. Compared with the current traditional fan-out panel-level packaging, the fan-out packaging method of the present invention can provide higher interconnection density to meet the needs of high-performance devices.

[0097] It should be noted that, in the embodiments given, a 3-layer or 4-layer dielectric structure is used. In practice, the present invention can be applied to a variety of layers and can be adjusted according to actual design needs. The number of interconnect layers used in wafer-level and panel-level processes can also be adjusted according to actual design needs. For example, if the second interconnect layer also requires high-density interconnection (which cannot be achieved by panel-level processes), two interconnect layers can be produced using wafer-level processes and then transferred to panel-level processes.

[0098] It should be further explained that, in the present invention, Figure 2 As shown, the middle area of the wafer carrier 110 is the chip placement area 112. The chip placement area 112 is as shown in FIG. Figure 3 In the first array A shown, the chip placement area 112 is a square structure, and its diagonal length is equivalent to the diameter of the wafer carrier 110. Through temporary bonding and wafer-level rewiring, a high-density interconnection wiring layer is formed in the middle area. The chip placement area 112 with high-density interconnection is cut to form a Figure 4 The form of the second array B shown is integrally constructed onto the panel carrier 120.

[0099] like Figure 4 As shown, the size of the currently commonly used panel carrier 120 is 510×515 mm. In this case, four chip layout areas 112 can be placed at the same time, and the subsequent processes can be completed using panel-level packaging interconnection technology. The production efficiency can reach 4 times that of wafer-level packaging technology. In the future, if LCD panel technology is used, the production efficiency can be increased to 6 to 8 times, and the cost will be greatly reduced.

[0100] like Figure 2 As shown, since the area of the chip placement area 112 is smaller than the area of the wafer carrier 110, a certain area loss will occur. Taking into account that the chips are all rectangular or square in size, the main loss area is the blank area 113 in the figure, whose short side dimension is 28 mm. For samples with a package size close to or greater than 28 mm, this area is an invalid area, but for samples with a package size close to or less than 28 mm, the blank area 113 can still be used, so the design of the chip placement area 112 will not increase the cost of wafer-level packaging. Since high-density interconnection is mainly used in fields such as high-performance computing, packaging in this field is developing towards large sizes, so the present invention has a significant cost-reducing effect.

[0101] In packaging design, the interconnection layer density near the chip is usually high, while the interconnection layer density far from the chip is low, and the connection line width tends to expand step by step. Taking advantage of this feature, the packaging method of the fan-out packaging structure provided by the present invention integrates fan-out wafer-level packaging technology and fan-out panel-level packaging technology to complete fan-out packaging production. For the interconnection layer near the chip, wafer-level packaging technology is used to well meet the high-density interconnection requirements, while for the interconnection layer far from the chip, panel-level packaging technology is used to improve output and reduce manufacturing costs.

[0102] like Figure 18 As shown, another aspect of the present invention provides a fan-out packaging structure 100, which includes a functional chipset (not marked in the figure), a first chip 130, a passive device 140, a high-density interconnect wiring layer (not marked in the figure), a low-density interconnect wiring layer (not marked in the figure), a first plastic layer 170 and a second plastic layer 180.

[0103] It should be noted that each functional chipset includes at least two different types of chips, such as Figure 18As shown, in this embodiment, each group of functional chips includes a second chip 150 and a third chip 160. The second chip 150 and the third chip 160 are different types of chips, and the second chip 150 and the third chip 160 are high-performance chips, such as processors. Of course, each group of functional chips can also include other functional chips, which is not specifically limited in this embodiment. In this embodiment, the first chip 130 is a low-performance chip, or it can be another type of chip, which is not specifically limited in this embodiment. The passive device 140 can be at least one of a resistor, a capacitor, an inductor, a converter, a gradienter, a matching network, a resonator, a filter, a mixer, and a switch, which is not specifically limited in this embodiment.

[0104] like Figure 18 As shown, the high-density interconnect wiring layer is provided on the first plastic layer 170 and the front of the functional chips in the functional chipset. In other words, the high-density interconnect wiring layer is provided on the surface of the first plastic layer 170 and the front of the second chip 150 and the third chip 160.

[0105] like Figure 18 As shown, the low-density interconnect wiring layer is disposed on the high-density interconnect wiring layer and on the first surface of the first chip 130 and the passive device 140. In this embodiment, the first chip 130 and the passive device 140 are disposed on both sides of the functional chipset.

[0106] like Figure 18 As shown, the first plastic encapsulation layer 170 encapsulates the functional chipset, that is, the first plastic encapsulation layer 170 encapsulates the plurality of second chips 150 and the plurality of third chips 160 .

[0107] like Figure 18 As shown, the second molding layer 180 wraps the functional chipset, the first chip 130 and the passive components 140. In other words, the second molding layer 180 wraps the plurality of first chips 130, the plurality of passive components 140, the plurality of second chips 150 and the plurality of third chips 160.

[0108] For example, Figure 18 As shown, the high-density interconnect wiring layer includes a first dielectric layer 151 disposed on the front surface of the functional chips in the functional chip group, and a first metal interconnect layer 153 disposed on the first dielectric layer 151. In other words, the front surface of the second chip 150 and the third chip 160 in each group of functional chips is provided with the first dielectric layer 151.

[0109] Exemplarily, the low-density interconnect wiring layer includes a second dielectric layer 131 disposed on the first metal interconnect layer 153 , the first chip 130 and the first surface of the passive device 140 , and a second metal interconnect layer 133 disposed on the second dielectric layer 131 .

[0110] Exemplarily, the package structure further includes a third dielectric layer 134 and a plurality of solder balls 136 . The third dielectric layer 134 is disposed on the second metal interconnection layer 133 , and the plurality of solder balls 136 are disposed on the third dielectric layer 134 .

[0111] The fan-out packaging structure provided by the present invention not only has low cost and high output rate, but also can well meet the demand for high-density interconnection.

[0112] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A fan-out packaging method, characterized in that: The method comprises: Provide wafer carriers and panel carriers; Fixing the front sides of the plurality of functional chips in a first array on the surface of the wafer carrier, and forming a first plastic sealing layer on the back sides of the plurality of functional chips; Separating the plurality of functional chips from the wafer carrier, and forming a high-density interconnection wiring layer on the front surface of the plurality of functional chips; Cutting the plurality of functional chips and fixing the side having the high-density interconnection wiring layer formed thereon on the surface of the panel carrier in the form of a second array; Fixing the first surfaces of a plurality of first chips and a plurality of passive components on the surface of the panel carrier; forming a second plastic encapsulation layer on a side of the plurality of groups of functional chips away from the high-density interconnect wiring layer, and on a second surface of the plurality of first chips and the plurality of passive components; The plurality of groups of functional chips, the plurality of first chips, and the plurality of passive components are separated from the panel carrier, and a low-density interconnection wiring layer is formed on the high-density interconnection wiring layer.

2. The method according to claim 1, characterized in that The forming of a high-density interconnection wiring layer on the front surface of the plurality of functional chips comprises: forming a first dielectric layer on the front surface of the first plastic packaging layer and the plurality of groups of functional chips; patterning the first dielectric layer to form a plurality of first openings; forming a first metal interconnection layer on the surface of the patterned first dielectric layer; The first metal interconnection layer is patterned to form the high-density interconnection wiring layer.

3. The method according to claim 2, characterized in that The step of forming a low-density interconnection wiring layer on the high-density interconnection wiring layer comprises: forming a second dielectric layer on a surface of the high-density interconnect wiring layer, the plurality of first chips, and the first surfaces of the plurality of passive devices; patterning the second dielectric layer to form a plurality of second openings; forming a second metal interconnection layer on the surface of the patterned second dielectric layer; The second metal interconnection layer is patterned to form the low-density interconnection wiring layer.

4. The method according to claim 3, characterized in that The dielectric materials of the first dielectric layer and the second dielectric layer are different.

5. The method according to claim 4, characterized in that After forming the low-density interconnect wiring layer, the method further includes: forming a third dielectric layer on the surface of the patterned second metal interconnection layer; patterning the third dielectric layer to form a plurality of third openings; Ball planting is performed at the plurality of third openings to form a plurality of solder balls.

6. The method according to any one of claims 1 to 5, characterized in that Each group of functional chips includes at least two chips of different types.

7. A fan-out packaging structure, characterized in that: The fan-out packaging method according to any one of claims 1 to 6 is used for packaging, wherein the packaging structure includes a functional chipset, a first chip, passive components, a high-density interconnect wiring layer, a low-density interconnect wiring layer, a first plastic encapsulation layer, and a second plastic encapsulation layer; The high-density interconnect wiring layer is arranged on the front of the first plastic packaging layer and the functional chip in the functional chipset; The low-density interconnect wiring layer is disposed above the high-density interconnect wiring layer and the first surface of the first chip and the passive device; The first plastic packaging layer wraps the functional chipset; The second plastic packaging layer wraps the functional chipset, the first chip and the passive components.

8. The packaging structure according to claim 7, wherein: The high-density interconnect wiring layer includes a first dielectric layer arranged on the front side of the functional chip in the functional chipset, and a first metal interconnect layer arranged on the first dielectric layer; The low-density interconnect wiring layer includes a second dielectric layer disposed on the first metal interconnect layer, the first chip and the first surface of the passive device, and a second metal interconnect layer disposed on the second dielectric layer.

9. The packaging structure according to claim 7 or 8, characterized in that: The first chip and the passive components are respectively arranged on two sides of the functional chipset.

10. The packaging structure according to claim 7 or 8, characterized in that: The functional chipset includes at least two chips of different types.

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