Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: forming a core material layer on a substrate; doping the core material layer to improve the etching resistance of the core material layer, the doped core material layer being used as an anti-etching layer, and the undoped core material layer being used as an initial core layer; forming a gap penetrating a portion of the initial core layer in contact with the sidewall of the anti-etching layer, and the remaining initial core layer being used as a core layer; forming a groove penetrating a portion of the anti-etching layer between a first sidewall and a second sidewall; forming a mask sidewall filling the gap on the sidewall of the groove, the mask sidewall located on the sidewall of the groove forming a first groove; forming a second groove penetrating the anti-etching layer between the mask sidewall located on the first groove and the second sidewall; removing the core layer to form a third groove; using the mask sidewall and the anti-etching layer as a mask, patterning the target layer below the first groove, the second groove, and the third groove. The embodiment of the present invention improves the accuracy of the target pattern.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] In the development of integrated circuits, as the functional density (i.e. the number of internal connection structures of each chip) gradually increases, the geometric size (i.e. the minimum component size that can be produced using the process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] At present, as technology nodes continue to shrink, how to improve the matching degree between the pattern formed on the wafer and the target pattern has become a challenge. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the pattern transfer accuracy and process effect of a patterned target layer.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a target layer for forming a target pattern; forming a core material layer on the substrate; performing ion doping on the core material layer, which is suitable for improving the etching resistance of the core material layer, the core material layer doped with ions serves as an anti-etching layer, and the core material layer not doped with ions serves as an initial core layer, the initial core layer extends along a first direction and is arranged at intervals along a second direction, the first direction and the second direction being perpendicular to each other; forming a gap that penetrates a portion of the initial core layer in contact with a side wall of the anti-etching layer, and the remaining initial core layer serves as a core layer, adjacent to the first direction in the second direction. The opposite side walls of the core layer are respectively a first side wall and a second side wall; a groove is formed that penetrates a portion of the anti-etching layer located between the first side wall and the second side wall, the groove exposes the first side wall, and has a gap between the first side wall and the gap located on the second side wall; a mask side wall is formed on the side wall of the groove to fill the gap, and the mask side wall located on the side wall of the groove forms a first groove; a second groove is formed that penetrates the anti-etching layer between the mask side wall located on the first groove and the second side wall; the core layer is removed to form a third groove; using the mask side wall and the anti-etching layer as a mask, the target layer below the first groove, the second groove and the third groove is patterned to form a target pattern.

[0007] Accordingly, an embodiment of the present invention further provides a semiconductor structure, comprising: a substrate, comprising a target layer for forming a target pattern; a core layer separated from the substrate, extending along a first direction and arranged along a second direction, the second direction being perpendicular to the first direction, and the opposite side walls of adjacent core layers along the second direction are respectively a first side wall and a second side wall; an anti-etching layer, located on the substrate at the side of the core layer, a gap being formed between the anti-etching layer and the side wall of the core layer, the anti-etching layer and the core layer being made of the same material, and ions being doped in the anti-etching layer, the ions being suitable for making the etching resistance of the anti-etching layer greater than the etching resistance of the core layer. The core layer has an etching resistance of at least one embodiment of the present invention; a groove penetrating a portion of the anti-etching layer between the first sidewall and the second sidewall, the groove exposing the first sidewall and having a gap with the gap on the second sidewall; a mask sidewall located on the sidewall of the groove and filling the gap, wherein the mask sidewall located on the sidewall of the groove forms a first groove, and the mask sidewall and the anti-etching layer are used as a mask for patterning the target layer; a second groove penetrating the anti-etching layer between the first groove and the mask sidewall located on the second sidewall; wherein the core layer is used to occupy space for forming a third groove.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the method for forming a semiconductor structure provided by an embodiment of the present invention, ion doping is performed on a core material layer to form the anti-etching layer and the initial core layer, thereby realizing patterning of the core material layer, and the ion doping is suitable for improving the etching resistance of the core material layer, so that the etching resistance of the anti-etching layer is greater than that of the initial core layer, and the etching selectivity ratio of the initial core layer or the core layer to the anti-etching layer is correspondingly improved. In the process of forming the gap, it is beneficial to reduce the process difficulty of etching the portion of the initial core layer that is in contact with the side wall of the anti-etching layer, and in the step of removing the core layer to form a third groove, the anti-etching layer can be retained as a mask for patterning the target layer, and the anti-etching layer can be ensured to play a corresponding masking effect, thereby improving the graphic transfer accuracy and process effect of the patterned target layer, and further making the target graphic meet the process requirements.

[0010] In addition, the embodiment of the present invention uses the ion doping and the gap to define the shape and position of the core layer, thereby defining the shape and position of the third groove, and uses the groove and the mask sidewall to define the shape and position of the first groove. Compared with the solution of defining the shapes and positions of the first groove, the second groove and the third groove by etching process or a single film layer structure, the embodiment of the present invention defines the shapes and positions of the first groove, the second groove and the third groove respectively through different process steps, which is conducive to reducing the difficulty of forming the first groove, the second groove and the third groove, increasing the process window (for example, improving the optical proximity effect, alleviating the limitation of the resolution of the photolithography process), and improving the freedom and flexibility of the graphic design of the first groove, the second groove and the third groove, so that the graphic accuracy of the first groove, the second groove and the third groove is guaranteed. Moreover, after the first groove, the second groove and the third groove are formed, along the second direction, the third groove and the adjacent second groove or the first groove, and the second groove and the adjacent first groove are isolated by the mask sidewall, which is conducive to achieving the designed minimum spacing between adjacent grooves. space), and accordingly, after the target layer below the first groove, the second groove and the third groove is patterned to form a target pattern, the pattern quality and pattern accuracy of the target pattern are improved, and it is easy to achieve the minimum design spacing between adjacent target patterns along the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 26 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0012] As can be seen from the background technology, how to improve the matching degree between the pattern formed on the wafer and the target pattern has become a challenge. Specifically, in the current back-end process, the patterning process of metal interconnects is difficult and has a small process window.

[0013] For example, when the graphics of the interconnection pattern is more complex, the number of masks required for the photolithography process is large, which not only leads to excessively high process costs, but also the complexity of the mask pattern and the difficulty of optical proximity correction processing of the mask, resulting in poor graphic accuracy and quality of the formed interconnection lines, and even easily causing the interconnection lines to short-circuit (Bridge) at locations where they do not need to be connected.

[0014] One method uses dummy lines to increase the window of the photolithography process and reduce the complexity of the mask pattern. When the device is working, these dummy lines are in a floating state, that is, these lines are not electrically connected to the external circuit or other interconnection structures. However, these floating dummy lines are prone to increase the parasitic capacitance of the back-end interconnection, resulting in poor performance of the formed semiconductor structure.

[0015] In order to solve the technical problem, in the method for forming a semiconductor structure provided by an embodiment of the present invention, ion doping is performed on the core material layer to form the anti-etching layer and the initial core layer, thereby realizing the patterning of the core material layer, and the ion doping is suitable for improving the etching resistance of the core material layer, thereby improving the etching selectivity of the initial core layer or the core layer and the anti-etching layer. In the process of forming the gap, it is beneficial to reduce the process difficulty of etching the part of the initial core layer that is in contact with the side wall of the anti-etching layer, and in the step of removing the core layer to form a third groove, it is also beneficial to enable the anti-etching layer to be retained as a mask for patterning the target layer, and accordingly ensure that the anti-etching layer can play a corresponding masking effect, which is beneficial to improve the graphic transfer accuracy and process effect of the patterned target layer, and thus make the target graphic meet the process requirements.

[0016] In addition, compared with the solution of defining the shapes and positions of the first groove, the second groove and the third groove by etching process or a single film layer structure, the embodiment of the present invention defines the shapes and positions of the first groove, the second groove and the third groove by different process steps, which is conducive to reducing the difficulty of forming the first groove, the second groove and the third groove, increasing the process window (for example: improving the optical proximity effect, alleviating the limitation of the resolution of the photolithography process), and improving the freedom and flexibility of the graphic design of the first groove, the second groove and the third groove, so that the graphic accuracy of the first groove, the second groove and the third groove is guaranteed. Moreover, along the second direction, the third groove and the adjacent second groove or the first groove, and the second groove and the adjacent first groove are isolated by the mask sidewall, which is conducive to achieving the designed minimum spacing between adjacent grooves. Accordingly, after the target layer below the first groove, the second groove and the third groove is patterned to form the target pattern, the graphic quality and graphic accuracy of the target pattern are improved, and it is easy to achieve the design minimum spacing between adjacent target patterns along the second direction.

[0017] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figures 1 to 26 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0018] refer to Figure 1 and Figure 2 , Figure 1 is a top view, Figure 2 for Figure 1 In the cross-sectional view at the AA position, a substrate 100 is provided, including a target layer 110 for forming a target pattern. The substrate 100 is used to provide a platform for the process. The target layer 110 is a film layer to be patterned to form a target pattern. The target pattern can be a gate structure, an interconnection groove in the back-end process, a fin in a fin field effect transistor (FinFET), a channel stack or a hard mask (HM) layer in a gate-all-around (GAA) transistor, and the like.

[0019] In this embodiment, the target layer 110 is a dielectric layer, and the target pattern is an interconnection groove. The interconnection groove is used to provide a spatial position for forming an interconnection line, and the dielectric layer is used to achieve electrical isolation between the interconnections. Accordingly, semiconductor devices such as transistors and capacitors can be formed in the substrate, and functional structures such as a resistor structure and a conductive structure can also be formed in the substrate. In this embodiment, the substrate includes a substrate 120 and a target layer 110 located on the substrate 120. The dielectric layer is an intermetallic dielectric (IMD) layer, and the material of the dielectric layer includes a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride or silicon oxynitride, etc.

[0020] In this embodiment, the substrate 100 further includes a hard mask material layer 130 located on the target layer 110 .

[0021] Subsequently, the hard mask material layer 130 is first patterned to form a hard mask layer, and then the target layer 110 is patterned using the hard mask layer as a mask. This is beneficial to improving the process stability of the patterned target layer 110 and correspondingly improving the accuracy of the pattern transfer. Moreover, the hard mask material layer 130 can also define the etching stop position in the subsequent etching process to avoid damage to the target layer 110, and is also beneficial to preventing the problem of inconsistent etching.

[0022] The material of the hard mask material layer 130 includes one or more of titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxycarbonitride. As an example, the material of the hard mask material layer 130 is titanium nitride.

[0023] In a specific process, according to actual process requirements, a stress buffer layer can be provided between the hard mask material layer 130 and the target layer 110 to improve adhesion between the hard mask material layer 130 and the target layer 110 and reduce stress generated between film layers.

[0024] Continue to refer Figure 1 and Figure 2 , a core material layer 140 is formed on the substrate 100 .

[0025] The core material layer 140 is used to form an initial core layer and an anti-etching layer through subsequent ion doping.

[0026] The material of the core material layer 140 includes one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride and silicon carbonitride oxide. In this embodiment, the material of the core material layer 140 is amorphous silicon.

[0027] It should be noted that the formation method also includes: after forming the core material layer 140, forming an etch stop layer 150 on the core material layer 140. Subsequently, a sacrificial layer is formed on the etch stop layer 150, and a sacrificial sidewall is formed on the sidewall of the sacrificial layer. The process of forming the sacrificial layer and the sacrificial sidewall includes a process combining deposition and etching. The etch stop layer 150 is used to define the stop position of etching to avoid over-etching, thereby reducing the probability of inconsistent top surface height of the film layer to be etched below the etch stop layer 150. In this embodiment, the material of the etch stop layer 150 is silicon oxide. In other embodiments, the material of the etch stop layer can also be materials such as silicon nitride or silicon oxynitride.

[0028] Continue to refer Figure 1 and Figure 2 In this embodiment, after forming the core material layer 140, the forming method further includes: forming a separate sacrificial layer 160 on the core material layer 140, the sacrificial layer 160 along the first direction (such as Figure 1 X direction) and extends along the second direction (as shown in Figure 1 The first direction and the second direction are perpendicular to each other.

[0029] The sacrificial layer 160 is used to define the shape and position of the subsequent core layer, and the sacrificial layer 160 also provides support for the subsequent formation of sacrificial sidewalls. The material of the sacrificial layer 160 includes one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride and carbon silicon oxynitride. In this embodiment, the material of the sacrificial layer 160 is amorphous silicon.

[0030] Combined with reference Figure 3 and Figure 4 , Figure 3 is a top view, Figure 4 for Figure 3In the cross-sectional view at the AA position, a sacrificial sidewall 170 is formed on the sidewall of the sacrificial layer 160. The sacrificial sidewall 170 is used together with the sacrificial layer 160 as a mask for subsequent ion doping of the core material layer 140. The sacrificial sidewall 170 is also used to define the shape and position of the gap formed between the core layer and the anti-etching layer. Therefore, the thickness of the sacrificial sidewall 170 defines the opening width of the subsequent gap, and a mask sidewall is formed to fill the gap. The mask sidewall is used to isolate adjacent grooves, and the thickness of the sacrificial sidewall 170 defines the interval between the subsequent adjacent grooves.

[0031] The sacrificial spacer 170 is made of a material having etching selectivity with the sacrificial layer 160, and the material of the sacrificial spacer 170 includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium nitride and titanium oxide. In this embodiment, the material of the sacrificial spacer 170 is silicon nitride.

[0032] In this embodiment, the step of forming the sacrificial sidewall 170 includes: conformally covering the first sidewall film (not shown) on the top surface and sidewall of the sacrificial layer 160 and the etch stop layer 150; removing the first sidewall film located on the top surface of the sacrificial layer 160 and the etch stop layer 150, and the remaining first sidewall film located on the sidewall of the sacrificial layer 160 is used as the sacrificial sidewall 170. In this embodiment, an atomic layer deposition process is used to form the first sidewall film. The atomic layer deposition process has a high step coverage capability, which is beneficial to improve the coverage capability of the first sidewall film on the sidewall of the sacrificial layer 160, and is also beneficial to improve the thickness uniformity of the first sidewall film. In this embodiment, an anisotropic etching process is used to remove the first sidewall film located on the top surface of the sacrificial layer 160 and the etch stop layer 150. Specifically, the anisotropic etching process includes an anisotropic dry etching process.

[0033] refer to Figure 5 The core material layer 140 is ion-doped 180, which is suitable for improving the etching resistance of the core material layer 140. The core material layer 140 doped with ions serves as an anti-etching layer 210, and the core material layer 140 not doped with ions serves as an initial core layer 220. The initial core layer 220 extends along a first direction and is arranged at intervals along a second direction, and the first direction is perpendicular to the second direction.

[0034] After the first groove and the second groove are formed in the anti-etching layer 210, the remaining anti-etching layer 210 is used as a mask for the subsequent patterning of the target layer 110. The initial core layer 220 is used to form a core layer through a subsequent etching process, and the core layer is used to occupy a space position for the subsequent formation of the first groove.

[0035] In this embodiment, the core material layer 140 is ion doped 180 to form an anti-etching layer 210 and an initial core layer 220, thereby patterning the core material layer 140. The ion doping is suitable for improving the etching resistance of the core material layer 140, so that the etching resistance of the anti-etching layer 210 is greater than that of the initial core layer 220, and the etching selectivity ratio of the initial core layer 220 or the core layer and the anti-etching layer 210 is correspondingly improved. In the subsequent step of removing the core layer to form the third groove, it is beneficial to enable the anti-etching layer 210 to be retained as a mask for the patterned target layer 110, and accordingly ensure that the anti-etching layer 210 can play a corresponding masking effect, thereby facilitating the improvement of the pattern transfer accuracy and process effect of the patterned target layer 110, and further enabling the target pattern to meet the process requirements. Moreover, in the subsequent process of forming the gap, it is beneficial to reduce the difficulty of etching the part of the initial core layer 220 that contacts the side wall of the anti-etching layer 210.

[0036] In this embodiment, the ions used for ion doping 180 on the core material layer 140 include one or more of boron ions, phosphorus ions, and argon ions.

[0037] In this embodiment, the step of performing ion doping 180 on the core material layer 140 includes: performing ion doping 180 on the core material layer 140 exposed by the sacrificial layer 160 and the sacrificial sidewall 170. That is, in this embodiment, the sacrificial layer 160 and the sacrificial sidewall 170 are used as masks for ion doping 180, so that there is no need to form an additional mask for ion doping, which is conducive to saving costs and simplifying the process. In addition, the sacrificial layer 160 is also used to define the shape and position of the subsequent core layer, and the sacrificial sidewall 170 is used to define the shape and position of the subsequent gap. In this embodiment, the sacrificial layer 160 and the sacrificial sidewall 170 are also used as masks for ion doping 180, so as to integrate the step of ion doping 180 with the subsequent process of forming the core layer and the gap, which is conducive to improving the process integration and simplifying the process flow. In addition, the position of the subsequent gap can be self-aligned with the area of ​​the core material layer 140 (i.e., the initial core layer 220) that is not doped with ions, thereby avoiding errors caused by alignment and reducing the difficulty of the process.

[0038] Combined with reference Figure 6 to Figure 7 , Figure 6 is a top view, Figure 7 for Figure 6 In the cross-sectional view at position AA, the forming method further includes: after performing ion doping 180 and before forming the gap and the trench, forming a filling layer 190 covering the sidewalls of the sacrificial spacer 170 on the anti-etching layer 210 .

[0039] The filling layer 190 is used together with the sacrificial layer 160 as a mask for subsequent etching of the initial core layer 210. In this embodiment, the filling layer 190 is located on the etching stop layer 150.

[0040] The filling layer 190 is made of a material having etching selectivity with the material of the sacrificial sidewall 170, the etch stop layer 150 and the initial core layer 210. The material of the filling layer 190 includes one or more of spin-coated silicon oxide, metal oxide (e.g., titanium oxide), polysilicon and amorphous silicon. In this embodiment, the material of the filling layer 190 is spin-coated silicon oxide. The material of the filling layer 190 is suitable for the spin coating process, thereby reducing the difficulty of forming the filling layer 190, improving the filling quality of the filling layer 190 and the top surface flatness.

[0041] In this embodiment, the step of forming the filling layer 190 includes: forming a filling material layer (not shown) covering the sacrificial sidewall 170 and the sacrificial layer 160 on the anti-etching layer 210; removing the filling material layer above the top surface of the sacrificial sidewall 170 and the sacrificial layer 160 to form the filling layer 190.

[0042] The process of forming the filling material layer includes one or more of an atomic layer deposition process, a chemical vapor deposition process, and a spin coating process. As an example, the filling material layer is formed by a spin coating process. The spin coating process is simple to operate, has a low process cost, and is conducive to improving the flatness of the top surface of the filling material layer. In this embodiment, a planarization process is used to remove the filling material layer 150 that is higher than the top surface of the core layer 120. Specifically, the planarization process includes a dry etching process (e.g., an anisotropic dry etching process).

[0043] refer to Figures 8 to 9 , Figure 8 is a top view, Fig. 9 for Figure 8 In the cross-sectional view at position AA, the sacrificial spacer 170 is removed, and a mask groove 230 is formed between the sidewalls of the sacrificial layer 160 and the filling layer 190 .

[0044] The mask groove 230 is used to define the shape and position of the subsequent gap. After removing the sacrificial spacer 170 , the filling layer 190 and the sacrificial layer 160 are used as masks for etching the initial core layer 210 .

[0045] The process of removing the sacrificial sidewall 170 includes one or both of dry etching and wet etching. In this embodiment, a wet etching process is used to remove the sacrificial sidewall 170. The wet etching process is easy to achieve a high etching selectivity, which is conducive to cleanly removing the sacrificial sidewall 170 and is simple to operate. Specifically, the material of the sacrificial sidewall 170 is silicon nitride, and the etching solution of the wet etching process is a hot phosphoric acid solution.

[0046] refer to Figures 10 to 12, forming a gap 260 penetrating a portion of the initial core layer 220 in contact with the side wall of the anti-etching layer 210, and the remaining initial core layer 220 serves as the core layer 240, and the opposite side walls of adjacent core layers 240 along the second direction are the first side wall 11 and the second side wall 12 respectively.

[0047] The core layer 240 is used to occupy a space position for forming the third groove. The gap 260 is used to provide a space position for the subsequent formation of the mask sidewall. In this embodiment, the gap 260 surrounds the sidewall of the core layer 240, and the gap 260 is located between the sidewall of the core layer 240 and the anti-etching layer 210.

[0048] In this embodiment, the step of forming the gap 260 includes: etching the initial core layer 220 below the mask groove 230 to form the gap 260 between the core layer 240 and the sidewall of the anti-etching layer 210 .

[0049] Specifically, in this embodiment, the initial core layer 220 below the mask groove 230 is etched using the sacrificial layer 160 and the filling layer 190 as masks. The gap 260 is formed by etching the initial core layer 220 below the mask groove 230, so that there is no need to additionally form a mask for etching the initial core layer to form the gap, which is conducive to reducing the process difficulty of forming the gap 260, for example: avoiding alignment of the photolithography process, thereby preventing the problem of overlay offset, and correspondingly improving the pattern quality and pattern accuracy of the gap 260, so that the opening width of the gap 260 meets the process requirements. In this embodiment, the gap 260 corresponds to the position of the sacrificial sidewall 170.

[0050] In this embodiment, an etching process is used to etch the initial core layer 220 below the mask groove 230 to form a gap 260; the etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, which is conducive to improving the controllability of the etching profile and the etching accuracy, and correspondingly improving the accuracy of the pattern transfer. In this embodiment, the etching process is used to sequentially etch the etching stop layer 150 and the initial core layer 220 below the mask groove 230.

[0051] In this embodiment, the forming method further includes: after forming the gap 260, removing the filling layer 190 and the sacrificial layer 160. The filling layer 190 and the sacrificial layer 160 are removed to facilitate the subsequent formation of a mask sidewall in the gap 260 and prepare for subsequent process steps.

[0052] refer to Figures 13 to 16A groove 270 is formed that penetrates a portion of the anti-etching layer 210 between the first sidewall 11 and the second sidewall 12, exposing the first sidewall 11 and having a gap 260 on the second sidewall 12. The sidewall of the groove 270 is used to provide support for the subsequent formation of a mask sidewall, and the groove 270 is also used to define the pattern and position of the first groove with the subsequent mask sidewall.

[0053] By forming the groove 270, the first side wall 11 of the core layer 240 is exposed, so that after the mask side wall is subsequently formed, the mask side wall located on the side wall of the groove 270 forms a first groove, and the interval between the first groove and the first side wall 11 is the thickness of the mask side wall. Correspondingly, the interval between the subsequent third groove and the first groove is the thickness of the mask side wall 200, which is conducive to ensuring that the designed minimum interval between the third groove and the first groove is met.

[0054] In this embodiment, taking the process of forming the groove 270 after forming the gap 260 as an example, the specific steps of forming the groove 270 are described in detail.

[0055] like Fig.13 and Fig.14 As shown, Fig.13 is a top view, Fig.14 for Fig.13 In the cross-sectional view at position AA, a cover layer 261 is formed on the anti-etching layer 210 and the core layer 240, and the cover layer 261 fills the gap 260. A pattern opening 264 is formed in the cover layer 230, which is located above a portion of the anti-etching layer 210 between the first side wall 11 and the second side wall 12. The cover layer 261 is used as a mask for etching the anti-etching layer 210 to form a groove. In this embodiment, the material of the cover layer 261 is spin-on carbon (SOC).

[0056] In this embodiment, an anti-reflection layer 262 and a pattern layer 263 located on the anti-reflection layer 262 are also formed on the cover layer 261. In this embodiment, the material of the anti-reflection layer 262 is bottom anti-reflective coating (BARC), and the material of the pattern layer 263 is photoresist.

[0057] like Fig.15 and Fig.16 As shown, Fig.15 is a top view, Fig.16 for Fig.15 In the cross-sectional view at position AA, the anti-etching layer 210 below the pattern opening 264 is etched with the cover layer 261 as a mask; the cover layer 261 is removed. In this embodiment, an anisotropic dry etching process is used to etch the anti-etching layer 210 below the pattern opening 264, which is beneficial to improve the accuracy of pattern transfer.

[0058] The process of removing the capping layer 261 includes an ashing process. In this embodiment, the formation of the groove 270 after forming the gap 260 is taken as an example. In other embodiments, the gap and the groove can also be formed in the same step.

[0059] Correspondingly, in the step of forming the sacrificial layer, the opposite side walls of the sacrificial layers adjacent to each other along the second direction are the third side wall and the fourth side wall respectively; after forming the filling layer and before forming the gap and the groove, the method for forming the semiconductor structure further includes: forming an opening in the filling layer, penetrating the portion of the filling layer between the third side wall and the fourth side wall, the opening exposing the sacrificial side wall on the third side wall, and having a gap between the sacrificial side wall and the sacrificial side wall on the fourth side wall, or the opening exposing the third side wall, and having a gap between the mask groove and the third side wall. The step of forming the gap and the groove correspondingly includes: using the filling layer and the sacrificial layer as masks, etching the initial core layer below the mask groove and the anti-etching layer below the opening.

[0060] refer to Fig.17 and Fig.18 , Fig.17 is a top view, Fig.18 for Fig.17 In the cross-sectional view at position AA, a mask spacer 200 is formed on the sidewall of the trench 270 to fill the gap 260, and the mask spacer 200 located on the sidewall of the trench 270 forms a first groove 101. The first groove 101 is used to define the pattern and position of the target pattern.

[0061] The mask spacer 200 and the anti-etching layer 210 are used as a mask for patterning the target layer 110 .

[0062] In this embodiment, the groove 270 and the mask sidewall 200 are first formed, so that the mask sidewall 200 located on the sidewall of the groove 270 surrounds the first groove 101. Therefore, the shape and position of the first groove 101 are defined by the groove 270 and the mask sidewall 200, which is conducive to reducing the difficulty of forming the first groove 101 (for example, relieving the limitation of the photolithography resolution) and correspondingly ensuring the graphic accuracy of the first groove 101. In addition, the first groove 101 is isolated from the core layer 240 by the mask sidewall 200. Therefore, the first groove 101 is isolated from the subsequent third groove by the mask sidewall 200, and the first groove 101 is also isolated from the subsequent second groove by the mask sidewall 200, which is conducive to achieving the designed minimum spacing between adjacent grooves.

[0063] In this embodiment, along the direction parallel to the substrate 100, the thickness of the mask spacer 200 located on the sidewall of the trench 270 is greater than or equal to 0.5 times the thickness of the sacrificial spacer 170. The thickness of the mask spacer 200 is greater than or equal to 0.5 times the thickness of the sacrificial spacer 170, thereby ensuring that the sacrificial spacer 170 can fill the gap 260.

[0064] In this embodiment, along the direction parallel to the substrate 100, the thickness of the mask side wall 200 is the same as the thickness of the sacrificial side wall 170. Accordingly, after the second groove and the third groove are subsequently formed, the intervals between two adjacent grooves along the second direction are the same. After the target layer 110 below the first groove 101, the second groove and the third groove is patterned to form a target pattern, the intervals between the target patterns along the second direction are also the same, which is beneficial to improving the uniformity of the intervals of the target patterns.

[0065] In a specific implementation, the thickness of the mask sidewall 200 can also be different from the thickness of the sacrificial sidewall 170, so that the thickness of the mask sidewall 200 and the sacrificial sidewall 170 can be adjusted according to actual needs, so that the interval between two adjacent grooves is different, thereby improving the design flexibility and freedom of the interval between target graphics.

[0066] In this embodiment, the mask sidewall 200 is made of a material having etching selectivity with the core layer 240, the target layer 110 and the anti-etching layer 210, and the material of the mask sidewall 200 includes one or more of titanium oxide, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide and amorphous silicon. As an example, the material of the mask sidewall 200 is titanium oxide.

[0067] In this embodiment, the step of forming the mask sidewall 200 includes: forming a second sidewall film (not shown) on the top surface of the anti-etching layer 210 and the core layer 240, the sidewall and bottom of the groove 270, and the gap 260; removing the second sidewall film located on the top surface of the anti-etching layer 210 and the core layer 240 and the bottom of the groove 270, and the second sidewall film located on the sidewall of the groove 270 and in the gap 260 is used as the mask sidewall 200.

[0068] In this embodiment, the process of forming the second spacer film includes an atomic layer deposition process. In this embodiment, an anisotropic dry etching process is used to remove the second spacer film located on the top surfaces of the anti-etching layer 210 and the core layer 240 and the bottom of the trench 270 .

[0069] refer to Fig.19 and Fig. 20 , Fig.19 is a top view, Fig. 20 for Fig.19 In the cross-sectional view at position AA, a second groove 102 is formed, penetrating the anti-etching layer 210 between the first groove 101 and the mask sidewall 200 on the second sidewall 12. The second groove 102 is used to define the shape and position of the subsequent target pattern.

[0070] In the present embodiment, in the step of forming the second groove 102, since the materials of the anti-etching layer 210 and the mask sidewall 200 have a high etching selectivity, even if the mask layer used to form the second groove 102 exposes part of the mask sidewall 200, the probability of the mask sidewall 200 being mistakenly etched is low, so that in the second direction, the mask sidewall 200 located on the sidewall of the groove 270 and the second sidewall 12 can play a role in defining the etching stop position, so that the etching process for forming the second groove 102 can achieve self-alignment according to the position of the mask sidewall 200, which is beneficial to reducing the difficulty of forming the second groove 102 and increasing the process window for forming the second groove 102, thereby facilitating improving the graphic accuracy and graphic quality of the second groove 102, and enabling the second groove 102 and the first groove 101, as well as the second groove 102 and the core layer 240 to be separated by the mask sidewall 200, which is correspondingly beneficial to achieving the designed minimum spacing between adjacent grooves.

[0071] In this embodiment, an etching process (eg dry etching) is adopted to etch the anti-etching layer 210 between the first groove 101 and the mask sidewall 200 on the second sidewall 12 to form the second groove 102 .

[0072] refer to Fig.21 and Fig. 22 , Fig.21 is a top view, Fig. 22 for Fig.21 In the cross-sectional view at the AA position, the core layer 240 is removed to form the third groove 103. In this embodiment, the first groove 101, the second groove 102 and the third groove 103 are arranged along the first direction (eg Fig.21 ), and along the second direction (as shown in the X direction Fig.21 The two electrodes are arranged at intervals (as shown in the Y direction).

[0073] In this embodiment, the shape and position of the core layer 240 are defined by the ion doping 180 and the gap 260, thereby defining the shape and position of the third groove 103, and the shape and position of the first groove 101 are defined by the groove 270 and the mask sidewall 200. Compared with the solution of defining the shapes and positions of the first groove, the second groove and the third groove by etching process or a single film layer structure, the shape and position of the first groove 101, the second groove 102 and the third groove 103 are defined by different process steps in this embodiment, which is conducive to reducing the difficulty of forming the first groove 101, the second groove 102 and the third groove 103, increasing the process window (for example, improving The invention can improve the freedom and flexibility of the graphic design of the first groove 101, the second groove 102 and the third groove 103, so that the graphic accuracy of the first groove 101, the second groove 102 and the third groove 103 is guaranteed. Moreover, after the first groove 101, the second groove 102 and the third groove 103 are formed, along the second direction, the third groove 103 and the adjacent second groove 102 or the first groove 101, and the second groove 102 and the adjacent first groove 101 are isolated by the mask sidewall 200, which is conducive to achieving the designed minimum space between adjacent grooves. Accordingly, after the target layer below the first groove 101, the second groove 102 and the third groove 103 is patterned to form a target pattern, the graphic quality and graphic accuracy of the target pattern are improved, and it is easy to achieve the designed minimum space between adjacent target patterns along the second direction.

[0074] In addition, in this embodiment, a sacrificial layer 160 is first formed, and the sacrificial layer 160 is used to define the shape and position of the core layer 240. Then, a sacrificial sidewall 170 is formed on the sidewall of the sacrificial layer 160. The sacrificial sidewall 170 correspondingly defines the gap 260 and the width of the mask sidewall 200 located in the gap 260. Therefore, the distance between the third grooves 103 adjacent to each other along the first direction is defined by the core layer 240 (i.e., the sacrificial layer 160), which is conducive to achieving a smaller distance between the third grooves 103 adjacent to each other along the first direction. Accordingly, after the target layer 110 below the first groove 101, the second groove 102, and the third groove 103 is patterned to form a target pattern, the adjacent target patterns can achieve a smaller distance at a head-to-head position, which is conducive to improving the layout design flexibility and freedom of the target pattern. Moreover, the embodiment of the present invention is conducive to saving process costs.

[0075] In this embodiment, in the step of removing the core layer 240, the etching selectivity ratio between the core layer 240 and the anti-etching layer 210 is at least 20:1. The core layer 240 and the anti-etching layer 210 have a high etching selectivity ratio, thereby reducing the probability of the anti-etching layer 210 being erroneously etched by the process of removing the core layer 240, and correspondingly ensuring that the anti-etching layer 210 can be retained for use as a mask for patterning the target layer 110. Among them, when the ion doping concentration in the anti-etching layer 210 is high, the etching rate of the anti-etching layer 210 in the subsequent process of removing the core layer 240 is very low, and the anti-etching layer 210 is close to etching stop, so that the anti-etching layer 210 can be used as a stop layer for removing the core layer 240.

[0076] The process of removing the core layer 240 includes one or both of wet etching and dry etching. As an example, a wet etching process is used to remove the core layer 240. Specifically, the etching solution of the wet etching process includes a TMAH (tetramethylammonium hydroxide) solution, an SC1 solution, or an SC2 solution. Among them, the SC1 solution refers to a mixed solution of NH4OH and H2O2, and the SC2 solution refers to a mixed solution of HCl and H2O2.

[0077] refer to Fig.23 and 24 , Fig.23 is a top view, Fig.24 for Fig.23 In the cross-sectional view at position AA, the target layer 110 below the first groove 101, the second groove 102 and the third groove 103 is patterned with the mask sidewall 200 and the anti-etching layer 210 as masks to form a target pattern.

[0078] As can be seen from the foregoing, the graphic design freedom and flexibility of the first groove 101, the second groove 102 and the third groove 103 are high, so that the graphic accuracy of the first groove 101, the second groove 102 and the third groove 103 is guaranteed, and it is conducive to achieving the designed minimum spacing between adjacent grooves. Accordingly, after the target layer 110 below the first groove 101, the second groove 102 and the third groove 103 is patterned to form a target pattern, the graphic quality and graphic accuracy of the target pattern are improved, and it is easy to achieve the design minimum spacing between adjacent target patterns along the second direction. In addition, this embodiment is conducive to enabling adjacent target patterns to achieve a smaller distance at a head-to-head position.

[0079] In this embodiment, the target layer 110 is a dielectric layer. Therefore, the dielectric layer below the first groove 101, the second groove 102 and the third groove 103 is patterned with the mask sidewall 200 and the anti-etching layer 210 as a mask to form an interconnection groove 300. Accordingly, the target pattern is the interconnection groove 300. The interconnection groove 300 is used to provide space for forming an interconnection line. Specifically, in this embodiment, the hard mask material layer 112 below the first groove 101, the second groove 102 and the third groove 103 is patterned with the mask sidewall 200 and the anti-etching layer 210 as a mask to form a hard mask layer 175; the dielectric layer is patterned with the hard mask layer 175 as a mask to form an interconnection groove 300.

[0080] Combined with reference Fig.25 and Fig.26 , Fig.25 is a top view, Fig.26 for Fig.25 In the cross-sectional view at position AA, in this embodiment, the forming method further includes: forming an interconnection line 310 in the interconnection groove 300 .

[0081] In the present embodiment, the interconnection grooves 300 can achieve a smaller distance at the head-to-head position, and the interconnection lines 310 can also achieve a smaller distance at the head-to-head position, which is beneficial to improving the connection capability of the interconnection lines 310 at the head-to-head position, and is also beneficial to improving the freedom and flexibility of the layout design of the interconnection lines 310; moreover, the spacing between adjacent interconnection grooves 300 along the second direction is easy to meet the designed minimum spacing, and at the same time, the graphic accuracy of the interconnection grooves 300 is relatively high, which is correspondingly beneficial to make the spacing of the interconnection lines 310 in the second direction meet the designed minimum spacing, and improve the graphic accuracy of the interconnection lines 310, thereby improving the performance of the semiconductor structure.

[0082] The interconnection line 310 is used to realize the electrical connection between the semiconductor structure and the external circuit or other interconnection structure. In this embodiment, the material of the interconnection line 310 is copper. In other embodiments, the material of the interconnection line can also be a conductive material such as cobalt, tungsten, aluminum, etc. In this embodiment, in the step of forming the interconnection line 310, the anti-etching layer 210, the mask sidewall 200 and the hard mask layer 175 are also removed to prepare for subsequent processes.

[0083] Accordingly, the present invention also provides a semiconductor structure. Fig.19 and Fig. 20 , Fig.19 is a top view, Fig. 20 for Fig.19 The cross-sectional view at position AA shows a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0084] The semiconductor structure comprises: a substrate 100, comprising a target layer 110 for forming a target pattern; a core layer 240 separated on the substrate 100, along a first direction (eg Fig.19 X direction) and extends along the second direction (as shown in Fig.19 The second direction is perpendicular to the first direction, and the side walls of the adjacent core layers 240 along the second direction are the first side wall 11 and the second side wall 12 respectively; the anti-etching layer 210 is located on the substrate 100 at the side of the core layer 240, and a gap 260 (as shown in FIG. 2 ) is formed between the side walls of the anti-etching layer 210 and the core layer 240. Fig.15 and Fig.16 As shown), the anti-etching layer 210 and the core layer 240 are made of the same material, and the anti-etching layer 210 is doped with ions, which are suitable for making the etching resistance of the anti-etching layer 210 greater than the etching resistance of the core layer 240; the groove 270 (as shown Fig.15 and Fig.16 As shown), penetrating a portion of the anti-etching layer 210 between the first side wall 11 and the second side wall 12, the groove 270 exposes the first side wall 11, and has a gap with the gap 260 on the second side wall 12; the mask sidewall 200 is located on the side wall of the groove 270 and fills the gap 260, wherein the mask sidewall 200 located on the side wall of the groove 270 surrounds the first groove 101, and the mask sidewall 200 and the anti-etching layer 210 are used as masks for patterning the target layer 110; the second groove 102, penetrating the anti-etching layer 210 between the first groove 101 and the mask sidewall 200 located on the second side wall 12; wherein the core layer 240 is used to occupy space for forming a third groove.

[0085] The core layer 240 occupies space for forming the third groove, and the core layer 240 defines the pattern and position of the third groove; the pattern and position of the first groove 101 are defined by the groove 270 and the mask sidewall 200, and the first groove 101 and the third groove are isolated by the mask sidewall 200; the second groove 102 penetrates the anti-etching layer 210 between the first groove 101 and the mask sidewall 200 located on the second sidewall 12, and accordingly, the second groove 102 is isolated from the first groove 101 or the third groove by the mask sidewall 200; therefore, the embodiment of the present invention uses the core layer 240, the groove and the mask sidewall 200, respectively The pattern and position of the third groove and the first groove 101 should be defined, which is conducive to reducing the difficulty of forming the first groove 101, the second groove 102 and the third groove, and increasing the process window (for example: improving the optical proximity effect), thereby improving the freedom and flexibility of the pattern design of the first groove 101, the second groove 102 and the third groove, so that the pattern accuracy of the first groove 101, the second groove 102 and the third groove is guaranteed, and the first groove 101, the second groove 102 and the third groove are arranged at intervals along the second direction, and adjacent grooves are separated by the mask sidewall 200, which is conducive to achieving the designed minimum spacing between adjacent grooves.

[0086] Accordingly, the target layer 110 below the first groove 101, the second groove 102 and the third groove is subsequently patterned using the mask sidewall 200 and the anti-etching layer 210 as masks. After the target pattern is formed, the pattern quality and pattern accuracy of the target pattern are improved, and it is easy to achieve the minimum design spacing between adjacent target patterns along the second direction.

[0087] In this embodiment, the anti-etching layer 210 and the core layer 240 are made of the same material, and the anti-etching layer 210 is doped with ions, which are suitable for making the etching resistance of the anti-etching layer 210 greater than that of the core layer 240, thereby correspondingly improving the etching selectivity between the core layer 240 and the anti-etching layer 210. In the process of forming the gap 260, it is beneficial to reduce the process difficulty of etching the portion of the initial core layer in contact with the side wall of the anti-etching layer 210, and in the step of removing the core layer 240 to form the third groove, it is also beneficial to allow the anti-etching layer 210 to be retained for use as a mask for the patterned target layer 110, thereby correspondingly ensuring that the anti-etching layer 210 can play a corresponding masking effect, thereby facilitating improving the graphic transfer accuracy and process effect of the patterned target layer 110, thereby enabling the target graphic to meet the process requirements.

[0088] In addition, the mask sidewall 200 is located on the outer side wall of the core layer 240, and the mask sidewall 200 located on the outer side wall of the core layer 240 is the outer side wall; after removing the core layer 240 to form the third groove, the distance between the third grooves adjacent along the first direction is defined by the core layer 240, which is conducive to achieving a smaller distance between the third grooves adjacent along the first direction. Accordingly, after patterning the first groove 101, the second groove 102 and the target layer 110 under the third groove to form a target pattern, adjacent target patterns can achieve a smaller distance at a head-to-head position, which is conducive to improving the layout design flexibility and freedom of the target pattern.

[0089] The target layer 110 is a film layer to be patterned to form a target pattern, which may be a gate structure, an interconnection trench in a back-end process, a fin in a fin field effect transistor, a channel stack or a hard mask layer in a gate-all-around transistor, and the like.

[0090] In this embodiment, the target layer 110 is a dielectric layer, and the target pattern is an interconnection groove. The interconnection groove is used to provide a spatial position for forming an interconnection line, and the dielectric layer is used to achieve electrical isolation between adjacent interconnections. Accordingly, in this embodiment, semiconductor devices such as transistors and capacitors can be formed in the substrate 100, and functional structures such as a resistor structure and a conductive structure can also be formed in the substrate 100. In this embodiment, the substrate 100 includes a substrate 120 and a target layer 110 located on the substrate 120. Therefore, the dielectric layer is an IMD layer, and the material of the dielectric layer includes a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride or silicon oxynitride, etc.

[0091] In this embodiment, the substrate 100 further includes a hard mask material layer 130 located on the target layer 110 .

[0092] Subsequently, the hard mask material layer 130 is first patterned to form a hard mask layer, and then the target layer 110 is patterned using the hard mask layer as a mask, which is beneficial to improving the process stability of the patterned target layer 110 and correspondingly improving the accuracy of pattern transfer; the hard mask material layer 130 can also define the etching stop position in the subsequent etching process to avoid damage to the target layer 110. As an example, the material of the hard mask material layer 130 is titanium nitride.

[0093] The core layer 210 is used to occupy a spatial position for forming the third groove. The anti-etching layer 210 is used together with the mask sidewall 200 as a mask for the subsequent patterning of the target layer 110. In this embodiment, the materials of the anti-etching layer 210 and the core layer 240 include: one or more of amorphous silicon, polycrystalline silicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride and silicon carbonitride oxide. In this embodiment, the doping ions in the anti-etching layer 210 include one or more of boron ions, phosphorus ions and argon ions. In this embodiment, the etching selectivity between the core layer 240 and the anti-etching layer 210 is at least 20:1. There is a high etching selectivity between the core layer 240 and the anti-etching layer 210, thereby reducing the probability of the process of removing the core layer 240 causing mis-etching of the anti-etching layer 210, and correspondingly ensuring that the anti-etching layer 210 can be retained for use as a mask for the patterning target layer 110.

[0094] The gap 260 is used to provide a space for forming the mask sidewall 200. In this embodiment, the gap 260 surrounds the sidewall of the core layer 220, and the gap 260 is located between the sidewall of the core layer 220 and the anti-etching layer 210. Accordingly, the gap 260 is used to define the interval between the third groove and the adjacent second groove 102.

[0095] The sidewalls of the trench 270 are used to provide support for forming the mask spacer 200 . The trench 270 is also used to define the pattern and position of the first recess 101 together with the mask spacer 200 located on the sidewalls of the trench 270 .

[0096] The groove 270 exposes the first sidewall 11 of the core layer 240, so that the interval between the first groove 101 and the first sidewall 11 is the thickness of the mask sidewall 200. Accordingly, the interval between the subsequent third groove and the first groove 101 is the thickness of the mask sidewall 200, which is conducive to satisfying the designed minimum interval between the third groove and the first groove 101. The first groove 101 is used to define the pattern and position of the target pattern. The mask sidewall 200 is used to be used as a mask for patterning the target layer 110 with the anti-etching layer 210.

[0097] In this embodiment, the shape and position of the first groove 101 are defined by the groove 270 and the mask sidewall 200, which is conducive to reducing the difficulty of forming the first groove 101 and correspondingly ensuring the pattern accuracy of the first groove 101. In addition, the first groove 101 is isolated from the core layer 240 by the mask sidewall 200, the first groove 101 is isolated from the subsequent third groove by the mask sidewall 200, and the first groove 101 is also isolated from the subsequent second groove by the mask sidewall 200, which is conducive to achieving the designed minimum interval between adjacent grooves.

[0098] In this embodiment, along a direction parallel to the substrate 100 , the thickness of the mask spacer 200 located on the sidewall of the trench 270 is greater than or equal to 0.5 times the opening width of the gap 260 , thereby ensuring that the mask spacer 200 can fully fill the gap 260 .

[0099] In this embodiment, along the direction parallel to the substrate 100, the thickness of the mask sidewall 200 and the opening width of the gap 260 are the same. Accordingly, along the second direction, the intervals between the first groove 101 and the adjacent second groove 102, the first groove 101 and the adjacent third groove, and the second groove 102 and the adjacent third groove are the same, that is, the intervals between two adjacent grooves are the same. After patterning the target layer 110 under the first groove 101, the second groove 102 and the third groove to form a target pattern, along the second direction, the intervals between the target patterns are also the same, which is beneficial to improving the uniformity of the intervals of the target patterns.

[0100] In a specific implementation, the thickness of the mask sidewall 200 can also be different from the opening width of the gap 260, so that the opening widths of the mask sidewall 200 and the gap 260 can be adjusted according to actual needs, so that the intervals between two adjacent grooves are different, thereby improving the design flexibility and freedom of the intervals between target graphics.

[0101] The material of the mask spacer 200 includes one or more of titanium oxide, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide and amorphous silicon. As an example, the material of the mask spacer 200 is titanium oxide.

[0102] The second groove 102 is used to define the shape and position of the subsequent target pattern. The third groove is used to define the shape and position of the subsequent target pattern.

[0103] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0104] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate including a target layer for forming a target pattern; forming a core material layer on the substrate; Ion doping is performed on the core material layer, which is suitable for improving the etching resistance of the core material layer, the core material layer doped with ions is used as an anti-etching layer, and the core material layer not doped with ions is used as an initial core layer, the initial core layer extends along a first direction and is arranged at intervals along a second direction, and the first direction and the second direction are perpendicular to each other; forming a gap penetrating a portion of the initial core layer in contact with the side wall of the anti-etching layer, the remaining initial core layer serving as the core layer, and the side walls adjacent to the core layer along the second direction being opposite to each other being the first side wall and the second side wall; forming a groove penetrating a portion of the anti-etching layer between the first sidewall and the second sidewall, wherein the groove exposes the first sidewall and has a gap with the gap on the second sidewall; Forming a mask sidewall on the sidewall of the trench to fill the gap, wherein the mask sidewall located on the sidewall of the trench forms a first groove; forming a second groove penetrating the anti-etching layer between the first groove and the mask sidewall on the second sidewall; removing the core layer to form a third groove; The target layer below the first groove, the second groove and the third groove is patterned using the mask sidewall and the anti-etching layer as masks to form a target pattern.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the semiconductor structure further includes: after forming the core material layer and before performing ion doping, forming a separate sacrificial layer on the core material layer, the sacrificial layer extending along the first direction and arranged at intervals along the second direction; forming a sacrificial sidewall on the sidewall of the sacrificial layer; The step of ion doping the core material layer comprises: ion doping the core material layer exposed by the sacrificial layer and the sacrificial sidewall; The method for forming a semiconductor structure further comprises: after ion doping and before forming the gap and the groove, forming a filling layer covering the sidewalls of the sacrificial spacer on the anti-etching layer; removing the sacrificial spacer and forming a mask groove between the sidewalls of the sacrificial layer and the filling layer; The step of forming the gap includes: etching the initial core layer below the mask groove to form the gap between the core layer and the side wall of the anti-etching layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The groove is formed after the gap is formed; or the gap and the groove are formed in the same step.

4. The method for forming a semiconductor structure according to claim 3, wherein: After forming the gap, forming the groove; The step of forming the groove includes: forming a covering layer on the anti-etching layer and the core layer, the covering layer filling the gap, and a pattern opening formed in the covering layer above a portion of the anti-etching layer between the first sidewall and the second sidewall; Using the cover layer as a mask, etching the anti-etching layer below the pattern opening; The covering layer is removed.

5. The method for forming a semiconductor structure according to claim 2, wherein: forming the gap and the groove in the same step; In the step of forming the sacrificial layer, the opposite side walls of the sacrificial layers adjacent to each other along the second direction are respectively the third side wall and the fourth side wall; After forming the filling layer and before forming the gap and the trench, the method for forming the semiconductor structure further comprises: forming an opening in the filling layer, penetrating a portion of the filling layer between the third sidewall and the fourth sidewall, wherein the opening exposes a sacrificial sidewall on the third sidewall and has a gap with the sacrificial sidewall on the fourth sidewall, or the opening exposes the third sidewall and has a gap with the mask groove on the fourth sidewall; The step of forming the gap and the groove includes: using the filling layer and the sacrificial layer as masks, etching the initial core layer below the mask groove and the anti-etching layer below the opening to form the gap and the groove.

6. The method for forming a semiconductor structure according to claim 1, wherein: The ions used for ion doping the core material layer include one or more of boron ions, phosphorus ions and argon ions.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the core material layer includes one or more of amorphous silicon, polycrystalline silicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride and silicon carbonitride oxide.

8. The method for forming a semiconductor structure according to claim 2, wherein: The material of the sacrificial spacer includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium nitride and titanium oxide.

9. The method for forming a semiconductor structure according to claim 2, wherein: Using an etching process to etch the initial core layer below the mask groove to form the gap; The etching process is an anisotropic dry etching process.

10. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming a semiconductor structure further includes: forming an etch stop layer on the core material layer after forming the core material layer and before forming the sacrificial layer.

11. The method for forming a semiconductor structure according to claim 2, wherein: The material of the filling layer includes one or more of spin-on silicon oxide, metal oxide, polysilicon and amorphous silicon.

12. The method for forming a semiconductor structure according to claim 2, wherein: The step of forming the filling layer includes: forming a filling material layer covering the sacrificial sidewalls and the sacrificial layer on the anti-etching layer; and removing the filling material layer above the sacrificial sidewalls and the top surface of the sacrificial layer to form the filling layer.

13. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming a semiconductor structure further comprises: removing the filling layer and the sacrificial layer after forming the gap and before forming the mask sidewall.

14. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the mask sidewalls includes an atomic layer deposition process.

15. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the core layer includes a wet etching process.

16. The method for forming a semiconductor structure according to claim 1, wherein: The target layer is a dielectric layer; the target pattern is an interconnection groove.

17. A semiconductor structure, characterized in that: include: A substrate including a target layer for forming a target pattern; The core layers separated on the substrate extend along a first direction and are arranged along a second direction, the second direction is perpendicular to the first direction, and the opposite side walls of adjacent core layers along the second direction are respectively a first side wall and a second side wall; an anti-etching layer, located on the substrate at the side of the core layer, a gap is formed between the anti-etching layer and the sidewall of the core layer, the anti-etching layer and the core layer are made of the same material, and the anti-etching layer is doped with ions, and the ions are suitable for making the etching resistance of the anti-etching layer greater than the etching resistance of the core layer; a groove penetrating a portion of the anti-etching layer between the first sidewall and the second sidewall, wherein the groove exposes the first sidewall and has a gap with the gap on the second sidewall; A mask sidewall, located on the sidewall of the trench and filling the gap, wherein the mask sidewall located on the sidewall of the trench forms a first groove, and the mask sidewall and the anti-etching layer are used as a mask for patterning the target layer; The second groove penetrates the anti-etching layer between the first groove and the mask sidewall located on the second sidewall; wherein the core layer is used to occupy space for forming the third groove.

18. The semiconductor structure according to claim 17, wherein: The doping ions in the anti-etching layer include one or more of boron ions, phosphorus ions and argon ions.

19. The semiconductor structure according to claim 17, wherein: The materials of the anti-etching layer and the core layer include one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride and silicon carbonitride oxide.

20. The semiconductor structure according to claim 17, wherein: The target layer is a dielectric layer; The target pattern is an interconnection groove.

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