Semiconductor structure, three-dimensional memory and method of manufacturing the same

Abstract

The application provides a semiconductor structure, a three-dimensional memory and a manufacturing method thereof. The manufacturing method comprises: forming a first stack layer on a substrate, the first stack layer being divided into a chip region and a scribe lane region; forming a bottom select gate cut in the chip region, and forming a first part of a plurality of zero-layer-marked openings in the scribe lane region; and forming a second part of the openings in the substrate via the first part of the zero-layer-marked openings, wherein the first part and the second part of the openings are through. The application can form the bottom select gate cut and the plurality of zero-layer-marked openings through the same mask, in the same photolithography process and the same etching process, thereby simplifying the process steps.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a semiconductor structure, a three-dimensional memory, and a method for manufacturing the same. Background Technology

[0002] In the manufacturing process of 3D memory, zero-layer marks are usually formed in the dicing area that divides adjacent memory chips for process alignment. The zero-layer marks consist of formed openings and fillers that fill the openings. The optical parameters of the fillers are known, so the relative positions of some device structures of the 3D memory can be determined by the refraction and reflection of light.

[0003] It should be understood that the background section is intended to provide some useful background for understanding the technology; however, this content is not necessarily what was known or understood by a person skilled in the art prior to the filing date of this application. Summary of the Invention

[0004] One aspect of this application provides a method for manufacturing a three-dimensional memory, comprising: forming a first stacked layer on a substrate, the first stacked layer being divided into a chip region and a dicing region; forming a bottom selected gate cutout in the chip region and forming a first portion of an opening with a plurality of zero-layer markers in the dicing region; and forming a second portion of the opening in the substrate via the first portion of the opening with the zero-layer markers, wherein the first portion and the second portion of the opening are interconnected.

[0005] In one embodiment of this application, forming the bottom selection gate cutout and forming the first portion of the opening of the zero layer mark includes: forming a first mask layer on the first stacked layer and forming a first photoresist layer on the first mask layer; forming a pattern of the opening of the zero layer mark and the bottom selection gate cutout in the first photoresist layer; and transferring the pattern to the first mask layer and forming the first portion of the opening of the bottom selection gate cutout and the zero layer mark in the first stacked layer via the pattern.

[0006] In one embodiment of this application, forming a second portion of the opening in the substrate includes: forming a patterned second photoresist layer on the first mask layer and in the bottom selection gate cutout, the patterned second photoresist layer exposing a first portion of the opening; and removing a portion of the substrate via the pattern transferred to the first mask layer and the first portion of the opening to form the second portion.

[0007] In one embodiment of this application, the method further includes: removing the first mask layer.

[0008] In one embodiment of this application, forming a second portion of the opening in the substrate includes: forming a third photoresist layer on the first stacked layer and in the opening of the zero layer mark and in the bottom select gate cutout; forming a first pattern in the third photoresist layer, the first pattern corresponding to at least a portion of the first portion of the opening; and removing a portion of the substrate via the first pattern and the first portion of the opening to form the second portion, wherein the critical dimension of the first pattern is smaller than the critical dimension of the first portion of the opening.

[0009] In one embodiment of this application, forming a second portion of the opening in the substrate includes: forming a patterned fourth photoresist layer on the first stacked layer and in the bottom selected gate cutout, the patterned fourth photoresist layer exposing at least a first portion of the opening; and removing a portion of the substrate via the patterned fourth photoresist layer and the first portion of the opening to form the second portion.

[0010] In one embodiment of this application, forming a second portion of the opening in the substrate includes: forming a second mask layer on the first stacked layer and in the bottom selected gate cutout, and forming a fifth photoresist layer on the second mask layer; forming a second pattern in the fifth photoresist layer that at least partially corresponds to a first portion of the opening; and removing a portion of the second mask layer and the substrate via the second pattern and the first portion of the opening to form a second portion of the opening.

[0011] In one embodiment of this application, the method further includes filling the first portion and the second portion of the bottom selection grid cutout and the opening to form the bottom selection grid tangent and the zero layer mark, respectively.

[0012] In one embodiment of this application, filling the first and second portions of the bottom selection gate cutout and the opening includes: filling the first and second portions of the bottom selection gate cutout and the opening with an insulating material to form a fill layer; and performing a first planarization process on the fill layer.

[0013] In one embodiment of this application, the first stacked layer includes alternating dielectric layers and sacrificial layers, wherein filling the first portion and the second portion of the bottom select gate cutout and the opening further includes: removing at least one sacrificial layer from the top of the first stacked layer away from the substrate; and performing a second planarization process on the filling layer.

[0014] In one embodiment of this application, the method further includes: forming a second stacked layer on the first stacked layer; and forming a portion of the device structure of the three-dimensional memory in the chip region, using the zero-layer mark as a position reference.

[0015] In one embodiment of this application, forming a portion of the device structure of the three-dimensional memory includes: forming a stepped structure in the second stacked layer and the first stacked layer; and removing at least a portion of the zero-layer marker located in the first stacked layer.

[0016] In one embodiment of this application, forming the bottom selection grid cutout and forming the first portion of the opening of the zero layer mark includes: forming a groove for an auxiliary mark in the cutout area, the auxiliary mark being used as a position reference for forming the first portion and the second portion of the opening of the zero layer mark.

[0017] In one embodiment of this application, forming the second portion of the opening in the substrate includes removing a portion of the substrate via the groove to extend the groove into the substrate.

[0018] Another aspect of this application provides a three-dimensional memory manufactured by any of the methods described above.

[0019] Another aspect of this application provides a semiconductor structure, comprising: a chip structure located on a substrate, the chip structure including a first stacked structure and a second stacked structure having a stepped structure and sequentially disposed on the substrate; a dicing channel located between adjacent chip structures; a zero-layer marker located in the substrate corresponding to the dicing channel; and a bottom selected gate tangent line penetrating through the first stacked structure, wherein, in the penetrating direction, the cross-sectional shape of the zero-layer marker is different from that of the bottom selected gate tangent line.

[0020] In one embodiment of this application, the cross-sectional shape of the zero-layer marker includes an inverted trapezoid.

[0021] In one embodiment of this application, the cross-sectional shape of the bottom selection grid tangent includes a square.

[0022] In one embodiment of this application, the zero-layer marker and the bottom selection grid tangent are made of the same material.

[0023] In one embodiment of this application, the first stacked structure and the second stacked structure include alternately stacked gate layers and dielectric layers, wherein the number of gate layers stacked in the first stacked structure is ≥3.

[0024] In one embodiment of this application, at least one gate layer in the first stacked structure is a bottom selected gate layer.

[0025] In one embodiment of this application, the three-dimensional memory further includes: an auxiliary marker located in the cut path and extending into the substrate, the auxiliary marker serving as a position reference for the zero-layer marker.

[0026] In one embodiment of this application, the critical size range of the zero-layer marker is 1-20 μm.

[0027] In one embodiment of this application, the critical dimension range of the bottom selected gate tangent is 1-400 nm. Attached Figure Description

[0028] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings,

[0029] Figures 1-2 This is a partial schematic diagram of the semiconductor structure after forming the zero-layer marker and the bottom select gate tangent in a manufacturing method of a three-dimensional memory according to some embodiments of this application;

[0030] Figure 3 This is a schematic flowchart of a method 300 for manufacturing a three-dimensional memory according to an embodiment of this application.

[0031] Figures 4-22 This is a partial schematic diagram of a method for manufacturing a three-dimensional memory according to some embodiments of this application after performing certain steps;

[0032] Figure 23 This is a schematic diagram of a semiconductor structure according to some embodiments of this application;

[0033] Figure 24 This is a plan view top view of a semiconductor structure according to some embodiments of this application. Detailed Implementation

[0034] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements.

[0035] Note that references to "one embodiment," "implementation," "example embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly stated or not, implementing that feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0036] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0037] It should be readily understood that the meanings of “above,” “on top,” and “above” in this disclosure should be interpreted in the broadest sense, such that “above” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “on top” or “above” means not only “above” or “above” something but also includes “above” or “above” something without an intermediate feature or layer therebetween (i.e., directly on something).

[0038] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and another element(s)(s)(s) as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and accordingly, the spatial relative descriptors used herein may be interpreted similarly.

[0039] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire upper or lower structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers.

[0040] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the terms “approximately,” “about,” and similar terms used herein are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0041] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplarily" is intended to refer to an example or illustration.

[0042] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0043] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0044] like Figure 1As shown, in some 3D memory manufacturing processes, an opening (not shown) is typically formed in a substrate 10', then filled with an insulating material and planarized to form a layer zero marker 30'. In some embodiments, a stacked layer 20' for a bottom selective gate (BSG) structure may be formed on the substrate 10', and a bottom selective gate cutout (not shown) may be formed in the stacked layer 20'. The bottom selective gate cutout is then filled with an insulating material and planarized to form a bottom selective gate tangent 40'. The bottom selective gate tangent 40' can be used to partition the BSG for more precise selection of memory strings within each partition.

[0045] The inventors discovered through research that, in cases such as Figure 1 In the embodiment shown, the bottom selection gate tangent 40' and the zero-layer mark 30' are formed in steps, which usually requires two photomasks and at least two filling and at least two planarization processes. The zero-layer mark 30' is only used for alignment marks in subsequent processes and does not make a substantial contribution to the circuit structure. Forming the zero-layer mark 30' separately is not only complicated, but also increases the manufacturing cycle and cost of the device.

[0046] like Figure 2 As shown, in some other 3D memory manufacturing processes, after forming an opening (not shown) in the substrate 10', a stacked layer 20' for a bottom select gate (BSG) structure can be formed in the opening and on the substrate 10'. In some examples, the opening can be protected by a hard mask and a bottom select gate cutout (not shown) can be formed in the stacked layer 20'. Then, insulating material is filled into the opening and the bottom select gate cutout and planarized to form a zero layer mark 30' and a bottom select gate tangent 40', respectively.

[0047] The inventors discovered through research that, in cases such as Figure 2 In the embodiment shown, multiple stacked layers 20' need to be deposited in the opening of the zero-layer marker 30'. When forming some device structures using the zero-layer marker as a position reference, there may be a problem of poor optical signal intensity.

[0048] This application proposes a three-dimensional memory and a method for manufacturing the same to address at least one of the aforementioned problems. Figure 3 A flowchart of a three-dimensional memory manufacturing method 300 according to an embodiment of this application is shown. Figures 4-22 This is a partial schematic diagram showing the device structure after certain steps have been performed according to the manufacturing method 300 described above. In detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure will be partially enlarged, not to scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application.

[0049] The following will combine Figures 4-22 In describing the manufacturing method 300 above, it should be understood that the operations shown in the method are not exhaustive, and other operations may be performed before, after, or between any of the operations described.

[0050] Reference Figure 3 The manufacturing method 300 includes operation S310, wherein a first stacked layer can be formed on a substrate, the first stacked layer being divided into a chip region and a dicing region.

[0051] Figure 4 A partial cross-sectional view is shown of a method for manufacturing a three-dimensional memory according to some embodiments of this application, illustrating the formation of a first stacked layer 20 on a substrate 10. (See attached image.) Figure 4 As shown, the material of substrate 10 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof. In some examples, substrate 10 may include a base 100 and a stop layer 101 and a first sacrificial layer 102 sequentially formed on the base 100. Exemplarily, the base 111 may have a relatively thicker thickness compared to the stop layer 101 and the first sacrificial layer 102.

[0052] In some embodiments, the methods for forming the stop layer 101 and the first sacrificial layer 102 may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, thermal oxidation, or any combination thereof. Exemplarily, the material of the substrate 100 may include, for example, silicon, the material of the stop layer 101 may include, for example, silicon oxide, and the material of the first sacrificial layer 102 may include, for example, polycrystalline silicon.

[0053] In this step, a first stacked layer 20 may be formed on the substrate 10. The first stacked layer 20 may include a plurality of dielectric layers 201 and a plurality of sacrificial layers 200 alternately stacked in a direction perpendicular or substantially perpendicular to the substrate 10.

[0054] Refer again Figure 4 In some embodiments, prior to forming the first stacked layer 20, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to sequentially form a silicon oxide layer 103 and a polysilicon layer 104 on the substrate 10, for example, on the first sacrificial layer 102.

[0055] like Figure 4As shown, in some examples, a dielectric layer 201 may first be formed on the substrate 10. This dielectric layer 201 is an initial dielectric layer, which may include at least two layers, such as a first dielectric layer 201-1 and a second dielectric layer 201-2. Alternatively, the sacrificial layer 200 and the second dielectric layer 201-2 may be alternately stacked on the second dielectric layer 201-2 to complete the stacking of the first stacked layer 20.

[0056] Exemplarily, the method for forming the first stacked layer 20 may include a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Exemplarily, the first stacked layer 20 may include multiple pairs of dielectric layer 201 / sacrificial layer 200, the number of pairs being selected according to various application scenarios. For example, the number of dielectric layer 201 / sacrificial layer 200 pairs may be any suitable number, such as 3, 4, 5, 6, 7, or more.

[0057] In some examples, the number of dielectric / sacrificial layer pairs in the first stacked layer 20 can be greater than or equal to 3, thereby enabling the first stacked layer 20 to reach a certain thickness. In subsequent steps, the depth of the opening in the first stacked layer 20 is controlled by adjusting the key dimensions of the openings formed in the first stacked layer 20 (e.g., the first portion 301 of the zero-layer marker opening and the bottom select gate cutout 401 described below).

[0058] In some embodiments, under the same etching process, the sacrificial layer 200 has a higher etch selectivity than the dielectric layer 201, so that when the sacrificial layer 200 is removed, the dielectric layer 201 is hardly removed. Optionally, the insulating material for the dielectric layer 201 may include silicon oxide, and the material for the sacrificial layer 200 may include silicon nitride or silicon oxynitride.

[0059] Exemplarily, in a subsequent step, the sacrificial layer 200 of the first stacked layer 20 may be replaced with a conductive material, such as W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, silicide, or any combination thereof, to form the gate layer 202. Figure 24 At least one of the gate layers 202 can serve as the bottom select gate.

[0060] For example, as will be described below, substrate 10 can be used for forming structures such as channel structures 18 thereon. Figure 23 The grid line gap structure (not shown) provides mechanical support and is removed in subsequent processes.

[0061] In one example, a semiconductor layer (not shown) may be formed on the surface exposed after the substrate 10 is removed. The semiconductor layer may be connected to the channel via 17 described below. Figure 22 The channel layer (not shown) formed in the ) is contacted.

[0062] Substrate 10 may have opposing first and second surfaces. The top surface of substrate 10 may be either the first or second surface. "Top surface" can refer to a surface in contact with the first stacked layer (hereinafter referred to as "first stacked layer 20"). A first direction, either in or parallel to the top surface of substrate 10, represents the X direction. A second direction, either in or parallel to the top surface of substrate 10, represents the Y direction. Near the letter "Y," a symbol combining a circle and a cross indicates that the Y direction in the figure points inward relative to the drawing page. A third direction perpendicular to the top surface of substrate 10 represents the Z direction. The number of layers in the first stacked layer 20 may increase along the top surface of the substrate in the Z direction.

[0063] Figure 5 A partial top view schematic diagram of a three-dimensional memory manufacturing method according to some embodiments of this application, showing the division of a first stacked layer 20 into chip regions 12 and dicing regions 11. (See attached diagram.) Figure 5 As shown, multiple chip regions 12 and dicing regions 11 located between adjacent chip regions 12 can be defined on a wafer (not shown). The chip regions 12 are used to form device structures in the future, and the dicing regions 11 are used as cutting lines to divide the chip regions 12 during the packaging stage when the semiconductor structure is fabricated. Therefore, the dicing regions 11 are not used for device storage.

[0064] Continue to refer to Figure 3 The manufacturing method 300 includes operation S320, wherein a bottom selective gate slit can be formed in the chip region, and a first portion of an opening for a plurality of zero-layer markers is formed in the slit region.

[0065] In some implementations, the first portion of the openings for the bottom selection grid cutout and multiple zero-layer markers can be formed simultaneously using the same mask, which simplifies the process steps.

[0066] For example, the first portion forming the opening of the bottom selection gate cutout and the plurality of zero-layer markers may include: forming a first mask layer 210 on the first stacked layer 20. Figure 6 ), and a first photoresist layer 230 is formed on the first mask layer 210. Figure 6 ), optionally, such as Figure 6 As shown, a first anti-reflection layer 220 may also be formed on the first mask layer 210, and then a first photoresist layer 230 may be formed on the first anti-reflection layer. This application does not limit this.

[0067] like Figure 7As shown, in some examples, the first photoresist layer 230 can be patterned using the same mask (not shown) to simultaneously form a pattern 302 of the first portion of the openings of multiple zero-layer markers and a pattern 402 of the bottom selection gate cutout.

[0068] Optionally, the first mask layer 210 includes a hard mask, such as amorphous carbon (aC), spin-on carbon (SOC), ashable hard mask (AHM), transparent carbon (TC), and other types of carbon. The hard mask can serve as a protective layer, protecting the portion covered by the first mask layer 210 from damage.

[0069] Optionally, the first anti-reflective layer 220 comprises, for example, silicon oxynitride. In some examples of this application, the anti-reflective layer reduces light reflection and improves mask strength. Therefore, the hard mask used in conjunction with the anti-reflective layer allows the first portion 301 of the opening of the zero-layer mark formed by the etching process described below to be made possible. Figure 8 ) and bottom selection grid cutout 401 ( Figure 8 () has a better appearance.

[0070] Optionally, refer to Figure 7 When forming the pattern 302 of the first part of the opening for the zero-layer mark and the pattern 402 of the bottom selected gate cutout, multiple patterns 502 can be formed in the first photoresist layer 230 using the same mask and the same photolithography process. The patterns 502 can be used to form the grooves 501 of the auxiliary mark 50 in the subsequent formation. Figure 8 This allows for further improvements to the process flow. Alternatively, the groove 501 may be located in the cutting channel area 11 ( Figure 5 ).

[0071] For example, patterns 302, 402, and 502 formed in the first photoresist layer 230 can be transferred to the first mask layer 210, and formed in the first stacked layer 20 via the transferred patterns. Figure 8 The zero-layer mark shown includes the first part 301 of the opening, the bottom selection grid cutout 401, and the auxiliary mark 50. Figure 20 The groove 501 of the auxiliary mark 50 can be used as a position reference for the first part 301 of the opening that forms the zero layer mark.

[0072] As an example, the first portion of the opening of the zero layer mark extending into the first dielectric layer 201-1, the bottom selection gate cutout 401, and the groove 501 of the auxiliary mark 50 can be formed in the first stacked layer 20 by the same dry etching process or the same wet etching process.

[0073] It should be understood that the same dry etching process or the same wet etching process described above can be carried out in a certain temperature and chemical environment, which can almost remove the first photoresist layer 230 and most of the first antireflective layer 220.

[0074] Continue to refer to Figure 8 In some embodiments, the first portion 301 of the opening, the bottom selection gate cutout 401, and the groove 501 may have similar cross-sectional shapes in a direction perpendicular to or substantially perpendicular to the substrate 10, such similar cross-sectional shapes may include, for example, square shapes.

[0075] like Figure 8 As shown, in some examples, the critical dimension D1 of the first portion 301 of the opening is larger than the critical dimension of the bottom select gate cutout 401. It should be understood that the aforementioned critical dimension D1 and the critical dimension of the bottom select gate cutout 401 may, under certain circumstances, represent the dimensions of the first portion 301 of the opening and the bottom select gate cutout 401 in the direction parallel to the substrate 10.

[0076] In some embodiments, after forming the first portion 301 of the opening and the bottom selective grating cutout 401 and groove 501, the remaining portion of the first antireflective layer 220 and the first mask layer 210 may be removed.

[0077] Continue to refer to Figure 3 The manufacturing method 300 includes operation S330, wherein a second portion of an opening can be formed in a substrate via a first portion of an opening marked with a zero layer, wherein the first portion and the second portion of the opening are interconnected.

[0078] like Figure 9 As shown, in some embodiments, the first mask layer 210 can be removed ( Figure 7 After that, on the first stacked layer 20, the first portion 301 of the opening marked with the zero layer ( Figure 8 ) and bottom selection grid cutout 401 ( Figure 8 ) and groove 501 ( Figure 8 A third photoresist layer 240 is formed in the third photoresist layer 240, and then at least a portion of the first portion 301 of the opening is reopened in the third photoresist layer 240. In some examples, a first pattern 303 may be formed in the third photoresist layer 240, which corresponds to the first portion 301 of the opening. Figure 8 At least a portion of the first pattern 302. Optionally, the critical dimension D2 of the first pattern 302 may be smaller than the critical dimension D1 of the first portion 301 of the opening, thereby allowing a portion of the third photoresist layer 240 to be retained on the sidewall of the first portion 301 of the opening.

[0079] Continue to refer to Figure 9In some examples, the groove 501 can also be reopened via the third photoresist layer 240.

[0080] like Figure 10 As shown, in some examples, the second portion 307 of the zero-layer marker opening 306 can be formed in the substrate 10 using a suitable dry etching process or wet etching process. Optionally, the first portion 301 and the second portion 307 of the zero-layer marker opening 306 can be through-hole. As an example, it can be formed via the first pattern 303 ( Figure 9 The first portion 301 of the opening removes a portion of the substrate 10 to form the second portion 307 described above in the substrate 10. Alternatively, the second portion 307 of the opening 306 can be stopped in the stop layer 101 by controlling the etching time.

[0081] Continue to refer to Figure 10 In other examples, another portion of the substrate 10 may be removed via the reopened groove 501, such that the groove 501 extends into the substrate 10. Alternatively, the groove 501 may extend into the first sacrificial layer 102 by controlling the etching time.

[0082] Continue to refer to Figure 10 When the second portion 307 of the opening 306 is formed in the substrate 10 via the first portion 301 of the opening, the first portion 301 of the opening 306 and the groove 501 are processed by, for example, a dry etching process. The gas used in the dry etching process includes, for example, HBr. When the HBr gas comes into contact with the silicon-containing layer below the first portion 301 of the opening and the groove 501, for example, when it comes into contact with the polysilicon layer 104 or the stop layer 102, the HBr gas can combine with silicon atoms to form heavier atomic groups that adhere to the sidewalls of the first portion 301 of the opening and the groove 501. The adhered atomic groups have a narrowing effect, thereby making the cross-sectional profile of the second portion 307 of the opening 306 formed in the substrate 10 and the groove 501 extending into the substrate 10 form as shown in the figure. Figure 10 The shape shown is an inverted trapezoid.

[0083] by Figure 10 The structure shown is an example. In the first stacked layer 20, a portion of the third photoresist layer 240 is retained on the sidewall of the first portion 301 of the opening. Figure 9 In this way, during the process of forming the second portion 307 of the opening 306 in the substrate 10, the sidewall of the first portion 301 of the opening 306 can be protected, so that the contour and quality of the sidewall are maintained.

[0084] It is understandable that, for opening 306, when its cross-sectional profile includes an inverted trapezoid, the resulting zero-layer mark 30 ( Figure 20This serves as an alignment mark, enabling the acquisition of a better image of light reflection, thereby improving the intensity of the light signal. In some examples, the difference between the top and bottom surfaces of the inverted trapezoidal profile should be as large as possible to increase the optical signal.

[0085] like Figure 11 As shown, in some examples, the opening 306 may be located in the dicing region 11 surrounding the chip region 11. Alternatively, the shape of the opening 306 may be varied; for example, the top view shape of the opening 306 may include a square or a cross shape.

[0086] like Figure 12 As shown, in some embodiments, the first mask layer 210 can be removed ( Figure 7 After that, select gate cutout 401 on the first stack layer 20 and at the bottom. Figure 8 A patterned fourth photoresist layer 240' is formed in the first portion 301 of the opening. Alternatively, the patterned fourth photoresist layer 240' exposes at least the first portion 301 of the opening. In some examples, the pattern of the fourth photoresist layer 240' has a critical dimension D3 larger than the critical dimension D1 of the first portion 301, such that the sidewalls of the first portion 301 and the top portion of the first portion 301 are exposed in the pattern of the fourth photoresist layer 240'.

[0087] Continue to refer to Figure 12 In some examples, the groove 501 can also be reopened via a patterned fourth photoresist layer 240'.

[0088] like Figure 13 As shown, in some embodiments, this can be achieved via a patterned fourth photoresist layer 240' ( Figure 12 The first portion 301 of the opening removes a portion of the substrate 10 to form a second portion 307 of the zero-layer marking opening 306 in the substrate 10. Optionally, the second portion 307 of the opening 306 may stop in the stop layer 101.

[0089] Continue to refer to Figure 13 Due to Part 1 301 ( Figure 12 The sidewalls and part of the top of the first part 301 are exposed. During the process of forming the second part 301 of the opening, the first part 301 can be etched simultaneously to form an inverted trapezoidal cross-sectional shape. Optionally, the first part 301 and the second part 307 can be formed into inverted trapezoidal cross-sectional shapes with different inclination angles.

[0090] Alternatively, a further portion of the substrate 10 may be removed via the reopened groove 501, extending the groove 501 into the substrate 10. Optionally, the groove 501 may extend into the first sacrificial layer 102.

[0091] like Figure 14 and Figure 15 As shown, in some examples, the first mask layer 210 can be removed ( Figure 8 After that, on the first stacked layer 20, the first portion 301 of the opening of the aforementioned zero layer mark ( Figure 8 Select grid cutout 401 in the middle and bottom. Figure 8 ) and groove 501 ( Figure 8 A second mask layer 250 is sequentially formed in the first mask layer 210, and a fifth photoresist layer 270 is formed on the second mask layer 250. Optionally, a second anti-reflective layer 260 may be formed on the second mask layer 250, and then the fifth photoresist layer 270 may be formed on the second anti-reflective layer 260. Alternatively, the material of the second mask layer 250 may be the same as that of the first mask layer 210, which will not be described in detail here.

[0092] like Figure 15 As shown, in some examples, a first portion 301 (corresponding at least partially to the opening of the aforementioned zero-layer mark) may be formed in the fifth photoresist layer 270. Figure 8 The second pattern 305. Alternatively, the critical dimension D4 of the second pattern 305 is not less than the critical dimension D1 of the first part 301. Figure 8 ).

[0093] like Figure 16 As shown, in some examples, the critical dimension D4 of the second pattern 305 may be larger than the critical dimension D1 of the first portion 301, in connection with the aforementioned second pattern 305 ( Figure 15 When a portion of the substrate 10 is removed from the first portion 301 of the opening, the second pattern 305 described above can be transferred to the second mask layer 250 by, for example, etching on a machine, and the second pattern 305 exposes a portion of the top of the first portion 301 of the opening.

[0094] Optionally, on the same machine, the first portion 301 of the opening can be etched along the Z direction via the transferred second pattern 305, thereby forming the opening 306 in the substrate. Figure 13 Part 2 of 307 Figure 13 During this etching process, since a portion of the top of the first portion 301 and its sidewalls are exposed to the etching environment, the first portion 301 with the opening can form an inverted trapezoidal cross-sectional shape with different tilt angles in the first stacked layer 20 and the substrate 10. This cross-sectional shape can be referenced. Figure 13 The cross-sectional shape of the first part 301 of the opening is shown.

[0095] Back Figure 15 In some examples, when forming the second pattern 305, the same mask and the same photolithography process can be used to form the groove 501 in the fifth photoresist layer 270. Figure 8 Pattern 505.

[0096] Optionally, when transferring the second pattern 305 to the second mask layer 250, the same etching process can be used to transfer the pattern 505 to the second mask layer 250. Optionally, the groove 501 can be etched through the pattern 505 to extend the groove 501 into the substrate 10.

[0097] like Figure 17 and Figure 18 As shown, in some embodiments, after forming the first portion 301 of the opening and the bottom selection gate notch 401 and the groove 501 in the first stacked layer 20, the first photoresist layer 230 is removed. Figure 7 ) and the first anti-reflective layer 220 ( Figure 7 The patterned first mask layer 210 is retained. It should be understood that the patterned first mask layer 210 may carry the pattern of the first portion 301 of the opening and the bottom selection gate cutout 401 and the groove 501.

[0098] For example, such as Figure 18 As shown, gate cutouts 401 can be selected on and at the bottom of the patterned first mask layer 210. Figure 8 A patterned second photoresist layer 280 is formed in the substrate 10, which can expose the first portion 301 of the opening. In some examples, a portion of the substrate 10 can be removed via the patterned first mask layer 210 and the first portion 301 of the opening to form the second portion 307 of the opening. Figure 10 ).

[0099] Alternatively, the groove 501 can be reopened via the fourth photoresist layer 280, and the groove 501 can be etched again via the patterned first mask layer 210, so that the groove 501 extends into the substrate 10.

[0100] It is understandable that, compared with the use of a third photoresist layer 240 ( Figure 9 Formation such as Figure 10 Compared to the opening 306 shown, Figure 16 and Figure 18 In the example where a second mask layer 250 and a first mask layer 210, for example, are respectively employed as hard masks, since the hard mask can be used for the second stacked layer 20 ( Figure 16 and Figure 18 This protects the second stacked layer 20, thereby reducing the damage caused by the etching process to the second stacked layer 20.

[0101] It is also understandable that, with Figure 16 Compared to the example shown using a second mask layer 250, Figure 18In the example shown that uses the first mask layer 210, the cost can be reduced to some extent because the first mask layer 210 can be reused.

[0102] Continue to refer to Figure 3 Manufacturing method 300 includes operation S340, wherein a first portion and a second portion of the bottom selection gate cutout and opening are filled to form a bottom selection gate tangent and a zero layer mark, respectively.

[0103] like Figure 19 As shown, in some embodiments, the first portion 301 of a plurality of openings may be […]. Figure 10 ) and bottom selection grid cutout 401 ( Figure 10 The same insulating material is filled into the cavity, and then the insulating material is planarized at least once to form a shape as shown. Figure 20 The multiple zero-layer markers 30 and the bottom selection grid tangent 40 are shown.

[0104] For example, the process for filling the insulating material described above may include thin film deposition processes such as CVD, PVD, ALD, and any combination thereof. In some examples, it can also be achieved through HDP-CVD (High-density plasma chemical vapor deposition). HDP process has excellent pore-filling properties, reduces void formation, and can fill gaps with large aspect ratios at relatively low temperatures, resulting in a denser deposited film, at a lower cost than ALD deposition process.

[0105] Continue to refer to Figure 19 In some examples, it is also possible to use groove 501 ( Figure 10 The same insulating material is filled into the core to form an auxiliary mark (also known as a tuning fork) 50. This auxiliary mark 50 can serve as a positional reference for adjusting the critical dimensions of the zero-layer mark 30.

[0106] like Figure 19 As shown, in some examples, the process of forming the aforementioned zero-layer mark 30, bottom selection gate tangent 40, and auxiliary mark 50 may include: in the first portion 301 of the opening ( Figure 10 Bottom selection grid cutout 401 ( Figure 10 ) and groove 501 ( Figure 10 The inner wall of the film is deposited with a first filling layer 291 using an ALD process, and then a second filling layer 292 is deposited in the space defined by the first filling layer 291 using HDP-CVD. Compared with a one-step deposition process, this stepwise deposition process results in a film with fewer pores and relatively higher film density.

[0107] In one embodiment of this application, CMP can be used to perform a first planarization process on the above-mentioned filler material, so that the top surfaces of the zero layer mark 30, the bottom selection gate tangent 40, and the auxiliary mark 50 are coplanar with the top surface of the first stacked layer 20.

[0108] In some examples, the first part 301 of the opening forming the zero-layer mark ( Figure 8 ) and bottom selection grid cutout 401 ( Figure 8 During the process, it is possible that the first stacking layer 20 ( Figure 8 ) away from the substrate 10 ( Figure 8 At least one sacrificial layer 200 on top of ) Figure 8 Damage is caused by this, and the sacrificial layer 200 will be replaced by the gate layer 202 in a subsequent step. Figure 22 Therefore, after the first planarization process, at least one sacrificial layer 200 on the top of the first stacked layer 20 away from the substrate 10 can be removed, and then the aforementioned filler material can be subjected to a second planarization process to reduce potential damage to the gate layer 202.

[0109] Continue to refer to Figure 3 Manufacturing method 300 includes operation S350, wherein a second stacked layer can be formed on the first stacked layer.

[0110] like Figure 21 As shown, a zero-layer mark 30 can be formed. Figure 20 ) and bottom selection grid tangent 40 ( Figure 20 ) and auxiliary marker 50 ( Figure 20 After that, a second stacked layer 60 is formed on the first stacked layer 20. As an example, the second stacked layer 60 may be formed by stacking dielectric layer 201 / sacrificial layer 200 pairs of the first stacked layer 20, and the number of insulating layer / sacrificial layer pairs may be 32, 64, 96, 128, 160, 192, 224, 256 or more.

[0111] Exemplarily, in a subsequent suitable step, the sacrificial layer 200 in the second stacked layer 60 may be replaced with a conductive material, such as W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, silicide, or any combination thereof, to form the gate layer 202. Figure 24 The gate layer 202 can serve as a control gate. Alternatively, the sacrificial layer 200 of the first stacked layer 20 and the sacrificial layer 200 of the second stacked layer 60 can be replaced with the same conductive material in a subsequent process.

[0112] Continue to refer to Figure 3 Method 300 includes operation S360, wherein a portion of the device structure of a three-dimensional memory can be formed in a chip region by using a zero-layer marker as a location reference.

[0113] In some examples, such as Figure 22 As shown, the first stacked layer 20 and the second stacked layer 60 may include a step region 13 and a core region 14. Alternatively, a step structure 121 may be formed in the step region 13 of the first stacked layer 20 and the second stacked layer 60 using a zero-layer marker 30 as a location reference.

[0114] In one embodiment, a patterned photoresist can be used as a mask to perform a repeated etch-trimming process on the dielectric layer 201 and the sacrificial layer 200 from the side of the second stacked layer 60 away from the substrate 10, thereby forming a shape such as Figure 22 The step structure 121 is shown. In some examples, each step (not shown) of the step structure 121 includes the thickness of at least one pair of sacrificial layer 200 / dielectric layer 201.

[0115] In one embodiment, the first stacked layer 20 and the second stacked layer 60 may further include a test region 16 and a dicing region 11, the test region 16 being used to test the subsequent memory package structure. When the etching-trimming process reaches the test region 16, a stepped step 122 connected to the stepped structure 121 may be formed in a portion of the test region 16 adjacent to the chip region 12. Exemplarily, the stepped step 122 may be formed between the zero-layer marker 30 and the stepped structure 121. Alternatively, the first stacked layer 20 and the second stacked layer 60 of the dicing region 11 may be completely removed. Optionally, the portion of the zero-layer marker 30 protruding from the substrate 10 may be almost completely removed.

[0116] For example, the step structure of the formed step 122 is simpler than that of the formed step structure 121.

[0117] In one embodiment, a buffer layer (not shown) covering the top and side surfaces of each step of the stepped structure 121 and the stepped step 122 can be formed on each step by one or more deposition processes such as CVD, PVD, ALD or any combination thereof.

[0118] In one example, a dielectric layer 15 may be deposited over the step structure 121, filling the area above each step of the step structure 121 and the stepped steps 122, as well as the cut channel region 11. Alternatively, the dielectric layer 15 may fill the top of the second stacked layer 60. As an example, the dielectric layer 15 may be further planarized using processes such as chemical mechanical polishing (CMP) to provide a substantially flat upper surface for the step region 13.

[0119] In one implementation, such as Figure 22As shown, using the zero-layer marker 30 as a position reference, a channel hole 17 penetrating the first stacked layer 20 and the second stacked layer 60 can be formed in the core region 14. Then, a functional layer (not shown) and a channel layer (not shown) are sequentially formed on the inner wall of the channel hole 17. Alternatively, the space defined by the channel layer can be filled with an insulating material.

[0120] In one example, a gate gap (not shown) can be formed through the first stacked layer 20 and the second stacked layer 60 using the zero-layer marker 30 as a location reference. The sacrificial layer 200 of the first stacked layer 20 and the second stacked layer 60 can be removed through the gate gap and filled with conductive material to form a gate layer 202.

[0121] Another aspect of this application provides a three-dimensional memory, which can be manufactured using any of the methods described in the above embodiments. Alternatively, the three-dimensional memory may be, for example, a 3D NAND memory.

[0122] Another aspect of the embodiments of this application provides a semiconductor structure 400. Figure 23 A partial cross-sectional view of the semiconductor structure 400 is shown. (See figure) Figure 23 As shown, the semiconductor structure 400 includes: a semiconductor layer 110, a chip structure 120 located on the semiconductor layer 110, and dicing channels 11' dividing adjacent chip structures 120. It can be understood that the above-mentioned three-dimensional memory can be the diced chip structure 120.

[0123] In some examples, the chip structure 120 includes a first stacked structure 50 and a second stacked structure 80 located on the first stacked structure 50. Optionally, as... Figure 23 As shown, the first stacking structure 50 and the second stacking structure 80 include a step structure 123, which may be located on both sides of the first stacking structure 50 and the second stacking structure 80. Optionally, the step structure 123 may also be located in the middle of the first stacking structure 50 and the second stacking structure 80.

[0124] Continue to refer to Figure 23 In some examples, the first stacked structure 50 includes alternately stacked dielectric layers 201 and gate layers 202, with adjacent dielectric layers 201 and gate layers 202 forming a dielectric layer / gate layer pair. It is understood that the number of dielectric layer / gate layer pairs can be any suitable number selected. Alternatively, the number of dielectric layer / gate layer pairs is ≥3.

[0125] In some examples, the first stacked structure 50 includes at least one gate layer 202 which can serve as a bottom selected gate.

[0126] In some examples, the second stacked structure 80 includes alternately stacked dielectric layer 201 and gate layer 202, the gate layer 202 serving as a control gate layer.

[0127] In some examples, the chip structure 120 includes multiple memory planes (not shown), the number of which may include, for example, 2, 4, 6 or more, wherein each memory plane includes multiple memory blocks 70. Figure 24 ).

[0128] like Figure 24 As shown, in one example, each storage block 70 may include a step area 13 and a core area 14. Optionally, the step area 13 may be located on either side of the core area 14. In other options, the step area 13 may be located near the center of the core area 14.

[0129] In some examples, the step region 13 may include a step structure 123. In some examples, the core region 14 may include a channel structure 18. Figure 24 The channel structure 18 can extend through the first stacked structure 50 and the second stacked structure 80 into the semiconductor layer 110. Alternatively, the channel structure 18 may include a functional layer (not shown) and a channel layer (not shown) disposed sequentially from the outside to the inside. Alternatively, the channel layer may be in contact with the semiconductor layer 110.

[0130] In some examples, the semiconductor structure 400 also includes a test region 16, which may be located between the chip structure 120 and the dicing channel 11'. Alternatively, the test region 16 may be adjacent to the step structure 123.

[0131] like Figure 23 As shown, in some examples, the semiconductor structure 400 also includes a dielectric layer 15 that may fill the space above the stepped structure 123 until it is flush with the top of the chip structure 120.

[0132] In some examples, at least one side of the test area 16 may include a stepped step 124, which, alternatively, may be adjacent to the step structure 123. Exemplarily, the dielectric layer 15 may fill the space above the cut channel 11' and the stepped step 124.

[0133] In some examples, the semiconductor structure 400 also includes a zero-layer marker 30', which may be disposed in the semiconductor layer 110 corresponding to the dicing track 11'. Alternatively, the zero-layer marker 30' has a critical dimension ranging from 1 to 20 μm, and optionally, the critical dimension of the zero-layer marker 30 has a critical dimension ranging from 5 to 10 μm.

[0134] like Figure 24As shown, in some embodiments, the semiconductor structure 400 may further include components located in the first stacked structure 50. Figure 23 The bottom selected gate tangent 40 in the structure can, alternatively, extend through the first stacked structure 50 in a direction perpendicular to or substantially perpendicular to the semiconductor layer 110. Alternatively, the bottom selected gate tangent 40 can terminate at the bottom of a dielectric layer 201 adjacent to the semiconductor layer 110.

[0135] In some examples, the critical dimension of the zero-layer marker 30 is larger than the critical dimension of the bottom selection gate tangent 40.

[0136] In other examples, the critical dimension range of the bottom selected gate tangent 40 is 1-400 nm, and optionally, the critical dimension range of the bottom selected gate tangent 40 is 200-300 nm.

[0137] Optionally, the zero-layer marker 30' and the bottom selected gate tangent 40 can be made of the same material. Optionally, the cross-sectional shapes of the zero-layer marker 30' and the bottom selected gate tangent 40 can be different in a direction perpendicular to or substantially perpendicular to the semiconductor layer 110. As an option, the cross-sectional shape of the zero-layer marker 30' is an inverted trapezoid, and the cross-sectional shape of the bottom selected gate tangent 40 is a square.

[0138] Continue to refer to Figure 24 The semiconductor structure 400 also includes a first gate gap structure 701 arranged continuously and a second gate gap structure 702 arranged in segments. Alternatively, adjacent first gate gap structures 701 may define a memory block 70.

[0139] In some examples, the second gate gap structure 702 can be segmented between adjacent first gate gap structures 701. Alternatively, the second gate gap structure 702 can divide the memory block 70 into multiple sub-memory regions (not shown), with the gate layer 202 of adjacent sub-memory regions (…). Figure 23 The electrical connection is achieved through the segmented second grid gap structure 702.

[0140] In some examples, the number of second grid line gap structures 702 may be different in the step region 13 and the core region 14, so the second grid line gap structure 702 can change lanes at the junction of the step region 13 and the core region 14.

[0141] Continue to refer to Figure 24 In the first stacked structure 50, the bottom selected gate tangent 40 may be disposed between the segmented second gate gap structures 702. Alternatively, the bottom selected gate tangent 40 may physically connect each segment of the second gate gap structure 702.

[0142] Refer again Figure 24In some examples, the bottom selection gate tangent 40 includes a bottom selection gate tangent 40-1 located in the core region 14, a bottom selection gate tangent 40-2 located in the step region 13, and a bottom selection gate tangent 40-3 or a bottom selection gate tangent 40-4 including a second gate gap structure 702 connecting the core region 14 and the step region 13.

[0143] In some examples, since the second grid line gap structure 702 can change course at the junction of the step region 13 and the core region 14, the bottom selected grid tangent 40-3 or the bottom selected grid tangent 40-4 can be bent at the aforementioned junction.

[0144] Since the content and structure described in the manufacturing method 300 above are fully or partially applicable to the semiconductor structure 400 described herein, related or similar content will not be repeated.

[0145] Although a three-dimensional memory and its exemplary manufacturing method, as well as the semiconductor structure in some stages of forming the three-dimensional memory, have been described herein, it is understood that one or more features may be omitted, substituted, or added from the three-dimensional memory and semiconductor structure. Furthermore, the layers and materials described are merely exemplary.

[0146] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method of manufacturing a three-dimensional memory, comprising: forming a first stack on a substrate, the first stack being divided into a chip region and a street region; forming a first portion of a plurality of zero-layer-marking openings in the street region during a process of forming a bottom select gate cut in the chip region; and forming a second portion of the openings in the substrate via the first portion of the zero-layer-marking openings, wherein the first and second portions of the openings are through openings. The forming the first portion of the zero-layer-marking openings during the process of forming the bottom select gate cut comprises:

2. The method of claim 1, wherein, forming a first mask layer on the first stack and a first photoresist layer on the first mask layer; forming a pattern of the zero-layer-marking openings and the bottom select gate cut in the first photoresist layer; and transferring the pattern into the first mask layer and forming the bottom select gate cut and the first portion of the zero-layer-marking openings in the first stack via the pattern. The forming the second portion of the openings in the substrate comprises:

3. The method of claim 2, wherein, forming a patterned second photoresist layer on the first mask layer and in the bottom select gate cut, the patterned second photoresist layer exposing the first portion of the openings; and removing a portion of the substrate via the pattern transferred into the first mask layer and the first portion of the openings to form the second portion.

4. The method of claim 2, further comprising: removing the first mask layer. The forming the second portion of the openings in the substrate comprises:

5. The method of claim 4, wherein, forming a third photoresist layer on the first stack and in the zero-layer-marking openings and the bottom select gate cut; forming a first pattern in the third photoresist layer, the first pattern corresponding to at least a portion of the first portion of the openings; and removing a portion of the substrate via the first pattern and the first portion of the openings to form the second portion, wherein a critical dimension of the first pattern is smaller than a critical dimension the first portion of the openings has. The forming the second portion of the openings in the substrate comprises:

6. The method of claim 4, wherein, forming a patterned fourth photoresist layer on the first stack and in the bottom select gate cut, the patterned fourth photoresist layer exposing at least the first portion of the openings; and removing a portion of the substrate via the patterned fourth photoresist layer and the first portion of the openings to form the second portion. The forming the second portion of the openings in the substrate comprises:

7. The method of claim 4, wherein, forming a second mask layer on the first stack and in the bottom select gate cut and a fifth photoresist layer on the second mask layer; forming a second pattern in the fifth photoresist layer, the second pattern corresponding at least partially to the first portion of the openings; and removing the second mask layer and a portion of the substrate via the second pattern and the first portion of the openings to form the second portion of the openings. The method further comprises:

8. The method of any one of claims 1-7, wherein, filling the bottom select gate cut and the first and second portions of the openings to form the bottom select gate cutline and the zero-layer-marking, respectively. ​ 9. The method of claim 8, wherein, Filling the first and second portions of the bottom select gate cut and the opening includes: forming a fill layer by filling the first and second portions of the bottom select gate cut and the opening with an insulating material; and performing a first planarization process on the fill layer.

10. The method of claim 9, wherein, The first stack layer includes alternatingly stacked dielectric layers and sacrificial layers, wherein filling the first and second portions of the bottom select gate cut and the opening further includes: removing at least one sacrificial layer of the first stack layer distal to a top of the substrate; and performing a second planarization process on the fill layer.

11. The method of claim 8, wherein, Further comprising: forming a second stack layer on the first stack layer; and forming a partial device structure of the three-dimensional memory in the chip region with the zero layer mark as a location reference. Forming the partial device structure of the three-dimensional memory includes:

12. The method of claim 11, wherein, forming a step structure in the second stack layer and the first stack layer; and removing at least a portion of the zero layer mark located in the first stack layer. The method further comprises forming a recess of an auxiliary mark in the scribe lane region, the auxiliary mark used as a location reference for forming the first and second portions of the opening of the zero layer mark.

13. The method of claim 1, wherein, The method further comprises removing a portion of the substrate via the recess to extend the recess into the substrate.

14. The method of claim 13, wherein, The three-dimensional memory is manufactured by the method of any one of claims 1-14.

15. A three-dimensional memory characterized by, 16. A semiconductor structure, comprising: a chip structure on a substrate, the chip structure including a first stack structure and a second stack structure sequentially disposed on the substrate with a step structure; a scribe lane between adjacent chip structures; a zero layer mark in the substrate corresponding to the scribe lane; and a bottom select gate cut through the first stack structure, wherein, in a direction of the through, the zero layer mark has a cross-sectional shape different from that of the bottom select gate cut. The cross-sectional shape of the zero layer mark includes an inverted trapezoid. The cross-sectional shape of the bottom select gate cut includes a square.

17. The semiconductor structure of claim 16, wherein, The zero layer mark and the bottom select gate cut have the same material.

18. The semiconductor structure of claim 16, wherein, The first and second stack structures include alternatingly stacked gate layers and dielectric layers, wherein the number of stacked gate layers in the first stack structure is ≥ 3.

19. The semiconductor structure of claim 16, wherein, At least one gate layer in the first stack structure is a bottom select gate layer.

20. The semiconductor structure of claim 16, wherein, The semiconductor structure further comprises:

21. The semiconductor structure of claim 20, wherein, an auxiliary mark in the scribe lane and extending into the substrate, the auxiliary mark used as a location reference for the zero layer mark.

22. The semiconductor structure of claim 16, wherein, The critical dimension of the zero layer mark ranges from 1-20 um. The critical dimension of the bottom select gate cut ranges from 1-400 nm.

23. The semiconductor structure of claim 16, wherein, ​ 24. The semiconductor structure of claim 16, wherein, ​

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