Two-dimensional material heterojunction floating gate memory and method of making the same

Abstract

The application provides a two-dimensional material heterojunction floating gate memory, which comprises a gate layer, an insulating layer covering the gate layer, a plurality of floating gate layers formed on the insulating layer, a spacing between two adjacent floating gate layers in the plurality of floating gate layers, a barrier layer formed on the plurality of floating gate layers, a channel layer formed on the barrier layer, and an electrode layer comprising a plurality of sources and a plurality of drains, wherein a source or a drain is arranged on the channel layer corresponding to each spacing, and one source is arranged between two adjacent drains; each floating gate layer comprises an allowed state allowing storage and release of electrons and a forbidden state forbidding storage and release of electrons; a storage bias is applied to the gate layer, electrons of the channel layer tunnel into the floating gate layer in the allowed state, the floating gate layer in the allowed state stores the electrons, and the floating gate layer in the forbidden state does not store the electrons; a release bias is applied to the gate layer, the electrons stored in the floating gate layer in the allowed state tunnel back to the channel layer, and the floating gate layer in the allowed state releases the electrons.

Description

Technical Field

[0001] The embodiments of the present invention relate to a floating gate memory, and more particularly to a two-dimensional material heterojunction floating gate memory and its preparation method. Background Technology

[0002] The integrated circuit industry plays a vital role in the development of modern information society. Storage technology, as one of the core essential technologies in this field, faces unprecedented challenges in the era of big data. Flash memory (NAND), as a representative of storage technology, is approaching its physical limits. Traditional flash memory suffers from slow write / erase speeds and high power consumption. Summary of the Invention

[0003] In view of this, in order to solve at least one of the above-mentioned or other technical problems in the prior art, the present invention proposes a novel floating gate memory and its fabrication method to achieve fast and low-power erasure and writing of the floating gate memory, as well as multi-level storage of the floating gate memory.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In one aspect, the present invention provides a two-dimensional heterojunction floating gate memory, comprising: a substrate, the substrate being a gate layer; an insulating layer covering the gate layer; multiple floating gate layers formed on the insulating layer, wherein there is a spacing region between adjacent floating gate layers; a barrier layer formed on the multiple floating gate layers; a channel layer formed on the barrier layer, the channel layer being a two-dimensional semiconductor material; and an electrode layer including multiple sources and multiple drains, wherein a source or drain is disposed on the channel layer corresponding to each spacing region, and a source is disposed between adjacent drains.

[0005] Each floating gate layer includes an enabled state that allows the storage and release of electrons, and an disabled state that prohibits the storage and release of electrons. When a storage bias is applied to the gate layer, electrons from the channel layer tunnel into the floating gate layer in the enabled state, thus enabling the floating gate layer in the enabled state to store electrons. When a release bias is applied to the gate layer, electrons stored in the floating gate layer in the enabled state tunnel back to the channel layer, thus enabling the floating gate layer in the enabled state to release electrons.

[0006] In some embodiments, when one of the multiple floating gate layers is grounded, the floating gate layer is in a disabled state.

[0007] In some embodiments, the widths of the various floating gate layers are not equal.

[0008] In some embodiments, the width of each of the plurality of floating gate layers decreases sequentially in a predetermined direction.

[0009] In some embodiments, the floating gate layer is a two-dimensional material; the barrier layer is a two-dimensional material.

[0010] In some embodiments, the floating gate layer includes one of the following: MoS2, multilayer graphene (MLG), and MoTe2; the thickness of the floating gate layer (102) is 1 to 10 nm.

[0011] In some embodiments, the insulating layer includes one of the following: SiO2, SiN x Al2O3, HfO2, AlN; the thickness of the insulating layer is 300nm~1μm.

[0012] In some embodiments, the barrier layer includes one of the following: hexagonal boron nitride (h-BN), HfO2, Al2O3; the thickness of the barrier layer is 5 to 20 nm.

[0013] In some embodiments, the channel layer has an on / off ratio greater than 10. 3 Two-dimensional semiconductor materials; the channel layer includes one of the following: WSe2, MoS2, MoTe2, WS2, black phosphorus (BP); the thickness of the channel layer is 1-20 nm.

[0014] In some embodiments, the gate voltage is positively correlated with the thickness of the barrier layer, wherein the gate voltage is such that the on / off ratio of the channel layer is greater than 10. 3 The minimum voltage applied to the gate layer.

[0015] The present invention also provides a method for fabricating the above-mentioned floating gate memory, comprising: providing a gate layer; covering the gate layer with an insulating layer; forming a monolithic floating gate layer on the insulating layer using CVD growth or mechanical dissociation; decomposing the monolithic floating gate layer into multiple floating gate layers using electron beam lithography and reactive ion etching; covering the multiple floating gate layers with a barrier layer using a mechanical stripping method; covering the barrier layer with a channel layer using a mechanical stripping method; and forming an electrode layer on the channel layer using electron beam lithography and electron beam evaporation deposition to obtain the floating gate memory.

[0016] The two-dimensional heterojunction floating gate memory provided by the above embodiments of the present invention uses a two-dimensional semiconductor material for the channel layer, which is sensitive to electrons, has a large on / off ratio, and can form multiple distinguishable conductance states, satisfying the characteristics of multi-level storage. By setting multiple floating gate layers with unequal widths, the total resistance of the channel layer can be selectively rewritten, enabling the floating gate memory to achieve multi-level storage. Attached Figure Description

[0017] Figure 1 This is a cross-sectional schematic diagram of a two-dimensional material heterojunction floating gate memory according to an embodiment of the present invention;

[0018] Figure 2 In order to manufacture according to embodiments of the present invention Figure 1The diagram shown illustrates the process of forming an insulating layer on the gate layer in a two-dimensional heterojunction floating gate memory.

[0019] Figure 3 According to embodiments of the present invention, in Figure 2 The diagram shows an insulating layer with multiple floating gate layers formed on it.

[0020] Figure 4 According to embodiments of the present invention, in Figure 3 A schematic diagram showing multiple floating grid layers with barrier layers formed on them;

[0021] Figure 5 According to embodiments of the present invention, in Figure 4 A schematic diagram showing a channel layer formed on the barrier layer;

[0022] Figure 6 According to embodiments of the present invention, in Figure 5 A schematic diagram showing an electrode layer formed on the channel layer is shown; and

[0023] Figure 7 A flowchart illustrating a method for fabricating a two-dimensional heterojunction floating gate memory according to an embodiment of the present invention.

[0024] [Explanation of Labels in the Attached Image]

[0025] 100 - Gate layer; 101 - Insulating layer; 102 - Floating gate layer; 103 - Barrier layer; 104 - Channel layer; 105 - Electrode layer Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0027] Novel two-dimensional materials, such as graphene, transition metal sulfides, and black phosphorus, have excellent electrical and optical properties, which can improve existing storage technologies and enable the next generation of low-cost, flexible, and wearable storage devices.

[0028] Based on the above-mentioned inventive concept, the present invention provides a two-dimensional material heterojunction floating gate memory and its preparation method.

[0029] On one hand, the present invention provides a two-dimensional material heterojunction floating gate memory.

[0030] Figure 1 This is a cross-sectional schematic diagram of a two-dimensional material heterojunction floating gate memory according to an embodiment of the present invention.

[0031] like Figure 1As shown, a two-dimensional heterojunction floating gate memory according to an exemplary embodiment of the present invention includes: a substrate, the substrate being a gate layer 100; an insulating layer 101 covering the gate layer 100; a plurality of floating gate layers 102 formed on the insulating layer 101, wherein there is a spacer region between adjacent floating gate layers 102; a barrier layer 103 formed on the plurality of floating gate layers 102; a channel layer 104, being a two-dimensional semiconductor material, formed on the barrier layer 103; and an electrode layer 105 including a plurality of sources and a plurality of drains, wherein a source or drain is disposed on the channel layer 104 corresponding to each spacer region, and a source is disposed between adjacent drains.

[0032] Furthermore, each floating gate layer 102 includes an enabled state that allows the storage and release of electrons, and an disabled state that prohibits the storage and release of electrons. When a storage bias is applied to the gate layer 100, electrons from the channel layer 104 tunnel into the floating gate layer 103 in the enabled state, enabling the floating gate layer 102 in the enabled state to store electrons, while the floating gate layer 102 in the disabled state does not store electrons. When a release bias is applied to the gate layer 100, electrons stored in the floating gate layer 102 in the enabled state tunnel back to the channel layer 104, enabling the floating gate layer 102 in the enabled state to release electrons, while the floating gate layer 102 in the disabled state does not store electrons. The release bias has the opposite polarity to the storage bias.

[0033] According to an embodiment of the present invention, in a two-dimensional material heterojunction floating gate memory, each of the plurality of floating gate layers 102 can be in an enabled state or an disabled state. An enabled state indicates that the floating gate layer 102 allows the storage and release of electrons, while a disabled state indicates that the floating gate layer 102 prohibits the storage and release of electrons. When one of the plurality of floating gate layers 102 is grounded, that floating gate layer 102 is in a disabled state.

[0034] It should be noted that when the floating gate layer 102 in the controlled inhibit state is grounded, a positive bias voltage is applied to the gate layer 100, and electrons in the channel layer 104 tunnel into the floating gate layer 102 in the enabled state, thereby enabling the floating gate layer 102 in the enabled state to store electrons; when the floating gate layer 102 in the controlled inhibit state is grounded, a negative bias voltage is applied to the gate layer 100, and electrons stored in the floating gate layer 102 in the enabled state tunnel back to the channel layer 104, thereby enabling the floating gate layer 102 in the enabled state to release electrons.

[0035] According to an embodiment of the present invention, a switching ratio greater than 10 is used. 3A two-dimensional semiconductor material is used to form the channel layer 104. Because the two-dimensional semiconductor material has a large on / off ratio, discrete bit states can be obtained. Specifically, the two-dimensional semiconductor material is sensitive to an electric field perpendicular to its plane, and its large on / off ratio allows for the formation of multiple distinguishable conductance states, satisfying the characteristics of multi-level storage.

[0036] According to an embodiment of the present invention, the widths of the various floating gate layers 102 are not equal.

[0037] According to an embodiment of the present invention, the width of each of the plurality of floating gate layers 102 decreases sequentially in a predetermined direction.

[0038] It should be noted that the operation methods of the two-dimensional material heterojunction floating gate memory include write operations and erase operations. See also Figure 1 The write operation involves applying a positive bias voltage to the gate layer 100, causing a large number of electrons in the channel layer 104 to tunnel through the barrier layer 103 into the floating gate layer 102, achieving a high-speed write of state "1" at the microsecond level. After the bias voltage is removed, the electrons stored in the floating gate layer 102 cause a threshold drift in the floating gate memory device, resulting in a high current output and the storage of state "1". The erase operation involves applying a negative bias voltage to the gate layer 100, causing a large number of electrons to tunnel through the barrier layer 103 back to the channel layer 104, thus erasing state "1". By selecting a specific floating gate layer 102 and keeping it grounded, the selected floating gate layer 102 is in a disabled state. Then, a positive / negative bias voltage is applied to the gate 100. The selected floating gate layer 102 remains in a "0" state because it is grounded; while the unselected floating gate layers 102 are in an enabled state, and the electron storage state of the enabled floating gate layers 102 will change. Because the widths of the floating gate layers 102 are different, the resistances of the corresponding channel layers 104 on each floating gate layer 102 are different. The total resistance of the channel layers 104 formed by series connection is controlled by the floating gate layers 102. Each floating gate layer 102 has a different weight for controlling the total resistance of the channel layers 104, thereby realizing multi-bit control of the floating gate memory.

[0039] According to embodiments of the present invention, such as Figure 1 As shown, the width of each of the multiple floating gate layers 102 is not equal, and the storage capacity of each floating gate layer 102 is different. The floating gate memory includes multiple floating gate layers 102, for example, N layers, and each floating gate layer 102 can be in an enabled or disabled state, thus enabling 2n... NThere are multiple storage states. Since the channel layer 104 is sensitive to the amount of electrons stored in the floating gate layer 102, the amount of electrons stored in the floating gate layer 102 can be reflected by the change in the conductivity of the channel layer 104. By setting multiple floating gate layers 102 with different widths, the total resistance of the channel layer 104 can be selectively rewritten, thus realizing multi-level storage of the floating gate memory.

[0040] like Figure 1 As shown, in one embodiment of the present invention, the floating gate memory includes three floating gate layers, the widths of which decrease sequentially in a predetermined direction. This floating gate memory can achieve 2... 3 This enables 8 levels of storage, representing 8 storage states.

[0041] According to an embodiment of the present invention, the floating gate layer 102 is a two-dimensional material; the barrier layer 103 is a two-dimensional material; and the channel layer 104 is a two-dimensional semiconductor material.

[0042] According to an embodiment of the present invention, the floating gate layer, barrier layer and channel layer in the floating gate memory are all two-dimensional materials. This design can form a heterojunction. The interface of the heterojunction is flat and has few defects, which reduces the accumulation of electrons at the defect sites, reduces electron leakage, and facilitates fast writing and erasing of electrons in the floating gate memory.

[0043] According to an embodiment of the present invention, the floating gate layer 102 is used to store electrons. The floating gate layer 102 includes one of the following: MoS2, multilayer graphene (MLG), and MoTe2. For example, the floating gate layer 102 can be multilayer graphene (MLG), but is not limited thereto.

[0044] According to an embodiment of the present invention, the thickness of the floating gate layer 102 is 1 to 10 nm. For example, the thickness of the floating gate layer 102 can be 1 nm, 2 nm, 5 nm, 8 nm, or 10 nm, but is not limited thereto.

[0045] According to an embodiment of the present invention, the floating grid layer 102 can be a single-layer two-dimensional material or can be formed by multiple layers of two-dimensional materials.

[0046] According to embodiments of the present invention, the floating gate layer 102 is formed by CVD growth or mechanical dissociation, but is not limited thereto.

[0047] According to an embodiment of the present invention, the material of the gate layer 100 includes a conductive material; the gate layer 100 includes one of the following: a metal electrode, heavily doped silicon, gallium arsenide, gallium nitride, silicon carbide, gallium oxide, for example, the gate layer 100 is p-type doped silicon or n-type doped silicon, but is not limited thereto.

[0048] According to an embodiment of the present invention, the insulating layer 101 comprises one of the following: SiO2, SiN xAl2O3, HfO2, AlN, for example, the insulating layer 101 is SiO2, but not limited to these.

[0049] According to an embodiment of the present invention, the thickness of the insulating layer 101 is 300 nm to 1 μm. For example, the thickness of the insulating layer 101 can be 300 nm, 400 nm, 600 nm, 800 nm, or 1 μm, but is not limited thereto.

[0050] According to an embodiment of the present invention, the insulating layer 101 is an insulating medium used to prevent the gate layer 100 from contacting the floating gate layer 102. The insulating layer 101 can prevent electrons from the gate layer 100 from tunneling into the floating gate layer 102 and causing damage to the floating gate memory.

[0051] According to an embodiment of the present invention, the barrier layer 103 is a nanoscale two-dimensional material, and the barrier layer 103 includes one of the following: hexagonal lattice boron nitride (h-BN), HfO2, Al2O3. For example, the barrier layer 103 can be hexagonal lattice boron nitride (h-BN), but is not limited thereto.

[0052] According to an embodiment of the present invention, the thickness of the barrier layer 103 is 5 to 20 nm. For example, the thickness of the barrier layer 103 can be 5 nm, 7 nm, 10 nm, 15 nm, or 20 nm, but is not limited thereto.

[0053] According to an embodiment of the present invention, the turn-on voltage of the gate layer 100 is positively correlated with the thickness of the barrier layer 103. The turn-on voltage is defined as the on / off ratio of the channel layer 104 being greater than 10. 3 The minimum voltage applied to the gate 100. The thinner the barrier layer 103, the smaller the gate 100 turn-on voltage. The barrier layer material of the heterojunction floating gate memory provided in this embodiment of the invention can be a nanoscale two-dimensional material. The gate layer turn-on voltage is low, and tunneling can be achieved by applying a very small voltage, thus reducing power consumption.

[0054] According to an embodiment of the present invention, the channel layer 104 includes one of the following: WSe2, MoS2, MoTe2, WS2, black phosphorus (BP), for example, the channel layer 104 is WSe2, but is not limited thereto.

[0055] According to an embodiment of the present invention, the thickness of the channel layer 104 is 1 to 20 nm. For example, the thickness of the channel layer 104 can be 1 nm, 4 nm, 8 nm, 12 nm, 15 nm, or 20 nm, but is not limited thereto.

[0056] According to an embodiment of the present invention, the electrode layer 105 includes a plurality of source electrodes and a plurality of drain electrodes, wherein the source electrodes and drain electrodes are conductive two-dimensional materials or metals.

[0057] According to an embodiment of the present invention, the material of the electrode layer 105 includes one of the following: Ti / Au, Cr / Au, Pt, Al, and graphite.

[0058] Figure 2 In order to manufacture according to embodiments of the present invention Figure 1 The diagram shown illustrates the process of forming an insulating layer on the gate layer in a two-dimensional heterojunction floating gate memory. Figure 3 According to embodiments of the present invention, in Figure 2 The diagram shows an insulating layer with multiple floating gate layers formed on it. Figure 4 According to embodiments of the present invention, in Figure 3 A schematic diagram showing multiple floating grid layers with barrier layers formed on them; Figure 5 According to embodiments of the present invention, in Figure 4 A schematic diagram showing a channel layer formed on the barrier layer; Figure 6 According to embodiments of the present invention, in Figure 5 A schematic diagram showing an electrode layer formed on the channel layer; Figure 7 A flowchart illustrating a method for fabricating a two-dimensional heterojunction floating gate memory according to an embodiment of the present invention.

[0059] On the other hand, the present invention also provides a method for fabricating the above-mentioned two-dimensional material heterojunction floating gate memory, such as... Figure 2-6 As shown, the preparation method includes steps S101 to S106.

[0060] In step S101, a gate layer 100 is provided.

[0061] In step S102, as Figure 2 As shown, an insulating layer 101 is covered on the gate layer 100.

[0062] According to an embodiment of the present invention, an insulating layer 101 is formed on the gate layer 100 by thermal oxidation.

[0063] In step S103, as Figure 3 As shown, a plurality of floating gate layers 102 are formed on the insulating layer 101.

[0064] According to an embodiment of the present invention, a floating gate layer is covered onto the surface of the insulating layer 101 by CVD growth or mechanical dissociation to obtain a whole floating gate layer. Then, the whole floating gate layer is etched by electron beam lithography (EBL) and reactive ion etching (RIE) to obtain multiple floating gate layers 102.

[0065] In step S104, as Figure 4 As shown, a barrier layer 103 is formed on multiple floating gate layers 102.

[0066] According to an embodiment of the present invention, a mechanical peeling method is used to cover the barrier layer 103 onto a plurality of floating gate layers 102.

[0067] In step S105, as Figure 5 As shown, a channel layer 104 is formed on the barrier layer 103.

[0068] According to an embodiment of the present invention, the channel layer 104 is covered onto the barrier layer 103 by a mechanical peeling method.

[0069] In step S106, as Figure 6 As shown, an electrode layer 105 is formed on the channel layer 104 to obtain a floating gate memory.

[0070] According to an embodiment of the present invention, an electrode layer 105 is formed on the surface of the channel layer 104 using electron beam lithography (EBL) and electron beam evaporation deposition (EBE), thereby obtaining... Figure 1 or Figure 6 The two-dimensional material heterojunction floating gate memory structure is shown.

[0071] According to embodiments of the present invention, such as Figure 1 As shown, n-type doped silicon is used as the gate layer 100; a 300 nm thick SiO2 layer is formed on the n-type doped silicon using thermal oxidation as the insulating layer 101; a 7.6 nm thick multilayer graphene (MLG) layer is formed on the SiO2 layer using CVD growth as the floating gate layer; the multilayer graphene (MLG) layer is decomposed into multiple layers using electron beam lithography and reactive ion etching to form multiple floating gate layers 102; a 10 nm thick Al2O3 layer is formed on the multiple floating gate layers 102 as the barrier layer 103; a 15 nm thick black phosphorus (BP) layer is formed on the Al2O3 layer as the channel layer 104; and graphite is formed on the black phosphorus (BP) layer as the electrode layer 105, thus obtaining a BP / Al2O3 / Graphene heterojunction floating gate memory.

[0072] According to another embodiment of the present invention, the structure of the two-dimensional material heterojunction floating gate memory has the same technical features as the above embodiment, except that the channel layer 104 is made of MoTe2 and the barrier layer 103 is made of h-BN, thus obtaining the MoTe2 / h-BN / Graphene heterojunction floating gate memory.

[0073] According to another embodiment of the present invention, the structure of the two-dimensional material heterojunction floating gate memory has the same technical features as the above embodiment, except that: the material of the floating gate layer 102 is MoTe2, the material of the barrier layer 103 is h-BN, and the material of the channel layer 104 is WSe2, thus obtaining the WSe2 / h-BN / MoTe2 heterojunction floating gate memory.

[0074] According to another embodiment of the present invention, the structure of the two-dimensional material heterojunction floating gate memory has the same technical features as the above embodiment, except that: the material of the floating gate layer 102 is MoS2, the material of the barrier layer 103 is h-BN, and the material of the channel layer 104 is WSe2, thus obtaining the WSe2 / h-BN / MoS2 heterojunction floating gate memory.

[0075] The two-dimensional heterojunction floating gate memory provided by the embodiments of the present invention uses a two-dimensional semiconductor material for the channel layer, which is sensitive to electrons, has a large on / off ratio, and can form multiple distinguishable conductance states, satisfying the characteristics of multi-level storage. By setting multiple floating gate layers with unequal widths, the total resistance of the channel layer can be selectively rewritten, enabling the floating gate memory to achieve multi-level storage.

[0076] According to the embodiments of the present invention, the two-dimensional material heterojunction floating gate memory, the floating gate layer, the barrier layer and the channel layer are all two-dimensional materials to form a heterojunction. The interface of the heterojunction is flat and has few defects, which reduces the accumulation of electrons at the defect sites, reduces electron leakage, and facilitates fast writing and erasing of electrons.

[0077] According to the embodiments of the present invention, the barrier layer is made of nanoscale two-dimensional material, and the gate layer has a low turn-on voltage. When a very small voltage is applied, electrons can tunnel through, thereby reducing the power consumption of the floating gate memory.

[0078] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A two-dimensional material heterojunction floating gate memory, characterized in that, include: Substrate, wherein the substrate is a gate layer; An insulating layer covers the gate layer; Multiple floating gate layers are formed on the insulating layer, and there is a gap between two adjacent floating gate layers in the multiple floating gate layers; A barrier layer is formed on the plurality of floating gate layers; A channel layer is formed on the barrier layer, wherein the channel layer is a two-dimensional semiconductor material; An electrode layer includes multiple sources and multiple drains. A source or drain is disposed on a channel layer corresponding to each of the interval regions. A source is disposed between two adjacent drains. Each of the floating gate layers includes an enabled state that allows the storage and release of electrons, and an inhibited state that prohibits the storage and release of electrons. When a storage bias is applied to the gate layer, electrons in the channel layer tunnel into the floating gate layer in the allowed state, thereby enabling the floating gate layer in the allowed state to store electrons. When a release bias is applied to the gate layer, the electrons stored in the floating gate layer in the enabled state tunnel back to the channel layer, thereby enabling the floating gate layer in the enabled state to release electrons.

2. The floating gate memory according to claim 1, characterized in that, When one of the multiple floating gate layers is grounded, the floating gate layer is in a disabled state.

3. The floating gate memory according to claim 1, characterized in that, The widths of the various floating gate layers are not equal.

4. The floating gate memory according to claim 3, characterized in that, The width of each of the plurality of floating grid layers decreases sequentially in a preset direction.

5. The floating gate memory according to claim 1, characterized in that, The floating grid layer is a two-dimensional material; The barrier layer is a two-dimensional material.

6. The floating gate memory according to claim 1, characterized in that, The floating gate layer includes one of the following: MoS2, multilayer graphene (MLG), and MoTe2; The thickness of the floating gate layer is 1~10nm.

7. The floating gate memory according to claim 1, characterized in that, The insulating layer includes one of the following: SiO2, SiN x Al2O3, HfO2, AlN; The thickness of the insulating layer is 300 nm to 1 μm.

8. The floating gate memory according to claim 1, characterized in that, The barrier layer comprises one of the following: hexagonal boron nitride (h-BN), HfO2, or Al2O3; The thickness of the barrier layer is 5~20nm.

9. The floating gate memory according to claim 1, characterized in that, The channel layer has an on / off ratio greater than 10. 3 Two-dimensional semiconductor materials; The channel layer includes one of the following: WSe2, MoS2, MoTe2, WS2, black phosphorus (BP); The thickness of the channel layer is 1~20nm.

10. The floating gate memory according to claim 1, characterized in that, The turn-on voltage of the gate layer is positively correlated with the thickness of the barrier layer, wherein the turn-on voltage is such that the on / off ratio of the channel layer is greater than 10. 3 The minimum voltage applied to the gate layer at that time.

11. A method for fabricating a floating-gate memory as described in any one of claims 1 to 10, characterized in that, include: Provide a gate layer; An insulating layer is covered on the gate layer; A monolithic floating gate layer is formed on the insulating layer using CVD growth or mechanical dissociation methods, and the monolithic floating gate layer is decomposed into multiple floating gate layers using electron beam lithography and reactive ion etching. The barrier layer is applied to the multiple floating grid layers using a mechanical peeling method; The trench layer is covered onto the barrier layer using a mechanical peeling method; An electrode layer is formed on the channel layer using electron beam lithography and electron beam evaporation deposition to obtain a floating gate memory.

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