A floating gate split-gate flash memory process method

Abstract

The present invention discloses a floating gate split-gate flash memory process method, the process method steps of which are as follows: defining the active area of ​​the floating gate flash memory and the peripheral logic area; removing the silicon nitride layer, and sequentially forming a silicon oxide layer, a silicon nitride layer, a sacrificial silicon oxide layer, and a silicon nitride layer; depositing a polysilicon layer and performing anisotropic etching to form a first sidewall control gate; depositing and etching to form a second sidewall dielectric layer; etching away the floating gate polysilicon layer within the opening; performing thermal oxidation to form a protective etch on top of the select gate polysilicon layer; implanting to form a lightly doped drain Halo ion implantation layer; and performing source and drain heavy doping implantation to form a source and drain heavy doping ion implantation layer. The present invention improves the compatibility of the flash memory device with advanced processes; in subsequent processes, metal silicide can be formed on top of the polysilicon simultaneously with the select gate, thereby reducing the on-resistance of the control gate and improving the integration of the flash memory.

Description

Technical Field

[0001] The present invention relates to the technical field of flash memory, in particular to a floating gate split-gate flash memory process method. Background Art

[0002] Flash memory is a non-volatile memory device, meaning data is not lost even when power is turned off. Because flash memory does not rewrite data in byte units like RAM (random access memory), it cannot replace RAM. Flash cards utilize flash memory technology to store electronic information. They are commonly used as storage media in small digital products such as digital cameras, PDAs, and MP3 players. Because of their compact size, resembling a card, they are called flash cards. Depending on the manufacturer and application, flash memory cards include SmartMedia (SM card), Compact Flash (CF card), MultiMediaCard (MMC card), Secure Digital (SD card), Memory Stick (Memory Stick), XD-PictureCard (XD card), and Microdrive (MICRODRIVE). While these flash cards may differ in appearance and specifications, they all share the same technical principles. NOR and NAND flash memory differ significantly. For example, NOR flash memory is more like RAM, with separate address and data lines, but it's more expensive and has a smaller capacity. NAND, on the other hand, is more like a hard drive, with shared address and data lines, similar to how all information on a hard drive is transmitted over a single line. Furthermore, NAND flash memory is less expensive and has a much larger capacity than NOR flash memory. Therefore, NOR flash memory is more suitable for frequent random reads and writes, typically used to store program code and run it directly within the flash memory. Mobile phones are a major user of NOR flash memory, so their "memory" capacity is typically small. NAND flash memory is primarily used for data storage, and commonly used flash products like flash drives and digital memory cards all use NAND flash memory. It's important to note that flash memory has a limited speed. Its inherent operating speed and frequency are much lower than RAM, and NAND flash memory's hard drive-like operation is much slower than direct RAM access. Therefore, don't assume that the performance bottleneck of a flash drive lies in its interface, or even assume that adopting a USB 2.0 interface will significantly improve performance. As mentioned earlier, NAND flash memory operates inefficiently, a consequence of its architectural and interface design. While it does operate much like a hard drive (indeed, NAND flash memory was designed with hard drive compatibility in mind), its performance characteristics are also similar to hard drives: operations on small data blocks are slow, while operations on large data blocks are very fast. This difference is far greater than other storage media. This performance characteristic is highly noteworthy. Flash memory offers fast access times, is silent, and generates minimal heat. If user space requirements are small, consider purchasing a flash drive without further consideration; for the same storage space, opt for flash memory. If you require a larger capacity (e.g., 500GB), opt for a hard drive, which is more affordable and can meet your application needs.Flash memory has become the mainstream of non-volatile semiconductor storage technology. Flash memory is divided into two types: stacked-gate and split-gate. Split-gate flash technology, due to its tolerance to over-erase effects, is widely used in various embedded electronic products such as financial IC cards and automotive electronics. Increasing storage integration density helps save chip area and reduce manufacturing costs.

[0003] The manufacturing process of the existing 2-bit / cell (two bits per storage cell) split gate floating gate flash memory is as follows Figure 1 As shown, its structure is as Figure 2 shown.

[0004] As shown in the figure: 101—a medium-high voltage P-type well formed on a P-type substrate, 102—a floating gate dielectric layer, 103—a floating gate polysilicon, 104—an ONO (Oxide-Nitride-Oxide) dielectric stack between polysilicon layers, 105—a control gate polysilicon, 106—a second spacer dielectric layer, 107—a select gate dielectric layer, 108—a select gate polysilicon layer, 109—a third spacer dielectric layer, 110—a lightly doped drain (LDD) ion implantation, 111—a source-drain heavily doped ion implantation, 112—a first spacer dielectric layer, and 113—a metal silicide.

[0005] As CMOS technology continues to advance, the height of CMOS devices continues to decrease. To improve the compatibility of flash memory cells with advanced CMOS processes, the height of flash memory cells also needs to be appropriately reduced. However, the unique triple self-alignment process of 2-bit / cell split-gate floating-gate flash memory makes the height of the flash memory cells much higher than CMOS devices, which reduces compatibility. Summary of the Invention

[0006] The object of the present invention is to provide a floating gate split-gate flash memory process method to solve the problems raised in the above background technology.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A floating gate split-gate flash memory process method includes a medium-high voltage P-type well, a floating gate dielectric layer silicon oxide, a floating gate polysilicon layer, an ONO dielectric stack between polysilicon layers (silicon oxide layer, a first silicon nitride layer, a top silicon oxide layer), a first sidewall control gate polysilicon layer, a second sidewall dielectric layer, a select gate dielectric layer silicon oxide, a control gate polysilicon, a third sidewall dielectric layer, a lightly doped drain and Halo ion implantation layer, a heavily doped source and drain ion implantation layer, a metal silicide, a trench, a second silicon nitride layer, a sacrificial silicon oxide layer, a third silicon nitride layer, and an etch protection oxide layer. The process method steps are as follows:

[0009] S1: defines the active area of ​​the floating gate flash memory and the peripheral logic area;

[0010] S2: removing the silicon nitride layer, and sequentially forming a silicon oxide layer, a silicon nitride layer, a sacrificial silicon oxide layer, and a silicon nitride layer;

[0011] S3: depositing a polysilicon layer and performing anisotropic etching to form a first sidewall control gate;

[0012] S4: depositing and etching to form a second sidewall dielectric layer;

[0013] S5: etching and removing the floating gate polysilicon layer in the opening;

[0014] S6: performing thermal oxidation to form a protective etch on the top of the select gate polysilicon layer;

[0015] S7: Implanting to form a lightly doped drain Halo ion implantation layer;

[0016] S8: Perform source-drain heavy doping injection to form a source-drain heavy doping ion injection layer.

[0017] As a further solution of the present invention: in S1, a floating gate oxide layer is first grown by thermal oxidation on a P-type substrate, a floating gate polysilicon layer and a second silicon nitride layer are grown, and then the active areas of the floating gate flash memory and the peripheral logic area are simultaneously defined using the STI process.

[0018] As a further solution of the present invention: in S2, the second silicon nitride layer is removed, and a silicon oxide layer, a first silicon nitride layer, a sacrificial silicon oxide layer, and a third silicon nitride layer 504 are formed in sequence; the flash memory cell area is defined by photolithography, and the third silicon nitride layer 504 in the opening area is etched away using the sacrificial silicon oxide layer as an etch stop layer, and then the sacrificial silicon oxide layer in the opening is etched away.

[0019] As a further embodiment of the present invention, in S3, a top silicon oxide layer is formed in the ONO layer between the control gate and the floating gate by deposition or thermal oxidation, and then a polysilicon layer is deposited and anisotropically etched to form the first sidewall control gate. Because the control gate is formed by the sidewall process, the thickness of the stack formed by the floating gate dielectric layer silicon oxide, the floating gate polysilicon layer, the silicon oxide layer, the first silicon nitride layer, the sacrificial silicon oxide layer, and the third silicon nitride layer is thinner than the stack formed by the floating gate dielectric layer, the floating gate polysilicon layer, the ONO layer, the control gate polysilicon layer, and the silicon nitride layer in the existing process (the height is smaller, which facilitates integration into more advanced process steps).

[0020] As a further solution of the present invention: in S4, the ONO stack in the opening is removed by etching, and then a second sidewall dielectric layer is formed by depositing and etching.

[0021] As a further solution of the present invention: in S5, the floating gate polysilicon layer in the opening is etched away. Since the first sidewall control gate is also a polysilicon layer, part of the first control gate polysilicon layer will also be etched away when etching the floating gate polysilicon layer.

[0022] As a further solution of the present invention: in the S6, a selection gate dielectric layer and a selection gate polysilicon layer are deposited in sequence, chemical mechanical polishing (CMP) is performed with the third silicon nitride layer as a stop layer, and low-energy, high-dose N / P-type impurity ion implantation is performed to achieve simultaneous doping of the selection gate and the first sidewall control gate, and thermal oxidation is performed, and an etching protection oxide layer is formed on the top of the selection gate and the first sidewall control gate.

[0023] As a further solution of the present invention: in S7, the third silicon nitride layer is removed by a wet method, and the ONO layer and the floating gate polysilicon layer are self-alignedly etched in sequence using the second sidewall dielectric layer, the top silicon oxide layer, the select gate dielectric layer silicon oxide, and the etching protection oxide layer as masks, and LDD / Halo implantation is performed to form a lightly doped drain and a Halo ion implantation layer.

[0024] As a further solution of the present invention: in the above S8, a third sidewall dielectric layer is deposited and etched to form a source / drain heavy doping injection to form a source / drain heavy doping ion injection, and a metal silicide process simultaneously forms a low-resistivity metal silicide on the silicon surface, the control gate polysilicon surface, and the select gate polysilicon surface.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] 1. The present invention differs from existing processes in that the control gate in this structure is formed by isotropic deposition and anisotropic etching of the polysilicon layer to form the first sidewall control gate polysilicon. The present invention removes the control gate polysilicon from the existing stack of floating gate dielectric layer, floating gate polysilicon, inter-polysilicon ONO dielectric layer, control gate polysilicon, and silicon nitride layer, reducing the stack height. Furthermore, because the first sidewall control gate and floating gate are made of the same material, the first etching of the floating gate also removes part of the control gate polysilicon layer, further reducing the cell height. This increases the compatibility of the flash memory device with advanced processes.

[0027] 2. In the present invention, the select gate and the control gate share the polysilicon doping implantation, which reduces the process steps and lowers the process manufacturing cost.

[0028] 3. The present invention can simultaneously form metal silicide with lower resistivity on the surfaces of the control gate polysilicon and the first sidewall control gate polysilicon layer, thereby greatly reducing the resistivity of the control gate and further improving the integration of the flash memory (the contact holes on the CG-poly can be reduced). BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a process step diagram for an existing floating gate split-gate flash memory process.

[0030] Figure 2 The structure diagram of the existing 2-bit / cell floating gate split-gate flash memory.

[0031] Figure 3 This is a process step diagram for a floating gate split-gate flash memory process.

[0032] Figure 4 It is a schematic diagram of the local structure in the floating gate split gate flash memory process method.

[0033] Figure 5 It is a schematic diagram of the local structure in the floating gate split gate flash memory process method.

[0034] Figure 6 It is a schematic diagram of the local structure in the floating gate split gate flash memory process method.

[0035] Figure 7 It is a schematic diagram of the local structure in the floating gate split gate flash memory process method.

[0036] Figure 8 It is a schematic diagram of the local structure in the floating gate split gate flash memory process method.

[0037] Figure 9 It is a schematic diagram of the local structure in the floating gate split gate flash memory process method.

[0038] Figure 10 It is a schematic diagram of the local structure in the floating gate split gate flash memory process method.

[0039] Figure 11 It is a structural diagram of the floating gate split gate flash memory process method.

[0040] As shown in the figure: 101 - a medium-high voltage P-type well formed on the substrate, 102 - a floating gate dielectric layer silicon oxide, 103 - a floating gate polysilicon layer, 104 - an ONO dielectric stack between polysilicon layers, 104-1 - a silicon oxide layer, 104-2 - a first silicon nitride layer, 104-3 - a top silicon oxide layer, 105 - a first spacer control gate polysilicon layer, 106 - a second spacer dielectric layer, 107 - a select gate dielectric layer silicon oxide, 108 - a select gate polysilicon layer, 109 - a third spacer dielectric layer, 110 - a lightly doped drain and Halo ion implantation layer, 111 - a heavily doped source and drain ion implantation layer, 113 - a metal silicide, 501 - a trench, 502 - a second silicon nitride layer, 503 - a sacrificial silicon oxide layer, 504 - a third silicon nitride layer, and 505 - an etching protection oxide layer. DETAILED DESCRIPTION

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0042] See also Figures 1 to 11 In an embodiment of the present invention, a floating gate split-gate flash memory process method includes 101—a medium-high voltage P-type well formed on a substrate, 102—a floating gate dielectric layer of silicon oxide, 103—a floating gate polysilicon layer, 104—an ONO dielectric stack between polysilicon layers, 104-1—a silicon oxide layer, 104-2—a first silicon nitride layer, 104-3—a top silicon oxide layer, 105—a first sidewall control gate polysilicon layer, 106—a second sidewall dielectric layer, 107—a select gate dielectric layer of silicon oxide, 108—a select gate polysilicon layer, 109—a third sidewall dielectric layer, 110—a lightly doped drain and Halo ion implantation layer, 111—a heavily doped source and drain ion implantation layer, 113—a metal silicide, 501—a trench, 502—a second silicon nitride layer, 503—a sacrificial silicon oxide layer, 504—a third silicon nitride layer, and 505—an etch protection oxide layer. The process method steps are as follows:

[0043] S1: defines the active area of ​​the floating gate flash memory and the peripheral logic area;

[0044] S2: removing the silicon nitride layer, and sequentially forming a silicon oxide layer, a silicon nitride layer, a sacrificial silicon oxide layer, and a silicon nitride layer;

[0045] S3: depositing a polysilicon layer and performing anisotropic etching to form a first sidewall control gate;

[0046] S4: depositing and etching to form a second sidewall dielectric layer;

[0047] S5: etching and removing the floating gate polysilicon layer in the opening;

[0048] S6: performing thermal oxidation to form a protective etch on the top of the select gate polysilicon layer;

[0049] S7: Implanting to form a lightly doped drain Halo ion implantation layer;

[0050] S8: Perform source-drain heavy doping injection to form a source-drain heavy doping ion injection layer.

[0051] In the above S1, firstly, a floating gate oxide layer 102 is grown by thermal oxidation on a P-type substrate; a floating gate polysilicon (Poly) layer 103 and a silicon nitride layer 502 are grown; and then the active area of ​​the floating gate flash memory and the peripheral logic area are simultaneously defined by the STI (shallow-trench-isolation) process. Figure 4 shown.

[0052] In S2, the second silicon nitride layer 502 is removed, and the silicon oxide layer 104-1, the first silicon nitride layer 104-2, the sacrificial silicon oxide layer 503, and the third silicon nitride layer 504 are formed in sequence; the flash memory cell area is defined by photolithography, and the silicon nitride layer 504 in the opening area is etched away using the sacrificial silicon oxide layer 503 as an etch stop layer, and then the sacrificial silicon oxide layer 503 in the opening is etched away. Figure 5 shown.

[0053] In the above S3, a top silicon oxide layer 104-3 is formed in the ONO layer between the control gate and the floating gate by deposition or thermal oxidation, and then a polysilicon layer 105 is deposited and anisotropically etched to form the first sidewall control gate 105, as shown in the figure above. Since the control gate is formed by the sidewall process, the thickness of the stack formed by 102, 103, 104-1, 104-2, 503, and 504 is thinner than the stack formed by the floating gate dielectric layer 102, the floating gate polysilicon layer 103, the ONO 104, the control gate polysilicon layer 105, and the third silicon nitride layer 504 in the existing process (the height is smaller, which is conducive to integration into more advanced process technology), as shown in the figure above. Figure 6 shown.

[0054] In the step S4, the ONO stack in the opening is removed by etching, and then a second spacer dielectric layer 106 is formed by deposition and etching. Figure 7 shown.

[0055] In the above S5, the floating gate polysilicon layer 103 in the opening is removed by etching. Since the first sidewall control gate is also a polysilicon layer, part of the first control gate polysilicon layer will also be etched away when etching 103. Figure 8 shown.

[0056] In S6, a select gate dielectric layer 107 and a select gate polysilicon layer 108 are sequentially deposited, and chemical mechanical polishing (CMP) is performed using 504 as a stop layer. Low-energy, high-dose N / P-type impurity ion implantation is performed to simultaneously dope the select gate 108 and the first sidewall control gate 105. Thermal oxidation is then performed, and an etching protection oxide layer 505 is formed on top of 105 and 108. Figure 9 shown.

[0057] In the step S7, the silicon nitride layer 504 is wet-removed, and the ONO layer 104 and the floating gate polysilicon layer 103 are sequentially etched in a self-aligned manner using 106, 104-3, 107, and 505 as masks, and LDD / Halo implantation is performed to form 110. Figure 10 shown.

[0058] In the step S8, a third sidewall dielectric layer 109 is deposited and etched, and a source / drain heavy doping implantation is performed to form 111. A metal silicide process simultaneously forms a low-resistivity metal silicide 113 on the silicon surface, the control gate polysilicon surface, and the select gate polysilicon surface. Figure 11 shown.

[0059] Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A floating gate split-gate flash memory process method, which is used to form a floating gate split-gate flash memory device including a medium-high voltage P-type well, a floating gate dielectric layer of silicon oxide, a floating gate polysilicon layer, an ONO (Oxide-Nitride-Oxide) dielectric stack between the polysilicon layers (silicon oxide layer, a first silicon nitride layer, a top silicon oxide layer), a first sidewall control gate polysilicon layer, a second sidewall dielectric layer, a select gate dielectric layer of silicon oxide, a select gate polysilicon layer, a third sidewall dielectric layer, a lightly doped drain and Halo ion implantation layer, a heavily doped source and drain ion implantation layer, and a metal silicide, characterized in that: The process steps are as follows: S1: defining active areas of a floating gate flash memory and a peripheral logic area on a substrate using an STI process, wherein the floating gate dielectric layer silicon oxide, the floating gate polysilicon layer and the second silicon nitride layer have been formed on the P-type substrate before defining the active areas; S2: removing the second silicon nitride layer, and sequentially forming a silicon oxide layer, a first silicon nitride layer, a sacrificial silicon oxide layer, and a third silicon nitride layer on the floating gate polysilicon layer; defining a flash memory cell area by photolithography to form an opening; etching away the third silicon nitride layer in the opening using the sacrificial silicon oxide layer as an etch stop layer; and then etching away the sacrificial silicon oxide layer in the opening, thereby exposing a portion on the first silicon nitride layer for forming a subsequent structure; S3: forming a top silicon oxide layer in the inter-polysilicon ONO dielectric stack, then depositing a polysilicon layer and performing anisotropic etching to form a first spacer control gate polysilicon layer in the opening and on the sidewalls of the first silicon nitride layer and the top silicon oxide layer; S4: etching away the top silicon oxide layer, the first silicon nitride layer and the silicon oxide layer at the bottom of the opening, and then depositing and anisotropically etching to form the second spacer dielectric layer adjacent to the first spacer control gate polysilicon layer; S5: etching and removing the floating gate polysilicon layer located between the second sidewall dielectric layers in the opening, and also etching away a portion of the first sidewall control gate polysilicon layer; S6: sequentially depositing the select gate dielectric layer silicon oxide and the select gate polysilicon layer, performing chemical mechanical polishing with the third silicon nitride layer as a stop layer, performing N / P type impurity ion implantation to simultaneously dope the select gate polysilicon layer and the first sidewall control gate polysilicon layer, and then performing thermal oxidation to simultaneously form an etching protection oxide layer on top of the select gate polysilicon layer and the first sidewall control gate polysilicon layer; S7: removing the third silicon nitride layer, and using the second sidewall dielectric layer, the top silicon oxide layer, the select gate dielectric layer silicon oxide, and the etching protection oxide layer as masks, self-aligningly etching the inter-polysilicon ONO dielectric stack and the floating gate polysilicon layer in sequence, and then performing LDD / Halo ion implantation to form the lightly doped drain and the Halo ion implantation layer; S8: Deposit and anisotropically etch to form the third sidewall dielectric layer, then perform source and drain heavy doping injection to form the source and drain heavy doping ion injection layer, and finally perform a metal silicide process to simultaneously form the metal silicide with low resistivity on the silicon surface, the surface of the first sidewall control gate polysilicon layer, and the surface of the select gate polysilicon layer.

2. The floating gate split-gate flash memory process according to claim 1, wherein: In S1, a floating gate oxide layer is first grown by thermal oxidation on a P-type substrate, a floating gate polysilicon layer and a second silicon nitride layer are grown, and then an STI process is used to simultaneously define active areas of a floating gate flash memory and a peripheral logic area.

3. The floating gate split-gate flash memory process according to claim 1, wherein: In S3, a top silicon oxide layer is formed in the ONO layer between the control gate and the floating gate by deposition or thermal oxidation, and then a polysilicon layer is deposited to form the polysilicon layer and anisotropic etching is performed to form the first sidewall control gate. Since the control gate is formed by the sidewall process, the thickness of the stack formed by the floating gate dielectric layer silicon oxide, the floating gate polysilicon layer, the silicon oxide layer, the first silicon nitride layer, the sacrificial silicon oxide layer, and the third silicon nitride layer is thinner than the stack formed by the floating gate dielectric layer, the floating gate polysilicon layer, the ONO layer, the control gate polysilicon layer, and the silicon nitride layer in the existing process.

4. The floating gate split-gate flash memory process according to claim 1, wherein: Perform low-energy, high-dose N / P-type impurity ion implantation.

5. The floating gate split-gate flash memory process method according to claim 1, wherein: In S7 , the third silicon nitride layer is removed by a wet method.

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