Semiconductor memory device and method of manufacturing the same

Abstract

The present application relates to a semiconductor memory device and a method for manufacturing the semiconductor memory device. The semiconductor memory device includes: a gate stack including an interlayer insulating layer and a word line alternately stacked in a first direction; a channel pillar passing through the gate stack and gradually narrowing toward the first direction; a source selection line surrounding the channel pillar and extending to overlap with the gate stack; and a source isolation insulating layer overlapping with the gate stack between the source selection lines and gradually narrowing toward a direction opposite to the first direction.

Description

Technical Field

[0001] The present disclosure may generally relate to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device and a method of manufacturing the same. Background Art

[0002] A semiconductor memory device includes a plurality of memory cells capable of storing data. A three-dimensional semiconductor memory device may include memory cells arranged in three dimensions. The memory cells may constitute a plurality of cell memory strings. The memory cell strings may be connected to word lines and selection lines. The selection lines may include source selection lines and drain selection lines. Summary of the invention

[0003] A semiconductor memory device according to one embodiment of the present disclosure may include: a gate stack including interlayer insulating layers and word lines alternately stacked in a first direction; a channel pillar passing through the gate stack and gradually narrowing toward the first direction; a source selection line surrounding the channel pillar and extending to overlap with the gate stack; and a source isolation insulating layer overlapping with the gate stack between the source selection lines and gradually narrowing toward a direction opposite to the first direction.

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor memory device may include the following steps: forming a preliminary structure including channel pillars, an interlayer insulating layer and a conductive pattern, each of the channel pillars gradually narrowing toward a first end facing a first direction, the interlayer insulating layer and the conductive pattern surrounding the channel pillars and alternately stacked in the first direction; forming a trench passing through a first conductive pattern among the conductive patterns and gradually narrowing toward a direction opposite to the first direction; and forming a source isolation insulating layer filling the trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a circuit diagram showing a memory block of a semiconductor memory device according to one embodiment of the present disclosure.

[0006] Figure 2 A layout diagram showing a gate stack, a channel pillar, and a bit line of a semiconductor memory device according to an embodiment of the present disclosure is shown.

[0007] Figure 3A It is along Figure 2 A cross-sectional view of the semiconductor memory device taken along line AA' shown in FIG. Figure 3B yes Figure 3A An enlarged cross-sectional view of region R1 is shown.

[0008] Figure 4A is a cross-sectional view of a semiconductor memory device according to one embodiment of the present disclosure, and Figure 4B yes Figure 4A An enlarged cross-sectional view of region R2 is shown.

[0009] Figure 5 is an enlarged cross-sectional view of a source selection line of a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Fig. 6A is a cross-sectional view of a semiconductor memory device according to one embodiment of the present disclosure, and Figure 6B yes Fig. 6A An enlarged cross-sectional view of region R3 is shown.

[0011] 7A to 7H is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0012] FIG. 8A to FIG. 8D It is shown in Figure 7H An enlarged cross-sectional view of a subsequent process following the illustrated process.

[0013] 9A to 9C is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0014] FIG. 10A to FIG. 10C It is shown in Fig. 9C An enlarged cross-sectional view of a subsequent process following the illustrated process.

[0015] FIG. 11A to FIG. 11D is an enlarged cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0016] FIG. 12A to FIG. 12D is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Fig.13A and Fig. 13B It is shown in Fig.12D An enlarged cross-sectional view of a subsequent process following the illustrated process.

[0018] Fig.14 is a block diagram showing a configuration of a memory system according to one embodiment of the present disclosure.

[0019] Fig.15 is a block diagram showing a configuration of a computing system according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The specific structural description or functional description disclosed herein is only shown for the purpose of describing the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be implemented in various forms, and they should not be interpreted as limited to the specific embodiments set forth herein.

[0021] Hereinafter, the terms "first" and "second" are used to distinguish one component from another component, and are not intended to imply a specific number or order of the components. These terms can be used to describe various components, but these components are not limited by these terms.

[0022] One embodiment of the present disclosure may provide a semiconductor memory device capable of improving an alignment margin of a source isolation insulating layer separating source selection lines from each other and a method of manufacturing the same.

[0023] Figure 1 is a circuit diagram showing a memory block BLK of a semiconductor memory device according to one embodiment of the present disclosure.

[0024] Reference Figure 1 , the semiconductor memory device may include a plurality of memory blocks BLK. Each memory block BLK may include a plurality of memory cell strings MS1, MS2, and MS3 connected to a common source layer CSL and a bit line BL.

[0025] Each of the memory cell strings MS1, MS2, and MS3 may include a plurality of memory cells MC connected in series, at least one source select transistor SST, and at least one drain select transistor DST. In one embodiment, each of the memory cell strings MS1, MS2, and MS3 may include a source select transistor SST connected between the plurality of memory cells MC and the common source layer CSL. In one embodiment, each of the memory cell strings MS1, MS2, and MS3 may include two or more source select transistors SST connected in series between the plurality of memory cells MC and the common source layer CSL. In one embodiment, each of the memory cell strings MS1, MS2, and MS3 may include a drain select transistor DST connected between the plurality of memory cells MC and the bit line BL. In one embodiment, each of the memory cell strings MS1, MS2, and MS3 may include two or more drain select transistors DST connected in series between the plurality of memory cells MC and the bit line BL.

[0026] The plurality of memory cells MC may be connected to the common source layer CSL via the source select transistor SST. The plurality of memory cells MC may be connected to the bit line BL via the drain select transistor DST.

[0027] The gates of the source selection transistors SST disposed at the same level may be connected to the source selection lines SSL1, SSL2, and SSL3 separated from each other. The gates of the drain selection transistors DST disposed at the same level may be connected to the drain selection lines DSL1, DSL2, and DSL3 separated from each other. The gates of the plurality of memory cells MC may be connected to a plurality of word lines WL. The word lines WL may be disposed at different levels, and the gates of the memory cells MC disposed at the same level may be connected to a single word line WL.

[0028] Hereinafter, the present disclosure is described based on an embodiment in which the memory block BLK includes a first source selection line SSL1, a second source selection line SSL2, and a third source selection line SSL3 separated from each other at the same level, and includes a first drain selection line DSL1, a second drain selection line DSL2, and a third drain selection line DSL3 separated from each other at the same level. The embodiments of the present disclosure are not limited thereto, and the memory block BLK may include two source selection lines separated from each other at the same level, or may include four or more source selection lines separated from each other at the same level. Similarly, the memory block BLK may include two drain selection lines separated from each other at the same level, or may include four or more drain selection lines separated from each other at the same level.

[0029] A plurality of memory cell strings MS1, MS2, and MS3 may be connected to each of the word lines WL. The plurality of memory cell strings MS1, MS2, and MS3 may include a first group, a second group, and a third group that may be individually selected by a first source selection line SSL1, a second source selection line SSL2, and a third source selection line SSL3. The first group may include a first memory cell string MS1, a second group may include a second memory cell string MS2, and a third group may include a third memory cell string MS3.

[0030] The first memory cell string MS1 may be connected to the bit line BL via a drain selection transistor DST connected to the first drain selection line DSL1, respectively. The second memory cell string MS2 may be connected to the bit line BL via a drain selection transistor DST connected to the second drain selection line DSL2, respectively. The third memory cell string MS3 may be connected to the bit line BL via a drain selection transistor DST connected to the third drain selection line DSL3, respectively. One of the first memory cell string MS1, one of the second memory cell string MS2, and one of the third memory cell string MS3 may be connected to a single bit line BL.

[0031] The first memory cell string MS1 may be connected to the common source layer CSL under the control of the source selection transistor SST connected to the first source selection line SSL1. The second memory cell string MS2 may be connected to the common source layer CSL under the control of the source selection transistor SST connected to the second source selection line SSL2, and the third memory cell string MS3 may be connected to the common source layer CSL under the control of the source selection transistor SST connected to the third source selection line SSL3. Therefore, during a read operation or a verification operation, for each of the source selection lines SSL1, SSL2, and SSL3, a plurality of memory cell strings MS1, MS2, and MS3 may be divided into groups that may be individually selected at the same time. In one embodiment, during a read operation or a verification operation, one of the first group of the first memory cell string MS1, the second group of the second memory cell string MS2, and the third group of the third memory cell string MS3 may be connected to the common source layer CSL by selecting one of the first source selection line SSL1, the second source selection line SSL2, and the third source selection line SSL3. Therefore, the embodiments of the present disclosure can reduce channel resistance compared to the case where the first memory cell string MS1, the second memory cell string MS2, and the third memory cell string MS3 are simultaneously connected to the common source layer CSL during a read operation or a verification operation. Therefore, the embodiments of the present disclosure can reduce read disturbance.

[0032] Figure 2 A layout diagram showing gate stacks G1 , G2 , and G3 , channel pillars CH, and bit lines BL of a semiconductor memory device according to an embodiment of the present disclosure is shown.

[0033] Reference Figure 2 The gate stacks G1, G2, and G3 may be separated from each other by the gate isolation insulating layer SG. The gate stacks G1, G2, and G3 may surround the channel pillar CH extending in the first direction D1.

[0034] The channel pillars CH may be arranged in a plurality of rows arranged along the second direction D2 in a plane intersecting the channel pillars CH and a plurality of columns arranged along the third direction D3 in a plane intersecting the channel pillars CH. In one embodiment, the plurality of channel pillars CH respectively passing through the gate stacks G1, G2, and G3 may include a first channel pillar CH1, a second channel pillar CH2, and a third channel pillar CH3 arranged to be spaced apart from each other in the second direction D2.

[0035] Each of the gate stacks G1 , G2 , and G3 may include a word line WL and drain selection lines DSL1 , DSL2 , and DSL3 .

[0036] In one embodiment, each of the gate stacks G1, G2, and G3 may include a first drain selection line DSL1 surrounding a first channel pillar CH1, a second drain selection line DSL2 surrounding a second channel pillar CH2, and a third drain selection line DSL3 surrounding a third channel pillar CH3. The first drain selection line DSL1, the second drain selection line DSL2, and the third drain selection line DSL3 may be spaced apart from each other in the second direction D2 by a drain isolation insulating layer SD. The first drain selection line DSL1, the second drain selection line DSL2, the third drain selection line DSL3, and the drain isolation insulating layer SD may extend in a third direction D3. The shape of the drain isolation insulating layer SD may be various, such as a wave shape or a straight line shape.

[0037] The word lines WL may overlap the drain selection lines DSL1, DSL2, and DSL3. Each of the word lines WL may extend in the second direction D2 to surround the first, second, and third channel pillars CH1, CH2, and CH3. Each of the word lines WL may overlap the drain isolation insulating layer SD.

[0038] Each of the word lines WL may be penetrated by a dummy channel pillar DCH. The dummy channel pillar DCH may overlap the drain isolation insulating layer SD. The dummy channel pillars DCH may be arranged in a row in the extension direction of the drain isolation insulating layer SD. Although not shown in the figure, the dummy channel pillars DCH may be omitted.

[0039] The bit line BL may extend in a direction crossing the drain selection lines DSL1, DSL2, and DSL3. In one embodiment, the bit line BL may extend in the second direction D2. The bit line BL may be connected to the channel pillar CH through the contact plug CT. Each of the bit lines BL may be commonly connected to a channel pillar that may be controlled by different drain selection lines DSL1, DSL2, and DSL3. In one embodiment, each of the bit lines BL may be commonly connected to a first channel pillar CH1 that may be controlled by a first drain selection line DSL1, a second channel pillar CH2 that may be controlled by a second drain selection line DSL2, and a third channel pillar CH3 that may be controlled by a third drain selection line DSL3.

[0040] Figure 3A It is along Figure 2 A cross-sectional view of the semiconductor memory device taken along line AA' shown in FIG. Figure 3B yes Figure 3A An enlarged cross-sectional view of region R1 is shown.

[0041] Figure 2 The illustrated line AA′ overlaps the dummy channel pillar DCH between the first channel pillar CH1 and the second channel pillar CH2 , but does not overlap the dummy channel pillar DCH between the second channel pillar CH2 and the third channel pillar CH3 .

[0042] Reference Figure 3A , the semiconductor memory device may include a common source layer CSL overlapping the bit line BL. The gate stacks G1 and G2 may be disposed between the common source layer CSL and the bit line BL. The semiconductor memory device may include a peripheral circuit structure 50. The bit line BL may be disposed between the gate stacks G1 and G2 and the peripheral circuit structure 50. The semiconductor memory device may include source selection lines SSL1, SSL2, and SSL3 overlapping each of the gate stacks G1 and G2. The source selection lines SSL1, SSL2, and SSL3 may be disposed between each of the gate stacks G1 and G2 and the common source layer CSL.

[0043] The channel pillar CH may extend in the first direction D1 to pass through the gate stacks G1 and G2 and the source selection lines SSL1, SSL2 and SSL3. The channel pillar CH may extend into the common source layer CSL. Each of the channel pillars CH may include a channel layer CL, a core insulation layer CO and a capping pattern CAP. The core insulation layer CO and the capping pattern CAP may be disposed in a central region of the channel pillar CH. The core insulation layer CO may overlap with the capping pattern CAP. The capping pattern CAP may include a doped semiconductor layer. In one embodiment, the capping pattern CAP may include doped silicon containing n-type impurities. The channel layer CL may surround the sidewalls of the capping pattern CAP and the sidewalls of the core insulation layer CO. The channel layer CL may extend onto the surface of the core insulation layer CO facing the common source layer CSL. The channel layer CL may constitute a channel region of a memory cell string. The channel layer CL may include a semiconductor layer. In one embodiment, the channel layer CL may include silicon.

[0044] The common source layer CSL may include a doped semiconductor layer 181 and a metal layer 185 stacked in the first direction D1. The common source layer CSL may further include a first metal barrier layer 183. The doped semiconductor layer 181 may include at least one of an n-type impurity and a p-type impurity. In one embodiment, the doped semiconductor layer 181 may include silicon doped with an n-type impurity. The common source layer CSL may be insulated from the source selection lines SSL1, SSL2, and SSL3 by a first insulating layer 11. The first insulating layer 11 may extend between the common source layer CSL and each of the source selection lines SSL1, SSL2, and SSL3.

[0045] The channel pillar CH may extend into the doped semiconductor layer 181 of the common source layer CSL. The channel layer CL of the channel pillar CH may be in contact with the doped semiconductor layer 181 of the common source layer CSL.

[0046] The source selection lines SSL1, SSL2, and SSL3 may be separated from each other by a source isolation insulating layer SS. In other words, the source isolation insulating layer SS may be disposed between the source selection lines SSL1, SSL2, and SSL3. The source isolation insulating layer SS may overlap the drain isolation insulating layer SD. The source isolation insulating layer SS may extend parallel to the drain isolation insulating layer SD. In one embodiment, the source isolation insulating layer SS may extend in a third direction D3. The source isolation insulating layer SS may extend in the first direction D1 to pass through the first insulating layer 11.

[0047] The source isolation insulating layer SS may have a tapered shape opposite to the tapered shape of each of the channel pillars CH. Each of the channel pillars CH may have a tapered shape that gradually narrows toward the first direction D1. Therefore, the distance between the protrusions of the channel pillars CH extending beyond the gate stack G1 in the first direction may be defined as being greater than the distance between the portions of the channel pillars CH disposed inside the gate stack G1. Therefore, according to one embodiment of the present disclosure, the margin space for aligning the source isolation insulating layer SS between the protrusions of the channel pillars CH may be increased.

[0048] The source isolation insulating layer SS may have a tapered shape gradually narrowing toward a direction opposite to the first direction D1. Therefore, the width of the upper end of the source isolation insulating layer SS facing the common source layer CSL may be formed wider than the width of the lower end of the source isolation insulating layer SS facing the gate stack G1.

[0049] Because the channel pillars CH may have a tapered shape that gradually narrows toward the first direction D1, the space between the channel pillars CH may become wider as the channel pillars CH approach the common source layer CSL. Therefore, the space between the channel pillars CH at the upper end where the source isolation insulating layer SS is disposed may be defined as wider than the space between the channel pillars CH at the lower end where the source isolation insulating layer SS is disposed. As a result, the margin space for aligning the upper end of the source isolation insulating layer SS with a wider width may be increased between the channel pillars CH. Therefore, according to one embodiment of the present disclosure, the alignment margin of the source isolation insulating layer SS may be improved.

[0050] Each of the gate stacks G1 and G2 may include an interlayer insulating layer 21 and a conductive pattern 23 alternately stacked in a first direction D1. Each of the gate stacks G1 and G2 may surround a channel pillar CH and a memory pattern ML is interposed between the channel pillar CH and each of the gate stacks G1 and G2. The memory pattern ML may extend along a sidewall of the channel pillar CH. The memory pattern ML may extend between each of the source selection lines SSL1, SSL2, and SSL3 and the channel pillar CH.

[0051] The conductive patterns 23 may include the same conductive material. Each conductive pattern 23 may surround the channel pillar CH and the first blocking insulating layer 25 is interposed between the channel pillar CH and each conductive pattern 23. The first blocking insulating layer 25 may be disposed between each conductive pattern 23 and the memory pattern ML. The first blocking insulating layer 25 may extend between each of the conductive patterns 23 and the interlayer insulating layer 21.

[0052] The conductive pattern 23 may be used as a word line WL and drain selection lines DSL1, DSL2, and DSL3. At least one layer of the conductive pattern 23 adjacent to the bit line BL may be used as the drain selection lines DSL1, DSL2, and DSL3, and the remaining layers may be used as the word line WL. In one embodiment, the drain selection lines DSL1, DSL2, and DSL3 may include first to third drain selection lines DSL1 to DSL3 of two layers consisting of a first horizontal conductive pattern 23A and a second horizontal conductive pattern 23B adjacent to the bit line BL. The drain selection lines DSL1, DSL2, and DSL3 may be spaced apart from each other at the same level by a drain isolation insulating layer SD. The drain isolation insulating layer SD may have a tapered shape that gradually narrows toward the first direction D1.

[0053] The source selection lines SSL1, SSL2, and SSL3 may overlap with the drain selection lines DSL1, DSL2, and DSL3 and the word lines WL are interposed therebetween. In one embodiment, the source selection lines SSL1, SSL2, and SSL3 may include a first source selection line SSL1, a second source selection line SSL2, and a third source selection line SSL3 extending parallel to the first drain selection line DSL1, the second drain selection line DSL2, and the third drain selection line DSL3, respectively. The first source selection line SSL1 may surround the first channel pillar CH1, the second source selection line SSL2 may surround the second channel pillar CH2, and the third source selection line SSL3 may surround the third channel pillar CH3.

[0054] The word line WL may be penetrated by a dummy channel pillar DCH. The dummy channel pillar DCH may be disposed between a source isolation insulating layer SS and a drain isolation insulating layer SD. The sidewall of the dummy channel pillar DCH may be surrounded by a dummy memory pattern DML. The dummy channel pillar DCH may include a dummy core insulating layer DCO and a dummy channel layer DCL. The dummy core insulating layer DCO may be disposed in a central region of the dummy channel pillar DCH, and the dummy channel layer DCL may be disposed between the dummy core insulating layer DCO and the dummy memory pattern DML.

[0055] The conductive material of the source selection lines SSL1, SSL2, and SSL3 may be various. The manufacturing process of the semiconductor memory device may include a plurality of etching processes performed using various etching materials. The source selection lines SSL1, SSL2, and SSL3 may include a material having etching resistance to some etching materials. In one embodiment, each of the source selection lines SSL1, SSL2, and SSL3 may include silicon.

[0056] The contact plug CT may pass through at least one insulating layer disposed between the bit line BL and the channel pillar CH. In one embodiment, the second insulating layer 133 and the third insulating layer 165 may be disposed between each of the gate stacks G1 and G2 and the bit line BL. The contact plug CT may contact the capping pattern CAP and may extend toward the bit line BL to pass through the second insulating layer 133 and the third insulating layer 165.

[0057] The semiconductor memory device may include a first insulating structure 171 , a first interconnection structure 173 , and a first bonding metal pattern 175 .

[0058] The first insulating structure 171 may be disposed between the peripheral circuit structure 50 and the bit line BL. The first insulating structure 171 may include two or more insulating layers. The first interconnect structure 173 and the first bonding metal pattern 175 may be buried in the first insulating structure 171. The first interconnect structure 173 may include conductive patterns of various shapes. The first interconnect structure 173 may be disposed between the bit line BL and the first bonding metal pattern 175. The bit line BL may be electrically connected to the first bonding metal pattern 175 via the first interconnect structure 173. The first bonding metal pattern 175 may face the peripheral circuit structure 50.

[0059] The peripheral circuit structure 50 may include a substrate 101 having a transistor TR, a second insulating structure 121 , a second interconnection structure 123 , and a second bonding metal pattern 125 .

[0060] The transistor TR may be disposed in an active region of the substrate 101 separated by the element isolation layer 103. Each transistor TR may include a gate insulating layer disposed on the active region, a gate 115 disposed on the gate insulating layer 113, and junctions 111A and 111B formed in the active region on both sides of the gate insulating layer 113. Some transistors TR may constitute a page buffer circuit PB that controls a precharge operation and a discharge operation of a bit line BL. The page buffer circuit PB may be connected to the bit line BL via the second interconnect structure 123 and the first interconnect structure 173.

[0061] The second insulating structure 121 may be disposed between the first insulating structure 171 and the substrate 101. The second insulating structure 121 may include two or more insulating layers. The second insulating structure 121 may be bonded to the first insulating structure 171. The second interconnect structure 123 and the second bonding metal pattern 125 may be buried in the second insulating structure 121. The second interconnect structure 123 may include conductive patterns of various shapes. The second interconnect structure 123 may be disposed between the transistor TR and the second bonding metal pattern 125. The transistor TR of the page buffer circuit PB may be electrically connected to the second bonding metal pattern 125 via the second interconnect structure 123. The second bonding metal pattern 125 may face the first bonding metal pattern 175 and may be bonded to the first bonding metal pattern 175.

[0062] Reference Figure 3B , the conductive pattern 23 may include a metal layer MT and a second metal barrier layer BM.

[0063] The channel pillar CH may protrude beyond the memory pattern ML into the doped semiconductor layer 181 of the common source layer. The channel layer CL of the channel pillar CH may extend between the doped semiconductor layer 181 and the core insulating layer CO.

[0064] The memory pattern ML may be disposed between the source selection line SSL2 or SSL3 and the channel pillar CH. The memory pattern ML may extend between the channel pillar CH and each of the interlayer insulating layer 21, the conductive pattern 23, and the first insulating layer 11. The memory pattern ML may include a tunneling insulating layer TI, a data storage layer DL extending along the outer wall of the tunneling insulating layer TI, and a second blocking insulating layer BI extending along the outer wall of the data storage layer DL. The data storage layer DL may be formed of a material layer capable of storing data. In one embodiment, the data storage layer DL may be formed of a material layer capable of storing data changed using the Fowler-Nordheim tunneling effect. The material layer may include a nitride layer capable of capturing charges. The second blocking insulating layer BI may include an oxide layer capable of blocking charges. The tunneling insulating layer TI may be formed of a silicon oxide layer capable of performing charge tunneling.

[0065] The first blocking insulating layer 25 may include a material layer having a higher dielectric constant than the second blocking insulating layer BI. In one embodiment, the first blocking insulating layer 25 may include an aluminum oxide layer. One of the first blocking insulating layer 25 and the second blocking insulating layer BI may be omitted.

[0066] The source isolation insulating layer SS may include a bottom surface facing the interlayer insulating layer 21 and an upper surface facing the doped semiconductor layer 181. According to one embodiment of the present disclosure, the bottom surface width W11 of the source isolation insulating layer SS may be narrower than the upper surface width W12 of the source isolation insulating layer SS through the tapered shape.

[0067] Figure 4A is a cross-sectional view of a semiconductor memory device according to one embodiment of the present disclosure, and Figure 4B yes Figure 4A An enlarged cross-sectional view of region R2 is shown.

[0068] Reference Figure 4A , the semiconductor memory device may include Figure 2 and Figure 3A The bit line BL, common source layer CSL, gate stacks G1 and G2, drain isolation insulating layer SD and contact plug CT have the same structure as the bit line BL', common source layer CSL', gate stacks G1' and G2', drain isolation insulating layer SD' and contact plug CT'. Figure 3A As described above, each of the gate stacks G1' and G2' may be penetrated by a channel pillar CH' and a dummy channel pillar DCH'. The channel pillar CH' and the dummy channel pillar DCH' may extend in the first direction D1. The sidewall of the channel pillar CH' may be surrounded by a memory pattern ML', and the sidewall of the dummy channel pillar DCH' may be surrounded by a dummy memory pattern DML'.

[0069] In addition, the semiconductor memory device may include Figure 3A The peripheral circuit structure 50, the first interconnect structure 173 and the first bonding metal pattern 175 are shown to have the same structure as the peripheral circuit structure 50', the first interconnect structure 173' and the first bonding metal pattern 175. In addition, the semiconductor memory device may include source selection lines SSL1', SSL2' and SSL3' disposed between the gate stacks G1' and G2' and the common source layer CSL'.

[0070] Each of the source selection lines SSL1', SSL2', and SSL3' may extend in the second direction D2 and the third direction D3 in a plane intersecting the channel pillar CH'. The source selection lines SSL1', SSL2', and SSL3' may be arranged to be spaced apart from each other in the second direction D2. The source selection lines SSL1', SSL2', and SSL3' may be insulated from the common source layer CSL' by the first insulating layer 11'.

[0071] The source selection lines SSL1', SSL2', and SSL3' may be separated from each other by the first source isolation insulating layer SS1' and the second source isolation insulating layer SS2'. Each of the first source isolation insulating layer SS1' and the second source isolation insulating layer SS2' may include a first portion disposed between the source selection lines SSL1', SSL2', and SSL3' and a second portion passing through the first insulating layer 11'. The first portion of each of the first source isolation insulating layer SS1' and the second source isolation insulating layer SS2' may be formed in a tapered shape. The tapered shape of each of the first source isolation insulating layer SS1' and the second source isolation insulating layer SS2' may be as described with reference to Figure 3A The shape described is the opposite of the tapered shape of the channel pillar CH'. Figure 3A As described above, the embodiments of the present disclosure can improve the alignment margin of the first source isolation insulating layer SS1 ′ and the second source isolation insulating layer SS2 ′.

[0072] The first source isolation insulating layer SS1' may overlap the gate stack G1'. The first source isolation insulating layer SS1' may extend parallel to the drain isolation insulating layer SD'. In one embodiment, the first source isolation insulating layer SS1' and the drain isolation insulating layer SD' may extend in a third direction D3.

[0073] The second source isolation insulating layer SS2' may overlap the gate isolation insulating layer SG'. The second source isolation insulating layer SS2' may extend parallel to the gate isolation insulating layer SG'. In one embodiment, the second source isolation insulating layer SS2' and the gate isolation insulating layer SG' may extend in a third direction D3.

[0074] The source selection lines SSL1', SSL2' and SSL3' may overlap with the drain selection lines DSL1', DSL2' and DSL3' of the gate stack G1'. In one embodiment, each of the source selection lines SSL1', SSL2' and SSL3' may include a silicon layer 13' and a metal silicide layer 15'. Figure 4A , the silicon layer 13' may be used as an etch stop layer in a manufacturing process of a semiconductor memory device. The metal silicide layer 15' may be disposed between each of the first source isolation insulating layer SS1' and the second source isolation insulating layer SS2' and the silicon layer 13'. The metal silicide layer 15' may be in contact with the silicon layer 13'. The metal silicide layer 15' may reduce the resistance of the source selection lines SSL1', SSL2', and SSL3'.

[0075] The second insulating layer 133' and the third insulating layer 165' may be Figure 3A The second insulating layer 133 and the third insulating layer 165 are formed with the same structure.

[0076] Reference Figure 4B , as referenced Figure 3B As described above, the channel pillar CH' may protrude beyond the memory pattern ML' into the doped semiconductor layer 181' of the common source layer. The channel layer CL' and the core insulating layer CO' of the channel pillar CH' may extend into the doped semiconductor layer 181'.

[0077] As reference Figure 3B As described above, the memory pattern ML' may include a tunneling insulating layer TI', a data storage layer DL', and a blocking insulating layer BI'.

[0078] The first source isolation insulating layer SS1' may include a bottom surface facing the gate stack G1' and an upper surface facing the doped semiconductor layer 181'. According to one embodiment of the present disclosure, the bottom surface width W21 of the first source isolation insulating layer SS1' may be narrower than the upper surface width W22' of the first source isolation insulating layer SS1' through the tapered shape.

[0079] Figure 5 is an enlarged cross-sectional view of a source selection line SSL of a semiconductor memory device according to an embodiment of the present disclosure.

[0080] Reference Figure 5 The gate stack G1', the first insulating layer 11', the memory pattern ML', the tunnel insulating layer TI', the data storage layer DL', the blocking insulating layer BI', the channel pillar CH', the core insulating layer CO', the channel layer CL' and the doped semiconductor layer 181' of the common source layer can be referred to Figure 4A and Figure 4B Describe the structure formation.

[0081] The source selection lines SSL may be separated from each other by a source isolation insulating layer SS1″ overlapping the gate stack G1′. Each of the source selection lines SSL may include a silicon layer 13A and a sidewall conductive pattern 20. Figure 4A As described above, the silicon layer 13A can be used as an etch stop layer in the manufacturing process of the semiconductor memory device. The sidewall conductive pattern 20 can be arranged between the source isolation insulating layer SS1" and the silicon layer 13A. The sidewall conductive pattern 20 may include a metal barrier layer 17 in contact with the silicon layer 13A and a metal layer 19 arranged between the metal barrier layer 17 and the source isolation insulating layer SS1". The metal layer 19 can reduce the resistance of the source selection line SSL. The metal barrier layer 17 can extend between the metal layer 19 and the first insulating layer 11'. The metal barrier layer 17 can extend between the metal layer 19 and the gate stack G1'.

[0082] Fig. 6A is a cross-sectional view of a semiconductor memory device according to one embodiment of the present disclosure, and Figure 6Byes Fig. 6A An enlarged cross-sectional view of region R3 is shown.

[0083] Reference Fig. 6A , the semiconductor memory device may include Figure 2 and Figure 3A The bit lines BL, common source layers CSL, gate stacks G1 and G2, drain isolation insulating layers SD, and contact plugs CT have the same structure as shown in FIG. Figure 3A As described above, each of the gate stacks G1 ″ and G2 ″ may be penetrated by the channel pillar CH1 ″ and the dummy channel pillar DCH ″. A sidewall of the channel pillar CH1 ″ may be surrounded by the memory pattern ML ″, and a sidewall of the dummy channel pillar DCH ″ may be surrounded by the dummy memory pattern DML ″.

[0084] In addition, the semiconductor memory device may include Figure 3A The peripheral circuit structure 50, the first interconnect structure 173 and the first bonding metal pattern 175 shown have the same structure as the peripheral circuit structure 50", the first interconnect structure 173" and the first bonding metal pattern 175". In addition, the semiconductor memory device may include source selection lines SSL1", SSL2" and SSL3" arranged between the gate stacks G1" and G2" and the common source layer CSL".

[0085] Each of the source selection lines SSL1", SSL2" and SSL3" may extend in a second direction D2 and a third direction D3 in a plane intersecting the first direction D1 which is an extension direction of the channel pillar CH". The source selection lines SSL1", SSL2" and SSL3" may include the same conductive material as the word lines WL" of the gate stack G1". The source selection lines SSL1", SSL2" and SSL3" may overlap with the drain selection lines DSL1", DSL2" and DSL3". The source selection lines SSL1", SSL2" and SSL3" may be arranged on two or more layers spaced apart from each other along the first direction D1.

[0086] In one embodiment, the source selection lines SSL1", SSL2", and SSL3" may be formed by a selection stack 30 disposed between the word line WL" and the first insulating layer 11". The selection stack 30 may include a first conductive pattern 31A, an interlayer insulating layer 33, and a second conductive pattern 31B. The first conductive pattern 31A may be disposed between the interlayer insulating layer 33 and the first insulating layer 11", and the second conductive pattern 31B may be disposed between the interlayer insulating layer 33 and the gate stack G1".

[0087] The selection stack 30 may be penetrated by the source isolation insulating layer SS” and the gate isolation insulating layer SG”. Each of the first conductive pattern 31A and the second conductive pattern 31B may be separated into source selection lines SSL1”, SSL2” and SSL3” by the source isolation insulating layer SS”. In one embodiment, the source selection lines SSL1”, SSL2” and SSL3” may include two layers of first source selection lines SSL1”, two layers of second source selection lines SSL2” and two layers of third source selection lines SSL3”. The two layers of first source selection lines SSL1” to the two layers of third source selection lines SSL3” may be composed of the first conductive pattern 31A and the second conductive pattern 31B.

[0088] As reference Figure 3A As described above, the source isolation insulating layer SS" may be formed in a shape opposite to the tapered shape of the channel pillar CH". Figure 3A As described above, the embodiments of the present disclosure can improve the alignment margin of the source isolation insulating layer SS″.

[0089] The source isolation insulating layer SS" may overlap the gate stack G1". The source isolation insulating layer SS" may extend parallel to the drain isolation insulating layer SD". In one embodiment, the source isolation insulating layer SS" and the drain isolation insulating layer SD" may extend in a third direction D3.

[0090] The second insulating layer 133" and the third insulating layer 165" may be formed with Figure 3A The second insulating layer 133 and the third insulating layer 165 are formed with the same structure.

[0091] Reference Figure 6B , each of the first conductive pattern 31A and the second conductive pattern 31B of the selection stack 30 may include a metal layer MT” and a metal barrier layer BM”. The metal barrier layer BM” may be disposed between the metal layer MT” and the memory pattern ML”. The metal barrier layer BM” may extend between the metal layer MT” and the first insulating layer 11”. The metal barrier layer BM” may extend between the metal layer MT” and the interlayer insulating layer 33. The metal barrier layer BM” may extend between the metal layer MT” and the gate stack G1”.

[0092] As reference Figure 3B As described above, the memory pattern ML" may include a tunneling insulating layer TI", a data storing layer DL" and a blocking insulating layer BI". Figure 3B As described above, the channel pillar CH" may protrude beyond the memory pattern ML" into the doped semiconductor layer 181" of the common source layer. The channel layer CL" and the core insulating layer CO" of the channel pillar CH" may extend into the doped semiconductor layer 181".

[0093] The source isolation insulating layer SS" may include a bottom surface facing the gate stack G1" and an upper surface facing the doped semiconductor layer 181". According to one embodiment of the present disclosure, through the tapered shape, the bottom surface width W31 of the source isolation insulating layer SS" may be narrower than the upper surface width W32 of the source isolation insulating layer SS".

[0094] 7A to 7H is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0095] Reference Fig. 7A , a protection layer 603 may be formed on the sacrificial substrate 601. The protection layer 603 may include a material having an etching selectivity to the sacrificial substrate 601. In one implementation, the sacrificial substrate 601 may be a silicon substrate, and the protection layer 603 may include a silicon nitride layer.

[0096] Subsequently, a first insulating layer 605 and a first conductive pattern 607 may be stacked on the protective layer 603. Thereafter, an interlayer insulating layer 611 and a sacrificial layer 613 may be alternately stacked on the first conductive pattern 607.

[0097] The first insulating layer 605 may include a silicon oxide layer. The first conductive pattern 607 may include a conductive material having an etching selectivity to the interlayer insulating layer 611 and the sacrificial layer 613. In one embodiment, the first conductive pattern 607 may include a silicon layer, the interlayer insulating layer 611 may include a silicon oxide layer, and the sacrificial layer 613 may include a silicon nitride layer.

[0098] Thereafter, a first mask pattern 615 may be formed on the stack of the interlayer insulating layer 611 and the sacrificial layer 613. Subsequently, a channel hole 619 may be formed that passes through the interlayer insulating layer 611 and the sacrificial layer 613 and extends into the protective layer 603. A dummy hole 619D having the same shape as each channel hole 619 may be formed by using a process for forming the channel hole 619.

[0099] Each of the channel hole 619 and the dummy hole 619D may be formed by etching the interlayer insulating layer 611, the sacrificial layer 613, the first conductive pattern 607, and the first insulating layer 605 through an etching process using the first mask pattern 615 as an etching barrier. During the etching process of forming the channel hole 619 and the dummy hole 619D, a portion of the protection layer 603 may be etched, but the protection layer 603 may remain along the bottom surface of each of the channel hole 619 and the dummy hole 619D.

[0100] The etching process for forming the channel hole 619 and the dummy hole 619D may be performed by sequentially etching the interlayer insulating layer 611, the sacrificial layer 613, the first conductive pattern 607, and the first insulating layer 605 from the interlayer insulating layer 611 adjacent to the first mask pattern 615 toward the protective layer 603. Therefore, each of the channel hole 619 and the dummy hole 619D may have a tapered shape that gradually narrows toward the sacrificial substrate 601 along the first direction D1.

[0101] Subsequently, a memory layer 621 and a dummy memory layer 621D may be formed on the surfaces of the channel hole 619 and the dummy hole 619D, respectively. Each of the memory layer 621 and the dummy memory layer 621D may include Fig. 8A The first blocking insulating layer 621A, the data storage layer 621B and the tunneling insulating layer 621C are shown.

[0102] Thereafter, a channel pillar 630 may be formed in a central region of the channel hole 619 opened by the memory layer 621. When forming the channel pillar 630, a dummy channel pillar 630D may be formed in a central region of the dummy hole 619D opened by the dummy memory layer 621D.

[0103] The step of forming the channel pillar 630 and the dummy channel pillar 630D may include: forming a semiconductor layer along the surface of each of the channel hole 619 and the dummy hole 619D; forming a filling insulating layer on the semiconductor layer; removing a portion of the filling insulating layer; filling the area where the filling insulating layer is removed with a doped semiconductor layer; and flattening the doped semiconductor layer and the semiconductor layer so that the first mask pattern 615 is exposed. Through the above series of processes, the filling insulating layer can be retained as a core insulating layer 625 inside the channel hole 619, and can be retained as a dummy core insulating layer 625D inside the dummy hole 619D. In addition, the semiconductor layer can be retained as a channel layer 623 inside the channel hole 619, and can be retained as a dummy channel layer 623 inside the dummy hole 619D. In addition, the doped semiconductor layer can be retained as a capping pattern 627 inside the channel hole 619, and can be retained as a dummy capping pattern 627D inside the dummy hole 619D. The semiconductor layer may include a silicon layer, and the doped semiconductor layer may include a doped silicon layer containing n-type impurities.

[0104] Each of the channel pillars 630 may include a first end EP1A facing the first direction D1 and a second end EP2A facing a direction opposite to the first end EP1A. Each of the channel pillars 630 may have a tapered shape that gradually narrows as the channel pillar 630 approaches the first end EP1A.

[0105] After forming the channel pillar 630 and the dummy channel pillar 630D, the first mask pattern 615 may be removed.

[0106] Reference Figure 7B , a second insulating layer 635 covering the channel pillar 630 and the dummy channel pillar 630D may be formed. The second insulating layer 635 may extend to overlap the interlayer insulating layer 611 .

[0107] Subsequently, a first slit 637 may be formed to pass through the second insulating layer 635, Fig. 7A An interlayer insulating layer 611 and a sacrificial layer 613 are shown. During the etching process of forming the first slits 637, the first conductive pattern 607 may be used as an etch stop layer.

[0108] Thereafter, by selectively removing the sacrificial layer 613 through the first slits 637 , a horizontal space 639 may be opened between the interlayer insulating layers 611 .

[0109] Reference Figure 7C , can be respectively formed by the first slit 637 Figure 7B The second conductive pattern 649 is shown to be formed inside the horizontal space 639. Before forming the second conductive pattern 649, a second blocking insulating layer 641 may be formed on a surface of each horizontal space 639.

[0110] The step of forming the second conductive pattern 649 may include filling the horizontal space 639 opened by the second blocking insulating layer 641 with a conductive material, and removing the conductive material inside the first slit 637 so that the conductive material can be separated into the second conductive pattern 649. The conductive material of the second conductive pattern 649 may include Fig. 8A Metal barrier layer 643 and metal layer 645 are shown.

[0111] You can refer to the above FIG. 7A to FIG. 7C The preliminary structure 650 may include a channel pillar 630 having a tapered shape, a first conductive pattern 607 surrounding the channel pillar 630 , and an interlayer insulating layer 611 and a second conductive pattern 649 alternately stacked on the first conductive pattern 607 and surrounding the channel pillar 630 .

[0112] Thereafter, the second slit 651 may be formed by etching the first conductive pattern 607 exposed through the first slit 637. The second slit 651 may pass through the first conductive pattern 607, and may be connected to the first slit 637.

[0113] Reference Fig.7D , the gate isolation insulating layer 653 can be used to fill Figure 7C The first slit 637 and the second slit 651 are shown. Thereafter, a drain trench 657 may be formed. The drain trench 657 may pass through Figure 7CThe second conductive pattern 649 through which the drain trench 657 penetrates is adjacent to the second end EP2A of the channel pillar 630 .

[0114] The drain trench 657 may extend along the third direction D3 between the channel pillars 630 . Figure 7C The illustrated second conductive pattern 649 may be separated into drain selection lines 649D by the drain trench 657. The drain selection line 649D may extend in the second direction D2 and the third direction D3 in a plane crossing the channel pillar 630 to surround the channel pillar 630.

[0115] During the etching process for forming the drain trench 657, a portion of the dummy channel pillar 630D may be etched. Figure 7C The second conductive pattern 649 shown in the figure sequentially etches the second insulating layer 635, the interlayer insulating layer 611 and the Figure 7C An etching process for forming the drain trench 657 is performed by etching at least one layer of the second conductive pattern 649. Therefore, the drain trench 657 may have a tapered shape that gradually narrows toward the first direction D1.

[0116] You can Figure 7C Some of the illustrated second conductive patterns 649 are defined as word lines 649W. The word lines 649W may not be penetrated by the drain trench 657 and may be disposed between the drain selection line 649D and the first conductive pattern 607 .

[0117] Some areas of the drain trench 657 may overlap with the dummy channel pillar 630D, and other areas may overlap with some areas of the word line 649W that are not penetrated by the dummy channel pillar 630D. Although not shown in the figure, Fig.7D The dummy channel pillar 630D shown may be adjacent to another dummy channel pillar in the third direction D3. Some areas of the word line 649W overlapping the drain trench 657 may be disposed between the dummy channel pillars adjacent to each other along the third direction D3. Figure 2 The arrangements of the dummy channel pillars DCH and the drain isolation insulating layer SD are shown to be the same.

[0118] Reference Fig. 7E , the drain isolation insulating layer 659 can be used to fill Fig.7D The drain trench 657 is shown. The drain isolation insulating layer 659 may have a Fig.7D The drain trench 657 is shown with the same tapered shape.

[0119] According to one embodiment of the present disclosure, when using Figure 7C The second conductive pattern 649 shown replaces Fig. 7AThe sacrificial layer 613 is then followed by a drain isolation insulating layer 659. Figure 7C The second conductive pattern 649 shown replaces Fig. 7A When the sacrificial layer 613 is formed, there will be no problem of blocking the inflow of etching materials or conductive materials caused by the drain isolation insulating layer 659. Therefore, according to one embodiment of the present disclosure, since the layout of the drain isolation insulating layer 659 can be designed without design restrictions on the inflow of etching materials or conductive materials, the design freedom of the drain isolation insulating layer 659 can be improved.

[0120] Subsequently, a third insulating layer 661 may be formed on the second insulating layer 635. Thereafter, a contact plug 663 may be formed to pass through the second insulating layer 635 and the third insulating layer 661 to overlap the channel pillar 630. The contact plug 663 may contact the capping pattern 627 of the channel pillar 630.

[0121] Subsequently, a bit line 665 may be formed. The bit line 665 may face the second end EP2A of each channel pillar 630. The bit line 665 may be formed on the third insulating layer 661 and may contact the contact plug 663. The bit line 665 may extend in a direction crossing the drain isolation insulating layer 659. In the present embodiment, the bit line 665 may extend in the second direction D2.

[0122] After forming the bit line 665, a first interconnect structure 668 and a first bonding metal pattern 669 may be formed. The first interconnect structure 668 and the first bonding metal pattern 669 may be buried in the first insulating structure 667. The first interconnect structure 668 may include conductive patterns of various shapes. The first bonding metal pattern 669 may be connected to the first interconnect structure 668. At least one of the first bonding metal patterns 669 may overlap with the bit line 665 and may be connected to the bit line 665 via the first interconnect structure 668.

[0123] Reference Figure 7F , a peripheral circuit structure 670 may be provided. The peripheral circuit structure 670 may include a substrate 671 including a transistor 675 , a second insulating structure 681 covering the substrate 671 , and a second interconnect structure 682 and a second bonding metal pattern 683 buried in the second insulating structure 681 .

[0124] The substrate 671 may be a semiconductor substrate such as a silicon substrate or a germanium substrate. The transistors 675 may be formed in an active region of the substrate 671 separated by the element isolation layer 673. Each of the transistors 675 may be configured to be connected to a reference Figure 3A Some of the transistors 675 may be included in the page buffer circuit 679 .

[0125] The second interconnect structure 682 may include conductive patterns of various shapes. The second bonding metal patterns 683 may be connected to the second interconnect structure 682. At least one of the second bonding metal patterns 683 may overlap with the page buffer circuit 679 and may be connected to the page buffer circuit 679 via the second interconnect structure 682.

[0126] The sacrificial substrate 601 may be aligned with the peripheral circuit structure 670 such that the first bonding metal pattern 669 faces the second bonding metal pattern 683 of the peripheral circuit structure 670. Thereafter, the first bonding metal pattern 669 and the second bonding metal pattern 683 may be bonded to each other.

[0127] Reference Figure 7G , you can remove Figure 7F The sacrificial substrate 601 is shown. When removing the sacrificial substrate 601, Figure 7F The protective layer 603 shown can protect the channel pillar 630 and the memory layer 621. Subsequently, the Figure 7F The protective layer 603 is shown to expose the first insulating layer 605 .

[0128] The memory layer 621 may be retained to cover a surface of each of the channel pillars 630 protruding beyond the first insulating layer 605 in the first direction, and the dummy memory layer 621D may be retained to cover a surface of the dummy channel pillars 630D protruding beyond the first insulating layer 605 in the first direction.

[0129] Reference Figure 7H , a second mask pattern 685 may be formed on the first insulating layer 605. Subsequently, a second insulating layer may be formed by an etching process using the second mask pattern 685 as an etching barrier layer. Figure 7G The first insulating layer 605 and Figure 7G The source trench 687 of the first conductive pattern 607 is shown. Therefore, Figure 7G The illustrated first conductive pattern 607 may be separated into source selection lines 607S by source trenches 687 .

[0130] The source selection line 607S may extend in the second direction D2 and the third direction D3 to surround the channel pillar 630. The source trench 687 may extend in the third direction D3 between the channel pillars 630. The source trench 687 may overlap the drain isolation insulating layer 659 and the word line 649W is interposed between the source trench 687 and the drain isolation insulating layer 659. The source trench 687 may overlap the dummy channel pillar 630D. During the etching process for forming the source trench 687, a portion of the dummy memory layer 621D and a portion of the dummy channel pillar 630D may be etched.

[0131] The etching may be performed in sequence in a direction opposite to the first direction D1. Figure 7G The first insulating layer 605 and Figure 7G The first conductive pattern 607 is shown to perform an etching process for forming the source trench 687. Therefore, the source trench 687 may have a tapered shape that gradually narrows toward a direction opposite to the first direction D1.

[0132] FIG. 8A to FIG. 8D It is shown in Figure 7H An enlarged cross-sectional view of a subsequent process following the illustrated process. FIG. 8A to FIG. 8D yes Figure 7H An enlarged cross-sectional view of region RA is shown.

[0133] Reference Fig. 8A , can be achieved by removing Figure 7H The second mask pattern 685 shown is used to expose the first insulating layer 605 and the memory layer 621. The memory layer 621 may include a first blocking insulating layer 621A, a data storage layer 621B, and a tunneling insulating layer 621C. The first blocking insulating layer 621A may include a silicon oxide layer, the data storage layer 621B may include a silicon nitride layer, and the tunneling insulating layer 621C may include a silicon oxide layer. The second blocking insulating layer 641 may include a material layer having a dielectric constant higher than that of the first blocking insulating layer 621A. In one embodiment, the second blocking insulating layer 641 may include an aluminum oxide layer.

[0134] Reference Figure 8B , the source isolation insulating layer 693 can be used to fill Fig. 8A A source trench 687 is shown. The source isolation insulating layer 693 may include an oxide layer.

[0135] Subsequently, a portion of the first blocking insulating layer 621A may be removed to expose the data storage layer 621B. At this time, a portion of the source isolation insulating layer 693 may be removed. A portion of the first blocking insulating layer 621A and a portion of the source isolation insulating layer 693 may be removed using an etch-back process.

[0136] Reference Figure 8C , the memory pattern 621ML may be defined by sequentially performing an etching process of selectively etching the data storage layer 621B and an etching process of selectively etching the tunnel insulating layer 621C. The channel layer 623 and the core insulating layer 625 of the channel pillar 630 may protrude beyond the memory pattern 621ML, and a surface of the channel layer 623 may be exposed at the protrusion of the channel pillar 630.

[0137] When etching the data storage layer 621B and the tunneling insulating layer 621C, a portion of the source isolation insulating layer 693 may be etched, but the first insulating layer 605 may remain to surround the channel pillar 630 .

[0138] Reference Fig.8D , a doped semiconductor pattern 695 in contact with the exposed surface of the channel layer 623 may be formed. The doped semiconductor pattern 695 may constitute a common source layer. The doped semiconductor pattern 695 may extend to overlap the source selection line 607S and the source isolation insulating layer 693. The doped semiconductor pattern 695 may be spaced apart from the source selection line 607S by the first insulating layer 605.

[0139] 9A to 9C is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0140] Reference Fig.9A , can be referenced by using FIG. 7A to FIG. 7C The described process forms a protective layer 703 , a first insulating layer 705 , and a preliminary structure 750 on a sacrificial substrate 701 .

[0141] The first conductive pattern 707 of the preliminary structure 750 may include silicon. The interlayer insulating layer 711 of the preliminary structure 750 and the second conductive pattern 749 may be alternately stacked on the first conductive pattern 707. The conductive material of the second conductive pattern 749 may include, for example, Fig. 10A Metal barrier layer 743 and metal layer 745 are shown.

[0142] Each of the channel pillars 730 of the preliminary structure 750 may have a tapered shape gradually narrowing toward the first direction D1 facing the sacrificial substrate 701 .

[0143] The interlayer insulating layer 711, the second conductive pattern 749, and the first conductive pattern 707 may be penetrated by a dummy channel pillar 730D having a shape similar to that of the channel pillar 730. The channel pillar 730 and the dummy channel pillar 730D may pass through the first insulating layer 705 and extend into the protection layer 703.

[0144] As reference Fig. 7A As described above, each of the channel pillars 730 may include a core insulating layer 725, a capping pattern 727, and a channel layer 723. Each of the channel pillars 730 may include a first end EP1B facing the first direction D1 and a second end EP2B facing the direction opposite to the first direction D1. The memory layer 721 may extend along the first end EP1B of the channel pillar 730 and the sidewall of the channel pillar 730. Fig. 10A As shown, the memory layer 721 may include a first blocking insulating layer 721A, a data storage layer 721B, and a tunnel insulating layer 721C.

[0145] The second blocking insulating layer 741 may be formed along a surface of each of the second conductive patterns 749 .

[0146] As reference Fig. 7A As described, the dummy channel pillar 730D may be surrounded by the dummy memory layer 721D, and may include a dummy channel layer 723D, a dummy core insulating layer 725D, and a dummy capping pattern 727D.

[0147] The second end EP2B of each of the channel pillars 730 and the dummy channel pillar 730D may be covered by the second insulating layer 735 .

[0148] The gate isolation insulating layer 753 separating the preliminary structure 750 may be disposed on the first conductive pattern 707 without passing through the first conductive pattern 707 .

[0149] Reference Fig. 9B After forming the gate isolation insulating layer 753, the gate isolation insulating layer 753 can be formed by referring to Fig.7D and Fig. 7E The process described above forms the drain isolation insulating layer 759 having a tapered shape that gradually narrows toward the first direction D1. The drain isolation insulating layer 759 may Fig.9A At least one layer of the second conductive pattern 749 is divided into a drain selection line 749D. The second conductive pattern divided into the drain selection line 749D is adjacent to the second end EP2B of the channel pillar 730. Among the second conductive patterns 749, the second conductive pattern between the drain isolation insulating layer 759 and the first conductive pattern 707 may be defined as a word line 749W.

[0150] Some regions of the drain isolation insulating layer 759 may overlap with the dummy channel pillar 730D, and other regions may overlap with some regions of the word line 749W that are not penetrated by the dummy channel pillar 730D.

[0151] Reference Fig. 9C , you can refer to Fig. 7E The described process forms a third insulating layer 761, a contact plug 763, a bit line 765, a first interconnect structure 768 and a first bonding metal pattern 769. Fig. 7E As described above, the first interconnection structure 768 and the first bonding metal pattern 769 may be buried in the first insulating structure 767 .

[0152] Subsequently, the second bonding metal pattern 783 of the peripheral circuit structure 770 can be Figure 7F The process described above is bonded to the first bonding metal pattern 769. Figure 7F As described above, the peripheral circuit structure 770 may include a substrate 771 having a transistor 775 , a second insulating structure 781 covering the substrate 771 , and a second interconnect structure 782 and a second bonding metal pattern 783 buried in the second insulating structure 781 .

[0153] Then, you can remove Fig. 9B The sacrificial substrate 701 and the protective layer 703 are shown. Therefore, the first insulating layer 705 can be exposed.

[0154] Thereafter, a mask pattern 785 may be formed on the first insulating layer 705. Subsequently, a through-hole may be formed by an etching process using the mask pattern 785 as an etching barrier. Fig. 9B The source trench 787 of the first insulating layer 705 and the first conductive pattern 707 is shown. Figure 7H As described above, the source trench 787 may have a tapered shape that gradually narrows in a direction opposite to the first direction D1.

[0155] Fig. 9B The first conductive pattern 707 shown may be separated into preliminary selection lines 707A by source trenches 787. The preliminary selection lines 707A may extend in the second direction D2 and the third direction D3 in a plane intersecting the channel pillars 730. The source trenches 787 may extend in the third direction D3 between the channel pillars 730. The source trenches 787 may overlap the dummy channel pillars 730D, the drain isolation insulating layer 759, and the gate isolation insulating layer 753.

[0156] FIG. 10A to FIG. 10C It is shown in Fig. 9C An enlarged cross-sectional view of a subsequent process following the illustrated process. FIG. 10A to FIG. 10C yes Fig. 9C An enlarged cross-sectional view of region RB is shown.

[0157] Reference Fig. 10A , can be achieved by removing Fig. 9C The mask pattern 785 shown is used to expose the first insulating layer 705 and the memory layer 721. Subsequently, a metal layer 789 may be formed on the sidewalls of the preliminary selection line 707A exposed by the source trench 787. The metal layer 789 may extend along the surface of the source trench 787. The metal layer 789 may extend along the surface of the first insulating layer 705 and the surface of the memory layer 721.

[0158] The metal layer 789 may include a conductive material capable of providing a metal silicide layer by reacting with the preliminary selection line 707A through a silicidation process performed at a temperature of 450° C. or less. In one implementation, the metal layer 789 may include nickel.

[0159] Reference Fig. 10B , by performing the silicidation process at 450°C or lower, Fig. 10A A portion of the preliminary selection line 707A is shown converted into a metal silicide layer. Thereafter, the remaining metal layer that has not reacted with the silicon layer may be removed. Fig. 10ASome areas of the preliminary selection line 707A shown in FIG. 7 may not be converted into a metal silicide layer, but may be retained as a silicon layer. The retained silicon layer may constitute a first selection pattern 707B. In addition, the metal silicide layer may constitute a second selection pattern 791 extending along the sidewall of the first selection pattern 707B.

[0160] The above process may define a source selection line 790SSL including a first selection pattern 707B and a second selection pattern 791. The second selection pattern 791 formed of a metal silicide layer may compensate for the resistance of the first selection pattern 707B formed of a silicon layer, thereby reducing the resistance of the source selection line 790SSL.

[0161] In high temperature processes exceeding 450°C, Fig. 9C Defects may occur in the first bonding metal pattern 769 and the second bonding metal pattern 783 shown. Since the silicidation process according to one embodiment of the present disclosure is performed at a low temperature of 450° C. or lower, according to this embodiment of the present disclosure, Fig. 9C In the first bonding metal pattern 769 and the second bonding metal pattern 783 shown, the occurrence of defects due to high temperature can be reduced.

[0162] Reference Fig. 10C , you can use the reference Figure 8B The process described utilizes a source isolation insulating layer 793 to fill Fig. 10B Source trench 787 is shown.

[0163] Then, as referenced Figure 8B and Figure 8C As described above, the memory pattern 721M may be defined by sequentially performing an etching process of the first blocking insulating layer 721A, an etching process of the data storage layer 721B, and an etching process of the tunnel insulating layer 721C. The channel layer 723 and the core insulating layer 725 of the channel pillar 730 may protrude beyond the memory pattern 721ML, and a surface of the channel layer 723 may be exposed at the protrusion of the channel pillar 730.

[0164] Thereafter, a doped semiconductor pattern 795 contacting a surface of the exposed channel layer 723 may be formed.

[0165] FIG. 11A to FIG. 11D is an enlarged cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0166] In execution FIG. 11A to FIG. 11D Before the process shown, you can refer to 9A to 9C Thus, a preliminary selection line 707S' divided by the source trench 787' can be formed.

[0167] The preliminary selection line 707S' may overlap with the stack of the conductive pattern 749' and the interlayer insulating layer 711'. The conductive pattern 749', the interlayer insulating layer 711' and the preliminary selection line 707S' may surround the channel pillar 730'. The channel pillar 730' may have a tapered shape that gradually narrows toward the first direction D1. The channel pillar 730' may include a core insulating layer 725' and a channel layer 723'. The sidewall of each of the channel pillars 730' may be surrounded by the memory layer 721'.

[0168] The memory layer 721' may extend to cover the first end EP1C of each channel pillar 730' facing the first direction D1. The memory layer 721' may include a first blocking insulating layer 721A', a data storage layer 721B', and a tunnel insulating layer 721C'.

[0169] The preliminary selection line 707S' may be disposed closer to the first end EP1C of the channel pillar 730' than the conductive pattern 749'. Each of the preliminary selection lines 707S' may be formed of a silicon layer.

[0170] The conductive pattern 749' may include a metal barrier layer 743' and a metal layer 745'. The second blocking insulating layer 741' may be disposed between the conductive pattern 749' and the memory layer 721'. The second blocking insulating layer 741' may extend between the conductive pattern 749' and the interlayer insulating layer 711'.

[0171] The source trench 787' may extend to pass through the first insulating layer 705'. A portion of each of the preliminary selection lines 707' may be etched through the source trench 787'. Thus, a recess 788' may be defined between the first insulating layer 705' and the interlayer insulating layer 711'.

[0172] The mask pattern 785' may be used as an etch barrier during an etching process for forming the source trench 787'. The mask pattern 785' may protect the memory layer 721' and the channel pillar 730' during an etching process for forming the recess 788'.

[0173] Reference Fig. 11B , can be filled with conductive layer 789' Fig.11A. The conductive layer 789' may include various conductive materials that may be deposited in a process at 450°C or lower. In one embodiment, the conductive layer 789' may include various conductive materials deposited by a physical vapor deposition (PVD) method or an atomic layer deposition method. The conductive layer 789' may include a metal layer 789B and a metal barrier layer 789A located between the metal layer 789B and the preliminary selection line 707S'. The metal barrier layer 789A may contact the sidewalls of the preliminary selection line 707S'. The metal layer 789B and the metal barrier layer 789A may compensate for the resistance of the preliminary selection line 707S' formed by the silicon layer.

[0174] Since the conductive layer 789' for compensating the resistance of the silicon layer is formed at a low temperature of 450°C or lower, according to one embodiment of the present disclosure, Fig. 9C In the first bonding metal pattern 769 and the second bonding metal pattern 783 shown, the occurrence of defects due to high temperature can be reduced.

[0175] Reference Fig. 11C , the metal layer 789B and the metal barrier layer 789A in the source trench 787' may be removed by an etching process such as etch back. Thus, a source selection line 790SSL' including a sidewall conductive pattern 789P and a preliminary selection line 707S' may be defined. The sidewall conductive pattern 789P may remain on the sidewall of the preliminary selection line 707S'.

[0176] Reference Fig.11D , by using the reference Figure 8B The process described above can be filled with a source isolation insulating layer 793'. Fig. 11C Source trench 787' is shown.

[0177] Then, as referenced Figure 8B and Figure 8C As described above, the memory pattern 721ML' may be defined by sequentially performing an etching process of the first blocking insulating layer 721A', an etching process of the data storage layer 721B', and an etching process of the tunnel insulating layer 721C'. In addition, the channel layer 723' and the core insulating layer 725' of the channel pillar 730' may protrude beyond the memory pattern 721ML', and a surface of the channel layer 723' may be exposed at the protrusion of the channel pillar 730'.

[0178] Thereafter, a doped semiconductor pattern 795 ′ contacting the exposed surface of the channel layer 723 ′ may be formed.

[0179] FIG. 12A to FIG. 12D is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0180] Reference Fig. 12A After forming the first insulating layer 805 on the sacrificial substrate 801 , sacrificial layers 813 and interlayer insulating layers 811 may be alternately stacked on the first insulating layer 805 .

[0181] The first insulating layer 805 may include a silicon oxide layer. The sacrificial layer 813 may include a silicon nitride layer. The interlayer insulating layer 811 may include a silicon oxide layer.

[0182] You can use reference Fig. 7A The channel pillar 830 may be formed by the process described above. When forming the channel pillar 830, a dummy channel pillar 830D may be formed. The channel pillar 830 and the dummy channel pillar 830D may extend into the sacrificial substrate 801.

[0183] Each of the channel pillars 830 may include a first end EP1D and a second end EP2D facing opposite directions. The first end EP1D may face the first direction D1. The sidewall of the channel pillar 830 may be surrounded by the memory layer 821. The memory layer 821 may extend between the first end EP1D and the sacrificial substrate 801. The channel pillar 830 may include a channel layer 823, a core insulating layer 825, and a capping pattern 827. The channel pillar 830 may have a tapered shape that gradually narrows toward the first end EP1D. The memory layer 821 may include Fig.13A The first blocking insulating layer 821A, the data storage layer 821B and the tunneling insulating layer 821C are shown.

[0184] The dummy channel pillar 830D may be surrounded by the dummy memory layer 821D. The dummy channel pillar 830D may include a dummy channel layer 823D, a dummy core insulation layer 825D, and a dummy capping pattern 827D.

[0185] The channel pillar 830 and the dummy channel pillar 830D may be covered by a second insulating layer 835 .

[0186] The second insulating layer 835 , the interlayer insulating layer 811 , the sacrificial layer 813 , and the first insulating layer 805 may be penetrated by the slit 837 .

[0187] Reference Fig. 12B , can be replaced by the conductive pattern 849 through the slit 837 Fig. 12A The sacrificial layer 813 shown in FIG. 840 and the conductive pattern 849 may be formed of the same conductive material. Fig.13A As shown, each of the conductive patterns 849 may include a metal barrier layer 843 and a metal layer 845. Before forming the conductive patterns 849, Fig. 12A A second blocking insulating layer 841 is formed on the surface of each of the regions where the sacrificial layer 813 is removed as shown.

[0188] Through the above reference Fig. 12A and Fig. 12B Through the described process, a preliminary structure 850 may be formed, which includes a channel pillar 830 having a tapered shape, and a conductive pattern 849 and an interlayer insulating layer 811 surrounding the channel pillar 830 and alternately stacked on the first insulating layer 805 .

[0189] Reference Fig. 12C , the gate isolation insulating layer 853 can be used to fill Fig. 12B The slit 837 shown. Subsequently, a Fig. 12B At least one of the conductive patterns 849 is a drain isolation insulating layer 859. The conductive pattern penetrated by the drain isolation insulating layer 859 is adjacent to the second end EP2D of the channel pillar 830.

[0190] The conductive pattern adjacent to the second end EP2D may be separated into a drain selection line 849D by a drain isolation insulating layer 859. The drain selection line 849D may extend in the second direction D2 and the third direction D3 in a plane intersecting the channel pillar 830 to surround the channel pillar 830. The drain isolation insulating layer 859 may extend in the third direction D3 between the channel pillars 830. The drain isolation insulating layer 859 may have a tapered shape that gradually narrows toward the first direction D1.

[0191] The drain isolation insulating layer 859 may include a region overlapping with the dummy channel pillar 830D and a region not overlapping with the dummy channel pillar 830D.

[0192] Reference Fig.12D , you can use the reference Fig. 7E The described process forms a third insulating layer 861, a contact plug 863, a bit line 865, a first interconnect structure 868 and a first bonding metal pattern 869. Fig. 7E As described above, the first interconnection structure 868 and the first bonding metal pattern 869 may be buried in the first insulating structure 867 .

[0193] Then, by referring to Figure 7F The described process bonds the second bonding metal pattern 883 of the peripheral circuit structure 870 to the first bonding metal pattern 869. Figure 7F As described above, the peripheral circuit structure 870 may include a substrate 871 having a transistor 875 , a second insulating structure 881 covering the substrate 871 , and a second interconnection structure 882 and a second bonding metal pattern 883 buried in the second insulating structure 881 .

[0194] Then, you can remove Fig. 12C The sacrificial substrate 801 is shown. Therefore, the first insulating layer 805 can be exposed.

[0195] Thereafter, a mask pattern 885 may be formed on the first insulating layer 805. Subsequently, a source trench 887 may be formed by an etching process using the mask pattern 885 as an etching barrier. The source trench 887 may pass through Fig. 12C At least one layer of the conductive pattern 849 shown. The conductive pattern through which the source trench 887 penetrates is adjacent to the first end EP1D of the channel pillar 830. Figure 7H As described above, the source trench 887 may have a tapered shape that gradually narrows toward a direction opposite to the first direction D1.

[0196] The conductive pattern penetrated by the source trench 887 may be separated into source selection lines 849S. The source selection lines 849S may extend in the second direction D2 and the third direction D3 to surround the channel pillars 830. The source trench 887 may extend in the third direction D3 between the channel pillars 830. The source trench 887 may overlap the drain isolation insulating layer 859.

[0197] Fig.13A and Fig. 13B It is shown in Fig.12D An enlarged cross-sectional view of a subsequent process following the illustrated process. Fig.13A and Fig. 13B yes Fig.12D An enlarged cross-sectional view of region RC is shown.

[0198] Reference Fig.13A , can be achieved by removing Fig.12D The mask pattern 885 shown is used to expose the first insulating layer 805. Subsequently, the source trench 887 can be filled with a source isolation insulating layer 893. Figure 8B As described above, in the process for forming the source isolation insulating layer 893, the first blocking insulating layer 821A may be etched, and the data storage layer 821B may be exposed.

[0199] The source isolation insulating layer 893 may electrically insulate adjacent source selection lines 849S at the same level. The source isolation insulating layer 893 may overlap some regions of the word line 849W overlapping the source trench 887 .

[0200] Reference Fig. 13B , as referenced Figure 8C As described above, the memory pattern 821ML may be defined by sequentially performing an etching process of the data storage layer 821B and an etching process of the tunnel insulation layer 821C. The channel layer 823 and the core insulation layer 825 of the channel pillar 830 may protrude beyond the memory pattern 821ML, and a surface of the channel layer 823 may be exposed at the protrusion of the channel pillar 830.

[0201] Thereafter, a doped semiconductor pattern 895 contacting the exposed surface of the channel layer 823 may be formed.

[0202] According to one embodiment of the present disclosure, the source isolation insulating layer 893 is formed by using Fig. 12B The conductive pattern 849 shown replaces Fig. 12A Therefore, the embodiment of the present disclosure can design the layout of the source isolation insulating layer 893, and in order to utilize Fig. 12B The conductive pattern 849 shown replaces Fig. 12A The sacrificial layer 813 shown has no design restrictions on the flow of etching materials or conductive materials. Therefore, according to one embodiment of the present disclosure, the design freedom of the source isolation insulating layer 893 can be improved.

[0203] Fig.14 is a block diagram showing a configuration of a memory system 1100 according to one embodiment of the present disclosure.

[0204] Reference Fig.14 , the memory system 1100 may include a memory device 1120 and a memory controller 1110 .

[0205] The memory device 1120 may include a channel pillar having a tapered shape, a source isolation insulating layer having a tapered shape opposite to that of the channel pillar, and source selection lines surrounding the channel pillar and separated from each other at the same level. The source isolation insulating layer may be disposed between the source selection lines.

[0206] The memory device 1120 may be a multi-chip package composed of a plurality of flash memory chips.

[0207] The memory controller 1110 may be configured to control the memory device 1120. The memory controller 1110 may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 may be used as an operation memory of the CPU 1112, the CPU 1112 may perform an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 may include a data exchange protocol of a host connected to the memory system 1100. In addition, the error correction block 1114 may detect and correct errors included in data read from the memory device 1120. The memory interface 1115 may perform an interface connection with the memory device 1120. In addition, the memory controller 1110 may further include a read-only memory (ROM) or the like for storing code data for interfacing with the host.

[0208] Fig.151 is a block diagram showing a configuration of a computing system 1200 according to one embodiment of the present disclosure.

[0209] Reference Fig.15 , the computing system 1200 may include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0210] The memory system 1210 may include a memory device 1212 and a memory controller 1211. The memory device 1212 may include a channel pillar having a tapered shape, a source isolation insulating layer having a tapered shape opposite to the tapered shape of the channel pillar, and source selection lines surrounding the channel pillar and separated from each other at the same level. The source isolation insulating layer may be provided between the source selection lines.

[0211] According to the present disclosure, since the source isolation insulating layer disposed between the channel pillars gradually narrows in a direction opposite to the channel pillars, an alignment margin of the source isolation insulating layer between the channel pillars may be improved.

[0212] CROSS-REFERENCE TO RELATED APPLICATIONS

[0213] This application claims the priority of Korean Patent Application No. 10-2020-0116060 filed on September 10, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: A gate stack, the gate stack comprising interlayer insulating layers and word lines alternately stacked in a first direction; A channel pillar, the channel pillar passes through the gate stack and gradually narrows toward the first direction; a source selection line surrounding the channel pillar and extending to overlap the gate stack; as well as A source isolation insulating layer overlaps the gate stack between the source selection lines and gradually narrows toward a direction opposite to the first direction.

2. The semiconductor memory device according to claim 1, wherein The gate stack further comprises: drain select lines, the drain select lines respectively overlapping the source select lines and the word lines being interposed between the drain select lines and the source select lines; and A drain isolation insulating layer is disposed between the drain selection lines and gradually narrows toward the first direction.

3. The semiconductor memory device according to claim 2, wherein: The source isolation insulating layer overlaps the drain isolation insulating layer.

4. The semiconductor memory device according to claim 2, wherein: The channel pillar comprises a first channel pillar and a second channel pillar, The drain selection line includes a first drain selection line surrounding the first channel pillar and a second drain selection line surrounding the second channel pillar, wherein the second drain selection line is separated from the first drain selection line by the drain isolation insulating layer, and The source selection lines include a first source selection line surrounding the first channel pillar and a second source selection line surrounding the second channel pillar, wherein the second source selection line is spaced apart from the first source selection line by the source isolation insulating layer.

5. The semiconductor memory device according to claim 1, wherein: Each of the source select lines comprises silicon.

6. The semiconductor memory device according to claim 1, wherein: Each of the source selection lines comprises: a silicon layer; and A metal silicide layer is in contact with the silicon layer, and the metal silicide layer is located between the silicon layer and the source isolation insulating layer.

7. The semiconductor memory device according to claim 1, wherein: Each of the source selection lines includes a silicon layer and a sidewall conductive pattern disposed between the silicon layer and the source isolation insulating layer, and The sidewall conductive pattern includes a metal barrier layer contacting the silicon layer and a metal layer disposed between the metal barrier layer and the source isolation insulating layer.

8. The semiconductor memory device according to claim 1, wherein: The source select line and the word line include the same conductive material.

9. The semiconductor memory device according to claim 8, wherein: Each of the source selection lines includes at least two layers of conductive patterns stacked apart from each other in the first direction.

10. The semiconductor memory device according to claim 1, further comprising: a common source layer, the common source layer being in contact with the channel pillar, wherein the common source layer overlaps the gate stack and the source selection line is interposed between the common source layer and the gate stack; a bit line connected to the channel pillar, wherein the bit line overlaps the common source layer and the gate stack is interposed between the bit line and the common source layer; and A peripheral circuit structure overlaps the gate stack and the bit line is interposed between the peripheral circuit structure and the gate stack.

11. A method for manufacturing a semiconductor memory device, the method comprising: forming a preliminary structure including channel pillars, an interlayer insulating layer, and a conductive pattern, wherein each of the channel pillars gradually narrows toward a first end facing a first direction, and wherein the interlayer insulating layer and the conductive pattern surround the channel pillars and are alternately stacked in the first direction; forming a groove that passes through a first conductive pattern among the conductive patterns and gradually narrows in a direction opposite to the first direction, wherein the first conductive pattern is adjacent to the first end of each of the channel pillars; and A source isolation insulating layer filling the trench is formed.

12. The method according to claim 11, wherein: The conductive pattern comprises: metal layers, the metal layers being spaced apart from each other in the first direction by the interlayer insulating layer; and A silicon layer is spaced apart from the metal layer in the first direction, wherein the trench passes through the silicon layer.

13. The method according to claim 12, further comprising the steps of: A silicidation process of converting a portion of the silicon layer into a metal silicide layer is performed at a temperature of 450° C. or less through the trench.

14. The method according to claim 12, further comprising the steps of: etching a portion of the silicon layer through the trench; and forming a sidewall conductive pattern filling the region where the silicon layer is etched at a temperature of 450° C. or lower, The sidewall conductive pattern includes a metal barrier layer in contact with the silicon layer and a metal layer arranged between the metal barrier layer and the source isolation insulating layer.

15. The method according to claim 11, wherein: The conductive patterns each include the same conductive material.

16. The method according to claim 11, further comprising the steps of: Before forming the trench, forming a drain isolation insulating layer that passes through a second conductive pattern among the conductive patterns and gradually narrows toward the first direction, The second conductive pattern is adjacent to a second end of each of the channel pillars, and the second end faces a direction opposite to the first end of each of the channel pillars.

17. The method according to claim 16, wherein: The conductive pattern includes a word line disposed between the first conductive pattern and the second conductive pattern, and The source isolation insulating layer overlaps the drain isolation insulating layer and the word line is interposed between the source isolation insulating layer and the drain isolation insulating layer.

18. The method according to claim 11, further comprising: Before forming the trench, forming a bit line facing a second end of each of the channel pillars and connected to the channel pillars, wherein the second end of each of the channel pillars faces in a direction opposite to the first end of each of the channel pillars; forming a first bonding metal pattern overlapping the bit line; forming a peripheral circuit structure including a substrate having a page buffer circuit and a second bonding metal pattern overlapping the page buffer circuit; and The first bonding metal pattern and the second bonding metal pattern are bonded to each other.

19. The method according to claim 18, wherein: forming the preliminary structure on a sacrificial substrate, and After bonding the first bonding metal pattern and the second bonding metal pattern to each other and before forming the trench, the sacrificial substrate is removed.

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