Micro LED transfer method and Micro LED panel

Abstract

The present invention provides a Micro LED transfer method and a Micro LED panel. The Micro LED transfer method may include the following steps: an electrode array is provided on a first substrate; a conductive layer is formed above a portion of the electrodes; an isolation layer is deposited on the first substrate and the surface of the conductive layer is exposed; a buffer layer is deposited on the isolation layer and a through hole is opened at a portion of the corresponding conductive layer, the width of the through hole is greater than the width of the conductive layer; a first bonding layer is deposited on the surface of the conductive layer; and a plurality of Micro LED chips and a second bonding layer are sequentially arranged on a side surface of the second substrate, the second bonding layer is bonded to the first bonding layer; the width of the through hole is greater than or equal to the width of the Micro LED chip, and the height of the through hole is greater than or equal to the height of the bonding layer formed by the first bonding layer and the second bonding layer.

Description

Technical Field

[0001] The present invention relates to the technical field of micro light emitting diodes, and in particular to a mass transfer method of micro light emitting diodes (MicroLEDs). Background Art

[0002] Compared to light emitting diodes (LEDs), micro-LEDs (also called mLEDs, μLEDs or micro-LEDs) are a new type of self-luminous display technology, with LEDs at the micron level in size. Micro LED displays have the characteristics of self-luminescence, high efficiency, low power consumption, and high stability. They are an important choice for the new generation of mainstream display technology and have the potential to replace existing technologies in many fields. Currently, one of the main and potential markets for Micro LEDs is the high-resolution home consumer electronics market.

[0003] According to the different application scenarios of different types of product terminals, Micro LED can directly produce high-resolution display screens on substrates such as Si, GaN, Sapphire (sapphire) for small-sized wearable displays (such as smart bracelets), VR / AR near-eye displays and other products. Micro LED chips can also be assembled on larger substrates with logic circuits through mass transfer after being produced on the substrate, thus meeting the needs of larger display screen application scenarios such as mobile phone and tablet computer displays and TV displays. There are many problems to be solved in the commercial application or mass production of Micro LED, and mass transfer technology is the most critical link.

[0004] Mass transfer refers to the transfer of micron-scale LED crystals to the driving circuit substrate after chip manufacturing is completed. Whether it is a TV screen or a mobile phone screen, the transfer quantity is quite huge, and the display product has a very low tolerance for pixel errors. At present, the mainstream Micro LED mass transfer technologies mainly include electrostatic force adsorption transfer, fluid assembly transfer technology, elastic mold transfer technology, selective release transfer technology (such as laser transfer, laser-assisted transfer), roller transfer transfer technology, etc. The transfer efficiency, transfer accuracy, transfer success rate, bonding technology, etc. in the mass transfer process deeply affect the manufacturing cost, production efficiency, production yield, and the popularity and promotion time of commercial applications of Micro LED display screens. In the combination technology of Micro LED mass transfer, when metal bonding is used, there is a gap between the metal usage assessment and the actual amount, or the bonding alignment deviation is too large during bonding, resulting in the metal bonding layer overflowing the hole range for bonding, causing bonding abnormalities and other undesirable phenomena. Summary of the invention

[0005] In order to solve the problem of improving the transfer success rate in Micro LED mass transfer, the present invention provides a Micro LED transfer method and a corresponding Micro LED panel.

[0006] To achieve at least one of the above advantages or other advantages, an embodiment of the present invention provides a Micro LED transfer method, which at least includes the following steps:

[0007] Providing a first substrate, on which an electrode array is disposed;

[0008] forming a conductive layer on a portion of the electrodes in the first substrate;

[0009] Depositing an isolation layer on the conductive first substrate and exposing the surface of the conductive layer;

[0010] Depositing a buffer layer on the isolation layer, wherein at least a portion of the buffer layer corresponding to the conductive layer is provided with a through hole, and a width of the through hole is greater than a width of the conductive layer;

[0011] depositing a first bonding layer on the surface of the conductive layer; and

[0012] Providing a second substrate, wherein a plurality of the Micro LED chips are disposed on one side surface of the second substrate, and a second bonding layer is disposed on a side surface of each Micro LED chip away from the second substrate, wherein the second bonding layer is bonded to the first bonding layer;

[0013] The width of the through hole is greater than or equal to the width of the Micro LED chip, and the height of the through hole is greater than or equal to the height of a bonding layer formed after the first bonding layer and the second bonding layer are bonded.

[0014] In some embodiments, forming an isolation layer, a buffer layer and a first bonding layer on the first substrate includes the following steps:

[0015] Depositing a flat isolation layer on the first substrate, wherein the isolation layer completely covers the conductive layer;

[0016] Using chemical mechanical polishing (CMP) to reduce the thickness of the isolation layer until the surface of the conductive layer is exposed;

[0017] Depositing a buffer layer on the surfaces of the isolation layer and the conductive layer, wherein a through hole is provided in at least a portion of the buffer layer corresponding to the conductive layer to expose the surface of the conductive layer, and the width of the through hole is greater than the width of the conductive layer;

[0018] The first bonding layer is deposited on the surface of the conductive layer, wherein the width of the first bonding layer is greater than or equal to the width of the conductive layer, and the width of the first bonding layer is less than or equal to the width of the through hole.

[0019] Furthermore, in some embodiments, the thickness of the buffer layer is greater than 1 μm, which can ensure that the flowing metal liquid can be completely retained in the preset holes when the first bonding layer and the second bonding layer are metal-bonded, without overflowing. The buffer layer is an elastic organic photoresist material, which can ensure that there is enough buffer space during eutectic bonding to avoid damage to the substrate or LED device due to pressure during the bonding process.

[0020] In some embodiments, forming the isolation layer, the buffer layer and the first bonding layer on the first substrate includes the following steps:

[0021] Depositing a flat isolation layer on the conductive first substrate, wherein the isolation layer completely covers the conductive layer;

[0022] An opening is formed in the isolation layer at least partially corresponding to the conductive layer to expose the surface of the conductive layer, and the width of the opening is less than or equal to the width of the conductive layer;

[0023] Depositing the first bonding layer on the surface of the conductive layer, wherein the width of the first bonding layer is less than or equal to the width of the conductive layer and less than or equal to the width of the opening;

[0024] A buffer layer is deposited on the isolation layer and the first bonding layer, and a through hole is opened in the buffer layer corresponding to the first bonding layer and the conductive layer, wherein the width of the through hole is greater than the width of the conductive layer.

[0025] Furthermore, in some embodiments, the isolation layer is an organic photoresist material with elasticity; and the buffer layer is an organic photoresist layer.

[0026] In some embodiments, the first substrate is at least one of a driving substrate, a glass substrate, a Si substrate, a PI substrate, and a display backplane.

[0027] In some embodiments, the conductive layer is one or more combinations of gold, tin, nickel, titanium, aluminum, silver, indium, or an alloy composed of metal materials.

[0028] In some embodiments, the buffer layer is one of an insulating layer, an organic photoresist layer, and a passivation layer.

[0029] In some embodiments, the first bonding layer and the second bonding layer are respectively one or more of gold, tin, nickel, titanium, aluminum, silver, indium, or alloys of metal materials.

[0030] In some embodiments, the bonding method between the first bonding layer and the second bonding layer is one or more of alloy eutectic bonding, diffusion bonding, and transient liquid phase bonding.

[0031] In some embodiments, the second bonding layer and the first bonding layer are bonded together by using a laser heating method to melt the metal in the second bonding layer and the first bonding layer, and then continuously pressing them together to form a metal bonding layer.

[0032] In order to achieve at least one of the above advantages or other advantages, an embodiment of the present invention provides a Micro LED panel, which can be manufactured by the Micro LED transfer method as described above. The Micro LED panel at least includes:

[0033] a first substrate, on which an electrode array is provided;

[0034] A plurality of conductive layers, disposed on the first substrate and covering at least a portion of the electrode array;

[0035] An isolation layer, disposed on the first substrate and separating the plurality of conductive layers;

[0036] a buffer layer, disposed on the isolation layer, wherein the buffer layer is provided with a through hole at a position corresponding to the conductive layer; and

[0037] A bonding layer, at least partially located in the through hole, wherein the Micro LED chip is connected to the conductive layer via the bonding layer;

[0038] Among them, the width of the through hole is greater than or equal to the width of the Micro LED chip, and the height or thickness of the through hole is greater than or equal to the height or thickness of the bonding layer.

[0039] In some embodiments, the isolation layer is an insulating layer, and the thickness of the isolation layer is greater than or equal to the thickness of the conductive layer.

[0040] In some embodiments, the buffer layer is one of an insulating layer, an organic photoresist layer, and a passivation layer.

[0041] In some embodiments, the width of the bonding layer is smaller than and / or larger than the width of the conductive layer.

[0042] Compared with the prior art, the Micro LED transfer method provided by the present invention and the Micro LED panel manufactured according to the method have at least the following advantages:

[0043] 1. When the Micro LED chip is bonded during the transfer process, the corresponding bonding layer can be bonded more accurately, and the alloy metal of the bonding layer after bonding will not overflow from the holes or cavity areas defined during bonding, causing waste of the alloy metal of the bonding layer.

[0044] 2. After bonding, the Micro LED chip is at least partially located in the hole area defined during bonding, making the bonding of the Micro LED chip more stable. At the same time, the amount of alloy metal required for the bonding layer during bonding can be effectively controlled according to actual needs, saving or controlling manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 Schematic diagram of the process of the Micro LED transfer method of the present invention;

[0047] Figure 2 for Figure 1 A schematic diagram of a process of a first embodiment of a Micro LED transfer method is shown;

[0048] Figure 3a to Figure 3h for Figure 2 The process diagram corresponding to the process shown, and Figure 3h A cross-sectional schematic diagram of a first embodiment of a Micro LED panel in the present invention;

[0049] Figure 4 for Figure 1 A schematic diagram of a second embodiment of a Micro LED transfer method; and

[0050] Figure 5a to Figure 5h for Figure 4 The process diagram corresponding to the process shown, and Figure 5h A cross-sectional schematic diagram of a second embodiment of a Micro LED panel in the present invention.

[0051] Reference numerals:

[0052] 1-Micro LED panel 10-first substrate 11-electrode

[0053] 20-conductive layer 30-isolation layer 31-opening

[0054] 40- buffer layer 41- through hole 50- bonding layer

[0055] 51-first bonding layer 52-second bonding layer 60-Micro LED chip

[0056] 70 - second substrate H1, H2 - height L1, L2, L3, L4, L5 - width DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] In the description of the present invention, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variation thereof all mean "at least including".

[0059] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integrally formed connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] The terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "one", "one" and "item" used herein are also intended to include plural numbers. It should also be understood that the terms "include" and / or "comprise" used herein specify the existence of stated features, integers, steps, operations, units and / or components, without excluding the existence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0061] See also Figure 1 , Figure 1 Schematic diagram of the process of the Micro LED transfer method of the present invention. To achieve at least one of the above advantages or other advantages, an embodiment of the present invention provides a Micro LED transfer method, which may include at least the following steps:

[0062] Step (S01): Provide a first substrate, on which an electrode array is disposed. A surface of at least some of the electrodes in the electrode array is flush with a surface of the first substrate. It can be understood that a surface of some of the electrodes is exposed on the same side of the first substrate.

[0063] The first substrate may be a driving substrate, a glass substrate, a Si substrate, a PI substrate, a display backplane, etc., but is not limited thereto. In some embodiments, the first substrate may also be a self-carrier substrate, an intermediate substrate, a carrier substrate, etc.

[0064] Here, the first substrate is explained and illustrated as a Si driving backplane. At least three electrode arrays are arranged on the Si driving backplane, wherein one surface of two electrodes is exposed to one side of the Si driving backplane.

[0065] Step (S02): forming a conductive metal layer on the first substrate and forming a conductive layer on part of the electrode. It is further explained that the conductive layer is formed on the surface of the electrode exposed to the first substrate. The material of the conductive layer can be one or more combinations of gold, tin, nickel, titanium, aluminum, silver, indium or an alloy composed of metal materials. That is, the conductive layer can be pure metal or metal alloy.

[0066] Specifically, a photoresist (or photoresist) is coated on one side of the exposed electrode surface in the Si driving backplane. Exposure and development are performed to form a conductive metal pattern on the exposed electrode surface. A conductive metal layer is deposited on the photoresist. The photoresist and the conductive metal layer in unnecessary areas are removed at the same time, and conductive metal is formed only on the exposed electrode surface. When at least three electrode arrays are provided on the Si driving backplane, the conductive layer is correspondingly formed on one surface of two electrodes.

[0067] Step (S03): depositing an isolation layer on the conductive metal layer to separate and protect the formed conductive layers. At the same time, the surface of each conductive layer is exposed in the isolation layer. The isolation layer can be an insulating layer, a buffer insulating layer, etc.

[0068] Step (S04): depositing a buffer layer on the isolation layer. The buffer layer may be one of an insulating layer, an organic photoresist layer, and a passivation layer. The buffer layer is provided with through holes at least at the locations corresponding to the conductive layers. The through holes may be used as bonding activity spaces or activity areas required for transfer bonding of the Micro LED chip. The width of each through hole is greater than the width of each conductive layer. With such a configuration, the Micro LED chip can achieve effective electrical connection with the conductive layer via the bonding layer after bonding.

[0069] Step (S05): depositing a first bonding layer on the surface of the conductive layer. The first bonding layer can be used as a connecting layer of the first substrate in the transfer bonding of the Micro LED chip. The material of the first bonding layer can be one or more of gold, tin, nickel, titanium, aluminum, silver, indium, or an alloy composed of metal materials.

[0070] Step (S06): Provide a second substrate, on one side of which a plurality of Micro LED chips are arranged. The Micro LED chips are arranged in an array on the second substrate. The width of the through hole is greater than or equal to the width of the Micro LED chip. Each of the Micro LED chips is provided with a second bonding layer on a side surface away from the second substrate. The material of the second bonding layer can be one or more of gold, tin, nickel, titanium, aluminum, silver, indium, or an alloy composed of metal materials.

[0071] When the Micro LED chips are transferred to the first substrate, the second bonding layer is bonded to the first bonding layer. The height of the through hole is greater than or equal to the height of the bonding layer formed after the first bonding layer and the second bonding layer are bonded. The bonding method of the first bonding layer and the second bonding layer can be one or more of alloy eutectic bonding, diffusion bonding, and transient liquid phase bonding.

[0072] In one embodiment, the second substrate may be an original substrate, a growth substrate, a base substrate, etc. A plurality of the Micro LED chips may be flip-chip mounted on the second substrate in an array.

[0073] Please combine Figure 1 See also Figure 2 and Figure 3a to Figure 3h , Figure 2 for Figure 1 The schematic diagram of the process of the first embodiment of the Micro LED transfer method is shown in FIG. Figure 3a to Figure 3h for Figure 2 The specific process steps of the first embodiment of the MicroLED transfer method shown in these figures are described as follows.

[0074] like Figure 3a As shown, see Figure 1 Step (S01) provides a first substrate 10, on which an array of electrodes 11 is disposed. In the figure, the first substrate 10 is a Si driving backplane. The Si driving backplane 10 is provided with at least three arrays of electrodes 11, wherein the upper surfaces of two electrodes 11 are exposed on the same side of the Si driving backplane 10, which is the upper surface of the first substrate 10 in the example shown.

[0075] like Figure 3b As shown, see Figure 1 Step ( S02 ) forms a conductive metal layer on the first substrate 10 , and forms a conductive layer 20 on a portion of the electrode 11 . To further explain, the conductive layer 20 is formed on the surface of the electrode 11 exposed to the first substrate 10 .

[0076] Specifically, in Figure 3a The upper surface of the Si driving backplane 10 is coated with a photoresist (or photoresist) layer, and the photoresist layer covers the upper surface of a portion of the electrode 11 in the Si driving backplane 10. Exposure and development are performed on the photoresist layer to form a conductive metal pattern on the upper surface of the portion of the electrode 11. Then, a conductive metal layer is deposited on the photoresist layer. It can be understood that the conductive metal layer covers the photoresist layer and the conductive metal pattern. The photoresist layer is removed and the conductive metal layer in the unnecessary area is removed at the same time, and finally a conductive layer 20 is formed only on the upper surface of the portion of the electrode 11. As shown in FIG. Figure 3b As shown, a conductive layer 20 is formed on the upper surface of at least two electrodes 11 in the array of three electrodes 11 on the Si driving backplane 10. The conductive layer 20 is a pure metal or alloy with conductive properties.

[0077] like Figure 3c As shown, see Figure 1 Step (S03), Figure 2 Step (S11), depositing a flat isolation layer 30 on the Si driving backplane 10. The isolation layer 30 completely covers each conductive layer 20 formed in the above steps and other areas on the upper surface of the Si driving backplane 10. The isolation layer 30 can separate the conductive layers 20 and achieve conductive protection.

[0078] like Figure 3d As shown, see Figure 2Step (S12) uses chemical mechanical polishing (CMP) to reduce the thickness of the isolation layer 30 until the upper surface of each conductive layer 20 is exposed. In the example shown in the figure, the height or thickness of the conductive layer 20 is equal to the height or thickness of the isolation layer 30. In this way, subsequent process operations are performed on the upper surface of the conductive layer 20 and the upper surface of the isolation layer 30.

[0079] like Figure 3e As shown, see Figure 1 Step (S04), Figure 2 Step (S13), depositing a buffer layer 40 on the surfaces of the isolation layer 30 and the conductive layers 20. The buffer layer 40 has through holes 41 at least corresponding to the conductive layers 20, exposing the upper surfaces of the conductive layers 20. The width of the through holes 41 is greater than the width of the conductive layers 20.

[0080] Specifically, a photoresist layer is coated on the buffer layer 40. Exposure is performed on the photoresist layer to form a through hole 41 in the buffer layer 40 at a portion corresponding to the conductive layer 20, and then the photoresist layer is removed. The corresponding through hole 41 on the upper surface of the conductive layer 20 can be used as a bonding activity space or activity area required for the transfer bonding of the Micro LED chip.

[0081] In the example shown in the figure, the isolation layer 30 can be an insulating layer. The side space of the conductive layer 20 is covered and protected by the isolation layer 30, which can increase the scope for opening the through hole 41 in the buffer layer 40 later, thereby increasing the change space or activity space during the bonding process of the Micro LED chip.

[0082] The buffer layer 40 shown in the figure is an elastic organic photoresist material, which can ensure that there is enough buffer space during eutectic bonding to avoid damage to the substrate or LED device due to pressure during the bonding process. The thickness of the buffer layer 40 is greater than 1μm, which can ensure that the flowing metal liquid can be completely retained in the preset holes when the first bonding layer and the second bonding layer are metal-bonded, without overflowing.

[0083] like Figure 3f As shown, see Figure 1 Step (S05), Figure 2Step (S14), depositing and forming a first bonding layer 51 on the upper surface of the conductive layer 20. Specifically, a photoresist (or photoresist) layer is coated on the buffer layer 40 and in the through hole 41. A metal pattern is formed on the Si driving backplane 10 at the through hole 41 by exposure and development above the photoresist layer. Then a metal film layer is deposited on the photoresist layer and the metal pattern. The photoresist layer is removed, and a first bonding layer 51 is formed on the metal pattern in the through hole 41. It can be understood that the first bonding layer 51 is a metal film layer at this time. The first bonding layer 51 is an alloy metal layer. The first bonding layer 51 can be one of gold, tin, nickel, titanium, aluminum, silver, indium, or an alloy composed of metal materials. In this process, the width of the first bonding layer 51 is less than or equal to the width of the through hole 41, and the width of the first bonding layer 51 needs to be greater than or equal to the width of the conductive layer 20 to ensure that there is a sufficient electrical connection surface between the subsequent Micro LED chip and the conductive layer 20 to obtain good conductive performance.

[0084] In the illustrated embodiment, the first bonding layer 51 is completely located in the through hole 41 in the buffer layer 40. The width L1 of the first bonding layer 51 is greater than the width L2 of the conductive layer 20, and the width L1 of the first bonding layer 51 is less than or equal to the width L3 of the through hole 41. However, it is not limited thereto. In practice, depending on the type and model of the Micro LED chip, the width L1 of the first bonding layer 51 may be less than the width L2 of the conductive layer 20. The Micro LED chip can achieve effective electrical connection with the conductive layer 20 via the first bonding layer 51.

[0085] like Figure 3g As shown, see Figure 1 Step (S06), providing a second substrate 70, on one side of which a plurality of Micro LED chips 60 are arranged. The Micro LED chips 60 are arranged in an array on the second substrate 70. In the figure, the Micro LED chip 60 is flip-chip arranged on the second substrate 70. A second bonding layer 52 is arranged on the side surface of each Micro LED chip 60 away from the second substrate 70. The material of the second bonding layer 52 can be one of gold, tin, nickel, titanium, aluminum, silver, indium, or an alloy composed of metal materials. The thickness of the second bonding layer 52 is related to the space required for the curing of the bonding layer 50 after bonding and the thickness of the buffer layer 40. The width of the second bonding layer 52 is less than or equal to the width of the Micro LED chip 60 to ensure that the Micro LED chip 60 has a good electrical connection with the first substrate 10 through the second bonding layer 52. In the example shown in the figure, the width of the second bonding layer 52 is less than the width of the Micro LED chip 60.

[0086] When the Micro LED chips 60 are transferred to the first substrate 10, the second bonding layer 52 on the second substrate 70 is aligned and bonded with the first bonding layer 51 on the first substrate 10. Laser heating is used to melt the metal or alloy on the first bonding layer 51 and the second bonding layer 52. At the same time, the other side of the second substrate 70 (the side away from the Micro LED chip 60 in the figure) is continuously pressed to complete eutectic bonding between the first bonding layer 51 and the second bonding layer 52 to form a bonding layer 50. Then, the second substrate 70 is removed to obtain the Micro LED panel 1, as shown in FIG. Figure 3h In the example shown in the figure, the bonding layer 50 is completely located in the through hole 41 in the buffer layer 40 .

[0087] The width L3 of the through hole 41 in the buffer layer 40 is greater than or equal to the width L4 of the Micro LED chip 60 , which facilitates the Micro LED chip 60 to move in the through hole 41 and align and bond with the conductive layer 20 during the transfer bonding process of the Micro LED chip 60 .

[0088] In the example shown in the figure, the height H1 of the through hole 41 is greater than the height H2 of the bonding layer 50, which can prevent the bonding layer 50 from overflowing outside the through hole 41 or overflowing to the upper surface of the buffer layer 40, causing abnormal bonding of the Micro LED chip 60, thereby affecting the transfer efficiency of a large number of Micro LED chips 60. However, it is not limited to this. In one embodiment, the height H1 of the through hole 41 is equal to the height H2 of the bonding layer 50. At this time, the surface of the Micro LED chip 60 is bonded to the upper surface of the buffer layer 40, and is electrically connected to the conductive layer 20 through the bonding layer 50. In this state, the width L4 of the Micro LED chip 60 is equal to or slightly greater than the width L3 of the through hole 41 in the buffer layer 40.

[0089] The width L3 of the through hole 41 in the buffer layer 40 is greater than or equal to the width L2 of the conductive layer 20, so that the width of the bonding layer 50 in the through hole 41 is greater than or equal to the width of the conductive layer 20, thereby ensuring excellent electrical connection performance between the bonding layer 50 and the conductive layer 20. In the example shown in the figure, the width L3 of the through hole 41 in the buffer layer 40 is greater than the width L2 of the conductive layer 20.

[0090] Combination Figure 1 And compare Figure 2 See also Figure 4 and Figure 5a to Figure 5h , Figure 4 for Figure 1 The schematic diagram of the process of the second embodiment of the Micro LED transfer method is shown in FIG. Figure 5a to Figure 5h for Figure 4The specific process steps of the second embodiment of the Micro LED transfer method shown in these figures are described as follows.

[0091] like Figure 5a As shown, see Figure 1 Step (S01) provides a first substrate 10, on which an array of electrodes 11 is disposed. In the figure, the first substrate 10 is a Si driving backplane. The Si driving backplane 10 is provided with at least three arrays of electrodes 11, wherein the upper surfaces of two electrodes 11 are exposed on the same side of the Si driving backplane 10, which is the upper surface of the first substrate 10 in the example shown.

[0092] like Figure 5b As shown, see Figure 1 Step ( S02 ) forms a conductive metal layer on the first substrate 10 , and forms a conductive layer 20 on a portion of the electrode 11 . To further explain, the conductive layer 20 is formed on the surface of the electrode 11 exposed to the first substrate 10 .

[0093] Specifically, in Figure 5a The upper surface of the Si driving backplane 10 is coated with a photoresist (or photoresist) layer, and the photoresist layer covers the upper surface of a portion of the electrode 11 in the Si driving backplane 10. Exposure and development are performed on the photoresist layer to form a conductive metal pattern on the upper surface of the portion of the electrode 11. Then, a conductive metal layer is deposited on the photoresist layer. It can be understood that the conductive metal layer covers the photoresist layer and the conductive metal pattern. The photoresist layer is removed and the conductive metal layer in the unnecessary area is removed at the same time, and finally a conductive layer 20 is formed only on the upper surface of the portion of the electrode 11. As shown in FIG. Figure 5b As shown, a conductive layer 20 is correspondingly formed on the upper surface of at least two electrodes 11 in the array of three electrodes 11 on the Si driving backplane 10 .

[0094] like Figure 5c As shown, see Figure 1 Step (S03), Figure 4 Step (S21), depositing a flat isolation layer 30 on the Si driving backplane 10. The isolation layer 30 completely covers the conductive layers 20 formed in the above steps and other areas on the upper surface of the Si driving backplane 10. The isolation layer 30 can separate the conductive layers 20 and achieve conductive protection. The isolation layer 30 can be a buffer insulating layer. In the example shown in the figure, the height or thickness of the isolation layer 30 is greater than the height or thickness of the conductive layer 20.

[0095] For further information, see Figure 4Step (S22), at least one opening 31 is formed in the isolation layer 30 corresponding to the conductive layer 20, and the upper surface of the conductive layer 20 is exposed. Specifically, a photoresist (or photoresist) layer is coated on the isolation layer 30. An opening 31 is formed above the conductive layer 20 by exposure and development processes above the photoresist layer.

[0096] In the illustrated embodiment, the isolation layer 30 is an elastic organic photoresist material, which can ensure that there is enough buffer space during eutectic bonding to avoid damage to the substrate or LED device due to pressure during the bonding process. The width L5 of the opening 31 is less than or equal to the width L2 of the conductive layer 20, which can ensure that the bonding layer metal is confined within the hole range in the subsequent eutectic process and will not overflow the opening 31, thereby causing a short circuit of the adjacent conductive layer 20 signal. In the illustrated example, the width L5 of the opening 31 is less than the width L2 of the conductive layer 20.

[0097] like Figure 5d As shown, see Figure 1 Step (S05), Figure 4 Step (S23), depositing and forming a first bonding layer 51 on the upper surface of the conductive layer 20. Specifically, a photoresist (or photoresist) layer is coated on the isolation layer 30 and in the opening 31. A metal pattern is formed on the Si driving backplane 10 at the opening 31 by exposure and development above the photoresist layer. Then a metal layer or alloy layer is deposited on the photoresist layer and the metal pattern. The photoresist layer is removed, and a first bonding layer 51 is formed on the metal pattern in the opening 31. The first bonding layer 51 can be one of gold, tin, nickel, titanium, aluminum, silver, indium, or an alloy composed of metal materials. In this process method, the width of the first bonding layer 51 is less than or equal to the width of the opening 31, and the width of the first bonding layer 51 is less than or equal to the width of the conductive layer 20, so as to ensure that there is sufficient electrical connection surface between the subsequent Micro LED chip and the conductive layer 20 to obtain good conductive performance.

[0098] The upper surface of the first bonding layer 51 is flush with the upper surface of the isolation layer 30, or the upper surface of the first bonding layer 51 is lower than the upper surface of the isolation layer 30. In other words, the height or thickness of the first bonding layer 51 is less than or equal to the height or thickness of the opening 31 in the isolation layer 30. This arrangement facilitates subsequent process operations above the isolation layer 30 and the first bonding layer 51.

[0099] In the illustrated embodiment, the width L1 of the first bonding layer 51 is smaller than the width L2 of the conductive layer 20, and smaller than or equal to the width L5 of the opening 31. In this way, it is ensured that the metal fluid of the first bonding layer 51 is confined within the range of the hole in the subsequent eutectic process and does not overflow from the opening 31, thereby causing a signal short circuit of the adjacent conductive layer 20.

[0100] like Figure 5e , 5f As shown, see Figure 1 Step (S04) and step (S05), Figure 4 Step (S24), depositing a buffer layer 40 on the isolation layer 30 and the first bonding layer 51. A through hole 41 is provided in the buffer layer 40 corresponding to the first bonding layer 51 and the conductive layer 20. Specifically, a buffer layer 40 is deposited on the isolation layer 30 and the first bonding layer 51. A photoresist (or photoresist) layer is coated on the buffer layer 40. Through an exposure and development process above the photoresist layer, a through hole 41 is provided in the buffer layer 40 corresponding to the first bonding layer 51 and the conductive layer 20, and then the photoresist layer is removed. The corresponding through hole 41 on the upper surface of the first bonding layer 51 can be used as a bonding activity space or activity area required for the transfer bonding of the Micro LED chip. The width of the through hole 41 is greater than the width of the conductive layer 20.

[0101] In the illustrated embodiment, the buffer layer 40 is an organic photoresist layer, which can ensure that there is sufficient buffer space during eutectic bonding to avoid damage to the substrate or LED device due to pressure during the bonding process.

[0102] like Figure 5g As shown, see Figure 1 Step (S06), providing a second substrate 70, on one side of which a plurality of Micro LED chips 60 are arranged. The Micro LED chips 60 are arranged in an array on the second substrate 70. In the figure, the Micro LED chip 60 is flip-chip arranged on the second substrate 70. A second bonding layer 52 is arranged on the side surface of each Micro LED chip 60 away from the second substrate 70. The material of the second bonding layer 52 can be one of gold, tin, nickel, titanium, aluminum, silver, indium, or an alloy composed of metal materials. The thickness of the second bonding layer 52 is related to the space required for the curing of the bonding layer 50 after bonding and the thickness of the buffer layer 40. The width of the second bonding layer 52 is less than or equal to the width of the Micro LED chip 60 to ensure that the Micro LED chip 60 has a good electrical connection with the first substrate 10 through the second bonding layer 52. In the example shown in the figure, the width of the second bonding layer 52 is less than the width of the Micro LED chip 60.

[0103] When the Micro LED chips 60 are transferred to the first substrate 10, the second bonding layer 52 on the second substrate 70 is aligned and bonded with the first bonding layer 51 on the first substrate 10. Laser heating is used to melt the metal or alloy on the first bonding layer 51 and the second bonding layer 52. At the same time, the other side of the second substrate 70 (the side away from the Micro LED chip 60 in the figure) is continuously pressed to complete eutectic bonding between the first bonding layer 51 and the second bonding layer 52 to form a bonding layer 50. Then, the second substrate 70 is removed to obtain the Micro LED panel 1, as shown in FIG. Figure 5h In the example shown in the figure, the bonding layer 50 is located in both the opening 31 in the isolation layer 30 and the through hole 41 in the buffer layer 40 .

[0104] The width L3 of the through hole 41 in the buffer layer 40 is greater than or equal to the width L4 of the Micro LED chip 60 , which facilitates the Micro LED chip 60 to move in the through hole 41 and align and bond with the conductive layer 20 during the transfer bonding process of the Micro LED chip 60 .

[0105] In the example shown in the figure, the height H1 of the through hole 41 is greater than the height H2 of the bonding layer 50, which can prevent the bonding layer 50 from overflowing outside the through hole 41 or overflowing to the upper surface of the buffer layer 40, causing abnormal bonding of the Micro LED chip 60, thereby affecting the transfer efficiency of a large number of Micro LED chips 60. However, it is not limited to this. In one embodiment, the height H1 of the through hole 41 is equal to the height H2 of the bonding layer 50. At this time, the surface of the Micro LED chip 60 is bonded to the upper surface of the buffer layer 40, and is electrically connected to the conductive layer 20 through the bonding layer 50. In this state, the width L4 of the Micro LED chip 60 is equal to or slightly greater than the width L3 of the through hole 41 in the buffer layer 40.

[0106] The width L3 of the through hole 41 in the buffer layer 40 is greater than or equal to the width L2 of the conductive layer 20, so that the width of the bonding layer 50 in the through hole 41 is greater than and / or less than the width of the conductive layer 20, thereby ensuring excellent electrical connection performance between the bonding layer 50 and the conductive layer 20. In the example shown in the figure, the bonding layer 50 is located in the opening 31 of the isolation layer 30 and the through hole 41 of the buffer layer 40. Among them, the width of the bonding layer 50 located in the opening 31 is less than or equal to the width L2 of the conductive layer 20, and the width of the bonding layer 50 located in the through hole 41 is greater than or equal to the width L2 of the conductive layer 20.

[0107] Please combine Figure 1 , Figure 2 and Figure 4 See also Figure 3h , Figure 5h . It can be understood that, Figure 3hThe Micro LED panel structure shown is based on Figure 1 and Figure 2 Prepared by the method shown, Figure 5h The Micro LED panel structure shown is based on Figure 1 and Figure 4 Prepared by the method shown.

[0108] To achieve at least one of the above advantages or other advantages, an embodiment of the present invention provides a Micro LED panel 1 that can be manufactured using the Micro LED transfer method described above. The Micro LED panel 1 at least includes a first substrate 10, a plurality of conductive layers 20, an isolation layer 30, a buffer layer 40, and a bonding layer 50.

[0109] An array of electrodes 11 is disposed on the first substrate 10 . A plurality of conductive layers 20 are disposed on the first substrate 10 and cover at least a portion of the array of electrodes 11 .

[0110] The isolation layer 30 is disposed on the first substrate 10 and separates the conductive layers 20 to provide conductive protection for the conductive layers 20. The isolation layer 30 may be an insulating layer to ensure that the conductivity or signals of two adjacent conductive layers 20 are independent and prevent short circuits. The thickness of the isolation layer 30 is greater than or equal to the thickness of the conductive layer 20. Figure 3h In the embodiment, the thickness of the isolation layer 30 is equal to the thickness of the conductive layer 20 . Figure 5h In the embodiment, the thickness of the isolation layer 30 is greater than the thickness of the conductive layer 20 .

[0111] The buffer layer 40 is disposed on the isolation layer 30. The buffer layer 41 can be one of an insulating layer, an organic photoresist layer, and a passivation layer. A through hole 41 is provided in the buffer layer 40 at the locations corresponding to the conductive layers 20. The through hole 41 can be used as a bonding activity space or activity area required for the transfer bonding of the Micro LED chip 60. The width L3 of the through hole 41 is greater than or equal to the width L4 of the Micro LED chip 60. In this way, during the transfer bonding process of the Micro LED chip 60, it is convenient for the Micro LED chip 60 to move in the through hole 41 and to align and bond with the conductive layer 20. The height H1 of the through hole 41 is greater than or equal to the height H2 of the bonding layer 50, which can prevent the bonding layer 50 from overflowing from the outside of the through hole 41 or overflowing to the upper surface of the buffer layer 40, causing abnormal bonding of the Micro LED chip 60, thereby affecting the transfer efficiency of a large number of Micro LED chips 60.

[0112] The bonding layer 50 is at least partially located in the through hole 41, and the Micro LED chip 60 is electrically connected to the conductive layer 20 via the bonding layer 50 to ensure that the Micro LED chip 60 and the first substrate 10 have good electrical conductivity. The width of the bonding layer 50 is smaller than and / or larger than the width of the conductive layer 20. Figure 3h In the embodiment, the width of the bonding layer 50 is greater than the width of the conductive layer 20 . Figure 5h In the embodiment, the width of the bonding layer 50 in the opening 31 is smaller than the width of the conductive layer 20 , and the width of the bonding layer 50 in the through hole 41 is larger than the width of the conductive layer 20 .

[0113] Although the terms such as Micro LED chip, first substrate, second substrate, conductive metal layer, isolation layer, buffer layer, bonding layer, height, width, etc. are frequently used in this article, the possibility of using other terms is not excluded. These terms are used only to more conveniently describe and explain the essence of the present invention; interpreting them as any additional restrictions is contrary to the spirit of the present invention.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A Micro LED transfer method, characterized in that: The Micro LED transfer method comprises at least the following steps: Providing a first substrate, wherein an electrode array is disposed on the first substrate; forming a conductive layer on a portion of the electrodes in the first substrate; Depositing an isolation layer on the first substrate and exposing a surface of the conductive layer; Depositing a buffer layer on the isolation layer, wherein at least a portion of the buffer layer corresponding to the conductive layer is provided with a through hole, and a width of the through hole is greater than a width of the conductive layer; depositing a first bonding layer on the surface of the conductive layer; and A second substrate is provided, wherein a plurality of Micro LED chips are disposed on one surface of the second substrate, and each of the Micro LED chips is disposed on a surface of a side away from the second substrate and a second bonding layer is bonded to the first bonding layer; The width of the through hole is greater than or equal to the width of the Micro LED chip, and the height of the through hole is greater than or equal to the height of the bonding layer formed after the first bonding layer and the second bonding layer are bonded; The steps of forming the isolation layer, the buffer layer and the first bonding layer on the first substrate include: Depositing a flat isolation layer on the first substrate, wherein the isolation layer completely covers the conductive layer; Using chemical mechanical polishing to reduce the thickness of the isolation layer until the surface of the conductive layer is exposed; Depositing a buffer layer on the surfaces of the isolation layer and the conductive layer, wherein a through hole is provided in at least a portion of the buffer layer corresponding to the conductive layer to expose the surface of the conductive layer, and the width of the through hole is greater than the width of the conductive layer; Depositing the first bonding layer on the surface of the conductive layer, wherein the width of the first bonding layer is greater than or equal to the width of the conductive layer, and the width of the first bonding layer is less than or equal to the width of the through hole; Alternatively, a flat isolation layer is deposited on the first substrate, wherein the isolation layer completely covers the conductive layer; An opening is formed in the isolation layer at least partially corresponding to the conductive layer to expose the surface of the conductive layer, and the width of the opening is less than or equal to the width of the conductive layer; Depositing the first bonding layer on the surface of the conductive layer, wherein the width of the first bonding layer is less than or equal to the width of the conductive layer and less than or equal to the width of the opening; A buffer layer is deposited on the isolation layer and the first bonding layer, and a through hole is opened in the buffer layer corresponding to the first bonding layer and the conductive layer, wherein the width of the through hole is greater than the width of the conductive layer.

2. The Micro LED transfer method according to claim 1, wherein: The thickness of the buffer layer is greater than 1 μm, and the buffer layer is an elastic organic photoresist material.

3. The Micro LED transfer method according to claim 1, wherein: The isolation layer is an organic photoresist material with elasticity; and the buffer layer is an organic photoresist layer.

4. The Micro LED transfer method according to claim 1, wherein: The first substrate is at least one of a driving substrate, a glass substrate, a Si substrate, a PI substrate, and a display backplane.

5. The Micro LED transfer method according to claim 1, wherein: The conductive layer is one or more combinations of gold, tin, nickel, titanium, aluminum, silver, indium, or an alloy composed of metal materials.

6. The Micro LED transfer method according to claim 1, wherein: The buffer layer is one of an insulating layer, an organic photoresist layer and a passivation layer.

7. The Micro LED transfer method according to claim 1, wherein: The first bonding layer and the second bonding layer are respectively one or more of gold, tin, nickel, titanium, aluminum, silver, indium, or alloys composed of metal materials.

8. The Micro LED transfer method according to claim 1, wherein: The bonding method between the first bonding layer and the second bonding layer is one or more of alloy eutectic bonding, diffusion bonding, and transient liquid phase bonding.

9. The Micro LED transfer method according to claim 1, wherein: The second bonding layer and the first bonding layer are bonded by using a laser heating method to melt the metal in the second bonding layer and the first bonding layer, and then continuously pressing them to form a metal bonding layer.

10. A Micro LED panel, manufactured by the Micro LED transfer method according to any one of claims 1 to 9, characterized in that The Micro LED panel at least includes: a first substrate, on which an electrode array is provided; A plurality of conductive layers, disposed on the first substrate and covering at least a portion of the electrode array; An isolation layer, disposed on the first substrate and separating the plurality of conductive layers; a buffer layer, disposed on the isolation layer, wherein the buffer layer is provided with a through hole at a position corresponding to the conductive layer; and A bonding layer, at least partially located in the through hole, and the Micro LED chip is connected to the conductive layer via the bonding layer; Among them, the width of the through hole is greater than or equal to the width of the Micro LED chip, and the height of the through hole is greater than or equal to the height of the bonding layer.

11. The Micro LED panel according to claim 10, wherein: The isolation layer is an insulating layer, and the thickness of the isolation layer is greater than or equal to the thickness of the conductive layer.

12. The Micro LED panel according to claim 10, wherein: The buffer layer is one of an insulating layer, an organic photoresist layer and a passivation layer.

13. The Micro LED panel according to claim 10, wherein: The width of the bonding layer is smaller than or larger than the width of the conductive layer.

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