A transistor, a manufacturing method thereof, and an electronic device

Abstract

The present application provides a transistor, a manufacturing method thereof, and an electronic device, relating to the field of semiconductors. The transistor includes a chip body and source / drain electrodes, and the source / drain electrodes are disposed on the surface layer of the chip body. Among them, the source / drain electrodes include: an indium-rich layer, an aluminum oxide layer on one side of the indium-rich layer, an aluminum layer on one side of the aluminum oxide layer, and a copper layer on one side of the aluminum layer. In the present application, the aluminum oxide layer can effectively prevent copper atoms from diffusing into the active layer. At the same time, the indium-rich layer can reduce the contact resistance between the source / drain electrodes and the active layer, thereby improving the device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and more particularly, to a transistor, a manufacturing method thereof, and an electronic device. Background Art

[0002] A thin film transistor (TFT) is a widely used semiconductor device, mainly used to drive the change of liquid crystal arrangement in a display or drive the light emission of OLED pixels. The structure of a thin film transistor at least includes a gate electrode, a gate insulating layer, an active layer, and source and drain electrodes.

[0003] Generally, copper electrodes are selected for the source and drain electrodes. The resistivity and stability of copper are both very ideal. However, after the copper electrodes are deposited on the active layer, copper atoms will diffuse into the active layer, thereby deteriorating the electrical properties of the active layer, and there is also a problem of relatively high contact resistance between the copper electrodes and the active layer. Summary of the Invention

[0004] An object of the present invention is to provide a transistor, a manufacturing method thereof, and an electronic device, which can effectively prevent copper atoms from diffusing into the active layer, reduce the contact resistance, and improve the device performance.

[0005] To achieve the above object, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, the present application provides a transistor, which includes a chip body and source and drain electrodes, and the source and drain electrodes are disposed on the surface layer of the chip body;

[0007] Wherein, the source and drain electrodes include:

[0008] An indium-rich layer;

[0009] An aluminum oxide layer located on one side of the indium-rich layer;

[0010] An aluminum layer located on one side of the aluminum oxide layer;

[0011] A copper layer located on one side of the aluminum layer.

[0012] Optionally, the chip body includes:

[0013] A substrate;

[0014] A bottom gate electrode and a gate insulating layer sequentially disposed on the substrate, and the gate insulating layer covers the bottom gate electrode;

[0015] An active layer covering the gate insulating layer, the active layer covering the middle part of the gate insulating layer, the source and drain electrodes respectively covering both sides of the gate insulating layer, and the source and drain electrodes partially covering the active layer.

[0016] Optionally, the chip body further includes a passivation layer covering the active layer and the source-drain electrodes.

[0017] Optionally, the thickness of the indium-rich layer is 1-10 nm.

[0018] Optionally, the thickness of the aluminum oxide layer is 1-10 nm.

[0019] Optionally, the thickness of the aluminum layer is 10-1000 nm.

[0020] Optionally, the thickness of the copper layer is 10-2000 nm.

[0021] In a second aspect, the present application further provides a method for manufacturing a transistor, the method including:

[0022] Providing a chip body

[0023] The chip body includes an active layer, and the active layer is an indium-containing oxide;

[0024] Depositing an aluminum layer on one side of the active layer;

[0025] Depositing a copper layer on one side of the aluminum layer;

[0026] Annealing the active layer and the aluminum layer so that a reduction reaction occurs between part of the aluminum layer and the active layer to form an indium-rich layer and an aluminum oxide layer.

[0027] Optionally, the method for manufacturing the chip body includes:

[0028] Providing a substrate;

[0029] Successively fabricating a bottom gate and a gate insulating layer on one side of the substrate, and the gate insulating layer covers the bottom gate;

[0030] Fabricating an active layer on one side of the gate insulating layer, and the active layer covers a part of the gate insulating layer;

[0031] Wherein, the active layer is an indium-containing oxide layer.

[0032] In a third aspect, the present application further provides an electronic device including the transistor.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] The present application provides a transistor, a manufacturing method thereof, and an electronic device. The transistor includes a chip body and source-drain electrodes disposed on the surface layer of the chip body. Among them, the source-drain electrodes include an indium-rich layer, an aluminum oxide layer on one side of the indium-rich layer, an aluminum layer on one side of the aluminum oxide layer, and a copper layer on one side of the aluminum layer. In the present application, the aluminum oxide layer can effectively prevent copper atoms from diffusing into the active layer. At the same time, the indium-rich layer can reduce the contact resistance between the source-drain electrodes and the active layer, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0036] Figure 1 FIG. 1 is one of the structural diagrams of the transistor provided by the embodiment of the present application;

[0037] Figure 2 FIG. 2 is another structural diagram of the transistor provided by the embodiment of the present application;

[0038] Figure 3 FIG. 3 is the resistance detection diagram of the transistor provided by the embodiment of the present application;

[0039] Figure 4 FIG. 4 is the element distribution diagram of the source-drain electrode interface provided by the embodiment of the present application.

[0040] Reference numerals: 100 - transistor; 10 - source-drain electrode; 20 - chip body; 110 - copper layer; 120 - aluminum layer; 130 - aluminum oxide layer; 140 - indium-rich layer; 210 - substrate; 220 - bottom gate; 230 - gate insulating layer; 240 - active layer; 250 - passivation layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] Regarding the problems existing in the prior art, they are all the results obtained by the inventors after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the embodiments of the present invention below for the above problems should all be the contributions made by the inventors during the invention process.

[0042] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. Components of the embodiments of the present invention generally described and illustrated in the figures herein can be arranged and designed in a variety of different configurations.

[0043] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0044] It should be noted that like reference numerals and letters denote like items in the following figures, and thus, once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

[0045] In the description of the present invention, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, or the orientations or positional relationships in which the inventive product is habitually placed during use, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0046] In addition, terms such as "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0047] The term "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device.

[0048] To facilitate a better understanding of the technical solutions provided in this application, the deficiencies in the prior art will be introduced in detail below.

[0049] A thin film transistor (TFT for short) is a semiconductor device with a wide range of applications, mainly used to drive the change of liquid crystal arrangement in a display or drive the emission of OLED pixels, etc. The structure of a thin film transistor at least includes a gate, a gate insulating layer, an active layer, and source-drain electrodes, where the source-drain electrodes are located above the active layer.

[0050] With the popularization of large-size, high-resolution, and high-refresh-rate displays, TFTs must have excellent mobility and conductivity to shorten signal latency, reduce energy consumption, and improve display quality.

[0051] Mobility is mainly determined by the active layer material of the TFT. Currently, popular active layer materials mainly include (low-temperature) polysilicon, amorphous silicon, metal oxides, etc. Low-temperature polysilicon and metal oxides have the advantage of relatively high electron mobility. However, TFTs with low-temperature polysilicon as the active layer have longer production processes, more photomasks, and higher costs. In contrast, metal oxide processes are simple and inexpensive, and are highly favored. The most well-known metal oxide material in the display industry is IGZO (indium gallium zinc oxide).

[0052] Conductivity is determined by the electrode material. Currently, commonly used high-conductivity electrode materials include silver, copper, aluminum, aluminum-neodymium alloy, molybdenum, titanium, etc. Among them, silver (1.6 μΩ·cm) and copper (1.7 μΩ·cm) have relatively low resistivity. However, silver has the problem of easy aggregation of silver particles during deposition, which seriously affects electron transport. In addition, the cost of silver is relatively expensive, resulting in very limited use of silver electrodes.

[0053] Copper is ideal in terms of resistivity, stability, and cost. However, copper has the following problems: after the copper electrode is deposited on the active layer, copper atoms will diffuse into the active layer, generating acceptor-like defects in the active layer, deteriorating the electrical properties of the active layer. At the same time, the contact resistance between copper (including silver) and the active layer is relatively high.

[0054] Therefore, in view of the deficiencies of the prior art, it is very necessary to provide a multi-layer high-conductivity source-drain electrode and a thin-film transistor with such an electrode to overcome the defects of the electrodes in the prior art.

[0055] It should be noted that all the problems existing in the prior art are the results obtained by the inventors through practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the embodiments of the present invention below for the above problems should be the contributions made by the inventors during the invention process.

[0056] In view of this, the embodiments of the present application provide a transistor that can effectively prevent copper atoms from diffusing into the active layer, reduce the contact resistance, and improve the device performance.

[0057] The following will describe in detail some embodiments of the present invention with reference to the accompanying drawings. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0058] Please refer to Figure 1, the transistor 100 provided by the embodiment of the present application includes a chip body 20 and source / drain electrodes 10. The source / drain electrodes 10 are disposed on the surface layer of the chip body 20. Among them, the source / drain electrodes 10 include:

[0059] An indium-rich layer 140;

[0060] An aluminum oxide layer 130 located on one side of the indium-rich layer 140;

[0061] An aluminum layer 120 located on one side of the aluminum oxide layer 130;

[0062] A copper layer 110 located on one side of the aluminum layer 120.

[0063] In the transistor 100 provided by the embodiment of the present application, the aluminum oxide layer 130 can effectively prevent copper atoms from diffusing into the active layer 240. At the same time, the indium-rich layer 140 can reduce the contact resistance between the source / drain electrodes 10 and the active layer 240, thereby improving the device performance. It not only overcomes the defect that copper atoms diffuse into the active layer 240 after the copper electrode in the prior art is deposited on the metal oxide active layer 240, but also has the advantages of good conductivity and low resistivity.

[0064] Please refer to Figure 2 , in another alternative embodiment, the chip body 20 includes:

[0065] A substrate 210;

[0066] A bottom gate 220 and a gate insulating layer 230 sequentially disposed on the substrate 210. The gate insulating layer 230 covers the bottom gate 220;

[0067] An active layer 240 covering the gate insulating layer 230. The active layer 240 covers the middle part of the gate insulating layer 230. The source / drain electrodes 10 respectively cover both sides of the gate insulating layer 230, and the source / drain electrodes 10 partially cover the active layer 240.

[0068] Please continue to refer to Figure 2 , in another possible embodiment, the chip body 20 further includes a passivation layer 250, and the passivation layer 250 covers the active layer 240 and the source / drain electrodes 10.

[0069] In another alternative embodiment, the thickness of the indium-rich layer 140 is 1-10 nm.

[0070] In another alternative embodiment, the thickness of the aluminum oxide layer 130 is 1-10 nm.

[0071] In another alternative embodiment, the thickness of the aluminum layer 120 is 10-1000 nm.

[0072] In another alternative embodiment, the thickness of the copper layer 110 is 10 - 2000 nm.

[0073] The present application also provides a method for manufacturing a transistor 100, the method comprising:

[0074] Step 201: Provide a chip body 20, the chip body 20 includes an active layer 240, and the active layer 240 is an indium-containing oxide;

[0075] Step 202: Deposit an aluminum layer 120 on one side of the active layer 240;

[0076] Step 203: Deposit a copper layer 110 on one side of the aluminum layer 120;

[0077] Step 204: Anneal the active layer 240 and the aluminum layer 120 so that a reduction reaction occurs between a part of the aluminum layer 120 and the active layer 240 to form an indium-rich layer 140 and an aluminum oxide layer 130.

[0078] It should be noted that in the above step 204, a reduction reaction occurs between the side of the aluminum layer 120 in contact with the active layer 240 and the active layer 240 to form an indium-rich layer 140 and an aluminum oxide layer 130. At this time, the aluminum layer 120 will become thinner because it participates in the reduction reaction.

[0079] After the above step 204, the method for manufacturing the transistor 100 further includes:

[0080] Step 205: Deposit a passivation layer 250 on the active layer 240 and the source-drain electrodes 10.

[0081] In another alternative embodiment, the method for manufacturing the chip body 20 includes:

[0082] Step 301: Provide a substrate 210;

[0083] Step 302: Sequentially fabricate a bottom gate 220 and a gate insulating layer 230 on one side of the substrate 210, and the gate insulating layer 230 covers the bottom gate 220;

[0084] Step 303: Fabricate an active layer 240 on one side of the gate insulating layer 230, and the active layer 240 covers a part of the gate insulating layer 230;

[0085] Wherein, the active layer 240 is an indium-containing oxide.

[0086] It should be noted that in this embodiment, the indium-containing oxide refers to an oxide based on indium oxide, such as IZO, ITO, IGO, IGZO, ITZO, etc. In this embodiment, IGZO is preferably used.

[0087] To better understand the technical solution provided by the embodiments of the present application, the transistor 100 provided by the present application will be introduced in detail below in combination with the specific manufacturing process.

[0088] The present application provides a transistor 100, which includes a chip body 20 and source-drain electrodes 10. Among them, the source-drain electrodes 10 are composed of an indium-rich layer 140, an aluminum oxide layer 130, an aluminum layer 120, and a copper layer 110 stacked in sequence, and the copper layer 110 is located above the aluminum layer 120.

[0089] Among them, the thickness of the aluminum layer 120 is set to 10 - 1000 nm, the thickness of the copper layer 110 is set to 10 - 2000 nm. Preferably, the thickness of the copper layer 110 is set to 200 nm, and the thickness of the aluminum layer 120 is 50 nm.

[0090] The transistor 100 of this embodiment is prepared through the following steps:

[0091] Step 401: Use DC sputtering deposition on a glass substrate to deposit a 300-nm molybdenum thin film, and pattern the molybdenum thin film through wet etching to form a bottom gate 220.

[0092] Step 402: Continue to use plasma-enhanced chemical vapor deposition to deposit a 200-nm-thick silicon oxide thin film as a gate insulating layer 230.

[0093] Step 403: Deposit a 25-nm active layer 240 by RF magnetron sputtering at room temperature, pattern it through wet etching, and then perform an annealing treatment in an air atmosphere at 400 °C for 60 minutes. Among them, the active layer 240 is IGZO.

[0094] Step 404: Use DC sputtering deposition to continuously deposit a 50-nm-thick aluminum layer 120 and a 200-nm-thick copper layer 110, and pattern them through wet etching.

[0095] Step 405: Use RF magnetron sputtering deposition to deposit a 100-nm-thick aluminum oxide as a passivation layer 250.

[0096] Step 406: Perform a post-annealing treatment in a nitrogen atmosphere at 300 °C for 10 minutes to promote the reaction between the aluminum layer 120 and the IGZO in the active layer 240 to form an aluminum oxide layer 130 and an indium-rich layer 140, thus obtaining the transistor 100 provided by the present application.

[0097] The sheet resistance of the Al / Cu (50 / 200 nm) thin film measured after annealing treatment in a nitrogen atmosphere at 300 °C is 0.1 Ω / square, indicating that the prepared multi-layer high-conductivity electrode has good conductivity.

[0098] Through experiments, it can be known that as Figure 3As described above, the measured contact resistance of the transistor 100 prepared in this application is only 2162.4 Ω, indicating good contact between the electrode and the semiconductor layer.

[0099] Similarly, as Figure 4 shown, for the element distribution at the interface of the source-drain electrode 10 of the transistor 100 prepared in this application, it can be seen that the diffusion of the copper layer 110 is completely blocked by the alumina layer 130 and does not enter the active layer 240.

[0100] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A transistor, characterized in that, The transistor includes a chip body and source-drain electrodes, and the source-drain electrodes are disposed on the surface layer of the chip body; Wherein, the source-drain electrodes include: An indium-rich layer; An aluminum oxide layer located on a side of the indium-rich layer away from the chip body; An aluminum layer located on a side of the aluminum oxide layer away from the chip body; A copper layer located on a side of the aluminum layer away from the chip body; The chip body includes an active layer, and the aluminum oxide layer is used to prevent copper atoms of the copper layer from diffusing into the active layer.

2. The transistor according to claim 1, characterized in that, The chip body includes: A substrate; A bottom gate electrode and a gate insulating layer sequentially disposed on the substrate, and the gate insulating layer covers the bottom gate electrode; An active layer covering the gate insulating layer, the active layer covering an intermediate portion of the gate insulating layer, the source-drain electrodes respectively covering both sides of the gate insulating layer, and the source-drain electrodes partially covering the active layer.

3. The transistor according to claim 2, characterized in that, The chip body further includes a passivation layer, and the passivation layer covers the active layer and the source-drain electrodes.

4. The transistor according to claim 1, characterized in that, The thickness of the indium-rich layer is 1 - 10 nm.

5. The transistor according to claim 1, characterized in that, The thickness of the aluminum oxide layer is 1 - 10 nm.

6. The transistor according to claim 1, characterized in that, The thickness of the aluminum layer is 10 - 1000 nm.

7. The transistor according to claim 1, characterized in that, The thickness of the copper layer is 10 - 2000 nm.

8. A method for manufacturing a transistor, characterized in that, The method includes: Providing a chip body; The chip body includes an active layer, and the active layer is an indium-containing oxide; Depositing an aluminum layer on a side of the active layer away from the chip body; Depositing a copper layer on a side of the aluminum layer away from the chip body; Annealing the active layer and the aluminum layer, so that a reduction reaction occurs between a part of the aluminum layer and the active layer to form an indium-rich layer and an aluminum oxide layer; the aluminum oxide layer is used to prevent copper atoms of the copper layer from diffusing into the active layer.

9. The method for manufacturing a transistor according to claim 8, characterized in that, The manufacturing method of the chip body includes: Providing a substrate; Sequentially fabricating a bottom gate electrode and a gate insulating layer on one side of the substrate, and the gate insulating layer covers the bottom gate electrode; Fabricating an active layer on one side of the gate insulating layer, and the active layer covers a part of the gate insulating layer; Wherein, the active layer is an indium-containing oxide layer.

10. An electronic device, characterized in that, Including the transistor according to any one of claims 1 - 7.

Images