High input impedance biomedical front-end detection circuit and related methods

Abstract

This application discloses a high input impedance biomedical front-end detection circuit, whose input impedance is increased by an on-chip automatic input impedance boosting circuit. Specifically, the front-end detection circuit includes a reconfigurable instrumentation amplifier, an adjustable gain amplifier, and an on-chip automatic input impedance boosting circuit. The reconfigurable instrumentation amplifier and the adjustable gain amplifier amplify biological signals at different gain rates; the on-chip automatic input impedance boosting circuit automatically adjusts the positive feedback capacitor connected to the reconfigurable instrumentation amplifier, boosting the input impedance of the amplification circuit while ensuring circuit stability. The high input impedance of this circuit improves its anti-interference capability and reduces the attenuation of biological signals at the detection electrodes in practical applications, enabling high-quality detection of biological signals.

Description

Technical Field

[0001] This invention pertains to integrated circuits, and particularly relates to a high input impedance biomedical front-end detection circuit and related methods. Background Technology

[0002] High input impedance amplifier circuits have wide applications in the field of biomedical front-end sampling. Biological signals are weak in amplitude (ranging from hundreds of microvolts (µV) to several millivolts (mV), and most biological signals are coupled into the amplifier circuit through electrodes. Common electrodes are divided into wet electrodes, dry electrodes, and non-contact electrodes. Dry electrodes and non-contact electrodes offer better comfort and stability, but because these two types of electrodes have high impedance (>MΩ), the equivalent internal resistance of the biological signal coupled into the amplifier circuit is relatively large. Therefore, a high input impedance amplifier circuit is needed to acquire biological signals with high quality.

[0003] Traditional high input impedance amplifier circuit structures include three-op-amp structures, pre-charge structures, and off-chip adjustable high input impedance amplifier circuits based on positive feedback loops. Three-op-amp structures have high power consumption and are not suitable for long-term biosignal detection; pre-charge structures, due to charging time and buffer non-idealities, cannot achieve a good input impedance boost; and the last type of structure requires off-chip manual intervention, increasing testing time and cost.

[0004] Invention CN109921751A discloses a method for improving the input impedance of an instrumentation amplifier used in analog front-ends in biomedicine, to increase the input impedance of the instrumentation amplifier to suppress electrostatic interference. The method employs an instrumentation amplifier with positive feedback and closed-loop negative feedback paths, a calibration signal detection circuit, a timing logic control circuit, and a positive feedback reduction circuit. When improving the input impedance, a calibration signal is input to the input terminal. The detection circuit detects whether the amplifier's output signal is out of phase with the input signal, thereby determining whether the value of the positive feedback capacitor array causes the circuit to be in an undercompensated or overcompensated state. However, the positive feedback capacitor array in this method is always connected to the circuit in a positive feedback configuration throughout the calibration cycle. The closer the positive feedback capacitor array is to the ideal calibration value, the longer it takes for the entire system to reach a steady-state output. Using a fixed calibration signal detection cycle to detect the output value can lead to the next calibration cycle starting before a stable output is observed within the calibration signal detection cycle. The accuracy of the input impedance improvement method is affected by the calibration signal detection cycle; it is a qualitative rather than a quantitative calibration, making it difficult to accurately find the calibration boundary. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention provides a high input impedance biomedical front-end detection circuit. The purpose of this invention is to realize an amplifier circuit that automatically increases the input impedance. By automatically adjusting the positive feedback capacitor of the input circuit, a higher input impedance can be achieved, ensuring that weak biological signals can be acquired with high quality.

[0006] The technical solution of the present invention is as follows:

[0007] A high input impedance biomedical front-end detection circuit includes a working mode and a calibration mode. In the working mode, the input signal is amplified, and in the calibration mode, the input impedance is automatically increased. Specifically, it includes a reconfigurable instrumentation amplifier, an adjustable gain amplifier, and an on-chip automatic input impedance boosting circuit. The reconfigurable instrumentation amplifier includes a fully differential gain circuit and an adjustable positive feedback capacitor loop. The adjustable gain amplifier has an adjustable gain. The on-chip automatic input impedance boosting circuit includes a calibration signal coupling circuit, a peak-to-peak comparison circuit, and a counter.

[0008] In calibration mode, the calibration signal coupling circuit is connected to the input of the reconfigurable instrumentation amplifier (AIA) via a coupling capacitor. The AIA switches between the first and second structures. The output values ​​of different structures are amplified by the adjustable gain amplifier. The on-chip automatic input impedance boosting circuit extracts the peak-to-peak values ​​of the amplified outputs of the first and second structures from the AIA and compares them. The comparator output determines whether the positive feedback capacitor in the input circuit should be increased or decreased. The comparator controls the output codeword of the digital logic to adjust the size of the positive feedback capacitor in the input circuit. Finally, the output codeword of the digital logic keeps the positive feedback compensation at the critical value. After calibration mode is completed, the circuit is switched to operating mode. The input of the AIA is disconnected from the calibration coupling circuit and connected to the normal signal input, maintaining the state of the adjustable positive feedback capacitor connected to the AIA during calibration. The output of the adjustable gain amplifier is disconnected from the on-chip automatic input impedance boosting circuit, allowing normal amplification of the input signal.

[0009] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0010] 1) By reconstructing the instrumentation amplifier in calibration mode and comparing the peak-to-peak values ​​of the output signals of different reconstruction structures, the parasitic capacitance that needs to be compensated at the input of the front-end circuit can be quantized into the difference between the peak and peak values.

[0011] 2) It can perform precise quantization and automatic adjustment, thereby realizing a high input impedance biomedical front-end detection circuit to achieve high-quality recording of biological signals.

[0012] 3) Compared with invention CN109921751A, the positive feedback loop of this invention only exists in the working mode. In the calibration mode, there is no positive feedback loop in the two reconstruction structures of the instrumentation amplifier, and calibration is always performed under a stable structure, thus avoiding the influence of positive feedback on calibration stability. At the same time, this invention quantifies the parasitic capacitance that needs to be compensated into the difference between peak and peak values, which is a quantitative calibration. Compared with invention CN109921751A, it can achieve higher accuracy calibration results. Attached Figure Description

[0013] Figure 1 A structural schematic diagram provided for an embodiment of the overall structure of the present invention;

[0014] Figure 2 A schematic diagram of the structure of an embodiment of the reusable peak-to-peak detection circuit of the present invention;

[0015] Figure 3 This is a schematic diagram of the timing and input / output signal relationship provided for an embodiment of the reusable peak-to-peak detection circuit of the present invention;

[0016] Figure 4 A structural and timing diagram provided for an embodiment of a prior art switched-capacitor integrator circuit;

[0017] Figure 5 This is a schematic diagram showing the input-output signal relationship of the switched-capacitor integrator circuit under calibration conditions. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] Figure 1 The schematic diagram provided for an overall structural embodiment of the present invention includes a reconfigurable instrumentation amplifier 1, an adjustable gain amplifier 2, and an on-chip automatic input impedance boosting circuit 3. The reconfigurable instrumentation amplifier 1 includes a fully differential gain circuit 11 and an adjustable positive feedback capacitor loop 12. The fully differential gain circuit 11 includes a fully differential operational amplifier, a capacitive negative feedback loop, a resistive negative feedback loop, and an input capacitor. The fully differential operational amplifier is a low-noise, low-power operational amplifier A used for biosignal detection. The capacitive negative feedback loop includes a first negative feedback capacitor C electrically connected between the positive input terminal and the negative output terminal of the fully differential operational amplifier. 2p And a second negative feedback capacitor C electrically connected between the negative input terminal and the positive output terminal. 2nThe first negative feedback capacitor is connected to the negative output terminal by a CMOS switch S5, and the second negative feedback capacitor is connected to the positive output terminal by a CMOS switch S6; the resistive negative feedback loop includes a first negative feedback resistor R electrically connected between the positive input terminal and the negative output terminal of the fully differential operational amplifier. P and the second negative feedback resistor R electrically connected between the negative input terminal and the positive output terminal. n The input capacitor includes a first input capacitor C connected to the positive input terminal of the reconfigurable instrumentation amplifier and the positive input terminal of the fully differential operational amplifier. 1p And the second input capacitor C that connects the negative input terminal of the reconfigurable instrumentation amplifier to the negative input terminal of the fully differential operational amplifier. 1n The first input capacitor C 1p The second input capacitor C is connected in parallel with CMOS switch S3. 1n It is connected in parallel with CMOS switch S4. The adjustable positive feedback capacitor loop 12 consists of the first positive feedback capacitor pool C. PFp Second positive feedback capacitor pool C PFn The first positive feedback capacitor bank consists of capacitors connected to the positive output terminal, negative output terminal, and ground of the reconfigurable instrumentation amplifier via CMOS switches S9, S8, and S1. 12 The connection between each capacitor in the second positive feedback capacitor bank and the negative output terminal, positive output terminal, and ground of the reconfigurable instrumentation amplifier is achieved via a CMOS switch S. 10 S7, S 11 Connection; all CMOS switches contained in the positive feedback capacitor bank are controlled by an on-chip automatic input impedance boosting circuit;

[0020] The adjustable gain amplifier is a low-noise, low-power amplifier G used for biosignal detection. Its input is connected to the output of a reconfigurable instrumentation amplifier, and its output is connected to the input impedance via an on-chip automatic boost circuit using a CMOS switch S. 13 Connected to the overall circuit output via CMOS switch S 14 Connected; in working mode, its gain is adjustable, and in calibration mode, its gain is fixed;

[0021] The on-chip automatic input impedance enhancement circuit 3 includes: a calibration signal coupling circuit 31, a peak-to-peak comparison circuit 32, and a counter 33. The calibration signal coupling circuit 31 includes a first coupling capacitor C connected to the positive input terminal of the reconfigurable instrumentation amplifier. Cp And a second coupling capacitor C connected to the negative input terminal of the reconfigurable instrumentation amplifier. Cn The first coupling capacitor is connected to the positive input terminal of the calibration input signal and the potential ground via a CMOS switch S. 17 S 15The connection, the second coupling capacitor, and the calibration input signal negative input terminal are connected via a CMOS switch S. 18 S 16 Connection. The coupling capacitor is connected to the calibration input signal in calibration mode and to ground in operating mode. The counter output controls the CMOS switch in the positive feedback capacitor cell;

[0022] The overall circuit is divided into a working mode and a calibration mode. In the working mode, the CAL signal is low, and Φa and Φ b When the signal is low, the signals to be detected, Vinp and Vinn, are connected to the circuit through CMOS switches S1 and S2. The calibration coupling capacitor is connected through CMOS switch S1. 15 S 16 Connected to ground, C PFp The capacitor cell is connected to the positive input and positive output terminals of the reconfigurable instrumentation amplifier via CMOS switch S9. PFn The capacitor cell is connected via a CMOS switch S 10 Connect the negative input and negative output terminals of the reconfigurable instrumentation amplifier, with CMOS switches S3 and S4 open, C 1p and C 1n Access circuit, C 2p and C 2n The CMOS switches S5 and S6 are connected to the output of the differential operational amplifier. 13 Disconnect, S 14 Closed, let C 1p and C 1n The capacitance value is C1, C 2p and C 2n The capacitance value is C2, C Cn and C Cp The capacitance value connected to the circuit is C. C C PFp and C PFn The capacitance value connected to the circuit is C. PF At this point, the amplification factor of the reconfigurable instrumentation amplifier is At this point, the gain of the adjustable gain amplifier is adjustable, and the output of the adjustable gain amplifier is disconnected from the on-chip automatic impedance boosting circuit. The input impedance of the overall circuit is then: To maximize the input impedance, C1+C must be satisfied. C =C PF (A0-1), where C PF Adjustable;

[0023] In calibration mode, the CAL signal is high, and Φa and Φ b The periodic transformation has the same period as the calibration signal, which is transmitted through a CMOS switch S.17 S 18 Connected to the calibration coupling capacitor, CMOS switches S1, S2, S 15 S 16 Disconnect, signal V to be detected inp V inn Disconnected from the circuit, the adjustable gain amplifier's gain is now fixed, and the CMOS switch S... 14 Disconnect, S 13 The output and input impedance of the closed, adjustable gain amplifier are automatically boosted by an on-chip circuit. The first structure of the reconfigurable instrumentation amplifier is: Φa is high level, Φ... b When the level is low, CMOS switches S3 and S4 are open, C 1p and C 1n Access circuit, C 2p and C 2n The output of the differential operational amplifier is connected via CMOS switches S5 and S6, and the positive feedback capacitor loop C... PFp and C PFn via CMOS switch S 12 S 11 When connected to ground, the gain of the reconfigurable instrumentation amplifier is: The second structure of the reconfigurable instrumentation amplifier is as follows: Φa is low level, Φ b For high level, C PFp The capacitor bank is connected to the positive input and negative output of the reconfigurable instrumentation amplifier via CMOS switch S8. PFn The capacitor bank is connected to the negative input and positive output of the reconfigurable instrumentation amplifier via CMOS switch S7. CMOS switches S3 and S4 are closed. 1p and C 1n Short-circuited, CMOS switches S5 and S6 open, C 2p and C 2n When the connection to the output of the differential amplifier is disconnected, the gain of the reconfigurable instrumentation amplifier is: When A a A b When they are equal, it is equivalent to That is, C1+C C =C PF (A0-1); that is, when the gains of the two structures are the same, the front-end circuit can reach its maximum input impedance. To compare the gains of the two structures, the output amplitudes of the two structures under the same input can be compared. Meanwhile, in calibration mode, there is no positive feedback loop in the two reconstruction structures of the instrumentation amplifier, and the first positive feedback capacitor pool C... PFp Second positive feedback capacitor pool C PFnIn the two reconstruction structures, the circuit is connected to ground and the negative feedback loop respectively. Throughout the calibration mode, the circuit remains in a stable state regardless of the change in the value of the positive feedback capacitor. The output of both structures is always a specific multiple of the input.

[0024] This invention designs a peak-to-peak value comparison circuit 32 to compare the output amplitudes of two structures and uses a counter to automatically adjust C. PF The value of the peak-to-peak value is adjusted to achieve the effect of automatically increasing the input impedance. The peak-to-peak value comparison circuit 32 includes a reusable peak-to-peak value detection circuit, a switched capacitor integrator, and a comparator.

[0025] Figure 2 This is a schematic diagram of the structure of an embodiment of the reusable peak-to-peak detection circuit of the present invention. The peak-to-peak comparison circuit includes: a reusable peak-to-peak detection circuit, a switched-capacitor integrator, and a comparator. The reusable peak-to-peak detection circuit includes a peak detection mode and a valley detection mode.

[0026] Peak detection mode: The gate of the positive input NMOS transistor M2 is connected to the output of the reusable peak-to-peak detection circuit through the CMOS switch S1, and its source is connected to the bias current source I. b1 The drain of the NMOS transistor M4 is connected to the PMOS transistor M4; the gate of the negative input NMOS transistor M1 is connected to the output of the adjustable gain amplifier via a CMOS switch, and its source is connected to the bias current source I. b1 The PMOS transistor M5 is connected to the PMOS transistor M3 via its drain; the gate of PMOS transistor M3 is connected to the gate of PMOS transistor M4, and its source is connected to the power supply potential; the gate of PMOS transistor M5 is connected to its drain and to the drain of the negative input transistor M1, and its source is connected to the power supply potential; the gate of PMOS transistor M6 is connected to the gate of PMOS transistor M5, and its drain is connected to the sampling capacitor C via CMOS switch S3. H Its source is connected to the power supply potential; the gate of the PMOS follower transistor M7 is connected to the drain of the PMOS transistor M6, and its drain is connected to the potential ground. Its source is connected to the gate of the positive input NMOS transistor M2.

[0027] Valley detection mode: The gate of the positive input PMOS transistor M9 is connected to the output of the reusable peak-to-peak detection circuit through the CMOS switch S2, and its source is connected to the bias current source I. b3 The connection is made between the drain of the NMOS transistor M and the drain of the NMOS transistor M. 11 Connections: The gate of the negative input PMOS transistor M8 is connected to the output of the adjustable gain amplifier via a CMOS switch, and its source is connected to the bias current source I. b3 The connection is made between the drain of the NMOS transistor M and the drain of the NMOS transistor M. 10 Connection; NMOS transistor M 10 The gate of the NMOS transistor M 11 The gate of the NMOS transistor is connected, and its source is connected to ground;12 The gate of the transistor is connected to its drain, and also to the drain of the negative input transistor M8, with its source connected to ground; NMOS transistor M 13 The gate of the NMOS transistor M 12 The gate is connected, and its drain is connected to the sampling capacitor C via CMOS switch S4. H Its source terminal is connected to ground; NMOS follower transistor M 14 The gate of the NMOS transistor M 13 The drain terminal is connected to ground, and the source terminal is connected to the gate of the positive input PMOS transistor M9.

[0028] One end of the sampling capacitor is connected to the common-mode potential, and the other end is connected to the gate of the PMOS follower transistor M7 and the NMOS follower transistor M7 respectively through CMOS switches S3, S4, S5, and S6. 14 The gate is connected to ground and the power supply potential.

[0029] Figure 3 This is a schematic diagram of the timing and input / output signal relationship provided by an embodiment of the reusable peak-to-peak detection circuit of the present invention; in valley detection mode, Φ v1 To achieve a high level, connect the sampling capacitor to the power supply potential, then Φ v2 When the signal is high, connect the sampling capacitor to M. 13 The drain terminal is connected, at which point the circuit discharges the sampling capacitor, causing Φ to... out When set to high level, the circuit output is the valley value of the input signal; in peak detection mode, Φ p1 To achieve a high level, connect the sampling capacitor to ground, then Φ v1 When the signal is high, connect the sampling capacitor to the drain of M6. The circuit then charges the sampling capacitor, causing Φ to... out When set to low level, the circuit output is the peak value of the input signal;

[0030] Figure 4 This provides a structural and timing diagram of an existing switched-capacitor integrator circuit embodiment, consisting of a sampling capacitor C. S Integrating capacitor C int It consists of amplifier amp3; in Phase 1, the control signals S3 and S1 are the same, and the control signals S4 and S2 are the same. At this point, the transfer function of the switched capacitor is: In Phase 2, control signals S3 and S2 are the same, and control signals S4 and S1 are the same. At this time, the transfer function of the switched capacitor is: The transfer functions of the two states are opposites of each other, which can be used to add or subtract signals;

[0031] Figure 5This is a schematic diagram of the input-output signal relationship of the switched-capacitor integrator circuit of the present invention in calibration mode. As the reconfigurable instrumentation amplifier switches between the first and second structures in calibration mode, the first structure's output valley value V1, the first structure's output peak value P1, the second structure's output valley value V2, and the second structure's output peak value P2, amplified by the adjustable gain amplifier, are sequentially held and output by the reusable peak-to-peak detection circuit. The switched-capacitor integrator samples the signals held by the first sampling capacitor in both peak and valley detection modes, and then performs addition or subtraction operations to realize the operation of P1-V1-P2+V2. By comparing the output result of the switched-capacitor integrator with the common-mode level through a comparator, the magnitude relationship between P1-V1 and P2-V2 can be determined.

[0032] The calibration process will be described next. The calibration signal is a sine wave signal with a period of T. in The peak value is P, and the valley value is V. Taking two cycles of the calibration signal sine wave as an example, in the first cycle, the reconfigurable instrumentation amplifier is switched to the first structure, and the sine wave signal is amplified by the first structure reconfigurable instrumentation amplifier. By fixing the gain of the adjustable gain amplifier to G0, the calibration signal is amplified a total of times at the output of the adjustable gain amplifier. The reusable peak-to-peak detection circuit is first set to valley detection mode, Φ v2 It is high level, then Φ out When the signal is high, the valley value of the acquired sine wave signal is output. When switches S1 and S3 of the switched capacitor are closed, the valley voltage is sampled and stored in capacitor C. S Then, S1 and S3 are opened, and S2 and S4 are closed. The output of the switched capacitor is... At this point, the reset signal Φ of the peak-to-peak detection circuit can be reused. p1 The voltage level is high, which applies to the first sampling capacitor C. H A reset is performed, after which the peak-to-peak detection circuit can be reused and set to peak detection mode. Φ p2 It is high level, then Φ out When the signal is low, the peak value of the acquired sine wave signal is output. When switches S1 and S4 of the switched capacitor are closed, the valley voltage is sampled. Then, switches S1 and S4 are opened, and switches S2 and S3 are closed. The output of the switched capacitor is... At this point, the reset signal Φ of the peak-to-peak detection circuit can be reused. v1 The voltage level is high, which applies to the first sampling capacitor C. H A reset is performed, after which the peak-to-peak detection circuit can be reused and set to valley detection mode.

[0033] In the second cycle, the reconfigurable instrumentation amplifier is switched to the second structure. The sinusoidal signal is amplified by the second structure and the adjustable gain amplifier, and is amplified in total at the output of the reconfigurable instrumentation amplifier in the second structure. The gain of the adjustable gain amplifier is fixed at G0; the reusable peak-to-peak detection circuit is first set to valley detection mode, Φ v2 It is high level, then Φ out When the signal is high, the valley value of the acquired sine wave signal is output. When switches S1 and S4 of the switched capacitor are closed, the valley voltage is sampled and stored in capacitor C. S Then, S1 and S4 are opened, and S2 and S3 are closed. The output of the switched capacitor is... At this point, the reset signal Φ of the peak-to-peak detection circuit can be reused. p1 The voltage level is high, which applies to the first sampling capacitor C. H A reset is performed, after which the peak-to-peak detection circuit can be reused and set to peak detection mode. Φ p2 It is high level, then Φ out When the signal is low, the peak value of the acquired sine wave signal is output. When switches S1 and S3 of the switched capacitor are closed, the valley voltage is sampled. Then, switches S1 and S3 are opened, and switches S2 and S4 are closed. The output of the switched capacitor is... At this point, the reset signal Φ of the peak-to-peak detection circuit can be reused. v1 The voltage level is high, which applies to the first sampling capacitor C. H A reset is performed, after which the peak-to-peak detection circuit can be reused and set to valley detection mode.

[0034] After the second cycle, the final output of the switched capacitor circuit is: At this point, the comparator compares the output of the switched-capacitor integrator with the common-mode level. The comparator outputs 1, at this time Conversely, the comparator outputs 0. After the comparison is complete, the reset signal of the switched capacitor is high, the circuit is reset, and the output voltage is the common-mode voltage. The counter initially outputs 0, and the output controls the switch in the positive feedback capacitor pool. Initially, no positive capacitor is connected to the circuit. When the comparator output is detected to be high, the counter output value increments by 1, and the positive feedback capacitor connected to the circuit increases by 1 LSB. The positive feedback capacitor connected to the circuit continues to increase until... When the comparator outputs 0, the counter output stops changing, the calibration is complete, and a definite counter output is finally obtained.

[0035] After calibration is complete, the CAL signal goes low, and the circuit will switch to operating mode. The input of the reconfigurable instrumentation amplifier is disconnected from the calibration coupling circuit and connected to the normal signal input. The coupling capacitor is connected to ground to maintain the counter output obtained during the calibration operation, i.e., to maintain the state of the adjustable positive feedback capacitor connected to the reconfigurable instrumentation amplifier. The output of the adjustable gain amplifier is disconnected from the on-chip automatic input impedance boosting circuit, allowing normal amplification of the input signal.

[0036] It should be noted that comparing the peak-to-peak values ​​of the two structures is equivalent to comparing... and The equivalent input impedance is maximized when the two values ​​are equal. To reduce the influence of the amplifier's output DC signal, the peak-to-peak values ​​of the outputs of the two structures are compared in this embodiment of the invention.

[0037] Finally, the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high input impedance biomedical front-end detection circuit, characterized in that, It includes a reconfigurable instrumentation amplifier, an adjustable gain amplifier, and an on-chip automatic input impedance boosting circuit; the circuit has an operating mode and a calibration mode; wherein, A reconfigurable instrumentation amplifier for amplifying input biological signals at a fixed gain in operating mode; An adjustable gain amplifier is used to amplify biological signals of different amplitudes with adjustable gain in the said operating mode. An on-chip automatic input impedance enhancement circuit is used to automatically adjust the positive feedback capacitor value of the reconfigurable instrumentation amplifier in calibration mode by controlling the reconfigurable instrumentation amplifier to switch to the first structure and the second structure, and comparing the peak-to-peak output values ​​of the two structures, so as to enhance the input impedance of the front-end circuit. A fully differential gain circuit is used to amplify an input signal with a fixed gain. An adjustable positive feedback capacitor loop is used to increase the input impedance of the amplifier; The fully differential gain circuit of the reconfigurable instrumentation amplifier includes a fully differential operational amplifier, a capacitive negative feedback loop, a resistive negative feedback loop, and an input capacitor. The fully differential operational amplifier is a low-noise, low-power operational amplifier used for biosignal detection. The capacitive negative feedback loop includes a first negative feedback capacitor electrically connected between the positive input terminal and the negative output terminal of the fully differential operational amplifier, and a second negative feedback capacitor electrically connected between the negative input terminal and the positive output terminal. The first negative feedback capacitor is connected to the negative output terminal by a CMOS switch one, and the second negative feedback capacitor is connected to the positive output terminal by a CMOS switch two. The resistive negative feedback loop includes a first negative feedback resistor electrically connected between the positive input terminal and the negative output terminal of the fully differential operational amplifier, and a second negative feedback resistor electrically connected between the negative input terminal and the positive output terminal. The input capacitor includes a first input capacitor connected between the positive input terminal of the reconfigurable instrumentation amplifier and the positive input terminal of the fully differential operational amplifier, and a second input capacitor connected between the negative input terminal of the reconfigurable instrumentation amplifier and the negative input terminal of the fully differential operational amplifier. The first input capacitor is connected in parallel with CMOS switch three, and the second input capacitor is connected in parallel with CMOS switch four. The adjustable positive feedback capacitor loop of the reconfigurable instrumentation amplifier consists of a first positive feedback capacitor pool and a second positive feedback capacitor pool. In the first positive feedback capacitor pool, one end of each capacitor is connected to the positive input port of the reconfigurable instrumentation amplifier, and the other end is connected to the positive output port, negative output port, and ground of the reconfigurable instrumentation amplifier via CMOS switches. In the second positive feedback capacitor pool, one end of each capacitor is connected to the negative input port of the reconfigurable instrumentation amplifier, and the second end is connected to the negative output port, positive output port, and ground of the reconfigurable instrumentation amplifier via CMOS switches. All CMOS switches in the positive feedback capacitor pool are controlled by an on-chip automatic input impedance boosting circuit.

2. The high input impedance biomedical front-end detection circuit according to claim 1, characterized in that, The reconfigurable instrumentation amplifier includes: The input port, including a positive input terminal and a negative input terminal, is used to receive differential input biological signals; The output port, including a positive output terminal and a negative output terminal, is used to output the amplified differential input signal.

3. The high input impedance biomedical front-end detection circuit according to claim 1, characterized in that, The input port of the reconfigurable instrumentation amplifier is connected to the biosignal via a complementary metal-oxide-semiconductor (CMOS) transistor switch. This switch is turned on in the operating mode and turned off in the calibration mode.

4. The high input impedance biomedical front-end detection circuit according to claim 1, characterized in that, The reconfigurable instrumentation amplifier can be reconfigured into two structures in calibration mode. The first structure connects the first positive feedback capacitor bank to the positive input terminal and ground of the reconfigurable instrumentation amplifier, and the second positive feedback capacitor bank to the negative input terminal and ground. Switches three and four are open, and the first and second input capacitors are connected to the circuit. Switches one and two are closed, and the first and second negative feedback capacitors are connected to the output terminal of the fully differential operational amplifier. The second structure connects the first positive feedback capacitor bank to the positive input terminal and the negative output terminal of the reconfigurable instrumentation amplifier, and connects the second positive feedback capacitor bank to the negative input terminal and the positive output terminal of the reconfigurable instrumentation amplifier. Connect the terminals, close switches three and four to short-circuit the first and second input capacitors, and open switches one and two to disconnect the first and second negative feedback capacitors from the output of the fully differential operational amplifier. The reconfigurable instrumentation amplifier in operating mode has the following structure: the first positive feedback capacitor is connected to the positive input and positive output of the reconfigurable instrumentation amplifier, and the second positive feedback capacitor is connected to the negative input and negative output of the reconfigurable instrumentation amplifier. With switches three and four open, the first and second input capacitors are connected to the circuit. With switches one and two closed, the first and second negative feedback capacitors are connected to the output of the fully differential operational amplifier.

5. The high input impedance biomedical front-end detection circuit according to claim 1, characterized in that, The adjustable gain amplifier is a low-noise, low-power amplifier used for biosignal detection. In its operating mode, its gain is adjustable, which is used to amplify the signal output by the reconfigurable instrumentation amplifier at different gain rates in different gain modes. In calibration mode, its gain is fixed, which is used to amplify the outputs of different structures of the reconfigurable instrumentation amplifier by the same factor.

6. The high input impedance biomedical front-end detection circuit according to claim 1, characterized in that, The on-chip automatic input impedance enhancement circuit includes: A calibration signal coupling circuit is used to couple the calibration signal into the reconfigurable instrumentation amplifier; Peak-to-peak comparison circuit, used to compare the peak-to-peak values ​​of the outputs of two reconfigurable instrumentation amplifier structures; A counter is used to control a CMOS switch connected to a positive feedback capacitor bank, thereby adjusting the input impedance.

7. The high input impedance biomedical front-end detection circuit according to claim 6, characterized in that, The calibration signal coupling circuit of the on-chip automatic input impedance enhancement circuit includes a first coupling capacitor connected to the positive input terminal of the reconfigurable instrumentation amplifier and a second coupling capacitor connected to the negative input terminal of the reconfigurable instrumentation amplifier. Both coupling capacitors are connected to the calibration input signal and the potential ground by CMOS switches. The coupling capacitors are connected to the calibration input signal in calibration mode and to the potential ground in operating mode.

8. The high input impedance biomedical front-end detection circuit according to claim 6, characterized in that, The on-chip automatic input impedance enhancement circuit's peak-to-peak comparison circuit includes a reusable peak-to-peak detection circuit, a switched-capacitor integrator, and a comparator. The reusable peak-to-peak detection circuit includes a peak detection mode circuit, a valley detection mode circuit, and a sampling capacitor. The peak detection mode circuit and the valley detection mode circuit are symmetrical and reuse a single sampling capacitor. The peak detection mode circuit includes two input NMOS transistors, two sets of PMOS current mirror structures, a bias current source, and a PMOS follower transistor. The input NMOS transistors include a first positive-input NMOS transistor and a first negative-input NMOS transistor. The two sets of PMOS current mirror structures include a first PMOS transistor... The system includes a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The bias current source includes a first bias current source and a second bias current source. The gate of the first positive input NMOS transistor is connected to the output of the reusable peak-to-peak detection circuit via a CMOS switch S1. Its source is connected to the first bias current source, and its drain is connected to the first PMOS transistor. The gate of the first negative input NMOS transistor is connected to the output of the adjustable gain amplifier via a CMOS switch S2. Its source is connected to the first bias current source, and its drain is connected to the second PMOS transistor. The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, and its source is connected to the power supply potential. The gate of the third PMOS transistor is connected to its drain and to the drain of the first negative input transistor, and its source is connected to the power supply potential; the gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor, its drain is connected to the sampling capacitor through CMOS switch S3, and its source is connected to the power supply potential; the gate of the PMOS follower transistor is connected to the drain of the fourth PMOS transistor, its drain is connected to the potential ground, and its source is connected to the gate of the first positive input NMOS transistor. The valley detection mode circuit includes two input PMOS transistors, two sets of NMOS current mirror structures, a bias current source, and an NMOS follower transistor. The input PMOS transistors include a first positive input PMOS transistor and a first negative input PMOS transistor. The two sets of NMOS current mirror structures include a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The bias current source includes a third bias current source and a fourth bias current source. The gate of the first positive input PMOS transistor is connected to the output of the reusable peak-to-peak detection circuit via a CMOS switch, its source is connected to the third bias current source, and its drain is connected to the first NMOS transistor. The gate of the first negative input PMOS transistor is connected to the output of the adjustable gain amplifier via a CMOS switch S2, and its source is connected to the third bias current source. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor; the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, and its source is connected to ground; the gate of the third NMOS transistor is connected to its drain and to the drain of the first negative input transistor, and its source is connected to ground; the gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, its drain is connected to the sampling capacitor through CMOS switch S4, and its source is connected to ground; the gate of the NMOS follower transistor is connected to the drain of the fourth NMOS transistor, its drain is connected to ground, and its source is connected to the gate of the first positive input PMOS transistor; one end of the sampling capacitor is connected to the common-mode potential, and the other end is connected to the power supply potential, ground, the gate of the PMOS follower transistor, and the gate of the NMOS follower transistor through CMOS switches S3, S4, S5, and S6, respectively.

9. A high input impedance biomedical front-end detection circuit according to claim 8, characterized in that, The on-chip automatic input impedance boosting circuit's switched capacitor integrator includes four sampling CMOS switches, a first reset switch, a first sampling capacitor, a first integrating capacitor, and a differential input single-ended output operational amplifier. The first sampling switch is connected to the reusable peak-to-peak detection circuit, and its other end is connected to the second sampling switch. The second and third sampling switches are connected through the first sampling capacitor. The other ends of the second and third sampling switches are both connected to ground. One end of the fourth sampling switch is connected to the third sampling switch, and the other end is connected to the negative input terminal of the differential input single-ended output operational amplifier. The negative input terminal and output terminal of the differential input single-ended output operational amplifier are connected through the first integrating capacitor, and its positive input terminal is connected to the common-mode potential. The first reset switch is connected in parallel with the first integrating capacitor. The comparator is a low kickback noise comparator. Its negative input terminal is connected to the output terminal of the switched capacitor integrator, its positive input terminal is connected to the common-mode potential, and its output terminal is connected to the input terminal of the counter. The input terminal of the counter is connected to the output of the comparator and the clock control signal. The output bit is connected to the gate of the CMOS switch in the positive feedback capacitor pool to control whether the switch is turned on or off.

10. An on-chip automatic input impedance enhancement method for a front-end sampling circuit, applied to the front-end detection circuit as described in any one of claims 1-8, wherein the front-end sampling circuit includes a reconfigurable instrumentation amplifier, an adjustable gain amplifier, and an on-chip automatic input impedance enhancement circuit; the on-chip automatic input impedance enhancement method is characterized in that, Include: Adjust the circuit to calibration mode, input the sine wave calibration signal into the reconfigurable instrumentation amplifier, and fix the gain of the adjustable gain amplifier. The reconfigurable instrumentation amplifier is switched between the first and second structures by the calibration signal period; The different outputs of the two reconfigurable instrumentation amplifier structures are amplified by the same factor using a fixed-gain adjustable-gain amplifier; The peak-to-peak value of the output signal of the adjustable gain amplifier is compared, and the output value of the counter is adjusted accordingly. The value of the positive feedback capacitor in the input circuit is adjusted by the output of the counter until the peak-to-peak values ​​of the two structures of the reconfigurable instrumentation amplifier are equal. Adjust the circuit to the working mode, disconnect the calibration signal from the circuit, connect the biological signal to be detected to the circuit, adjust the reconfigurable instrumentation amplifier to the working mode, and adjust the gain of the adjustable gain amplifier according to the amplification factor.

11. The method for automatically increasing the input impedance on-chip for a front-end sampling circuit according to claim 10, characterized in that, The frequency of the sinusoidal calibration signal needs to be less than the circuit bandwidth.

12. The method for automatically improving the input impedance of a front-end sampling circuit on-chip according to claim 10, characterized in that, The peak-to-peak comparison method is as follows: as the reconfigurable instrumentation amplifier switches between its first and second structures in the calibration mode, the valley value V1, peak value P1, valley value V2, and peak value P2 of the first structure output of the reconfigurable instrumentation amplifier, amplified by the adjustable gain amplifier, are sequentially maintained by the valley detection mode and peak detection mode of the reusable peak-to-peak detection circuit. The switched capacitor integrator samples V1, P1, V2, and P2 respectively, and then performs addition or subtraction operations to realize the operation of P1-V1-P2+V2. The output result of the switched capacitor integrator is compared with the common-mode level through a comparator to determine the relationship between the magnitudes of P1-V1 and P2-V2.

13. The method for automatically improving the input impedance of a front-end sampling circuit on-chip according to claim 10, characterized in that, The counter is adjusted as follows: when the output of the comparator is detected to be 1 at the rising edge of the input clock, the counter is incremented by one; when the output of the comparator is detected to be 0 at the rising edge of the input clock, the counter output remains unchanged. The final output codeword will cause the positive feedback compensation to stop at the critical value of the compensation, at which point P1-V1 and P2-V2 are equal.

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