SRAM with burst mode address comparator

Abstract

A memory is provided that is configured to implement both a normal read operation and a burst mode read operation. A burst mode address comparator compares a current row address with a previous row address to determine whether the read operation is a normal read operation or a burst mode read operation.

Description

[0001] Priority claim under 35 USC §119

[0002] This patent application claims priority to non-provisional application No. 16 / 523,768, filed on July 26, 2019, entitled “SRAM WITH BURST MODE ADDRESS COMPARATOR,” which is assigned to the assignee hereof and is hereby expressly incorporated by reference. Technical Field

[0003] The present application relates to a memory, and more particularly to a low-power memory. Background Art

[0004] In a traditional static random access memory (SRAM), a bit cell is connected to a bit line pair during a read operation. Prior to the read operation, the bit line is precharged to the supply voltage for the bit cell. Depending on the binary content of the bit cell, the bit cell will slightly discharge either the true or complement bit line in the bit line pair from its precharged state. For example, suppose the bit cell is storing a binary one. During a read operation, the word line is asserted, coupling the bit cell to its bit line pair. Due to the binary one value, the complement bit line will be discharged from its precharged state. However, the bit cell will maintain the true bit line in its precharged state. Therefore, the read operation generates a voltage difference across the bit line pair. This bit line voltage difference is not full rail, but rather a fraction of the supply voltage. For example, if the supply voltage is one volt, the voltage difference may be only 100 millivolts or less. To respond to this relatively small voltage difference and make a bit decision about the contents stored in the bit cell, a typical sense amplifier requires a relatively large gain.

[0005] Thus, there is a need in the art for memories with increased density and improved power efficiency. Summary of the Invention

[0006] A memory is disclosed, comprising a plurality of latches configured to store a previous row address of the memory; a first plurality of logic gates configured to assert a bit comparison word in response to a current row address of the memory being equal to the previous row address; a first transistor having a terminal coupled to a burst mode node for a burst mode signal; and a second plurality of logic gates configured to turn on the first transistor to ground the burst mode node in response to assertion of the bit comparison word.

[0007] In addition, a burst mode method for a memory is disclosed, including: precharging a sense amplifier in a first read cycle; latching a bit decision in the sense amplifier after the precharging in the first read cycle; in a second read cycle after the first read cycle, asserting a burst mode signal for a portion of the second read cycle in response to a row address of the second read cycle being equal to the row address of the first read cycle; and in response to asserting the burst mode signal, transferring the bit decision latched in the sense amplifier to a data output latch during the second read cycle without precharging the sense amplifier.

[0008] Finally, a memory is disclosed, comprising word lines; a plurality of columns, each of the plurality of columns comprising a bit cell at an intersection of the column and the word line, a sense amplifier, and a bit line coupled to a sense node of the sense amplifier through a charge transfer transistor; a burst mode address comparator configured to determine, for a series of read cycles, whether each read cycle is a burst mode read cycle or a normal read cycle; and a bit line precharge circuit configured to precharge the bit line in each column in each normal read cycle, wherein the bit line precharge circuit is further configured not to precharge the bit line in each column in each burst mode read cycle.

[0009] These and additional advantages will be better appreciated from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An SRAM including a burst mode address comparator for invoking a burst mode of operation is illustrated according to one aspect of the present disclosure.

[0011] Figure 2 Illustrated is a diagram of a system in which column multiplexing is 4:1 multiplexing according to one aspect of the present disclosure. Figure 1 SRAM modification.

[0012] Figure 3 is a circuit diagram of an example burst mode address comparator according to one aspect of the present disclosure.

[0013] Figure 4 yes Figure 2 Timing diagram of various signals in SRAM.

[0014] Figure 5 is a flow chart of a burst mode address comparison method according to one aspect of the present disclosure.

[0015] Figure 6 Several example electronic systems, each incorporating an SRAM with burst mode address comparison, are illustrated according to one aspect of the present disclosure.

[0016] Embodiments of the present disclosure and their advantages are best understood by referring to the following detailed description.It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures of the drawings. DETAILED DESCRIPTION

[0017] A memory such as an SRAM is provided with a plurality of bit cells arranged in rows and columns. Each column has a corresponding bit line pair. Each row has a corresponding word line. At the intersection of each row and each column, there is a corresponding bit cell in the bit cell. Before a normal (non-burst mode) read operation, the bit line pair of the column is precharged to the memory supply voltage. The clock signal then triggers the self-timing clock circuit to assert the word line of the addressed row in the row. The asserted word line turns on the access transistor of the row so that the bit cell in the addressed row can affect the precharge state of the bit line. Depending on the binary content of the addressed bit cell, one of the bit lines in each bit line pair is discharged to slightly below the memory supply voltage, while the second bit line in each bit line pair remains charged to the memory supply voltage.

[0018] Each column has its own sense amplifier, which latches a bit decision based on the voltage difference across the column's bit line pair when the word line voltage is asserted. The columns are arranged into multiplexed column groups. Each column includes a bit cell at the intersection of an asserted word line and the multiplexed column group. These bit cells form a bit cell group at the intersection of the multiplexed column group and the word line, so that only the column address of the bit cell varies across the multiplexed column group. Each multiplexed column group includes a column multiplexer that selects from the group's columns to drive the corresponding data output latch. The column multiplexer's selection depends on the column address. Each sense amplifier includes a pair of sense amplifier nodes for coupling to the column's bit line during the sense enable period in normal read operation. The sense amplifier nodes are precharged before normal read operation, although this precharge can be grounded, in contrast to the precharge of the bit lines. A normal read operation ends with the bit decision from the addressed column latched in the data output latch.

[0019] Whether consecutive read operations are normal read operations or burst mode read operations depends on whether the addresses for the consecutive read operations point to the same row. Note that during a normal read operation, each sense amplifier in the addressed multiplexed column group latches the bit decision for the bit cell group. If the address of the same row is the same as in the previous read operation, the burst mode address comparator disclosed herein advantageously invokes burst mode for consecutive read operations. In this way, the latched bit decision from the previous read operation is utilized without re-asserting the word line. Likewise, the bit line is not pre-charged, nor is the sense amplifier node pre-charged, thereby reducing power consumption.

[0020] Before the burst mode address comparator invokes burst mode, a normal read operation should occur so that the sense amplifiers latch their bit decisions. Once a normal read operation occurs, burst mode can be invoked again and again as long as the same row is addressed. For example, assume that four columns are multiplexed and the initial normal read operation occurs on the first of the four columns. If consecutive read operations are directed to the same row, burst mode is activated. For example, the second of the four columns can be read in the first burst mode read operation. Then, the third of the four columns can be read in the second burst mode read operation, and so on. During burst mode operation, the word lines, bit lines, and sense amplifier nodes are not precharged, which greatly reduces power consumption.

[0021] Generally speaking, column addresses are typically smaller than row addresses because column multiplexing is typically smaller than the number of rows. For example, for an embodiment with 4:1 column multiplexing, only two address bits are required to identify the addressed column. In contrast, in an embodiment with 128 rows, the row address may be 7 bits used to identify the addressed row. Therefore, the following discussion assumes that the row address bits are the most significant bits, while the column address bits are the least significant bits. In this embodiment, the burst mode address comparator is therefore used to determine whether the most significant bit of the read address of the current read operation is equal to the most significant bit of the read address in the previous read operation. More generally, the burst mode address comparator is used to determine whether the row address portion of the current read address is equal to the row address portion of the previous read address. If the row addresses are equal, the burst mode address comparator invokes burst mode for the current read cycle. If the row addresses are not equal, the burst mode address comparator does not invoke burst mode for the current read cycle.

[0022] The following discussion will be directed to advantageous charge transfer embodiments for implementing the burst mode invoked by the burst mode address comparison disclosed herein. However, it should be appreciated that the burst mode address comparison disclosed herein can be implemented by memories that do not implement charge transfer. As noted above, each column in a multiplexed column group has its own sense amplifier. However, because the charge transfer operation is implemented through the control of charge transfer transistors, the lack of multiplexing a single sense amplifier across multiple columns does not hinder density. Each bit line of a column is coupled to the sense amplifier node of the column's sense amplifier through a charge transfer transistor. The source of each charge transfer transistor is coupled to its bit line, and the drain of each charge transfer transistor is coupled to its sense amplifier node. Therefore, the gate-source voltage of each charge transfer transistor is determined by its gate voltage and its bit line voltage. The following discussion will assume that each charge transfer transistor is a p-type metal oxide semiconductor (PMOS) transistor, but it should be appreciated that charge transfer can also be accomplished using n-type metal oxide semiconductor (NMOS) transistors.

[0023] Before the wordline assertion of the initial normal read operation, the bitline is precharged to the supply voltage, while the sense amplifier nodes are fully discharged. The wordline is then asserted during the wordline assertion period, during which a bitline voltage difference is generated for each bitline pair, depending on the bit stored in each bit cell at the intersection of the wordline and the bitline pair of the multiplexed column group. Depending on the bit, either the true bitline or the complement bitline in each bitline pair is slightly discharged from the precharged state (supply voltage). The resulting bitline voltage difference is not full rail, but only a fraction of the supply voltage (e.g., approximately 100 mV). To make a bit decision from this relatively small bitline difference, a high-gain sense amplifier is conventionally required. Such a high-gain sense amplifier requires a large amount of die space, so it is typically multiplexed across the column group. However, the charge transfer technique discussed herein results in amplification of the bitline voltage difference across the sense node pairs of the bitline pair. Because of this amplification, the resulting sense amplifier does not need high gain, but can be implemented with a relatively dense reset-set (RS) latch with relatively low power consumption.Thus, each column can have its own sense amplifier.

[0024] Charge transfer occurs during a charge transfer period that begins near the end of the wordline assertion period. Prior to the charge transfer period, the gate voltage of each charge transfer transistor is maintained at the power supply voltage, turning off each charge transfer transistor. The charge transfer period is delayed relative to the assertion of the wordline to allow a bitline voltage difference to develop for each bitline pair. During the charge transfer period, the gate voltage of the charge transfer transistor drops from the power supply voltage to ground at a certain slew rate. For example, a relatively small inverter or dummy bitline voltage can be used to control the gate voltage of the charge transfer transistor. Depending on the bit value being read, either the true bitline or the complement bitline in each bitline pair will drop slightly from its pre-charged state (power supply voltage). This bitline is referred to as a partially charged bitline in the following discussion. However, the remaining bitline in each bitline pair will remain charged to the power supply voltage. This bitline is referred to as a fully charged bitline in the following discussion.

[0025] The gate voltage of each charge-transfer transistor in the multiplexed column group decreases during the charge transfer period so that the gate-source voltage (gate-bitline voltage) of the charge-transfer transistor of the fully charged bitline meets its threshold voltage. However, the decrease in the voltage of the partially charged bitline causes this same gate voltage to not meet the threshold voltage of the charge-transfer transistor of the partially charged bitline. Therefore, only the charge-transfer transistor of the fully charged bitline in the bitline pair initially conducts charge to its sense node. The capacitance of the sense node is relatively small compared to the capacitance of the bitline, so the resulting charge transfer causes the sense node to be charged nearly to the supply voltage. In contrast, the sense node of the partially discharged bitline remains in its discharged default state, resulting in the voltage difference between the sense nodes of the accessed bitline pair being nearly full rail (the voltage difference is nearly equal to the supply voltage). Therefore, the charge transfer causes the relatively small bitline voltage difference to be amplified to a voltage difference at the sense node that is close to full rail, allowing the sense amplifier to be a relatively compact and low-power RS ​​latch, such as one formed by a cross-coupled NAND gate pair. Sensing by the sense amplifier occurs during the sense enable period.

[0026] Because each column has its own sense amplifier, the charge transfer period and sense latch bit decisions for all columns in the multiplexed column group during the initial read operation on the first bit cell. A burst mode address comparator is disclosed that selects a burst mode read operation if a subsequent read operation is for another column in the multiplexed column group (assuming the same word line is involved). For example, if the multiplexed column group has four columns, there may be four bit cells at the intersection of a word line and the four columns. More generally, there are bit cell groups corresponding to the intersections of word lines and the multiplexed column group. During the initial read operation on a bit cell in the bit cell group, the burst mode address comparator will detect that a previous read operation has been performed on a bit cell outside the bit cell group. With respect to identifying whether a read address corresponds to a bit cell group, it is noted that the addresses of the bit cells in the bit cell group will be substantially similar. For example, if the bit cell group is four bit cells, the individual bit cell read addresses will each differ by only two bits. The remaining bits in the read address identify the wordline and are therefore the same for every bitcell in the bitcell group.

[0027] To identify whether the current read address and the previous read address point to the same bit cell group, the burst mode address comparator only needs to determine that the two addresses identify the same word line. The remaining bits in the read address depend on which specific bit cell is being addressed within the bit cell group. The position of these bits in the read address depends on the addressing convention. The following discussion will assume, without loss of generality, that it is the least significant bit (LSB) that identifies the bit cell within the bit cell group. Therefore, the burst mode address comparator in this embodiment may activate a burst mode read operation when it determines that the most significant bit (MSB) of the current read address and the previous read address are the same. As long as burst mode is activated, each consecutive read operation is performed simply by selecting the appropriate column in the multiplexed column group through the column multiplexer. For these additional burst mode read operations, the word line is not asserted, and the bit line and sense node are not pre-charged, providing advantageous power savings. Now, some example implementations are described in more detail.

[0028] Figure 1 , an example SRAM 100 is shown, which includes a burst mode address comparator 101. A bit line pair of bit line b1 and complement bit line b1b forms a first column. Bit cell 105 is located at the intersection of the first column and word line w1. Bit cell 105 is formed by a cross-coupled pair of inverters. The output node of the first inverter in the inverter is the true (Q) output of bit cell 105. This output node is coupled to bit line b1 through NMOS access transistor M4. Similarly, the output node of the remaining second inverter in the inverter is the complement (QB) output of bit cell 105, and the QB output is coupled to the complement bit line b1b through NMOS access transistor M3. Word line w1 is coupled to the gate of the access transistor so that the Q node and QB node drive their respective bit lines during the word line assertion period.

[0029] SRAM 100 includes a second column having a bit cell at its intersection with word line w1. Since the second column is a repeat of the structure in the first column, for clarity of illustration, Figure 1 The details of the second column are not shown. The two columns are multiplexed by column multiplexer 125. If a (burst or non-burst) read operation is directed to bit cell 105, column multiplexer 125 selects the sense amplifier output from sense amplifier 110 of the first column. For example, column multiplexer 125 may include a tri-state buffer 130 for the first column and a tri-state buffer 135 for the second column. The tri-state buffers of the unselected columns are tri-stated to form a selection in column multiplexer 125. The output of column multiplexer 125 is latched in data output latch 140.

[0030] The bit cell 105 of the first column and the corresponding bit cell in the second column form a bit cell group that shares a common address identifying word line w1 and a multiplexed column group. Only the column address changes within the bit cell group. Regardless of whether the read operation occurs in burst mode, each read operation responds to a clock cycle such as a clock cycle for memory clock signal 102. Assume that a first memory clock cycle corresponds to a read operation involving a different word line and / or column, and that the first memory clock cycle is followed by a second memory clock cycle in which the read operation is directed to bit cell 105. For this second read operation, burst mode is not activated by burst mode address comparator 101 because the previous address decoded in the first memory clock cycle identifies a different word line and / or a different multiplexed column group.

[0031] Before the word line is asserted during a normal read operation, the bit lines b1 and b1b are precharged to the supply voltage by the bit line precharge circuit 150. This precharging of the bit lines is conventional, and therefore, the details of the bit line precharge circuit 150 are not described herein. Figure 1 . The timing of various actions, such as precharging the bit lines, the pulse width of word line assertion, and enabling of the sense amplifier 110 during a read operation, is controlled by a self-timed clock circuit 155, as triggered by the memory clock signal 102. The timing of these actions during normal read operations is conventional. However, the self-timed clock circuit 155 is modified from this conventional functionality to accommodate burst mode. Thus, the self-timed clock circuit 155 responds to a burst mode signal, such as an active-low burst mode signal 145 (burst_n), so that the word lines are not asserted, the bit lines are not precharged, and the charge transfer transistors are not turned on during burst mode operations.

[0032] To control whether burst mode is active, burst mode address comparator 101 asserts or deasserts burst mode signal 145. As used herein, a signal is said to be "asserted" when it has a logically true state, regardless of whether the logically true state is active high or active low. In an alternative embodiment, the burst mode signal can instead be an active high signal. If burst mode address comparator 101 does not assert burst mode signal 145, SRAM 100 implements a normal read operation, in which the second memory clock cycle triggers self-timing clock circuit 155 to charge the voltage of word line w1. Before the word line is asserted, bit lines b1 and b1b are precharged to the power supply voltage by bit line precharge circuit 150. After the bit line precharge, bit line precharge circuit 150 floats the bit lines. Bit line b1 is coupled to the corresponding sense node s1 of sense amplifier 110 via PMOS charge transfer transistor P1. Similarly, complement bit line b1b is coupled to the corresponding sense node s1b via PMOS charge transfer transistor P2. Prior to wordline assertion, the gate voltage rm of the charge transfer transistor is charged to the supply voltage by the self-timing clock circuit 155 to prevent any charge from being transferred to the sense node. Since burst mode is not active, the self-timing clock circuit 155 charges the sense node pre-charge signal (cts_pre_n) to the supply voltage prior to wordline assertion. The charged sense node pre-charge signal drives the gates of NMOS transistor M1 and NMOS transistor M2. The sources of transistors M1 and M2 are connected to ground, while their drains are connected to the complementary sense node s1b and sense node s1, respectively. Since both transistors M1 and M2 are turned on to couple their respective bit lines to ground, assertion of the sense node pre-charge signal discharges both sense node s1 and sense node s1b of the first column. As previously noted, the structure of the second column is identical to that shown in the first column.

[0033] Therefore, both columns will discharge their sense nodes and precharge their bit lines before the word lines are asserted for normal read operations where burst mode is not active. However, if a subsequent read operation is directed to the second column, burst mode address comparator 101 activates burst mode by asserting burst mode signal 145. Self-timed clock circuit 155 responds to assertion of burst mode signal 145 by preventing word line w1 from being asserted. Similarly, gate voltage signal rm is maintained at the supply voltage by self-timed clock circuit 155 during burst mode to prevent charge transfer transistors P1 and P2 from turning on. In addition, self-timed clock circuit 155 maintains sense amplifier pre-charge signal cts_pre_n at ground during burst mode read operations to prevent pre-charging of sense nodes s1 and s1b.

[0034] During a normal read operation, turning on access transistors M4 and M3 by asserting the wordline voltage causes one of bitlines b1 or b1b to slightly discharge from its pre-charged state, depending on the binary content stored in bit cell 105. This slight bitline discharge is amplified during the charge transfer period, during which charge transfer transistors P1 and P2 are turned on as follows. The charge transfer period is triggered by the discharge of gate voltage rm. The discharge of gate voltage rm begins while the wordline voltage is still asserted. The discharge of gate voltage rm can end after the wordline voltage has discharged. The discharge of gate voltage rm has a slope to it. Due to this non-instantaneous discharge of gate voltage rm, gate voltage rm will discharge to the threshold voltage of the charge transfer transistor whose source is connected to the fully charged bitline, but will still be higher than the threshold voltage of the charge transfer transistor whose source is connected to the partially discharged bitline. Therefore, the charge transfer transistor of the fully charged bitline will conduct charge to its sense node before the other charge transfer transistor conducts charge from the partially discharged bitline. For example, assume that bit line b1 is a fully charged bit line such that charge transfer transistor P1 begins turning on before charge transfer transistor P2. Thus, sense node voltage s1 will increase before the increase of complement sense node voltage s1b.

[0035] Sense node s1 is connected to the input of NAND gate 115 in sense amplifier 110. Similarly, sense node s1b is connected to the input of NAND gate 120 in sense amplifier 110. NAND gates 115 and 120 are cross-coupled to form an RS latch. The zero volts precharged to the sense nodes causes both outputs of NAND gates 115 and 120 to be asserted high, equal to the supply voltage. The output of NAND gate 120 also forms the output terminal of the first column. The corresponding NAND gate in the second column (not shown) forms the output terminal of the second column. Compared to the bit line capacitance, conceptually represented by capacitor Cb1, the capacitance of the sense node, conceptually represented by capacitor Cs, is relatively small. Therefore, the brief amount of time that charge transfer transistor P1 begins conducting before charge transfer transistor P2 turns on causes the voltage of sense node s1 to increase significantly compared to sense node s1b. This voltage increase exceeds the threshold voltage of NAND gate 115, causing its output to discharge to zero. The zero output of NAND gate 115 enhances the binary high output of NAND gate 120 , causing the binary one value stored in bit cell 105 to be latched in sense amplifier 110 .

[0036] If the read operation is for the first column, column multiplexer 125 selects the output terminal of sense amplifier 110 in the first column, causing the binary content of bit cell 105 to be latched into data output latch 140 during the first memory cycle. Note, however, that the sense amplifiers in the second column also latch the bits stored in the remaining bit cells in the bit cell group. If a subsequent read operation is directed to these remaining bit cells, the bit sense is not discarded. Burst mode address comparator 101 detects that the address for the second read operation is directed to the same bit cell group and therefore triggers burst mode for the second memory clock cycle by asserting burst mode signal 145. In response to assertion of burst mode signal 145, self-timed clock circuit 155 prevents the word line w1 voltage from being charged during the second memory clock cycle. Similarly, self-timed clock circuit 155 prevents the sense node precharge signal from being asserted during the second memory clock cycle. Furthermore, self-timed clock circuit 155 prevents gate voltage rm from discharging due to the burst mode operation during the second memory clock cycle. Column multiplexer 125 then selects the second column through tri-state buffer 135 so that the bits from the bit cells of the second column can be stored in data output latch 140 .

[0037] To facilitate latching within sense amplifier 110, a sense node precharge signal drives the gate of PMOS transistor P5, whose source is tied to the power node for the power supply voltage. The drain of transistor P5 is connected to the sources of a pair of PMOS transistors, P4 and P3. The drain of transistor P4 is tied to sense node s1, while the drain of transistor P3 is tied to the complementary sense node s1b. The output of NAND gate 115 drives the gate of transistor P4. Similarly, the output of NAND gate 120 drives the gate of transistor P3. For example, assume that the output of NAND gate 115 is low. This low output turns on transistor P4, reinforcing the fully charged state of sense node s1, which in turn reinforces the zero output of NAND gate 115. Conversely, assume that the output of NAND gate 120 is low after the sense enable period. Then, transistor P3 may be turned on. Turning on transistor P3 reinforces the fully charged state of complementary sense node s1b, which in turn reinforces the zero output of NAND gate 120. In this manner, the latching of the sensed bit in the sense amplifier 110 is strengthened or enhanced.

[0038] It should be appreciated that the burst mode operation disclosed herein is not limited to any particular column multiplexing size. For example, Figure 2An SRAM 200 is shown in FIG, in which four columns are multiplexed by a column multiplexer 125, ranging from the first column CTS_Cell0 to the fourth column CTS_Cell3. Each column has a bit cell at the intersection of the column and the word line w1. The structure within each column is as discussed with respect to SRAM 100. For clarity of illustration, only the first column CTS_Cell0 is shown in detail. Since there are four columns in the multiplexed column group that shares the data output latch 140, there are four decoding bits bst_0, bst_1, bst_2, and bst_3 and their complements that control which column the column multiplexer 125 selects. The column multiplexer 125 is implemented by a tri-state buffer including a tri-state buffer 130, as discussed with respect to memory 100, but it should be appreciated that other types of column multiplexers can be used in SRAM 200. The gate voltage rm controls the pre-charge transistor in each column. Likewise, the sense node precharge signal (cts_pre_n) controls precharging of the sense node through transistors M1 and M2 in each column and latch boosting through transistors P3 , P4 , and P5 in each column, as discussed with respect to SRAM 100 .

[0039] Since there are four columns, only two bits (e.g., the two least significant bits) will be different for each bit cell address in the bit cell group. During the initial non-burst mode read operation, the discharge of the gate voltage rm can be performed by an inverter (not shown) in the self-timing clock circuit 155. The inverter is relatively small so that the discharge of the gate voltage rm has some transition, so the amplified bit line voltage difference occurs relative to the charge transfer to the corresponding sense node. Depending on which column is addressed, the corresponding bit from the addressed bit cell is selected by the column multiplexer 125 and latched into the data output latch 140. However, the sense amplifier 110 in each of the four columns latches its corresponding bit decision. If a subsequent read operation is directed to the same bit cell group, the burst mode address comparator 101 activates the burst mode.

[0040] Figure 3An embodiment 300 for a burst mode address comparator 101 is shown in more detail in FIG. The read address is n bits wide, ranging from the zeroth address bit Addr[0] to the (n-1)th address bit Addr[n-1]. Each address bit of the current read cycle is compared with the corresponding bit of the previous read cycle by a corresponding bit comparator 305. Thus, there is a bit comparator 305 for address bit Addr[0], a bit comparator 305 for address bit Addr[1], a bit comparator 305 for address bit Addr[2], and so on, until a final bit comparator 305 is provided for the final address bit Addr[n-1]. Each bit comparator 305 forms a one-bit output signal having a binary state that depends on the corresponding bit comparison. Since n-bit comparators 305 are used for n-bit wide read addresses, their one-bit output signals form an n-bit wide bit comparison word 321.

[0041] Each bit comparator 305 includes a master latch 310 and a slave latch 315, which continuously latch the corresponding bits from the read address. As used herein, the term "latch" refers to any suitable storage element that can be synchronous (e.g., a register or flip-flop) or asynchronous (e.g., a reset-set latch). The delay through the master-slave latch is one memory clock cycle, so that the address bit stored by the slave latch 315 is the address bit from the previous memory clock cycle. Each bit comparator also includes an XOR gate 320, which performs an exclusive OR operation on the current address bit and the corresponding previous address bit from its slave latch 315. Therefore, if the corresponding address bit is the same as the corresponding previous address bit, then the output signal from each XOR gate 320 is grounded. If the current memory read cycle points to the same bit unit group (same word line address), then the N-bit wide comparison word 321 is therefore all zero. Thus, the compare word is an active low signal that is asserted to invoke burst mode. In contrast, if the current memory read cycle does not target the same bit cell group that was addressed in the previous memory clock cycle, at least one of the bits in the N-bit wide compare word will be charged to the memory supply voltage. XOR gate 320 is an example of a first plurality of logic gates configured to assert the bit compare word in response to the current row address of the memory being equal to the previous row address.

[0042] Multiple OR gates 330 arranged in parallel process the N-bit-wide output signal formed by XOR gates 320. The XOR gates 320 are arranged into XOR gate groups so that the output bit from each group of XOR gates 320 drives the corresponding OR gate 330 in the OR gate 330. The input width of each OR gate 330 is three bits, but in alternative embodiments, this input width can be increased or decreased. The last OR gate 330 in the OR gate 330 also performs an OR operation on a delayed version of the memory clock signal 102, such as one delayed by an even number of inverters 340, to produce a delayed clock signal (cd). The output of the OR gate 330 is processed by a NOR gate 335. Therefore, the output of the NOR gate 335 will be high for a delay period after the rising edge of the memory clock signal 102 only when the row address of the current memory read cycle is equal to the row address of the previous memory read cycle. The length of the delay period is determined by the delay through the inverters 340. The output of the NOR gate 335 drives the gate of the NMOS transistor M5, whose source is connected to ground. Therefore, if the output of NOR gate 335 is high in response to the current row address matching the previous row address, the drain of transistor M5 will be grounded.Transistor M5 may also be denoted as a first transistor.

[0043] The drain of transistor M5 is connected to the source of NMOS transistor M6, which may also be represented as a second transistor. Since memory clock signal 102 drives the gate of transistor M6, the drain of transistor M6 is grounded in response to the rising edge of memory clock signal 102, while the current row address matches the previous row address, allowing two consecutive read operations. Once the delay period established by inverter 340 expires, the output of NOR gate 335 goes low, turning off transistor M5. The drain voltage of transistor M6 forms the burst mode node for burst mode signal 145. Therefore, if the current row address matches the previous row address, burst mode signal 145 is discharged to ground, signaling that burst mode is activated. A pulse latch 325, formed by a pair of inverters, latches burst mode signal 145. In one embodiment, OR gate 330 and NOR gate 335 are examples of a second plurality of logic gates configured to turn on the first transistor (M5) to ground the burst mode node in response to assertion of the bit comparison word.

[0044] For each successive read operation, the burst mode signal 145 is reevaluated. Therefore, the burst mode signal 145 should be reset by being charged to the memory supply voltage before the next cycle of the memory clock signal 102. For example, the burst mode signal 145 can be reset by a PMOS transistor P6, whose drain is connected to the drain of transistor M6. Transistor P6 can also be represented as a third transistor. The source of transistor P6 is connected to the power supply node of the memory supply voltage. If transistor P6 is turned on, the drain of transistor M6, and therefore the burst mode signal 145, will be charged to the memory supply voltage. The self-timing clock signal 345 generated by the self-timing clock circuit 155 drives the gate of transistor P6 to control whether the burst mode signal 145 is reset. The self-timing clock circuit 155 uses the falling edge of the self-timing clock signal 345 to trigger the release of the word line during normal read operations. Although the self-timing clock circuit 155 does not assert the word line during burst mode operation, the falling edge of the self-timing clock signal 345 is a convenient signal for controlling the resetting of the burst mode signal 145. In alternative embodiments, other suitable signals, such as the falling edge of the memory clock signal 102 , may be used to drive the gate of transistor P6 to control the resetting of the burst mode signal 145 .

[0045] Given the address comparator control for burst mode, now, regarding Figure 4 The timing of the various signals of the memory 200 is discussed. The memory clock signal 102 begins an initial read cycle at time t0. Because there is no previous read address for comparison, there is no burst mode in this clock cycle. The read address for this read cycle is an n-bit word. Since the memory 200 has 4:1 column multiplexing, the column address of the read operation in the memory 200 is two bits wide. Therefore, the row address portion of the read address in each read cycle of the memory 200 is the portion [n:2] of the n-bit wide read address. During the initial read cycle, the current address (CA) read address portion (2F) at time t0 is latched into the slave latch 315 ( Figure 3 Thus, the current read address portion 2F becomes the previous address (PA) for a subsequent read operation as triggered by the rising edge of the memory clock signal 102 at time t1.

[0046] During a normal read operation starting at time t0, the sense amplifier node is precharged by asserting the sense node precharge signal cts_pre_n as controlled by the self-timed clock circuit 155. The self-timed clock circuit 155 also asserts the active low gate voltage rm of the charge transfer transistor. The falling edge of the self-timed clock signal 345 triggers the de-assertion of the gate voltage rm.

[0047] The second read cycle is triggered by the rising edge of the memory clock signal 102 at time t1. The current row address of the second read cycle is FF, which is different from the previous row address 2F. The burst mode signal 145 remains unasserted by being maintained at the memory supply voltage, so that the second read cycle is also a normal read operation. Therefore, the same signal timing discussed in the first read cycle is repeated in the second read cycle.

[0048] The rising edge of memory clock signal 102 at time t2 initiates the third read cycle. The current row address FF is the same as the previous row address. Therefore, burst mode signal 145 is asserted low after the rising edge of memory clock signal 102 at time t2 to activate burst mode. Consequently, gate voltage rm and sense node pre-charge signal cts_pre_n are not asserted during the third read cycle. The falling edge of self-timing clock signal 345 resets burst mode signal 145 during the third read cycle.

[0049] The rising edge of memory clock signal 102 at time t3 triggers the fourth read cycle. The current row address FF is the same as the previous row address. Therefore, burst mode signal 145 is asserted low after the rising edge of memory clock signal 102 at time t3 to reactivate burst mode. Similarly, the row address of the fifth read cycle starting at time t4 is also FF, so burst mode is reactivated during the fifth read cycle.

[0050] Now, about Figure 5 The flowchart of FIG. 1 discusses a method for burst mode address comparison. The method includes act 500: precharging a sense amplifier in a first read cycle. Precharging s1 and s1b in memory 100 or 200 is an example of act 500. The method also includes act 505: latching a bit decision in the sense amplifier after the precharging in the first read cycle. Latching the RS flip-flop is an example of act 505. Additionally, the method includes act 510, which occurs in a second read cycle after the first read cycle and includes asserting a burst mode signal for a portion of the second read cycle in response to the row address of the second read cycle being equal to the row address of the first read cycle. Asserting burst mode signal 145 during a burst mode read operation is an example of act 510. Finally, the method includes act 515: in response to asserting the burst mode signal, transferring the bit decision latched in the sense amplifier to a data output latch during the second read cycle without precharging the sense amplifier. Propagating the bit decision to the data output latch 140 through the column multiplexer 125 during the burst mode read cycle is an example of action 515 .

[0051] The memory with burst mode address comparison as disclosed herein can be incorporated into a wide variety of electronic systems. Figure 6 As shown, a cellular phone 600, a laptop computer 605, and a tablet PC 610 can each include a memory having a burst mode address comparator according to the present disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers can also be configured with a burst mode address comparator constructed according to the present disclosure.

[0052] As will now be appreciated by those skilled in the art and depending on the particular application at hand, many modifications, substitutions and variations may be made to the materials, apparatus, configurations and methods of use of the apparatus of the present disclosure without departing from its scope. In view of this, since the specific embodiments shown and described herein are intended to be examples thereof only, the scope of the present disclosure should not be limited to the scope of these specific embodiments, but should be fully commensurate with the claims appended hereto and their functional equivalents.

Claims

1. A memory comprising: a plurality of latches configured to store a previous row address of the memory; a first plurality of logic gates configured to assert a bit comparison word in response to a current row address of the memory being equal to the previous row address stored in the plurality of latches; a first transistor having a terminal coupled to a burst mode node for a burst mode signal; as well as A second plurality of logic gates is configured to turn on the first transistor to ground the burst mode node through the terminal in response to the assertion of the bit comparison word by the first plurality of logic gates.

2. The memory according to claim 1, further comprising: A second transistor is coupled between the terminal of the first transistor and the burst mode node, wherein the second transistor is configured to turn on in response to a memory clock signal of the memory.

3. The memory of claim 1, wherein the plurality of latches comprises a plurality of master-slave latches.

4. The memory of claim 1, wherein the first plurality of logic gates comprises a plurality of XOR gates.

5. The memory of claim 4 , wherein the plurality of XOR gates are arranged into a plurality of XOR gate groups, and wherein the second plurality of logic gates comprises: a plurality of OR gates corresponding to the plurality of XOR gate groups, wherein each OR gate of the plurality of OR gates is configured to process an output signal from each XOR gate in a corresponding XOR gate group; and A NOR gate is configured to NOR the output signals from each OR gate, wherein the NOR gate is further configured to drive the gate of the first transistor. 6 . The memory of claim 5 , wherein a last one of the OR gates is further configured to process a delayed version of a memory clock signal of the memory.

7. The memory according to claim 2, further comprising: a self-timed clock circuit configured to assert a self-timed clock signal in response to the memory clock signal; as well as A third transistor is coupled between a power supply node for a memory power supply voltage and the burst mode node, wherein the third transistor is configured to turn on in response to a falling edge of the self-timed clock signal. 8 . The memory of claim 7 , wherein the first transistor is an n-type metal oxide semiconductor (NMOS) transistor, the second transistor is an NMOS transistor, and the third transistor is a p-type metal oxide (PMOS) transistor.

9. The memory according to claim 1, further comprising: a first column including a first sense amplifier configured to sense a first bit from a first bit cell through a first sense node pair and output the first bit at a first output terminal of the first column, a second column comprising a second sense amplifier configured to sense a second bit from a second bit cell through a second pair of sense nodes and output the second bit at a second output terminal of the second column; Data output latch; a column multiplexer configured to select between the first bit from the first output terminal and the second bit from the second output terminal to provide the selected bit to the data output latch; a sense node pre-charge circuit configured to pre-charge the first sense node pair and the second sense node pair in response to assertion of a sense node pre-charge signal; as well as A self-timed clock circuit is configured to assert the sense node pre-charge signal during a read cycle in which the burst mode signal is not asserted. 10 . The memory of claim 9 , wherein the first sense amplifier comprises a first reset-set latch, and wherein the second sense amplifier comprises a second reset-set latch.

11. The memory of claim 10 , wherein the first sense node pair includes a first sense node and a second sense node, and wherein the sense node precharge circuit includes a first transistor coupled between the first sense node and ground, and further includes a second transistor coupled between the second sense node and ground.

12. The memory of claim 11 , wherein the first column includes a bit line coupled to the first sense node through a first charge transfer transistor, and further includes a complement bit line coupled to the second sense node through a second charge transfer transistor, wherein the self-timed clock circuit is further configured to maintain the first charge transfer transistor and the second charge transfer transistor off during a read cycle in which the burst mode signal is asserted. 13 . The memory of claim 12 , wherein the first charge transfer transistor and the second charge transfer transistor are both p-type metal oxide semiconductor (PMOS) transistors.

14. The memory of claim 1, wherein the memory is incorporated into a cellular telephone.

15. The memory of claim 1, wherein the memory is incorporated into a laptop computer.

16. A burst mode method for a memory, comprising: precharging the sense amplifier in a first read cycle; latching a bit decision in the sense amplifier after the precharging of the sense amplifier in the first read cycle; in a second read cycle following the first read cycle, in response to a row address of the second read cycle being equal to a row address of the first read cycle, asserting a burst mode signal for a portion of the second read cycle; In response to the assertion of the burst mode signal, during the second read cycle, the bit decision latched in the sense amplifier is transferred to a data output latch without precharging the sense amplifier.

17. The burst mode method of claim 16, further comprising: asserting a word line during said first read cycle; initiating a charge transfer period in which a first charge transfer from a first precharged bit line in a first column to a first sense node of the sense amplifier depends on a binary value of a first bit of a first bit cell when the word line is asserted; as well as The first bit is sensed in response to the first charge transfer to form the bit decision that is latched in the sense amplifier.

18. The burst mode method of claim 17, further comprising: Prior to the charge transfer period, the first sensing node is discharged. 19 . The burst mode method of claim 16 , wherein in response to the assertion of the burst mode signal, the first sensing node of the sense amplifier is not discharged during the second read cycle.

20. A memory comprising: word line; a plurality of columns, each of the plurality of columns comprising a bit cell at an intersection of the column and the word line, a sense amplifier, and a bit line coupled to a sense node of the sense amplifier through a charge transfer transistor; a burst mode address comparator configured to determine, for a series of read cycles, whether each read cycle is a burst mode read cycle or a normal read cycle; as well as The bit line pre-charging circuit is configured to pre-charge the bit line in each column in each normal read cycle so that the corresponding sense amplifier is pre-charged, wherein the bit line pre-charging circuit is further configured not to pre-charge the bit line in each column in each burst mode read cycle so that the corresponding charge transfer transistor is turned off and the corresponding sense amplifier is not pre-charged.

21. The memory according to claim 20, further comprising: A self-timed clock circuit is provided, wherein the self-timed clock circuit is configured to assert the word line during each normal read cycle and not to assert the word line during each burst mode read cycle.

22. The memory of claim 21, wherein the self-timed clock circuit is further configured to prevent pre-charging of the sense node during each burst mode read cycle.

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